Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of suppressing a malfunction caused by a disconnection and a manufacturing method thereof. The semiconductor storage device of the embodiments includes a first stack, a second stack, an intermediate insulating layer, and a plurality of columnar bodies. The intermediate insulating layer is located between the first stack and the second stack, and has a thickness in a stacking direction that is greater than a thickness of one insulating layer included in a plurality of insulating layers of the first stack. The plurality of columnar bodies are provided across the first stack and the second stack, and include a semiconductor base, a charge accumulation film provided between at least one of a plurality of conductive layers and the semiconductor base, and a semiconductor film. The plurality of columnar bodies each have a first columnar portion formed in the first stack, a second columnar portion formed in the intermediate insulating layer, and a third columnar portion formed in the second stack. A width of the semiconductor film in a direction intersecting the stacking direction in the second columnar portion is shortest at an upper end of the intermediate columnar portion and longest at a lower end of the intermediate columnar portion.

Description

[0001] [Linked Application]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-43362 (filed on March 17, 2021). This application incorporates the entire contents of the basic application by reference to this basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] NAND flash memory is known to be composed of three-dimensional stacked storage cells. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor memory device capable of suppressing malfunctions caused by wire breaks, and a method for manufacturing a semiconductor memory device.

[0006] The semiconductor memory device of the embodiment includes a first stack, a second stack, an intermediate insulating layer, and a plurality of pillars. The first stack has a plurality of conductive layers and a plurality of insulating layers, with the conductive and insulating layers alternately stacked. The second stack is located above the first stack and has a plurality of conductive layers and a plurality of insulating layers, with the conductive and insulating layers alternately stacked. The intermediate insulating layer is located between the first and second stacks and has a thickness in the stacking direction greater than that of a single insulating layer included in the plurality of insulating layers of the first stack. The plurality of pillars are disposed across the first and second stacks and include: a core; a charge storage film disposed between at least one of the plurality of conductive layers and the core; and a semiconductor substrate disposed between the charge storage film and the core. Each of the plurality of pillars has: a first pillar portion formed within the first stack; an intermediate pillar portion formed within the intermediate insulating layer; and a second pillar portion formed within the second stack. The width of the intermediate columnar portion in the direction intersecting the stacking direction of the semiconductor substrate is the shortest at the upper end of the intermediate columnar portion and the longest at the lower end of the intermediate columnar portion. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the circuit structure of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of the memory cell array of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a top view of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is a cross-sectional view of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 This is a cross-sectional view showing the area near the central column of the memory cell array in the first embodiment.

[0012] Figure 6 This is a process diagram illustrating the manufacturing method of the memory cell array according to the first embodiment.

[0013] Figures 7 to 20 This is a cross-sectional view illustrating an example of the manufacturing process of the memory cell array according to the first embodiment.

[0014] Figure 21 This is a cross-sectional view showing the area near the central column of the memory cell array in the first modified example.

[0015] Explanation of reference numerals in the attached figures

[0016] 1…Semiconductor memory, 2…Memory controller, 10…Memory cell array, 11…Line decoder, 12…Sense amplifier, 13…Sequence generator, 20…Substrate, 22…Insulating layer, 30…Laminated structure, 30A…First laminate, 30B…Second laminate, 31, 32, 37…Conductive layer, 33…Insulating layer, 35…Intermediate insulating layer, 35A…Lower surface, 35B…Upper surface, 38…Conductive layer, 39…Insulating layer, 40…Columnar structure, 40A…First columnar portion 40A1…lower end, 40A2…upper end, 40B…second columnar portion, 40B1…lower end, 40B2…upper end, 40C…intermediate columnar portion, 40C1…lower end, 40C2…upper end, 41…core, 42…semiconductor substrate, 43…memory film, 44…barrier insulating film, 45…charge storage film, 46…tunnel insulating film, 50, 54…sacrificial layer, 51…first sacrificial material, 52…intermediate sacrificial material, 60A…first stacked precursor, 60B…second stacked precursor Detailed Implementation

[0017] Hereinafter, a semiconductor memory device and a method for manufacturing a semiconductor memory device according to embodiments will be described with reference to the accompanying drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as in reality. In the following description, structures having the same or similar functions are labeled with the same reference numerals. Furthermore, repeated descriptions of these structures are sometimes omitted. Numbers following the characters constituting the reference numerals are referred to by reference numerals containing the same characters and are used to distinguish elements having the same structure from each other. When it is not necessary to distinguish elements shown by reference numerals containing the same characters from each other, these elements are referred to by reference numerals containing only the same characters.

[0018] First, define the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction. The +X direction, -X direction, +Y direction, and -Y direction are related to the substrate 20 described later (refer to...). Figure 4 The surface of the +X direction is roughly parallel to the direction of the other string unit SU1 (see below). Figure 3 The -X direction is the opposite direction to the +X direction. Without distinguishing between the +X and -X directions, it is simply referred to as the "X direction". The +Y and -Y directions are directions that intersect (e.g., approximately orthogonal) the X direction. The +Y and -Y directions are opposite directions to each other. Without distinguishing between the +Y and -Y directions, it is simply referred to as the "Y direction". The +Z and -Z directions are directions that intersect (e.g., approximately orthogonal) the X and Y directions. The +Z direction is the direction from the first stack 30A (described later) towards the second stack 30B (see reference). Figure 4 The -Z direction is the direction opposite to the +Z direction. Without distinguishing between the +Z and -Z directions, it is simply referred to as the "Z direction" or "layering direction." In this specification, the "+Z direction" is sometimes referred to as "up" and the "-Z direction" as "down." However, these are for convenience and do not specify the direction of gravity. In this embodiment, the +Z direction is an example of a "first direction." The +X direction is an example of a "second direction."

[0019] In this specification, "connection" is not limited to physical connections, but also includes electrical connections. In this specification, "facing," "overlapping," and "adjacent" are not limited to situations where two components are in contact with each other, but also include situations where other components exist between the two components. In this specification, "extending along direction A" means, for example, that the dimension in direction A is larger than the smallest dimension among the dimensions in the X, Y, and Z directions. "Direction A" is any direction. Furthermore, in this specification, "width in direction A" refers to the width in direction A in a cross-section passing through or near the central axis C of the columnar body 40 in the Z direction, and approximately parallel to the X direction (see reference). Figure 4 "Central axis C of column 40" refers to a virtual axis passing through the center of column 40 in the X and Y directions in the Z direction.

[0020] (First Embodiment)

[0021] First, the overall structure of the semiconductor memory device (semiconductor memory) of this embodiment will be described.

[0022] The semiconductor memory 1 in this embodiment is a non-volatile semiconductor memory device, such as a NAND flash memory.

[0023] Figure 1This is a block diagram representing the system architecture of semiconductor memory 1.

[0024] The semiconductor memory 1 includes, for example, a memory cell array 10, a line decoder 11, a readout amplifier 12, and a sequence generator 13.

[0025] The memory cell array 10 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Block BLK is a non-volatile memory cell transistor MT (refer to...). Figure 2 The memory cell array 10 is a collection of data points. Multiple bit lines and multiple word lines are provided in the array. Each memory cell transistor MT is associated with one bit line and one word line. The detailed structure of the memory cell array 10 will be described later.

[0026] The row decoder 11 selects one block BLK based on the address information ADD received from the external memory controller 2. The row decoder 11 controls the writing and reading of data from the memory cell array 10 by applying desired voltages to multiple word lines.

[0027] The read amplifier 12 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 2. The read amplifier 12 determines the data stored in the memory cell transistor MT based on the voltage of the bit line and sends the determined read data DAT to the memory controller 2.

[0028] The sequence generator 13 controls the overall operation of the semiconductor memory 1 based on the instruction CMD received from the memory controller 2.

[0029] The semiconductor memory 1 and memory controller 2 described above can be combined to form a semiconductor device. Examples of semiconductor devices include memory cards such as SD cards (registered trademark) and SSDs (Solid State Drives).

[0030] Next, the electrical structure of the memory cell array 10 will be described.

[0031] Figure 2 This is a diagram representing the equivalent circuit of the memory cell array 10, and a block BLK is extracted for representation. The block BLK contains multiple (e.g., 4) serial cells SU (SU0 to SU3).

[0032] Each string cell SU is a collection of multiple NAND strings NS. One end of each NAND string NS is connected to a bit line BL (any one of BL0 to BLm (m is an integer greater than or equal to 1)). The other end of the NAND string NS is connected to the source line SL. Each NAND string NS contains multiple (e.g., 18) memory cell transistors MT (MT0 to MT17), a first selection transistor ST1, and a second selection transistor ST2.

[0033] Multiple memory cell transistors MT (MT0 to MT17) are connected in series. Each memory cell transistor MT includes a control gate and a charge storage film, storing data non-volatilely. The memory cell transistor MT accumulates charge in the charge storage film according to the voltage applied to the control gate. The control gate of the memory cell transistor MT is connected to a corresponding word line WL (any one of WL0 to WL17). The memory cell transistor MT is electrically connected to the line decoder 11 via the word line WL.

[0034] The first selection transistor ST1 is connected between multiple storage transistors MT (MT0 to MT17) and their corresponding bit lines BL. The drain of the first selection transistor ST1 is connected to the bit line BL. The source of the first selection transistor ST1 is connected to the multiple storage transistors MT. The control gate of the first selection transistor ST1 is connected to the corresponding selection gate line SGD (any one of SGD0 to SGD3). The first selection transistor ST1 is electrically connected to the line decoder 11 via the selection gate line SGD. When a specified voltage is applied to the selection gate line SGD, the first selection transistor ST1 connects the NAND string NS to the bit line BL.

[0035] The second selection transistor ST2 is connected between multiple memory transistors MT (MT0 to MT17) and the source line SL. The drain of the second selection transistor ST2 is connected to the multiple memory transistors MT. The source of the second selection transistor ST2 is connected to the source line SL. The control gate of the second selection transistor ST2 is connected to the select gate line SGS. The second selection transistor ST2 is electrically connected to the line decoder 11 via the select gate line SGS. When a specified voltage is applied to the select gate line SGS, the second selection transistor ST2 connects the NAND string NS to the source line SL.

[0036] Next, the physical structure of the storage cell array 10 will be described.

[0037] Figure 3This is a top view showing a portion of the memory cell array 10. For example, multiple string cells SU are arranged in the X direction and extend along the Y direction. The multiple string cells SU are separated from each other by slits SLT filled with insulating material. Each string cell SU includes multiple pillars 40 extending along the Z direction. Each pillar 40 is connected to a bit line BL via a contact plug BLC described later. For example, the bit line BL extends in the X direction.

[0038] Figure 4 This is a cross-sectional view showing a portion of the memory cell array 10. The memory cell array 10 includes, for example, a substrate 20, an insulating layer 22, a source line SL, a laminate 30, a columnar body 40, contact plugs BLC, and bit lines BL.

[0039] The substrate 20 has surfaces along the X and Y directions. The substrate 20 is, for example, a silicon substrate. An insulating layer 22 is disposed on top of the substrate 20. A driving circuit including CMOS (Complementary Metal-Oxide Semiconductor) is disposed inside the insulating layer 22. A source line SL, serving as a conductor, is disposed on top of the insulating layer 22. The source line SL is formed in a plate shape that is substantially parallel to the X and Y directions.

[0040] The laminate 30 is disposed above the source line SL. The laminate 30 includes a first laminate 30A, an intermediate insulating layer 35, and a second laminate 30B.

[0041] The first stack 30A includes a conductive layer 31, multiple conductive layers 32, and multiple insulating layers 33. In the first stack 30A, the multiple conductive layers 31, 32, and multiple insulating layers 33 are stacked in the Z direction. The conductive layer 31 functions as the select gate line (SGS). The multiple conductive layers 32, positioned above the conductive layer 31, function as word lines WL0 to WL8, respectively. The insulating layers 33 are disposed between the conductive layers 31 and 32, and between the multiple conductive layers 32. The conductive layers 31, 32, and insulating layers 33 are formed as plates along the X and Y directions, respectively.

[0042] The second stack 30B is positioned above the first stack 30A. The second stack 30B includes multiple conductive layers 37, one conductive layer 38, and multiple insulating layers 39. In the second stack 30B, the multiple conductive layers 37 and 38 and the multiple insulating layers 39 are stacked in the Z direction. The multiple conductive layers 37 function as word lines WL9 to WL17, respectively. The conductive layer 38 is located above the multiple conductive layers 37 and functions as the select gate line (SGD). The insulating layers 39 are disposed between the multiple conductive layers 37 and between the conductive layers 37 and 38. The conductive layers 37 and 38 and the insulating layer 39 are formed as plates along the X and Y directions, respectively.

[0043] The intermediate insulating layer 35 is located between the first laminate 30A and the second laminate 30B in the Z direction. The thickness (e.g., maximum thickness) t3 of the intermediate insulating layer 35 in the Z direction is thicker than the thickness t1 of any insulating layer 33 included in the first laminate 30A in the Z direction, and thicker than the thickness t2 of any insulating layer 39 included in the second laminate 30B in the Z direction. "Thickness t3 of the intermediate insulating layer 35" refers to the distance between the lower surface 35A of the intermediate insulating layer 35 in contact with the uppermost conductive layer 32 included in the first laminate 30A and the upper surface 35B of the intermediate insulating layer 35 in contact with the lowermost conductive layer 37 included in the second laminate 30B. The thickness t3 of the intermediate insulating layer 35 can be less than 30 nm.

[0044] The columnar body 40 functions as, for example, a NAND string NS. The columnar body 40 is disposed within the laminate 30 along the Z-direction, extending at least from the second laminate 30B through the intermediate insulating layer 35 to the first laminate 30A. The lower end of the columnar body 40 is connected to the source line SL. The upper end of the columnar body 40 is connected to the bit line BL via a contact plug BLC. The contact plug BLC refers to a connecting component formed of a conductive material, such as a columnar or frustum-shaped component. In this embodiment, the columnar body 40 includes a first columnar portion 40A, a second columnar portion 40B, and an intermediate columnar portion 40C.

[0045] A first columnar portion 40A is formed within a first laminate 30A and extends along the Z direction within the first laminate 30A. The first columnar portion 40A has a lower end 40A1 and an upper end 40A2. The lower end 40A1 contacts the source line SL. The upper end 40A2 contacts the second columnar portion 40B. For example, the width of the first columnar portion 40A gradually decreases in both the X and Y directions as it extends from the upper end 40A2 toward the lower end 40A1.

[0046] The second columnar portion 40B is formed within the second laminate 30B and extends along the Z direction within the second laminate 30B. The second columnar portion 40B has a lower end 40B1 and an upper end 40B2. The lower end 40B1 contacts the intermediate columnar portion 40C. The upper end 40B2 contacts the contact plug BLC. For example, the width of the second columnar portion 40B gradually tapers in both the X and Y directions as it moves from the upper end 40B2 toward the lower end 40B1.

[0047] An intermediate columnar portion 40C is formed within an intermediate insulating layer 35 and extends along the Z direction within the intermediate insulating layer 35. The intermediate columnar portion 40C has a lower end 40C1 and an upper end 40C2. The lower end 40C1 contacts the first columnar portion 40A. The upper end 40C2 contacts the second columnar portion 40B. The upper end 40C2 and the lower end 40C1 of the intermediate columnar portion 40C have the same width in, for example, the X and Y directions. The thickness of the intermediate columnar portion 40C in the Z direction (lamination direction) is set to be the same as the thickness t3 of the intermediate insulating layer 35.

[0048] The columnar body 40 has, from its inner side, a core 41, a semiconductor substrate 42, and a storage film 43. The columnar body 40 is formed within a hole, i.e., a storage hole, that penetrates the laminate 30 in the Z direction. The storage film 43 is disposed on the inner wall of the storage hole.

[0049] Core 41 extends along the Z direction and is columnar. Core 41 comprises, for example, silicon oxide. Core 41 is located inside the semiconductor substrate 42.

[0050] Semiconductor substrate 42 extends along the Z-direction. Semiconductor substrate 42 covers the outer surface of core 41. Semiconductor substrate 42 is located between the inner surface of storage film 43 and the outer surface of core 41. Semiconductor substrate 42 may contain silicon, for example. The silicon may be polycrystalline silicon formed by crystallizing amorphous silicon. Semiconductor substrate 42 serves as the channel for each of the first selection transistor S1, the storage cell transistor MT, and the second selection transistor S2. The channel is the flow path for charge carriers between the source and drain sides.

[0051] The storage film 43 extends along the Z-direction. The storage film 43 covers the outer surface of the semiconductor substrate 42. The storage film 43 is located between the inner surface of the storage via and the outer surface of the semiconductor substrate 42. The storage film 43 includes a barrier insulating film 44, a charge storage film 45, and a tunnel insulating film 46. The storage film 43 is located near the semiconductor substrate 42 in the order of barrier insulating film 44, charge storage film 45, and tunnel insulating film 46, starting from the inner wall of the storage via.

[0052] The barrier insulating film 44 is located between the conductive layers 31, 32, 37, 38 and the insulating layers 33, 39 of the first laminate 30A and the second laminate 30B, respectively, and the charge storage film 45. The barrier insulating film 44 is a laminated structure film consisting of a silicon oxide film, a metal oxide film, and multiple insulating films. An example of a metal oxide is aluminum oxide.

[0053] A charge storage film 45 is located between the barrier insulating film 44 and the tunnel insulating film 46. The charge storage film 45 may contain, for example, silicon nitride. The portions where the charge storage film 45 intersects with the multiple conductive layers 31, 32, 37, and 38 function as transistors. The storage cell transistor MT retains data based on the presence or absence of charge, or the amount of charge stored, in the portions where the charge storage film 45 intersects with the multiple conductive layers 31, 32, 37, and 38 (charge storage sections). The charge storage sections are located between each conductive layer 31, 32, 37, and 38 and the semiconductor substrate 42, and are surrounded by an insulating material.

[0054] A tunnel insulating film 46 is located between the charge storage film 45 and the semiconductor substrate 42. The tunnel insulating film 46 may comprise, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 46 acts as a potential barrier between the semiconductor substrate 42 and the charge storage film 45.

[0055] In this semiconductor memory 1 with such a structure, the intersections of the pillar 40 with the conductive layers 31, 32, 37, and 38 of the first stack 30A and the second stack 30B function as transistors. For example, the intersection of the pillar 40 with the conductive layer 38 functions as a first selection transistor ST1. The intersection of the pillar 40 with the conductive layer 31 functions as a second selection transistor ST2. The intersections of the pillar 40 with the multiple conductive layers 32 and 38 function as memory cell transistors MT (MT0 to MT17).

[0056] Figure 5 It is a cross-sectional view showing an enlarged view of the area near the central column 40C of the storage cell array 10.

[0057] In the memory cell array 10 of this embodiment, the width of the semiconductor substrate 42 in the intermediate columnar portion 40C in the direction intersecting the stacking direction is at the upper end 40C2 of the intermediate columnar portion 40C (in Figure 5 The shortest is DB), at the lower end of the middle columnar part 40C 40C1 (in Figure 5 The longest dimension is DA. The width of the semiconductor substrate 42 in the direction intersecting the stacking direction is the distance between the semiconductor substrate 42 and the core 41 within the cross-section of the memory cell array 10. Regarding the width of the semiconductor substrate 42 in the direction intersecting the stacking direction, if the cross-sectional shape of the semiconductor substrate 42 in this direction is circular, it is the diameter of the circle. If the cross-sectional shape is elliptical, it is the length of the major axis of the ellipse. If the cross-sectional shape is polygonal, it is the length of the longest diagonal of the polygon.

[0058] The width of the semiconductor substrate 42 in the intermediate columnar portion 40C in the direction intersecting the stacking direction can also increase as it approaches the lower end 40C1 from the upper end 40C2 of the intermediate columnar portion 40C. In this case, the width of the semiconductor substrate 42 in the direction intersecting the stacking direction can increase either continuously or in stages.

[0059] The thickness t3 of the intermediate insulating layer 35 in the stacking direction (Z direction) (the thickness of the intermediate columnar portion 40C in the stacking direction) is less than twice the average film thickness of the storage film 43 in the intermediate columnar portion 40C, that is, the average film thickness between the outer surface of the semiconductor substrate 42 and the outer surface of the intermediate columnar portion 40C. For example, when the thickness t3 of the intermediate insulating layer 35 is less than 30 nm, the average film thickness of the storage film 43 is less than 15 nm. In addition, the width of the storage film 43 (especially the charge storage film 45) in the intermediate columnar portion 40C in the direction where the stacking directions intersect can also be the largest between the upper end 40C2 and the lower end 40C1 of the intermediate columnar portion (that is, the portion other than the upper end 40C2 and the lower end 40C1).

[0060] The intermediate columnar portion 40C may also be more extensive than the first columnar portion 40A and the second columnar portion 40B in both the X and Y directions. For example, the outer perimeter length of the lower end 40C1 of the intermediate columnar portion 40C may be greater than the outer perimeter length of the upper end 40A2 of the first columnar portion 40A, and the outer perimeter length of the upper end 40C2 of the intermediate columnar portion 40C may also be greater than the outer perimeter length of the lower end of the second columnar portion 40B. Furthermore, the outer perimeter length of the lower end 40B1 of the second columnar portion 40B may be shorter than the outer perimeter length of the upper end 40A2 of the first columnar portion 40A.

[0061] Next, an example of a method for manufacturing the memory cell array 10 will be described.

[0062] Figure 6 This is a process diagram illustrating an example of a manufacturing method for the memory cell array 10. Figures 7 to 19 This is a cross-sectional view showing each manufacturing process of the storage cell array 10.

[0063] Figure 7 Is with Figure 6 This is a cross-sectional view corresponding to the preceding process of the first lamination process shown. In the preceding process, an insulating layer 22 and a source line SL are formed on the substrate 20. A driving circuit including CMOS and the like is formed on the insulating layer 22. In addition, an insulating layer 33 and a conductive layer 31 are laminated above the source line SL.

[0064] Figure 8 Is with Figure 6The diagram shows a cross-sectional view corresponding to the first lamination process (S10). In the first lamination process, an insulating layer 33 and a sacrificial layer 50 are alternately laminated on the conductive layer 31. This produces a first lamination precursor 60A. The sacrificial layer 50 is, for example, a silicon nitride (SiN) film.

[0065] Figure 9 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the first hole formation process (S11). In the first hole formation process, the first hole LH is formed by the first stacked precursor 60A stacked in the first stacking process (S10). The first hole LH is processed by photolithography and anisotropic etching. Anisotropic etching can be performed, for example, using RIE (Reactive Ion Etching).

[0066] Figure 10 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the first sacrificial material formation step (S12). In the first sacrificial material formation step, a first sacrificial material 51 is formed inside the hole LH formed by the first hole formation step (S11). The first sacrificial material 51 is, for example, amorphous silicon (aSi).

[0067] Figure 11 Is with Figure 6 The cross-sectional view corresponding to the intermediate insulating layer lamination process (S13) shown. In the intermediate insulating layer lamination process, the intermediate insulating layer 35 is laminated on the first sacrificial material 51 formed by the first sacrificial material formation process (S12) and the uppermost sacrificial layer 50 of the first lamination precursor 60A.

[0068] Figure 12 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the intermediate hole formation process (S14). In the intermediate hole formation process, an intermediate hole MH is formed in the intermediate insulating layer 35 stacked by the intermediate insulating layer stacking process (S13). The intermediate hole MH is processed by photolithography and anisotropic etching. Anisotropic etching can be used, for example, RIE. The intermediate hole MH can be expanded in both the X and Y directions compared to the first hole LH.

[0069] Figure 13 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the intermediate sacrificial material formation process (S15). In the intermediate sacrificial material formation process, intermediate sacrificial material 52 is formed inside the intermediate hole MH formed by the intermediate hole formation process (S14). The intermediate sacrificial material 52 is, for example, amorphous silicon (aSi).

[0070] Figure 14 Is with Figure 6The diagram shows a cross-sectional view corresponding to the second lamination process (S16). In the second lamination process, an insulating layer 33 and a sacrificial layer 54 are alternately laminated over the intermediate sacrificial material 52 and the intermediate insulating layer 35 formed by the intermediate sacrificial material formation process (S15). This produces a second lamination precursor 60B. The sacrificial layer 54 is, for example, a silicon nitride (SiN) film.

[0071] Figure 15 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the second hole formation process (S17). In the second hole formation process, a second hole UH is formed in the second stacked precursor 60B, which is stacked by the second stacking process (S16). The second hole UH is processed by photolithography and anisotropic etching. Anisotropic etching can be performed, for example, using RIE. The second hole UH is formed to be connected to the intermediate sacrificial material 52 of the intermediate insulating layer 35. The lower end of the second hole UH has a shape smaller than the intermediate sacrificial material 52.

[0072] Figure 16 Is with Figure 6 The cross-sectional view corresponding to the sacrificial material removal process (S18) is shown. In the sacrificial material removal process, the first sacrificial material 51 and the intermediate sacrificial material 52 are removed by wet etching. As a result, the inner wall surfaces of the first hole LH and the intermediate hole MH are exposed.

[0073] Figure 17 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the storage film formation process (S19). In the storage film formation process, a storage film 43 is formed by sequentially stacking a barrier insulating film 44, a charge storage film 45, and a tunnel insulating film 46 on the inner wall surfaces of the first hole LH, the intermediate hole MH, and the second hole UH, which are exposed by the sacrificial material removal process (S18).

[0074] Figure 18 , Figure 19 Is with Figure 6 The diagram shows a cross-sectional view corresponding to the semiconductor substrate formation process (S20). In the semiconductor substrate formation process, firstly, as shown... Figure 18 As shown, a semiconductor substrate 42 is formed inside the tunnel insulating film 46 of the storage film 43 formed in the storage film formation process (S19). Next, as... Figure 19 As shown, wet thinning is performed to adjust the film thickness. By performing wet thinning, the surface roughness of the semiconductor substrate 42 is reduced, and the width of the semiconductor substrate 42 in the direction intersecting the stacking direction tends to be the shortest at the top and the longest at the bottom.

[0075] Figure 20 Is with Figure 6 The cross-sectional view corresponding to the core forming process (S21) shown. In the core forming process, firstly, as... Figure 20 As shown, a core 41 is formed inside the semiconductor substrate 42 formed by the semiconductor substrate formation process S20.

[0076] In this way, columnar bodies 40 are formed inside the first hole LH, the intermediate hole MH, and the second hole UH.

[0077] Next, a slotted surface layer (SLT) is formed through a slotting process. This divides the space into multiple string units (SU). Then, sacrificial layers 50 and 54 are removed by wet etching via the slotted SLT. Next, conductive material is filled into the spaces left by the removal of sacrificial layers 50 and 54 to form conductive layers 32, 37, and 38. Through the above processes, a laminate 30 and a columnar structure 40 are formed.

[0078] In the manufacturing method of the memory cell array 10 of this embodiment, the thickness of the intermediate insulating layer 35 is set to be less than twice the average film thickness between the outer surface of the semiconductor substrate 42 formed by the intermediate hole MH and the inner wall surface of the intermediate hole MH. For example, in the film deposition process (S19), the thickness of the memory film 43 formed on the inner wall surface of the intermediate hole MH may also be set to less than twice the thickness of the intermediate insulating layer 35. In addition, the memory film 43 formed on the inner wall surface of the intermediate hole MH is preferably of a thickness that can fill the portion that expands beyond the first hole LH and the second hole UH.

[0079] In the manufacturing method of the semiconductor memory 1 described above, sacrificial layers 50 and 54 are used in the first stacked precursor 60A and the second stacked precursor 60B, but the method is not limited to this. For example, conductive layers may be used instead of sacrificial layers 50 and 54. In this case, the process of removing the sacrificial layers and filling them with conductive material is not required.

[0080] In the semiconductor memory 1 of this embodiment described above, the width of the semiconductor substrate 42 in the intermediate columnar portion 40C in the direction intersecting the stacking direction is shortest at the upper end 40C2 of the intermediate columnar portion 40C and longest at the lower end 40C1 of the intermediate columnar portion 40C. Therefore, the occurrence of breakage of the semiconductor substrate 42 can be suppressed, and thus malfunction of the semiconductor memory 1 can be suppressed. While the reason for suppressing the occurrence of breakage of the semiconductor substrate 42 may not be clear, it is considered as follows.

[0081] In a semiconductor memory 1 with an intermediate insulating layer 35 between a first stack 30A and a second stack 30B, during the manufacturing process, the size of the hole formed in the intermediate insulating layer 35 is generally larger than that of the first stack 30A and the second stack 30B. In this case, steps are formed at the upper and lower ends of the intermediate hole MH. With these steps, if a memory film 43 and a semiconductor substrate 42 are sequentially formed on the inner wall surface of the intermediate hole MH, the thickness of the semiconductor substrate 42 sometimes becomes too thin at the edge of the step, causing the semiconductor substrate 42 to break. The thinning of the semiconductor substrate 42 at the edge of the step tends to occur particularly easily when thinning the semiconductor substrate 42. In this embodiment, the semiconductor substrate 42 is thinned such that its width in the direction intersecting the stacking direction is shortest at the upper end 40C2 of the intermediate columnar portion 40C and longest at the lower end 40C1 of the intermediate columnar portion 40C. Therefore, the thickness of the semiconductor substrate 42 is not easily reduced excessively at the edge of the step. Consequently, the semiconductor substrate 42 is less prone to breakage.

[0082] In the semiconductor memory 1 of this embodiment, the width of the semiconductor substrate 42 in the direction intersecting the stacking direction can also increase as it approaches the lower end 40C1 from the upper end 40C2 of the intermediate columnar portion 40C. In this case, since the surface shape of the semiconductor substrate 42 becomes smooth, the semiconductor substrate 42 is less prone to breakage.

[0083] In the semiconductor memory 1 of this embodiment, the width of the charge storage film in the intermediate columnar portion in the direction intersecting the stacking direction can also be maximized in the portion other than the upper and lower ends of the intermediate columnar portion.

[0084] In the semiconductor memory 1 of this embodiment, the thickness t3 of the intermediate insulating layer 35 in the stacking direction can be less than twice the average film thickness (i.e., the average film thickness of the storage film 43) between the outer surface of the semiconductor substrate in the intermediate columnar portion 40C and the outer surface of the intermediate columnar portion. In this case, since the thickness t3 of the intermediate insulating layer 35 in the stacking direction is thinner, after the insulator 43 is formed, the inner perimeter of the intermediate insulating layer 35 becomes a smooth shape that monotonically increases as it approaches the lower end 40C1 from the upper end 40C2. As a result, it is less likely that the thickness of the semiconductor substrate 42 will become excessively thin.

[0085] In the semiconductor memory 1 of this embodiment, the thickness t3 of the intermediate insulating layer 35 in the stacking direction can also be 30 nm or less. In this case, since the thickness t3 of the intermediate insulating layer 35 in the stacking direction is thin to less than 30 nm, after the insulator 43 is formed, the inner perimeter of the intermediate insulating layer 35 becomes a smooth shape that monotonically increases further from the upper end 40C2 to the lower end 40C1. As a result, it is more difficult for the semiconductor substrate 42 to become excessively thin.

[0086] In the semiconductor memory 1 of this embodiment, the outer perimeter length of the lower end 40C1 of the intermediate columnar portion 40C may be greater than the outer perimeter length of the upper end 40A2 of the first columnar portion 40A, and the outer perimeter length of the upper end 40C2 of the intermediate columnar portion 40C may be less than the outer perimeter length of the lower end 40B1 of the second columnar portion 40B. In this case, the intermediate columnar portion 40C is larger than the first columnar portion 40A and the second columnar portion 40B in both the X and Y directions, thus facilitating the connection of the first columnar portion 40A and the second columnar portion 40B via the intermediate columnar portion 40C.

[0087] In the semiconductor memory 1 of this embodiment, the outer perimeter length of the lower end 40B1 of the second columnar portion 40B may be shorter than the outer perimeter length of the upper end 40A2 of the first columnar portion 40A. In this case, it is easier to connect the second columnar portion 40B than the intermediate columnar portion 40C, and therefore, it is easier to connect the first columnar portion 40A and the second columnar portion 40B via the intermediate columnar portion 40C.

[0088] In the manufacturing method of the semiconductor memory 1 of this embodiment, the thickness t3 of the intermediate insulating layer 35 is set to be less than twice the average film thickness between the outer surface of the semiconductor substrate 42 formed in the intermediate hole MH and the inner wall surface of the intermediate hole MH. As a result, the thickness t3 of the intermediate insulating layer 35 in the stacking direction is thinner, and the distance between the upper and lower steps of the intermediate hole MH is shorter. Therefore, in the obtained semiconductor memory 1, the width of the semiconductor substrate 42 in the intermediate columnar portion 40C in the direction intersecting the stacking direction is preferably shortest at the upper end 40C2 of the intermediate columnar portion 40C and longest at the lower end 40C1 of the intermediate columnar portion 40C, and the case where the thickness of the semiconductor substrate 42 becomes excessively thin at the edge of the step is less likely to occur.

[0089] In the semiconductor memory 1 of this embodiment, the thickness t3 of the intermediate insulating layer 35, which is configured as a memory cell array, is the same as the thickness of the intermediate pillar portion 40C in the stacking direction. However, the relationship between the thickness t3 of the intermediate insulating layer 35 and the thickness of the intermediate pillar portion 40C is not limited to this. That is, as long as there is a region within the intermediate insulating layer 35 for forming the intermediate pillar portion 40C, the overall thickness of the intermediate insulating layer 35 can be thicker than the thickness of the intermediate pillar portion 40C. In this case, the thickness of the intermediate pillar portion 40C in the stacking direction can be set to less than twice the average film thickness between the outer surface of the semiconductor substrate 42 in the intermediate pillar portion 40C and the outer surface of the intermediate pillar portion 40C. Alternatively, the thickness of the intermediate pillar portion 40C in the stacking direction can be set to 30 nm or less. Figure 21 An example of such a storage cell array is shown.

[0090] Figure 21 This is a cross-sectional view showing the area near the central column of the memory cell array in the first modified example.

[0091] Figure 21 The thickness t3 of the intermediate insulating layer 35 in the stacking direction of the first modified example differs from that of the first embodiment. In the first modified example, the thickness t3 of the intermediate insulating layer 35 is thicker than the thickness of the intermediate columnar portion 40C. That is, the intermediate insulating layer 35 has a connecting portion that connects the intermediate columnar portion 40C to the first columnar portion 40A, and a connecting portion that connects the intermediate columnar portion 40C to the second columnar portion 40B. The thickness t3 of the intermediate insulating layer 35 can, for example, be in the range of more than 1.1 times and less than 3.0 times the thickness of the intermediate columnar portion 40C. The other structures of the first modified example are the same as those of the first embodiment, so the same reference numerals are used and their descriptions are omitted. In addition, in the first modified example, the intermediate columnar portion 40C exists in the center of the intermediate insulating layer 35, but the intermediate columnar portion 40C can exist in a manner in which its lower end is horizontal with the lower end of the intermediate insulating layer 35, or in a manner in which its upper end is horizontal with the upper end of the intermediate insulating layer 35.

[0092] The intermediate insulating layer 35 of the first modification can be formed, for example, in the following manner.

[0093] In the intermediate hole forming process (S14), a hole with the same diameter as the first hole LH is formed in the intermediate insulating layer 35, which has been laminated in the intermediate insulating layer lamination process (S13). Next, a hole larger than the first hole LH is formed in both the X and Y directions at a position from the lower end of the intermediate insulating layer 35 upwards. In this way, an intermediate hole MH is formed in the intermediate insulating layer, which has a hole for forming an intermediate columnar portion 40C and a hole for forming a connecting portion connecting the intermediate columnar portion 40C and the first columnar portion 40A.

[0094] Next, in the intermediate sacrificial material forming process (S15), intermediate sacrificial material 52 is formed inside the intermediate hole MH.

[0095] Next, before performing the second lamination process (S16), an intermediate insulating layer 35 for forming a connecting portion that connects the intermediate columnar portion 40C and the second columnar portion 40B is formed on top of the intermediate insulating layer 35 on which the intermediate sacrificial material 52 is formed. Then, the second lamination process (S16) is performed on top of this intermediate insulating layer 35 to produce the second lamination precursor 60B.

[0096] Next, in the second hole formation process, a second hole UH is formed in the second stacked precursor 60B, and a hole for forming a connecting portion connecting the intermediate columnar portion 40C and the second columnar portion 40B is formed in the intermediate insulating layer 35. Then, the sacrificial material removal process (S18), the storage film formation process (S19), the semiconductor substrate formation process (S20), and the core formation process (S21) are performed sequentially.

[0097] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are also included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: The first laminate has multiple conductive layers and multiple insulating layers, with the conductive layers and insulating layers stacked alternately. The second stack, located above the first stack, has multiple conductive layers and multiple insulating layers, with the conductive layers and insulating layers stacked alternately. An intermediate insulating layer is located between the first laminate and the second laminate, and the thickness of the intermediate insulating layer in the lamination direction is thicker than that of a single insulating layer included in the plurality of insulating layers of the first laminate. as well as A plurality of columnar bodies, disposed across a first stack and a second stack, comprising: a core; a charge storage film disposed between at least one of the plurality of conductive layers and the core; and a semiconductor substrate disposed between the charge storage film and the core. The plurality of columnar bodies each have: a first columnar portion formed within the first laminate; an intermediate columnar portion formed within the intermediate insulating layer; and a second columnar portion formed within the second laminate. The width of the semiconductor substrate in the intermediate columnar portion in the direction intersecting the stacking direction is set to be the shortest at the upper end of the intermediate columnar portion and the longest at the lower end of the intermediate columnar portion, so as to suppress the breakage of the semiconductor substrate in the intermediate columnar portion.

2. The semiconductor memory device according to claim 1, wherein, The width of the semiconductor substrate in the intermediate columnar portion in the direction intersecting the stacking direction increases as it approaches the lower end of the intermediate columnar portion.

3. The semiconductor memory device according to claim 1 or 2, wherein, The width of the charge storage film in the intermediate columnar portion in the direction intersecting the stacking direction is the largest in the portion other than the upper and lower ends of the intermediate columnar portion.

4. The semiconductor memory device according to claim 1 or 2, wherein, The thickness of the intermediate columnar portion in the stacking direction is less than twice the average film thickness between the outer surface of the semiconductor substrate in the intermediate columnar portion and the outer surface of the intermediate columnar portion.

5. The semiconductor memory device according to claim 1 or 2, wherein, The thickness of the intermediate columnar portion in the stacking direction is less than 30 nm.

6. The semiconductor memory device according to claim 1 or 2, wherein, The outer perimeter of the lower end of the intermediate columnar portion is greater than the outer perimeter of the upper end of the first columnar portion. The outer perimeter of the upper end of the intermediate columnar portion is greater than the outer perimeter of the lower end of the second columnar portion.

7. The semiconductor memory device according to claim 1 or 2, wherein, The outer perimeter of the lower end of the second columnar portion is shorter than the outer perimeter of the upper end of the first columnar portion.

8. A method for manufacturing a semiconductor memory device, comprising the following steps: The process of creating a first-layered precursor by alternately stacking sacrificial or conductive layers with insulating layers; The process of forming a first hole inside the first layered precursor; The process of forming sacrificial material in the first hole of the first laminated precursor; The process of laminating an intermediate insulating layer on the first laminated precursor; The process of forming an intermediate hole in the intermediate insulating layer; The process of forming sacrificial material in the intermediate hole of the intermediate insulating layer; The process of fabricating a second-layer precursor by alternately stacking a sacrificial layer or a conductive layer with an insulating layer on the intermediate insulating layer; The process of forming a second hole inside the second-layered precursor; The process of removing the sacrificial material formed in the first hole and the sacrificial material formed in the intermediate hole; as well as The process of sequentially forming a charge storage film, a semiconductor substrate, and a core on the inner wall surfaces of the first hole, the intermediate hole, and the second hole. In the method for manufacturing the semiconductor memory device, the thickness of the intermediate insulating layer is less than twice the average film thickness between the outer surface of the semiconductor substrate formed on the inner wall surface of the intermediate hole and the inner wall surface of the intermediate hole, in order to suppress the breakage of the semiconductor substrate in the intermediate columnar portion.

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