A high-stability metal oxide thin film transistor array substrate and a manufacturing method thereof

Abstract

The application provides a high-stability metal oxide thin film transistor array substrate, comprising at least two back channel metal oxide TFTs with different structures arranged on a substrate. The application also provides a preparation method of the high-stability metal oxide thin film transistor array substrate, comprising the following steps: S1, forming a first metal layer on the substrate to serve as a first gate or a driving circuit trace; and S2, forming a second metal layer on the first metal layer or on the same horizontal plane to serve as a second gate, wherein the first metal layer and the second metal layer are different in material or thickness. According to the application, at least two back channel metal oxide TFTs with different structures are arranged on the array substrate, so that the metal oxide TFTs are designed differently according to different working states of the metal oxide TFTs, and finally, the metal oxide TFTs can maintain the same Vth in different working states, thereby avoiding circuit failure.

Description

Technical Field

[0001] This invention relates to the field of panel technology, and in particular to a high-stability metal oxide thin-film transistor array substrate and its fabrication method. Background Technology

[0002] With the diversification of consumer market demands, AMOLED, Mini-LED, Micro-LED, VR devices, and other equipment are gradually becoming mainstream, and display technology is further developing towards higher color saturation, higher resolution, and higher refresh rates. Along with the development of display technology, higher demands are placed on the performance and stability of the film transistor devices driving the display panels. Therefore, metal oxide TFTs are favored due to their advantages such as low leakage current, high field-effect mobility, and large regional uniformity.

[0003] Metal-oxide-semiconductor (MTBF) TFT devices possess excellent electrical characteristics, but for high-end display devices, manufacturing stable and reliable thin-film transistor (TFT) devices remains a significant challenge. For example, to reduce bezel width in display panels, driving circuits are typically placed on both sides of the panel to replace traditional wiring and achieve a narrow bezel design. These driving circuits contain multiple sets of MTBF TFTs of different sizes, metal circuitry, and capacitors, commonly referred to as GIP (Gate Driver In Panel) or GOA (Gate Driver On Array). Alternatively, in active-matrix display panels, each pixel may have a voltage regulator circuit composed of multiple MTBF TFTs to ensure the current stability of the light-emitting device; this is called a voltage regulator circuit. To ensure the normal operation of these circuits, the characteristics of the MTBF TFTs must meet certain requirements. Specifically, the MTBF TFTs cannot have large threshold voltage (Vth) deviations or fluctuations in on / off current. Furthermore, the tolerance for device characteristic deviations varies considerably depending on the function of the MTBF TFT in the circuit. However, in actual panel operation, due to the different functions of the circuitry within the metal oxide TFT, the operating states of the devices vary significantly. Some devices may remain in an off state for extended periods, while others require frequent activation. Furthermore, devices operating under high voltage in certain circuits also need to have minimal Vth deviation. Given these differences in device operating pressure, even if the Vth of the metal oxide TFT devices are initially identical, after prolonged use or stress testing in harsh environments, differences in Vth offset will inevitably appear. If these differences exceed the operating range allowed by the driving circuit or voltage regulator circuit, display abnormalities will occur.

[0004] The discrepancy between the functional characteristics of the circuit and the actual operating state of the device leads to variations in electrical degradation, placing higher demands on the stability of metal-oxide-semiconductor (MEO) TFT devices. Current development strategies focus on improving overall stability; however, given the trend towards miniaturization of MEO TFTs driven by high resolution, the short-channel effect caused by reduced channel length makes it even more difficult to maintain stable device characteristics during long-term operation. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a high-stability metal oxide thin film transistor array substrate and a method for its fabrication. At least two back-channel metal oxide TFTs with different structures are disposed on the array substrate, thereby making differentiated designs for the different operating states of each metal oxide TFT, so that each metal oxide TFT can maintain Vth consistency under different operating states and avoid circuit failure.

[0006] The present invention is implemented as follows: a high-stability metal oxide thin film transistor array substrate, comprising at least two back channel metal oxide TFTs with different structures disposed on the substrate.

[0007] Furthermore, the gate metal of different back-channel metal oxide TFTs has different materials or thicknesses.

[0008] Furthermore, there are two different back-channel metal oxide TFTs, referred to as the first metal oxide TFT and the second metal oxide TFT;

[0009] The substrate is provided with a first metal layer, the first metal layer includes a first gate, and the first metal layer is a single layer of pure Mo, pure Ti or an alloy.

[0010] A second metal layer is provided above the first metal layer or at the same horizontal plane as the first metal layer. The second metal layer includes a second gate and adopts a stacked structure containing Al or Cu.

[0011] A first insulating layer is provided above the gate: when the second metal layer is located above the first metal layer, the first insulating layer is located above the second metal layer; when the first metal layer and the second metal layer are on the same horizontal plane, the first insulating layer is located above the first metal layer and the second metal layer.

[0012] An active layer is provided on the first insulating layer, the active layer including a first active layer and a second active layer, the first active layer corresponding to a first gate and the second active layer corresponding to a second gate; the first insulating layer also has a first through hole to expose the surface of the first metal layer or the second metal layer.

[0013] The active layer is provided with a third metal layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, and a second source and a second drain electrically connected to the second active layer; wherein, the third metal layer is electrically connected to the first metal layer or the second metal layer through the first via.

[0014] A second insulating layer is provided on the third metal layer;

[0015] Wherein, the film structure corresponding to the first gate is the first metal oxide TFT;

[0016] The film structure corresponding to the second gate is the second metal oxide TFT.

[0017] Furthermore, the alloy is MoTi, MoAl, MoAlTi, MoNb, or MoTa.

[0018] Furthermore, the stacked structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti.

[0019] Furthermore, when the first metal layer and the second metal layer are on the same horizontal plane, that is, when the first gate and the second gate are on the same horizontal plane,

[0020] The first gate is made of pure Mo or a Mo-containing alloy material and is prepared by wet etching or dry etching.

[0021] The second gate adopts a Ti-containing stacked structure and is prepared by dry etching; wherein the Ti-containing stacked structure is Al / Ti or Ti / Al / Ti.

[0022] Furthermore, the thickness range of the gate metal for each back-channel metal-oxide TFT is as follows:

[0023] This invention also provides a method for fabricating a high-stability metal oxide thin-film transistor array substrate, comprising the following steps:

[0024] S1. A first metal layer is formed on the substrate to serve as the first gate or driving circuit trace.

[0025] S2. A second metal layer is formed on the first metal layer or on the same horizontal plane to serve as the second gate. The first metal layer and the second metal layer are made of different materials or have different thicknesses.

[0026] S3. A first insulating layer is formed on the gate as a gate insulating layer; wherein, when the second metal layer is located on the first metal layer, the first insulating layer is located on the second metal layer; when the first metal layer and the second metal layer are on the same horizontal plane, the first insulating layer is located on the first metal layer and the second metal layer.

[0027] S4. An active layer is formed on the first insulating layer. The active layer includes a first active layer and a second active layer. The first active layer corresponds to the first gate, and the second active layer corresponds to the second gate.

[0028] After the active layer is fabricated, a first through-hole is made in the first insulating layer to expose the surface of the first metal layer or the second metal layer.

[0029] S5. A third metal layer is formed on the active layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, and a second source and a second drain electrically connected to the second active layer; wherein the third metal layer is electrically connected to the first metal layer or the second metal layer through the first via.

[0030] S6. A second insulating layer is formed on top of the third metal as a passivation layer, and the material is the same as that of the first insulating layer.

[0031] Furthermore, the first metal layer is a single layer of pure Mo, pure Ti, or an alloy;

[0032] The second metal layer adopts a stacked structure containing Al or Cu.

[0033] Furthermore, the first insulating layer is made of an inorganic oxide or an insulating compound; the active layer is made of a metal oxide semiconductor material.

[0034] This invention offers the following advantages: It provides a high-stability metal-oxide-slim-film transistor (MTTFT) array substrate, comprising at least two back-channel MTTFTs with different structures disposed on the substrate. The invention also provides a method for fabricating this high-stability MTTFT array substrate, comprising the following steps: S1, forming a first metal layer on the substrate as a first gate or driving circuit trace; S2, forming a second metal layer on the first metal layer or on the same horizontal plane as a second gate, wherein the first and second metal layers are of different materials or thicknesses. By disposing of at least two different back-channel MTTFTs on the array substrate, this invention allows for differentiated design for the different operating states of each MTTFT, ultimately ensuring that each MTTFT maintains consistent Vth under different operating states, thus preventing circuit failure. Attached Figure Description

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0036] Figure 1 This is a schematic diagram of the array substrate of the present invention.

[0037] Figure 2 This is a schematic diagram of the film layer structure of the array substrate of the present invention.

[0038] Figure 3 This is a flowchart of the preparation method of the present invention.

[0039] Explanation of reference numerals in the attached figures:

[0040] substrate1;

[0041] First metal layer 2, first gate 21, driving circuit trace 22;

[0042] Second metal layer 3, second gate 31;

[0043] First insulating layer 4, first through hole 41;

[0044] Active layer 5, first active layer 51, second active layer 52;

[0045] Third metal layer 6, first source 61, first drain 62, second source 63, second drain 64, panel data line 65;

[0046] Second insulating layer 7;

[0047] First metal oxide TFT100;

[0048] Second metal oxide TFT200;

[0049] Metal trace area / capacitor area 300;

[0050] Other areas: 400. Detailed Implementation

[0051] In the description of the invention, it should be understood that the description indicating the orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the purpose of facilitating the description of the invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of the invention.

[0052] In the description of the invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the invention based on the specific circumstances.

[0053] The inventive concept of this invention is as follows:

[0054] At least two different back-channel metal oxide TFTs with different structures are set on the array substrate, which can correspond to at least two operating states. In practical use, differentiated designs can be made for the different operating states of each metal oxide TFT, so that each metal oxide TFT can maintain Vth consistency under different operating states and avoid circuit failure.

[0055] Different metal oxide TFTs have different gate metal materials or thicknesses, which results in different back channel structures.

[0056] Please see Figures 1 to 3 As shown.

[0057] A high-stability metal oxide thin-film transistor array substrate includes at least two back-channel metal oxide TFTs with different structures disposed on a substrate 1, which can correspond to at least two operating states. In practical use, differentiated designs can be made for the different operating states of each metal oxide TFT, so that each metal oxide TFT can maintain Vth consistency under different operating states and avoid circuit failure.

[0058] In a preferred embodiment, the gate metal of each back-channel metal oxide TFT with different structures has different materials or thicknesses. By changing the material or thickness of the gate metal, differentiated designs can be implemented for different operating states, thereby maintaining Vth consistency and avoiding circuit failure. In specific implementations, the gate metal of each back-channel metal oxide TFT with different structures can have different materials, different thicknesses, or both, which broadens the range of choices for differentiated designs.

[0059] Gate metals need to possess good conductivity, good contact with the gate insulating layer, and a similar coefficient of thermal expansion. Metals such as Al and Cu have low impedance and are good conductors, but their coefficients of thermal expansion differ significantly from typical gate insulating layer materials like silicon oxide and silicon nitride. After high-temperature processing, the threshold voltage of metal oxide TFTs with different channel aspect ratios (W / L) is not easily kept consistent. Prolonged use or environmental stress testing will cause the TFT to deteriorate further. The coefficient of thermal expansion of Mo is close to that of SiOx and SiNx, which can effectively overcome the Vth deviation of devices with different W / L ratios. However, its relatively high impedance can easily lead to increased panel power consumption. Therefore, in practical implementation, a more suitable gate metal should be selected according to different operating states to maintain a consistent Vth and avoid circuit failure.

[0060] In a preferred embodiment, there are two back-channel metal oxide TFTs with different structures, referred to as the first metal oxide TFT100 and the second metal oxide TFT200, corresponding to two different operating states. Of course, in specific implementations, it is not limited to this. Different metal oxide TFTs can be set according to various different operating states to achieve differentiated design and maintain Vth consistency.

[0061] The substrate 1 is provided with a first metal layer 2, which includes a first gate 21. The first metal layer 2 is made of a single layer of pure Mo, pure Ti or alloy, and is suitable for devices with large channel width in the driving circuit. It can adjust the Vth deviation between devices with different channel aspect ratios (W / L).

[0062] A second metal layer 3 is disposed above or at the same horizontal plane as the first metal layer 2. The second metal layer 3 includes a second gate 31. The second metal layer 3 adopts a stacked structure containing Al or Cu (also known as a sandwich structure). Al, Cu and other metals have low impedance and are good conductive materials. However, their coefficients of thermal expansion differ significantly from those of common gate insulating materials such as silicon oxide and silicon nitride. After high-temperature processing, the threshold voltage of metal oxide TFTs with different channel aspect ratios (W / L) is not easy to remain consistent. Long-term use or environmental stress testing will cause the TFT to deteriorate further. Therefore, the second metal oxide TFT is suitable for devices with small channel widths or for operating conditions where long-term use is not required.

[0063] A first insulating layer 4 is provided above the gate: when the second metal layer 3 is located above the first metal layer 2, the first insulating layer 4 is located above the second metal layer 3; when the first metal layer 2 and the second metal layer 3 are on the same horizontal plane, the first insulating layer 4 is located above the first metal layer 2 and the second metal layer 3.

[0064] An active layer 5 is provided on the first insulating layer 4. The active layer 5 includes a first active layer 51 and a second active layer 52. The first active layer 51 corresponds to the first gate 21, and the second active layer 52 corresponds to the second gate 31. The first insulating layer 4 also has a first through hole 41 to expose the surface of the first metal layer 2 or the second metal layer 3.

[0065] The active layer 5 is provided with a third metal layer 6, which includes a first source 61 and a first drain 62 electrically connected to the first active layer 51, and a second source 63 and a second drain 64 electrically connected to the second active layer 52; wherein the third metal layer 6 is electrically connected to the first metal layer 2 or the second metal layer 3 through the first through-hole 41.

[0066] The third metal layer 6 is provided with a second insulating layer 7;

[0067] Wherein, the film structure corresponding to the first gate 21 is the first metal oxide TFT100;

[0068] The film structure corresponding to the second gate 31 is the second metal oxide TFT200.

[0069] The alloy is MoTi, MoAl, MoAlTi, MoNb, or MoTa, but is not limited to these.

[0070] The stacked structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti, but is not limited to these.

[0071] When the first metal layer 2 and the second metal layer 3 are on the same horizontal plane, that is, when the first gate 21 and the second gate 31 are on the same horizontal plane,

[0072] The first gate 21 is made of pure Mo or a Mo-containing alloy material and is prepared by wet etching or dry etching.

[0073] The second gate 31 adopts a Ti-containing stacked structure and is prepared by dry etching; wherein the Ti-containing stacked structure is Al / Ti or Ti / Al / Ti.

[0074] The thickness range of the gate metal for each back-channel metal-oxide TFT is as follows:

[0075] This invention also provides a method for fabricating a high-stability metal oxide thin-film transistor array substrate, comprising the following steps:

[0076] S1. A first metal layer 2 is formed on the substrate 1 to serve as the first gate 21 or the driving circuit trace 22. The first metal layer 2 can be one or more metals with excellent conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten, or an alloy. Preferably, pure Mo, pure Ti, or an alloy can be used as the second metal layer.

[0077] S2. A second metal layer 3 is formed on the first metal layer 2 or on the same horizontal plane to serve as the second gate 31. The first metal layer 2 and the second metal layer 3 have different materials or thicknesses. The second metal layer 3 can be made of the same material as the first metal layer 2. At this time, the gate metal thicknesses of the two layers must be different, otherwise the purpose of differentiated design cannot be achieved.

[0078] Preferably, the second metal layer 3 adopts a stacked structure containing Al or Cu.

[0079] The second metal layer 2 can use a stacked structure such as Ti / Al / Ti, Al / Ti, Al / Mo, Mo / Al / Mo, etc., but is not limited to this;

[0080] In addition, when the first metal layer 2 and the second metal layer 3 are on the same horizontal plane, in this fabrication process, the first metal layer 2 and the second metal layer 3 are continuously formed into films. The first gate 21, the second gate 31, and the driving circuit are fabricated by utilizing the grayscale photomask and the difference in etching characteristics of different metal materials. At this time, the first gate 21 is composed of the first metal layer 2 and the second metal layer 3. The driving signal circuit can be composed of only the first metal layer 2 or the second metal layer 3, or it can be a double metal superposition.

[0081] S3. A first insulating layer 4 is formed on the gate as a gate insulating layer; wherein, when the second metal layer 3 is located on the first metal layer 2, the first insulating layer 4 is located on the second metal layer 3; when the first metal layer 2 and the second metal layer 3 are on the same horizontal plane, the first insulating layer 4 is located on the first metal layer 2 and the second metal layer 3; preferably, the material of the first insulating layer 4 is an inorganic oxide or an insulating compound, such as SiOx, SiNx, silicon oxynitride, titanium oxide, aluminum oxide, etc., in single or multiple layers, but not limited to these.

[0082] S4. An active layer 5 is formed on the first insulating layer 4. The active layer 5 includes a first active layer 51 and a second active layer 52. The first active layer 51 corresponds to the first gate 21, and the second active layer 52 corresponds to the second gate 31. Preferably, the active layer is made of a metal oxide semiconductor material, such as ZnO, IGZO, IGZTO, ITZO, Pr-IZO, etc., but not limited to these.

[0083] After the active layer 5 is fabricated, a first through hole 41 is made in the first insulating layer 4 to expose the surface of the first metal layer 2 or the second metal layer 3; that is, in a specific implementation, after patterning the active layer 5, a photomask is further used to make a first through hole 41 in the first insulating layer 4 to expose the surface of the first metal layer 2 or the second metal layer 3, so as to achieve the effect of signal connection.

[0084] S5. A third metal layer 6 is formed on the active layer 5. The third metal layer 6 includes a first source 61 and a first drain 62 electrically connected to the first active layer 51, and a second source 63 and a second drain 64 electrically connected to the second active layer 52. The third metal layer 6 is electrically connected to the first metal layer 2 or the second metal layer 3 through the first via 41. Preferably, the process and material selection of the third metal layer 6 are the same as those of the first metal layer 2. The third metal layer 6 can be designed as a touch sensing signal line, a common electrode signal line, a TFT signal input source / drain, a panel data line 65, etc., depending on the circuit design.

[0085] S6. A second insulating layer 7 is formed on the third metal 6 as a passivation layer. The material selection is the same as that of the first insulating layer, such as single or multiple layers of SiOx, SiNx, aluminum oxide, titanium oxide, etc.

[0086] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A high-stability metal oxide thin-film transistor array substrate, characterized in that: Includes back-channel metal oxide TFTs with at least two different structures disposed on a substrate; The gate metal of different back-channel metal oxide TFTs has different materials and / or thicknesses; There are two different back-channel metal oxide TFTs, referred to as the first metal oxide TFT and the second metal oxide TFT; The substrate is provided with a first metal layer, the first metal layer includes a first gate, and the first metal layer is a single layer of pure Mo, pure Ti or an alloy. A second metal layer is provided above the first metal layer or on the same horizontal plane as the first metal layer. The second metal layer includes a second gate and adopts a stacked structure containing Al or Cu. A first insulating layer is provided above the gate: when the second metal layer is located above the first metal layer, the first insulating layer is located above the second metal layer; When the first metal layer and the second metal layer are on the same horizontal plane, the first insulating layer is located above the first metal layer and the second metal layer. An active layer is provided on the first insulating layer, the active layer including a first active layer and a second active layer, the first active layer corresponding to a first gate and the second active layer corresponding to a second gate; the first insulating layer also has a first through hole to expose the surface of the first metal layer or the second metal layer. The active layer is provided with a third metal layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, and a second source and a second drain electrically connected to the second active layer; wherein, the third metal layer is electrically connected to the first metal layer or the second metal layer through the first via. A second insulating layer is provided on the third metal layer; Wherein, the film structure corresponding to the first gate is the first metal oxide TFT; The film structure corresponding to the second gate is the second metal oxide TFT.

2. The high-stability metal oxide thin-film transistor array substrate according to claim 1, characterized in that: The alloy is MoTi, MoAl, MoAlTi, MoNb, or MoTa.

3. A high-stability metal oxide thin-film transistor array substrate according to claim 1 or 2, characterized in that: The stacked structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti.

4. A high-stability metal oxide thin-film transistor array substrate according to claim 1 or 2, characterized in that: When the first metal layer and the second metal layer are on the same horizontal plane, that is, when the first gate and the second gate are on the same horizontal plane; at this time, The first gate is made of pure Mo or a Mo-containing alloy material and is prepared by wet etching or dry etching. The second gate adopts a Ti-containing stacked structure and is prepared by dry etching; wherein the Ti-containing stacked structure is Al / Ti or Ti / Al / Ti.

5. The high-stability metal oxide thin-film transistor array substrate according to claim 1, characterized in that: The thickness of the gate metal in each back-channel metal oxide TFT is selected in the range of 50 Å to 6000 Å.

6. A method for fabricating a high-stability metal oxide thin-film transistor array substrate, characterized in that: Includes the following steps: S1. A first metal layer is formed on the substrate to serve as the first gate or driving circuit trace. S2. A second metal layer is formed on the first metal layer or on the same horizontal plane to serve as the second gate. The first metal layer and the second metal layer are made of different materials or have different thicknesses. S3. A first insulating layer is formed on the gate as a gate insulating layer; wherein, when the second metal layer is located on the first metal layer, the first insulating layer is located on the second metal layer; when the first metal layer and the second metal layer are on the same horizontal plane, the first insulating layer is located on the first metal layer and the second metal layer. S4. An active layer is formed on the first insulating layer. The active layer includes a first active layer and a second active layer. The first active layer corresponds to the first gate, and the second active layer corresponds to the second gate. After the active layer is fabricated, a first through-hole is made in the first insulating layer to expose the surface of the first metal layer or the second metal layer. S5. A third metal layer is formed on the active layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, and a second source and a second drain electrically connected to the second active layer; wherein the third metal layer is electrically connected to the first metal layer or the second metal layer through the first via. S6. A second insulating layer is formed on top of the third metal layer as a passivation layer, and the material is the same as that of the first insulating layer.

7. The method for fabricating a high-stability metal oxide thin-film transistor array substrate according to claim 6, characterized in that: The first metal layer is a single layer of pure Mo, pure Ti, or an alloy; The second metal layer adopts a stacked structure containing Al or Cu.

8. A method for fabricating a high-stability metal oxide thin-film transistor array substrate according to claim 6 or 7, characterized in that: The first insulating layer is made of an insulating compound; the active layer is made of a metal oxide semiconductor material.

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