A power semiconductor element having high reliability and a manufacturing method thereof

Abstract

The application relates to the technical field of semiconductors, and particularly discloses a power semiconductor element with high reliability, wherein the N-type drift region epitaxial silicon layer with different epitaxial concentrations is arranged below the P-type base layer, the lateral epitaxial concentration of the N-type drift region epitaxial silicon layer is increased in a stepped mode from the trench downwards, the concentration of the overall N-drift region epitaxial silicon layer is improved, the size of the depletion region is increased, the electric field intensity becomes slow, the generation rate of electron-hole impact is reduced, the quality of the oxide layer below the trench is ensured, and the reliability of the power semiconductor element is improved. Under the condition of maintaining the same epitaxial dopant amount of the N-type drift region epitaxial silicon layer, only the doping design mode distribution is changed, so that the power semiconductor element can maintain low resistance and high current and can also maintain a relatively high breakdown voltage value, thereby improving the voltage resistance of the component while maintaining the existing low on-voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to the technical field classified under H01L, and more specifically to a power semiconductor device with high reliability and its manufacturing method. Background Technology

[0002] Since the development of discrete power semiconductors, various fields have developed structural designs to improve characteristics in order to achieve mass-producible high-power, low-on-resistance specifications and improve the reliability of power components. Patent CN100554016 discloses a power semiconductor component with light recovery characteristics, which can prevent damage from fast recovery phenomena to some extent; however, its voltage withstand capability is limited. The document "A Novel 800V Multi-RESURFLDMOS Utilizing a Linear RESURF Substrate" discloses a novel 800V multi-RESURF lateral double-diffused MOS (LDMOS) transistor and has successfully performed simulations. The proposed RESURFFLDMOS has low on-resistance and a breakdown voltage exceeding 800V. This document focuses on designing and improving the P-substrate, but does not improve reliability. Patent US 10,763,353B2 discloses a MOSFET semiconductor device that reduces electron-hole pair impacts by using P+ ion arrangement. Patent application CN 112271208 A discloses a silicon carbide single-gate dual-channel thyristor transport IGBT and its manufacturing method. In this patent, the thyristor is activated by a dual-channel gate through a parasitic P-type collector layer / N-type drift region / P-type base floating layer / N-type carrier layer. The PNP base acts as a hole blocking layer to increase the hole concentration at the top, and the NPN collector is used to extract electrons from the drift region to reduce the hole concentration at the bottom. This technical solution provides a semiconductor device with lower turn-off loss and turn-off time; however, the reliability of this semiconductor device is not high. In an IGBT, when a predetermined voltage is applied between the gate and emitter, a channel is formed along the trench in the p-type base layer, opening the connection between the collector and emitter and conducting current. At this time, the N-drift region below the base region generates a high electric field, affecting the reliability cycle of the device operation. The high electron-hole pair impact rate reduces the reliability of the gate oxide layer. The existing literature, "A convex p-based SiC trench MOSFET structure for low oxide field and enhanced switching performance," shows that a high electric field is generated below the trench. The low quality of the SiC oxide layer in the MOSFET structure reduces the reliability period of the MOSFET structure. However, the literature does not provide any solutions for reducing the high electric field or improving the reliability of the MOSFET structure.

[0003] There is an urgent need for a power semiconductor device that reduces the impact rate of electron holes and improves reliability. Summary of the Invention

[0004] To address the aforementioned issues, a high-reliability power semiconductor device is provided, comprising, from bottom to top, a collector layer, a P+ type silicon substrate layer, an N+ type buffer epitaxial silicon layer, an N- type drift region epitaxial silicon layer, an N-type field cutoff layer, a P-type base layer, a trench penetrating the N-type drift region epitaxial silicon layer, the N-type field cutoff layer, and the P-type base layer, a gate insulating oxide layer surrounding the trench sidewalls and bottom, an N+ emitter region and a P+ emitter region located above the P-type base layer on both sides of the trench, a second insulating isolation layer located above the trench, and emitter layers located above the N+ emitter region and the P+ emitter region on both sides of the trench, respectively. The interior of the trench is a polycrystalline silicon gate electrode, and the lateral epitaxial concentration of the N-type drift region epitaxial silicon layer increases in an intermittent, stepwise manner from the trench downwards.

[0005] As a preferred technical solution, the N-type drift region epitaxial silicon layer includes x layers with the same lateral epitaxial concentration and N layers with increased lateral epitaxial concentration, wherein each layer with increased lateral epitaxial concentration has layers with the same lateral epitaxial concentration on both sides, where x≥1 and N≥1.

[0006] As a preferred technical solution, the epitaxial concentration of the layer with the same transverse epitaxial concentration is between 1 and 2.0 e. 13 cm -3 The thickness is 20-25nm.

[0007] As a preferred technical solution, the epitaxial concentration of the layer with the same transverse epitaxial concentration is 2.0e. 13 cm -3 The thickness is 20-25nm.

[0008] As a preferred technical solution, the N lateral epitaxial concentration increase layers, from the trench downwards, include N3 lateral epitaxial concentration increase layer, N2 lateral epitaxial concentration increase layer and N1 lateral epitaxial concentration increase layer, wherein the epitaxial concentration of the N2 lateral epitaxial concentration increase layer is greater than that of the N3 lateral epitaxial concentration increase layer, and the epitaxial concentration of the N1 lateral epitaxial concentration increase layer is greater than that of the N2 lateral epitaxial concentration increase layer.

[0009] As a preferred technical solution, the epitaxial concentration of the N3 lateral epitaxial concentration-increasing layer is 1.0-4.0e. 14 cm -3 The thickness is 0.5-2.0 nm, and the epitaxial concentration of the N2 lateral epitaxial layer is 5.0-9.0 e.g. 14 cm -3The thickness is 0.5-2.0 nm, and the epitaxial concentration of the N1 lateral epitaxial layer is 2.0-6.0 e.g. 15 cm -3 The thickness is between 0.5 and 2.0 nm.

[0010] As a preferred technical solution, the resistivity of the P+ type silicon substrate is 0.01-0.03 Ω·m.

[0011] As a preferred technical solution, the epitaxial concentration in the N+ type buffer epitaxial silicon layer is 10. 16 -10 17 cm -3 The thickness is 2-5um.

[0012] As a preferred technical solution, the second insulating layer is an insulating oxide layer.

[0013] A second aspect of the present invention provides a method for manufacturing the aforementioned high-reliability power semiconductor device, comprising at least the following steps:

[0014] (1) Prepare a P+ type silicon substrate, form an N+ type buffer epitaxial silicon layer on the P+ type silicon substrate, form an N- type drift region epitaxial silicon layer on the N+ type buffer epitaxial silicon layer, and form an N- type diffusion layer on the N- type drift region epitaxial silicon layer. The thickness of the N-type diffusion layer is 4-6 μm, and the phosphorus atom implantation amount in the N-type diffusion layer is 3e. 13 -5e 13 cm -2 The energy is 50-120 keV, the annealing temperature is 1100-1200℃, and the annealing time is 150-240 min;

[0015] (2) The N-type drift region epitaxial silicon layer is formed by stacking, and the lateral epitaxial concentration increases in an intermittent step manner from top to bottom;

[0016] (3) The thickness of the N-type diffusion layer is 4-6 μm. An ion implantation mask is placed on the N-type diffusion layer, and a P-type base layer ion implantation mask is used to implant boron atoms. The amount of boron atoms implanted is 3e. 13 -9e 13 cm- 2 The energy is 50-150 keV, the annealing temperature is 1000-1200℃, and the annealing time is 3-30 min, so as to form an N-type field stop layer and a P-type base layer.

[0017] (4) A trench is formed by etching that penetrates the epitaxial silicon layer, the N-type field stop layer and the P-type substrate in the N-type drift region;

[0018] (5) A sacrificial oxide layer is formed at the bottom and sidewalls of the trench, the thickness of which is 350-500 Å, to remove etching defects on the surface of the trench.

[0019] (6) Remove the sacrificial oxide layer, and then form a gate insulating oxide layer on the sidewalls and bottom of the trench, wherein the thickness of the gate insulating oxide layer is 100-150 μm;

[0020] (7) Deposit a doped polycrystalline silicon gate electrode inside the trench and etch to define the polycrystalline silicon gate;

[0021] (8) Phosphorus atoms are implanted into the P-type substrate near both sides of the trench to form N+ emitter regions, and boron atoms are implanted on both sides of the N+ emitter regions to form P+ emitter regions. The amount of phosphorus atoms implanted is 1e. 15 -5e 15 cm -2 The energy is 50-110 keV, and the amount of boron atoms implanted is 1e. 14 -1e 15 cm -2 The energy is 50-110 keV;

[0022] (9) A second insulating isolation layer is provided above the trench, the second insulating isolation layer extends to both sides of the trench and extends into the N+ emitter polar regions on both sides of the trench respectively;

[0023] (10) Finally, an emitter layer metal is covered on the P+ emitter region and the N+ emitter region, and a collector layer metal is covered on the lower part of the P-type silicon substrate to obtain the final product.

[0024] Beneficial Effects: This technical solution involves setting N-type drift region epitaxial silicon layers with different epitaxial concentrations below the P-type substrate. This results in a stepped, intermittent increase in the lateral epitaxial concentration of the N-type drift region epitaxial silicon layer from the trench downwards, enhancing the overall concentration of the N-type drift region epitaxial silicon layer. This concentration distribution places the high-concentration distribution away from the gate bottom, thus minimizing the electron hole impact rate at the bottom of the gate trench and significantly improving the device's operational reliability. By maintaining the same epitaxial doping dose in the N-type drift region epitaxial silicon layer and only changing the doping design distribution, the power semiconductor device can maintain both low resistance and high current, as well as a relatively high breakdown voltage. Therefore, it can improve the device's withstand voltage while maintaining its existing low on-state voltage. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a structural diagram of the power semiconductor device in step (1) of the preparation method in Example 1.

[0027] Figure 2 This is a simulation diagram of the internal epitaxial concentration distribution of the epitaxial silicon layer in the N-type drift region during step (2) of the preparation method in Example 1.

[0028] Figure 3 This is a structural diagram of the power semiconductor device in step (3) of the preparation method in Example 1.

[0029] Figure 4 This is a structural diagram of the power semiconductor device when step (7) of the preparation method in Example 1 is completed.

[0030] Figure 5 This is a structural diagram of the power semiconductor device when step (8) of the preparation method in Example 1 is completed.

[0031] Figure 6 This is a complete structural diagram of the power semiconductor device in Example 1.

[0032] Figure 7 for Figure 6 Electric field distribution performance test diagram of different N-type drift region epitaxial silicon layer concentrations below the emitter at points A-A1.

[0033] Figure 8 for Figure 6 Electric field distribution performance test diagram of different N-type drift region epitaxial silicon layer concentrations below the trench at B-B1.

[0034] Figure 9 for Figure 6 Electron hole impact quantity performance test diagram for different N-type drift region epitaxial silicon layer concentrations below the trench at B-B1.

[0035] Figure 10 The graph shows the gate voltage variation performance under different N-type drift region epitaxial silicon layer concentrations.

[0036] Figure 11 The graph shows the performance test results of on-voltage variation with different N-type drift region epitaxial silicon layer concentrations.

[0037] Figure 12The graph shows the performance test results of the collapse voltage variation under different N-type drift region epitaxial silicon layer concentrations.

[0038] Among them, 1-N-type diffusion layer, 2-N-type drift region epitaxial silicon layer, 3-N+ type buffer zone epitaxial silicon layer, 4-P+ type silicon substrate layer, 21-x1 layer, 22-N1 lateral epitaxial concentration increase layer, 23-x2 layer, 24-N2 lateral epitaxial concentration increase layer, 25-x3 layer, 26-N3 lateral epitaxial concentration increase layer, 27-x4 layer, 5-P-type base layer, 6-N-type field stop layer, 7-trench etched photomask layer, 8-trench, 9-polycrystalline silicon gate electrode, 10-P+ emitter region, 11-N+ emitter region, 12-emitter layer metal, 13-second insulating isolation layer, 14-collector layer metal, 15-gate insulating oxide layer. Detailed Implementation

[0039] Example 1

[0040] To address the aforementioned problems, this invention provides a high-reliability power semiconductor device, comprising, from bottom to top, a collector layer 14, a P+ type silicon substrate layer 4, an N+ type buffer epitaxial silicon layer 3, an N- type drift region epitaxial silicon layer 2, an N-type field cutoff layer 6, a P-type base layer 5, a trench 8 penetrating the N-type drift region epitaxial silicon layer 2, the N-type field cutoff layer 6, and the P-type base layer 5, a gate insulating oxide layer 15 surrounding the sidewalls and bottom of the trench 8, an N+ emitter region 11 and a P+ emitter region 10 located above the P-type base layer 5 on both sides of the trench 8, a second insulating isolation layer 13 located above the trench 8, and emitter layers 12 located above the N+ emitter region 11 and the P+ emitter region 10 on both sides of the trench 8, respectively. The interior of the trench 8 is a polycrystalline silicon gate electrode 9, and the lateral epitaxial concentration of the N-type drift region epitaxial silicon layer 2 increases in an intermittent stepwise manner from the trench downwards. The N-type drift region epitaxial silicon layer 2 includes four lateral epitaxial layers with the same concentration and three lateral epitaxial layers with increased concentration. The four lateral epitaxial layers with the same concentration are x1 layer 21, x2 layer 23, x3 layer 25, and x4 layer 27. Each lateral epitaxial layer with increased concentration is flanked by lateral epitaxial layers with the same concentration. The epitaxial concentration of each lateral epitaxial layer with the same concentration is 2.0e. 13 cm -3 The thickness is 20 nm. The three lateral epitaxial density enhancement layers, from the trench downwards, sequentially include an N3 lateral epitaxial density enhancement layer 26, an N2 lateral epitaxial density enhancement layer 24, and an N1 lateral epitaxial density enhancement layer 22. The epitaxial density of the N2 lateral epitaxial density enhancement layer 24 is greater than that of the N3 lateral epitaxial density enhancement layer 26, and the epitaxial density of the N1 lateral epitaxial density enhancement layer 22 is greater than that of the N2 lateral epitaxial density enhancement layer 24. The epitaxial density of the N3 lateral epitaxial density enhancement layer 26 is 2.0 e. 14 cm-3 The thickness is 1.0 nm, and the epitaxial concentration of layer 24, which has an increased N2 lateral epitaxial concentration, is 7.0 e.g. 14 cm -3 The thickness is 1.0 nm, and the epitaxial concentration of layer 22, which increases the transverse epitaxial concentration of N1, is 4.0 e.g. 15 cm -3 The thickness is 1.0 nm. The resistivity of the P+ type silicon substrate layer 4 is 0.01 Ω·m. The epitaxial concentration in the N+ type buffer epitaxial silicon layer 3 is 10. 16 cm -3 The thickness is 3 μm. The second insulating layer 13 is an insulating oxide layer.

[0041] The second aspect of this embodiment provides a method for manufacturing the aforementioned high-reliability power semiconductor device, comprising the following steps:

[0042] (1) As Figure 1 As shown, a P+ type silicon substrate 4 is prepared, an N+ type buffer epitaxial silicon layer 3 is formed on the P+ type silicon substrate 4, an N- type drift region epitaxial silicon layer 2 is formed on the N+ type buffer epitaxial silicon layer 3, and an N- type diffusion layer 1 is formed on the N- type drift region epitaxial silicon layer 2. The thickness of the N-type diffusion layer 1 is 5 μm, and the phosphorus atom implantation amount in the N-type diffusion layer 1 is 4e. 13 cm -2 The energy was 80 keV, the annealing temperature was 1100℃, and the annealing time was 200 min;

[0043] (2) Figure 2 As shown, the N-type drift region epitaxial silicon layer 2 is formed by stacking, with each stack having an epitaxial concentration of 2.0e. 13 cm -3 The x1 layer is 21 with a thickness of 20 nm and an epitaxial density of 4.0 e.g. 15 cm -3 A transverse epitaxial layer 22 with a thickness of 1.0 nm and an epitaxial concentration of 2.0 e 13 cm -3 The 23x2 layer is 20nm thick and has an epitaxial density of 7.0e. 14 cm -3 A layer 24 with increased N2 lateral epitaxial density, 1.0 nm thick, is constructed, with an epitaxial density of 2.0 e.g. 13 cm -3 The 25x3 layer has a thickness of 20nm and an epitaxial density of 2.0e. 14 cm -3 A transverse epitaxial layer 26 with a thickness of 1.0 nm and an epitaxial concentration of 2.0 eJ / L is constructed. 13 cm -3The result is a 20nm x 4 layer 27;

[0044] (3) Figure 3 As shown, the thickness of the N-type diffusion layer 1 is 5 μm. An ion-implanted photomask is placed on the N-type diffusion layer 1, and a P-type base layer ion-implanted photomask is used to implant boron atoms. The amount of boron atoms implanted is 6e. 13 cm- 2 The energy is 100 keV, the annealing temperature is 1100℃, and the annealing time is 10 min, so as to form an N-type field stop layer 6 and a P-type base layer 5.

[0045] (4) A trench is formed by etching through the epitaxial silicon layer 2, the N-type field stop layer 6 and the P-type base layer 5 in the N-type drift region;

[0046] (5) A sacrificial oxide layer with a thickness of 450 Å is formed at the bottom and sidewalls of the trench 8 to remove etching defects on the trench surface.

[0047] (6) Remove the sacrificial oxide layer, and then form a gate insulating oxide layer 15 on the sidewall and bottom of the trench 8. The thickness of the gate insulating oxide layer 15 is 100 μm.

[0048] (7) Figure 4 As shown, a doped polycrystalline silicon gate electrode 9 is deposited inside the trench 8, and the polycrystalline silicon gate is etched to define it.

[0049] (8) Figure 5 As shown, phosphorus atoms are implanted into the P-type base layer 5 near both sides of the trench to form N+ emitter regions 11, and boron atoms are implanted on both sides of the N+ emitter regions 11 to form P+ emitter regions 10. The amount of phosphorus atoms implanted is 3e. 15 cm -2 The energy is 80 keV, and the amount of boron atoms injected is 1e. 15 cm -2 The energy is 70 keV;

[0050] (9) A second insulating isolation layer 13 is provided above the trench. The second insulating isolation layer 13 extends to both sides of the trench and extends into the N+ emitter pole regions 11 on both sides of the trench. The material of the second insulating isolation layer is silicon dioxide.

[0051] (10) such as Figure 6 As shown, finally, emitter layer metal 12 is covered on P+ emitter region 10 and N+ emitter region 11, and collector layer metal 14 is covered on the lower part of P-type silicon substrate layer 4, thus obtaining the desired product.

[0052] in, Figure 7 for Figure 6Electric field distribution performance test diagram of different N-type drift region epitaxial silicon layer concentrations below the emitter at points A-A1. Figure 8 for Figure 6 Electric field distribution performance test diagram of different N-type drift region epitaxial silicon layer concentrations below the trench at B-B1. Figure 9 for Figure 6 Electron hole impact quantity performance test diagram for different N-type drift region epitaxial silicon layer concentrations below the trench at B-B1. Figure 10 The graph shows the gate voltage variation performance under different N-type drift region epitaxial silicon layer concentrations. Figure 11 The graph shows the performance test results of on-voltage variation with different N-type drift region epitaxial silicon layer concentrations. Figure 12 The graph shows the performance test results of the collapse voltage variation under different N-type drift region epitaxial silicon layer concentrations. Figure 7-12 All simulations were performed using SYNOPSYS TCAD simulation software, among which Figure 7-12 In this context, "Low N-drift doping" indicates that the epitaxial silicon layer concentration in the N-type drift region is uniform at 2.0 e.g. 13 cm -3 The performance testing of the power semiconductor device, where all other technical features are the same as those in this embodiment, shows that High N-drift doping represents a uniform N-type drift region epitaxial silicon layer concentration of 9.0 e.g. 13 cm -3 The performance test results of the power semiconductor device, whose other technical features are the same as those in this embodiment, are shown in the Step-wise N-drift doping diagram. As can be seen from the performance test diagrams above, the power semiconductor device in this embodiment increases the depletion region and slows down the electric field strength, reducing the electron hole impact generation rate and improving the reliability of the power semiconductor device.

Claims

1. A power semiconductor device with high reliability, characterized in that, From bottom to top, the structure includes a collector layer, a P+ type silicon substrate layer, an N+ type buffer zone epitaxial silicon layer, an N- type drift region epitaxial silicon layer, an N- type field stop layer, a P-type base layer, a trench penetrating the N-type drift region epitaxial silicon layer, the N-type field stop layer, and the P-type base layer, a gate insulating oxide layer surrounding the trench sidewalls and bottom, an N+ emitter region and a P+ emitter region located above the P-type base layer on both sides of the trench, a second insulating isolation layer located above the trench, and emitter layers located above the N+ emitter region and the P+ emitter region on both sides of the trench, respectively. The interior of the trench is a polycrystalline silicon gate electrode, and the lateral epitaxial concentration of the N-type drift region epitaxial silicon layer increases in an intermittent stepwise manner from the trench downwards. The N-type drift region epitaxial silicon layer comprises x layers with the same lateral epitaxial concentration and N layers with increasing lateral epitaxial concentration. Each layer with increasing lateral epitaxial concentration is flanked by layers with the same lateral epitaxial concentration, where x ≥ 1 and N ≥ 1. The epitaxial concentration of the layers with the same lateral epitaxial concentration is between 1 and 2.0 e. 13 cm -3 The thickness is 20-25nm.

2. The high-reliability power semiconductor device according to claim 1, characterized in that, The epitaxial concentration of the layer with the same transverse epitaxial concentration is 2.0e. 13 cm -3 The thickness is 20-25nm.

3. The high-reliability power semiconductor device according to claim 2, characterized in that, The N lateral epitaxial concentration increase layers, from the trench downwards, include N3 lateral epitaxial concentration increase layer, N2 lateral epitaxial concentration increase layer and N1 lateral epitaxial concentration increase layer. The epitaxial concentration of the N2 lateral epitaxial concentration increase layer is greater than that of the N3 lateral epitaxial concentration increase layer, and the epitaxial concentration of the N1 lateral epitaxial concentration increase layer is greater than that of the N2 lateral epitaxial concentration increase layer.

4. The high-reliability power semiconductor device according to claim 3, characterized in that, The epitaxial concentration of the N3 lateral epitaxial layer is 1.0-4.0 e. 14 cm -3 The thickness is 0.5-2.0 nm, and the epitaxial concentration of the N2 lateral epitaxial layer is 5.0-9.0 e. 14 cm -3 The thickness is 0.5-2.0 nm, and the epitaxial concentration of the N1 lateral epitaxial layer is 2.0-6.0 e 15 cm -3 The thickness is between 0.5 and 2.0 nm.

5. The high-reliability power semiconductor device according to claim 1, characterized in that, The resistivity of the P+ type silicon substrate is 0.01-0.03 Ω·m.

6. The high-reliability power semiconductor device according to claim 1, characterized in that, The epitaxial concentration in the N+ type buffer epitaxial silicon layer is 10. 16 -10 17 cm -3 The thickness is 2-5um.

7. The high-reliability power semiconductor device according to any one of claims 1-6, characterized in that, The second insulating layer is an insulating oxide layer.

8. A method for manufacturing a high-reliability power semiconductor device according to any one of claims 1-7, characterized in that, At least the following steps are included: (1) Prepare a P+ type silicon substrate, form an N+ type buffer epitaxial silicon layer on the P+ type silicon substrate, form an N- type drift region epitaxial silicon layer on the N+ type buffer epitaxial silicon layer, and form an N- type diffusion layer on the N- type drift region epitaxial silicon layer. The thickness of the N-type diffusion layer is 4-6 μm, and the phosphorus atom implantation amount in the N-type diffusion layer is 3e. 13 -5e 13 cm -2 The energy is 50-120 keV, the annealing temperature is 1100-1200℃, and the annealing time is 150-240 min; (2) The N-type drift region epitaxial silicon layer is formed by stacking, and the lateral epitaxial concentration increases in an intermittent step manner from top to bottom; (3) The thickness of the N-type diffusion layer is 4-6 μm. An ion implantation mask is set on the N-type diffusion layer, and a P-type base layer ion implantation mask is used to implant boron atoms. The amount of boron atoms implanted is 3e. 13 -9e 13 cm- 2 The energy is 50-150 keV, the annealing temperature is 1000-1200℃, and the annealing time is 3-30 min, so as to form an N-type field stop layer and a P-type base layer. (4) A trench is formed by etching that penetrates the epitaxial silicon layer, the N-type field stop layer and the P-type substrate of the N-type drift region; (5) A sacrificial oxide layer is formed at the bottom and sidewalls of the trench, the thickness of which is 350-500 Å, to remove etching defects on the surface of the trench; (6) Remove the sacrificial oxide layer, and then form a gate insulating oxide layer on the sidewalls and bottom of the trench, wherein the thickness of the gate insulating oxide layer is 100-150 μm; (7) Deposit a doped polycrystalline silicon gate electrode inside the trench and etch to define the polycrystalline silicon gate; (8) Phosphorus atoms are implanted into the P-type base layer near both sides of the trench to form N+ emitter regions, and boron atoms are implanted on both sides of the N+ emitter regions to form P+ emitter regions. The amount of phosphorus atoms implanted is 1e. 15 -5e 15 cm -2 The energy is 50-110 keV, and the amount of boron atoms implanted is 1e. 14 -1e 15 cm -2 The energy is 50-110 keV; (9) A second insulating isolation layer is provided above the trench, the second insulating isolation layer extends to both sides of the trench and extends into the N+ emitter pole regions on both sides of the trench respectively; (10) Finally, an emitter layer metal is covered on the P+ emitter region and the N+ emitter region, and a collector layer metal is covered on the lower part of the P-type silicon substrate to obtain the final product.

Images