Transistor source / drain regions and their formation methods

Abstract

This disclosure relates to source / drain regions of transistors and methods for forming the same. In an embodiment, a device includes: a nanostructure; and a source / drain region adjacent to a channel region of the nanostructure, the source / drain region comprising: a first epitaxial layer on the sidewalls of the nanostructure, the first epitaxial layer comprising a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising a germanium-containing semiconductor material and a p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer comprising a germanium-containing semiconductor material and a p-type dopant.

Description

Technical Field

[0001] This disclosure relates to the source / drain regions of a transistor and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a nanostructure; and a source / drain region adjacent to a channel region of the nanostructure, the source / drain region comprising: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer comprising a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer comprising the germanium-containing semiconductor material and the p-type dopant.

[0005] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a fin extending from a substrate; a nanostructure on the fin; and a source / drain region including: a liner layer comprising boron-doped silicon-germanium; a first seed layer between the liner layer and the nanostructure, the first seed layer comprising boron-doped silicon; and a second seed layer between the liner layer and the fin, the second seed layer comprising boron-doped silicon.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor device is provided, the method comprising: etching source / drain recesses in a nanostructure and a fin; growing a first epitaxial layer from the sidewalls of the nanostructure and the top surface of the fin in the source / drain recess; growing a second epitaxial layer from the first epitaxial layer using a growth process having a first bottom-up growth rate from the first epitaxial layer and a second bottom-up growth rate from the fin and the nanostructure, the first bottom-up growth rate being less than the second bottom-up growth rate; and growing a third epitaxial layer from the second epitaxial layer. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) in a three-dimensional view is shown according to some embodiments.

[0009] Figure 2-Figure 22C This is a view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Figure 23 This is a view of a nanoFET according to some other embodiments.

[0011] Figure 24 This is a view of a nanoFET according to some other embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document may use spatially relevant terms (e.g., "below," "below," "below," "above," "upper," etc.) to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0014] According to various embodiments, the source / drain regions for a p-type device are epitaxially grown together with a seed layer. The seed layer comprises a semiconductor material having a low bottom-up growth rate, allowing for the subsequent growth of a lightly doped epitaxial layer. Therefore, the volume available for the heavily doped epitaxial layer can be increased. Consequently, the resistance of the epitaxial source / drain regions 98 can be reduced, thereby improving device performance.

[0015] The embodiments are described in a specific context in which the die includes a nanoFET. However, various embodiments can be applied to dies that include other types of transistors (e.g., fin field-effect transistors, planar transistors, etc.) (instead of or in combination with nanoFETs).

[0016] Figure 1 Examples of nanoFETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1 This is a 3D view, in which some features of nanoFETs are omitted for clarity. NanoFETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), etc.

[0017] The nanoFET includes a nanostructure 66 (e.g., nanosheet, nanowire, etc.) on fins 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 66 serves as a channel region for the nanoFET. The nanostructure 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70 (e.g., shallow trench isolation (STI) regions) are disposed between adjacent fins 62, which may protrude above and between adjacent isolation regions 70. Although the isolation regions 70 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate, or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 62 is shown as being a single, continuous material with the substrate 50, the bottom portion of the fin 62 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 62 refers to the portion extending above and between adjacent isolation regions 70.

[0018] A gate dielectric 122 is located above the top surface of the fin 62 and surrounds the top surface, sidewalls, and bottom surface of the nanostructure 66. A gate electrode 124 is located above the gate dielectric 122 and surrounds the gate dielectric 122. Epitaxial source / drain regions 98 are disposed on the fin 62 and at opposite sidewalls of the gate dielectric 122 and the gate electrode 124. An interlayer dielectric (ILD) 104 is formed on the epitaxial source / drain regions 98. Source / drain contacts (described later) are formed through the ILD 104 to the epitaxial source / drain regions 98. The epitaxial source / drain regions 98 can be shared between various nanostructures 66 and fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for example, by merging epitaxial source / drain regions 98 through epitaxial growth, or by coupling epitaxial source / drain regions 98 using the same source / drain contact.

[0019] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section A-A' is along the longitudinal axis of fin 62 and in the direction of current flow between, for example, the epitaxial source / drain regions 98 of the nanoFET. Cross section B-B' is along the longitudinal axis of gate electrode 124 and in a direction perpendicular to, for example, the direction of current flow between, the epitaxial source / drain regions 98 of the nanoFET. Cross section C-C' is parallel to cross section B-B' and extends through the epitaxial source / drain regions 98 of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0020] Some embodiments discussed herein are described in the context of using nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs) or fin field-effect transistors (finFETs).

[0021] Figure 2-Figure 22C This is a view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2-6 It is a 3D view, showing the relationship with Figure 1 A similar 3D view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A It shows Figure 1 The reference cross section A-A' is shown in the figure. Figure 7B , Figure 8B , Figure 9B , Figure 11B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B and Figure 22B It shows Figure 1 The reference cross section B-B' is shown in the figure. Figure 7C , Figure 8C , Figure 9C , Figure 11C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C and Figure 22C It shows Figure 1 The reference cross section C-C' shown is illustrated.

[0022] exist Figure 2 The diagram provides a substrate 50 for forming a nano-FET. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof, etc.

[0023] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor or an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor or a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (shown without separation), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0024] The substrate 50 may be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities may be implanted into the substrate 50. The impurities may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain regions in the nano-FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the impurity concentration in the APT region may be 10... 18 cm -3 Up to 10 19 cm -3 Within the range.

[0025] A multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials may be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0026] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed, and the second semiconductor layer 56 is patterned to form channel regions for a nanoFET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity relative to the etching of the second semiconductor layer 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0027] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanoFET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanoFET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-x The first semiconductor material 54 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc., where x can be in the range of 0 to 1. The second semiconductor material 56 can have high etch selectivity relative to each other, allowing the first semiconductor layer 54 to be removed in the n-type region 50N without removing the second semiconductor layer 56, and the second semiconductor layer 56 to be removed in the p-type region 50P without removing the first semiconductor layer 54.

[0028] Each layer in the multilayer stack 52 can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, for example, in the range of 5 nm to 30 nm. In some embodiments, some layers in the multilayer stack 52 (e.g., the second semiconductor layer 56) are formed to be thinner than other layers in the multilayer stack 52 (e.g., the first semiconductor layer 54).

[0029] exist Figure 3In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fins 62 are semiconductor strips patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 respectively comprise the remainders of the first semiconductor layer 54 and the second semiconductor layer 56. The trenches can be patterned using any acceptable etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof). The etching can be anisotropic.

[0030] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0031] Fins 62 and nanostructures 64, 66 may each have a width in the range of 8 nm to 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) are wider or narrower than fins 62 and nanostructures 64, 66 in another region (e.g., p-type region 50P).

[0032] exist Figure 4 In this embodiment, an STI region 70 is formed on the substrate 50 and between adjacent fins 62. The STI region 70 is disposed around at least a portion of the fins 62 such that at least a portion of the nanostructures 64, 66 protrudes between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within the range of process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI region 70 separates features of adjacent devices.

[0033] The STI region 70 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In embodiments, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although the STI region 70 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Subsequently, a filler material, such as those previously described, can be formed on the liner.

[0034] A removal process is then applied to the insulating material to remove excess insulating material on top of the nanostructures 64, 66. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be used. In embodiments where the mask remains on the nanostructures 64, 66, the planarization process may expose the mask or remove the mask. After the planarization process, the insulating material and the top surface of the mask (if present) or nanostructures 64, 66 are coplanar (within the range of process variations). Therefore, the top surface of the mask (if present) or nanostructures 64, 66 is exposed through the insulating material. In the illustrated embodiment, no mask remains on the nanostructures 64, 66. The insulating material is then recessed to form the STI region 70. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 may have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof, as shown. The top surface of STI region 70 can be formed into a flat, raised, and / or recessed shape through appropriate etching. Any acceptable etching process can be used to recess the insulating material, such as a material-selective process for the insulating material (e.g., selectively etching the insulating material of STI region 70 at a faster rate compared to the materials of fins 62 and nanostructures 64, 66). For example, dilute hydrofluoric acid (dHF) can be used to perform oxide removal.

[0035] The previously described process is merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structures can include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structures, the epitaxially grown material can be in-situ doped during growth, which can avoid prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0036] Furthermore, suitable wells (not shown separately) can be formed in nanostructures 64, 66, fins 62, and / or substrate 50 by doping (e.g., with p-type or n-type impurities). The wells can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0037] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask (not shown separately), such as a photoresist. For example, a photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be at a ratio of 10... 13 cm -3 To about 10 14 cm -3 Phosphorus, arsenic, antimony, etc., are injected into the region at concentrations within a certain range. After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0038] After or before implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be in the form of 10 13 cm -3 To about 10 14 cm -3 Boron, boron fluoride, indium, etc., are implanted into the region at concentrations within a certain range. After implantation, the photoresist can be removed, for example, by any acceptable ashing process.

[0039] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments of epitaxial growth of fins 62 and / or nanostructures 64, 66, the grown material can be in-situ doped during growth, which avoids implantation, although in-situ doping and implantation doping can be used together.

[0040] exist Figure 5In this configuration, a dummy dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The dummy dielectric layer 72 can be formed of a dielectric material, such as silicon oxide, silicon nitride, combinations thereof, etc., which can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 can be deposited on the dummy dielectric layer 72 and then planarized, for example, by CMP. The dummy gate layer 74 can be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal, metal nitride, metal silicide, metal oxide, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 74 can be formed of one or more materials with high etch selectivity relative to the etching of insulating materials (e.g., STI region 70 and / or dummy dielectric layer 72). A mask layer 76 may be deposited over the dummy gate layer 74. The mask layer 76 may be formed of a dielectric material, such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and the STI region 70, such that the dummy dielectric layer 72 is over the STI region 70 and extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and the nanostructures 64, 66.

[0041] exist Figure 6 In this process, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 using any acceptable etching technique to form dummy gate 84. Optionally, the pattern of mask 86 can be further transferred to dummy dielectric layer 72 using any acceptable etching technique to form dummy dielectric 82. Dummy gate 84 covers portions of nanostructures 64, 66 that will be exposed in subsequent processing to form channel regions. Specifically, dummy gate 84 extends along portions of the second nanostructure 66 that will be patterned to form channel region 68. The pattern of mask 86 can be used to physically separate adjacent dummy gates 84. The longitudinal direction of dummy gate 84 can also be substantially perpendicular (within process variations) to the longitudinal direction of fin 62. Mask 86 can optionally be removed after patterning, for example, by any acceptable etching technique.

[0042] Figures 7A-22C Various additional steps in the manufacture of the embodiment device are shown. Figures 7A-9C , Figures 11A-11C and Figures 17A-22CFeatures of either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. Differences (if any) in the structure of the n-type region 50N and the p-type region 50P will be explained in the description of each figure.

[0043] exist Figures 7A-7C In this process, a gate spacer 88 is formed on the nanostructures 64 and 66, on the mask 86 (if present), on the exposed sidewalls of the dummy gate 84 and the dummy dielectric 82. The gate spacer 88 can be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc.). Other insulating materials formed by any acceptable process may be used. Any acceptable etching process (e.g., dry etching, wet etching, etc., or combinations thereof) can be performed to pattern the dielectric materials. The etching may be anisotropic. The dielectric materials, when etched, have portions remaining on the sidewalls of the dummy gate 84 (thus forming the gate spacer 88). One or more dielectric materials may also have portions remaining on the sidewalls of fins 62 and / or nanostructures 64, 66 during etching (thus forming fin spacers 90). After etching, fin spacers 90 (if present) and gate spacers 88 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0044] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for wells, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurity can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity previously described, and the p-type impurity can be any p-type impurity previously described. During implantation, the channel region 68 remains covered by the dummy gate 84, such that the channel region 68 remains substantially free of impurities implanted for forming the LDD region. The LDD region can have a value of 10. 15 cm -3 Up to 10 19 cm -3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0045] It should be noted that the previous disclosures have described the process for forming spacers and LDD regions in a general manner. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0046] exist Figures 8A-8CIn the illustrated embodiment, the source / drain recess 92 is formed within the nanostructures 64, 66. The source / drain recess 92 extends through the nanostructures 64, 66 and into the fin 62. The source / drain recess 92 may also extend into the substrate 50. In various embodiments, the source / drain recess 92 may extend to the top surface of the substrate 50 without etching the substrate 50; the fin 62 may be etched such that the bottom surface of the source / drain recess 92 is set below the top surface of the STI region 70; and so on. The source / drain recess 92 can be formed by etching the nanostructures 64, 66 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process used to form the source / drain recess 92, the gate spacer 88 and the dummy gate 84 jointly mask portions of the fin 62 and / or the nanostructures 64, 66. Each nanostructure 64, 66 can be etched using a single etching process, or multiple etching processes can be used to etch the nanostructures 64, 66. A timed etching process can be used to stop etching the source / drain recess 92 after it has reached the desired depth. The fin spacer 90 (if present) can be etched during or after etching the source / drain recess 92, thereby reducing the height of the fin spacer 90. The size of the source / drain region subsequently formed in the source / drain recess 92 can be controlled by adjusting the height of the fin spacer 90.

[0047] exist Figures 9A-9C In this process, internal spacers 96 are formed on the sidewalls of the remaining portion of the first nanostructure 64 (e.g., those sidewalls exposed by the source / drain recesses 92). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recesses 92, and the first nanostructure 64 will subsequently be replaced by a corresponding gate structure. The internal spacers 96 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for subsequent removal of the first nanostructure 64).

[0048] As an example of forming the internal spacer 96, the source / drain recess 92 can extend laterally. Specifically, the portion of the sidewall of the first nanostructure 64 exposed by the source / drain recess 92 can be recessed. Although the sidewall of the first nanostructure 64 is shown as straight, the sidewall can be concave or convex. The sidewall can be recessed by any acceptable etching process, such as a process selective for the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate relative to the material of the second nanostructure 66). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF). In some embodiments, the same etching process can be performed continuously to form the source / drain recess 92 and to recess the sidewall of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material can be silicon nitride, silicon carbonitride, or silicon oxycarbonitride, although any suitable material can be used, such as a low-k dielectric material (e.g., a dielectric material with a k value less than about 3.5). The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching (e.g., RIE, NBE, etc.). Although the outer wall of the internal spacer 96 is shown as flush with the sidewall of the gate spacer 88, the outer wall of the internal spacer 96 may extend beyond the sidewall of the gate spacer 88, or be recessed relative to the sidewall of the gate spacer 88. In other words, the internal spacer 96 may partially fill, fully fill, or overfill the sidewall recess. Furthermore, although the outer wall of the internal spacer 96 is shown as concave, the outer wall of the internal spacer 96 may be straight or convex.

[0049] In some embodiments, the width of the gate spacer 88 is reduced, for example by one or more etching processes used to form the inner spacer 96. Furthermore, the sidewalls of the second nanostructure 66 can be etched by one or more etching processes used to form the inner spacer 96. In some embodiments, at this stage of processing, the sidewalls of the second nanostructure 66 are rounded convex sidewalls.

[0050] After the source / drain recess 92 and the internal spacer 96 are formed, the source / drain recess 92 extending into the fin 62 can have a variety of bottom types. Figures 10A-10C It shows Figure 9A Different bottom types in region 50B. For example... Figure 10A As shown, the bottom of the source / drain recess 92 extending into the fin 62 can be a shallowly rounded concave bottom. For example... Figure 10B As shown, the bottom of the source / drain recess 92 extending into the fin 62 can be a deep rounded concave bottom. Figure 10B The deep rounded concave bottom shown is larger than Figure 10A The shallow rounded concave bottom shown extends further into the fin 62. In some embodiments, the shallow rounded concave bottom has a depth D1 in the range of 0 nm to 3 nm, and the deep rounded concave bottom has a depth D2 in the range of 3 nm to 5 nm. Figure 10C As shown, the bottom of the source / drain recess 92 extending into fin 62 can be a polygonal concave bottom. For Figure 10A The embodiments illustrate subsequent processing steps, although those processing steps can be performed for any embodiment.

[0051] exist Figures 11A-11C In this embodiment, epitaxial source / drain regions 98 are formed in source / drain recesses 92. The epitaxial source / drain regions 98 are formed in the source / drain recesses 92 such that each dummy gate 84 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 88 and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 and the first nanostructure 64 by appropriate lateral distances, such that the epitaxial source / drain regions 98 are not short-circuited with the gate subsequently formed in the resulting nanoFET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel regions 68, thereby improving performance.

[0052] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 98 in the n-type region 50N is epitaxially grown in the source / drain recess 92 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type device. For example, if the second nanostructure 66 is silicon, the epitaxial source / drain region 98 in the n-type region 50N can include a material on which tensile strain is applied to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N can be referred to as the "n-type source / drain region". The epitaxial source / drain region 98 in the n-type region 50N can have surfaces rising from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have small facets.

[0053] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 98 in the p-type region 50P is epitaxially grown in the source / drain recess 92 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type device. For example, if the second nanostructure 66 is silicon, the epitaxial source / drain region 98 in the p-type region 50P can include a material on which compressive strain is applied to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P can be referred to as the "p-type source / drain region". The epitaxial source / drain region 98 in the p-type region 50P can have surfaces rising from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have small facets.

[0054] Epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The source / drain regions can have a [value missing] 10 [value missing] 19 cm -3 Up to 10 21 cm -3 The impurity concentration is within the range specified. The n-type and / or p-type impurities in the source / drain regions can be any impurities previously described. In some embodiments, the epitaxial source / drain regions 98 can be in-situ doped during growth.

[0055] As a result of the epitaxial process used to form the epitaxial source / drain regions 98, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge, such as... Figure 11C As shown. In some embodiments, adjacent epitaxial source / drain regions 98 remain separated after the epitaxial process is completed (not shown separately). In the illustrated embodiment, the spacer etching for forming the gate spacer 88 is adjusted to further form fin spacers 90 on the sidewalls of the fins 62 and / or nanostructures 64, 66. The fin spacers 90 are formed to cover portions of the sidewalls of the fins 62 and / or nanostructures 64, 66 extending above the STI region 70, thereby preventing epitaxial growth. In another embodiment, the spacer etching for forming the gate spacer 88 is adjusted not to form fin spacers, thereby allowing the epitaxial source / drain regions 98 to extend to the surface of the STI region 70.

[0056] The epitaxial source / drain region 98 includes multiple layers of semiconductor material. Specifically, each epitaxial source / drain region 98 includes a seed layer 98A, a liner layer 98B, and a main layer 98C (or more generally, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer). Other epitaxial layers may be used for the epitaxial source / drain region 98. The seed layer 98A is grown on the surface of the semiconductor features exposed in the source / drain recess 92 (e.g., the surface of the fin 62 and the second nanostructure 66). The liner layer 98B is grown on the seed layer 98A. The main layer 98C is grown on the liner layer 98B. Each of the seed layer 98A, the liner layer 98B, and the main layer 98C may be formed of different semiconductor materials and may be doped (e.g., with p-type or n-type impurities) to different impurity concentrations. In some embodiments, the liner layer 98B has a lower impurity concentration than the main layer 98C. Forming a liner layer 98B with a lower impurity concentration than the main layer 98C can increase adhesion in the source / drain recess 92. In some embodiments, layers 98A, 98B, and 98C in the p-type region 50P each include the same p-type impurity (e.g., boron), and layers 98A, 98B, and 98C in the n-type region 50N each include the same n-type impurity (e.g., phosphorus).

[0057] In some embodiments, the liner layer 98B and the main layer 98C in the p-type region 50P are formed of boron-doped silicon-germanium, which has a relatively large bottom-up growth rate relative to silicon. As described above, the second nanostructure 66 and the fin 62 can be formed of silicon. According to various embodiments, a seed layer 98A is grown from the fin 62 and the second nanostructure 66, and the liner layer 98B is then grown from the seed layer 98A. The seed layer 98A comprises a material such that the material of the liner layer 98B (e.g., boron-doped silicon-germanium) has a relatively low bottom-up growth rate relative to that material. In some embodiments, the seed layer 98A in the p-type region 50P is formed of boron-doped silicon. By growing the liner layer 98B from the seed layer 98A (instead of from the fin 62), the bottom-up growth rate of the liner layer 98B is reduced, and therefore the thickness of the liner layer 98B at the bottom of the source / drain recess 92 (e.g., the portion of the source / drain recess 92 on the fin 62) can be reduced. This increases the available volume for the master layer 98C in the source / drain recess 92. The master layer 98C is a highly doped epitaxial layer with a higher impurity concentration than the liner layer 98B, and increasing the volume of the master layer 98C helps reduce the resistance of the epitaxial source / drain region 98, thereby improving device performance. Furthermore, the material of the seed layer 98A can help reduce the diffusion of p-type dopants from the master layer 98C into the second nanostructure 66 or fin 62 during subsequent processing (e.g., including thermal drive-in steps). Therefore, dopant diffusion into the channel region 68 can be reduced, thereby lowering the resistance of the channel region 68 and improving device performance.

[0058] The semiconductor material of the seed layer 98A in the p-type region 50P is different from one or more semiconductor materials of the liner layer 98B and the main layer 98C in the p-type region 50P. The liner layer 98B and the main layer 98C may be formed of the same semiconductor material or different semiconductor materials. In some embodiments, the seed layer 98A is formed of a doped germanium-free semiconductor material (e.g., boron-doped silicon), and the liner layer 98B and the main layer 98C are formed of a doped germanium-containing semiconductor material (e.g., boron-doped silicon-germanium). The germanium concentration of the seed layer 98A (e.g., zero) is less than the germanium concentration of the liner layer 98B and the main layer 98C (e.g., non-zero).

[0059] Figures 12-16 The process for forming epitaxial source / drain regions 98 in p-type region 50P is shown. Figures 12-16 It shows Figure 11A Features in region 50A. As previously described, seed layer 98A comprises a material such that the material of liner layer 98B has a lower bottom-up growth rate relative to that material, and the material also helps to reduce the outward diffusion of p-type dopants into the second nanostructure 66 or fin 62 during subsequent processing.

[0060] exist Figure 12 In the middle, source / drain recesses 92 and internal spacers 96 are formed, such as for... Figures 8A-9C As described. In this embodiment, the internal spacer 96 is recessed relative to the sidewall of the second nanostructure 66 after formation. In other embodiments, the internal spacer 96 extends beyond the sidewall of the second nanostructure 66 after formation, or is flush with the sidewall of the second nanostructure 66.

[0061] exist Figure 13 In this embodiment, a sidewall recess 92S is formed by recessing the portion of the sidewall of the second nanostructure 66 that is exposed by the source / drain recess 92. After the sidewall of the second nanostructure 66 is recessed, the second nanostructure 66 can have various sidewall types. In this embodiment, the second nanostructure 66 has concave sidewalls. In other embodiments (hereinafter referred to as…),… Figures 23-24(Described as described), the second nanostructure 66 has straight or convex sidewalls. The sidewalls of the second nanostructure 66 can be recessed by any acceptable etching process, such as a process selective for the material of the second nanostructure 66 (e.g., selectively etching the material of the second nanostructure 66 at a faster rate relative to the material of the inner spacer 96). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the inner spacer 96 is formed of silicon nitride, the etching process can be a wet etching using potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), etc. A timed etching process can be used to stop etching the second nanostructure 66 after the sidewalls of the second nanostructure 66 have been recessed to a desired extent. Specifically, the sidewalls of the second nanostructure 66 are etched until they are recessed relative to the outer sidewalls of the inner spacer 96. In this way, the outer sidewalls of the inner spacer 96 are set to be farther from the first nanostructure 64 (and the alternative gate structure subsequently formed therefrom) compared to the sidewalls of the second nanostructure 66. In some embodiments, the second nanostructure 66 is etched for a duration ranging from 15 seconds to 60 seconds.

[0062] exist Figure 14 In the p-type region 50P, a seed layer 98A is epitaxially grown on the surface of the semiconductor features exposed in the source / drain recess 92 (e.g., the surface of the fin 62 and the second nanostructure 66). Specifically, the seed layer 98A is grown in the sidewall recess 92S and on the fin 62. The seed layers 98A are grown such that they remain separated and do not merge in the source / drain recess 92. Specifically, the growth of the seed layers 98A is stopped before they merge in the source / drain recess 92. Therefore, the outer wall of the inner spacer 96 is at least partially not covered by the seed layer 98A (e.g., not in contact with the seed layer 98A) and remains exposed after the growth of the seed layer 98A. In other words, the outer wall of the inner spacer 96 does not contact the seed layer 98A. After growth, the outer wall of the seed layer 98A extends beyond the outer wall of the inner spacer 96. In this way, the outer wall of the seed layer 98A is set to be farther from the first nanostructure 64 (and the alternative gate structure subsequently formed therefrom) than the outer wall of the inner spacer 96 and the sidewall of the second nanostructure 66.

[0063] The epitaxial growth process used to form the seed layer 98A has a first bottom-up growth rate (e.g., in the Z direction) and a first lateral growth rate (e.g., in the X direction), wherein the ratio of the first bottom-up growth rate to the first lateral growth rate is small, for example, less than 2. Thus, the thickness T of the seed layer 98A at the bottom of the source / drain recess 92 is... 1B The thickness T of the seed layer 98A at the sidewall of the source / drain recess 92 (e.g., in the sidewall recess 92S).1S The difference is small. Specifically, although the thickness T 1B Greater than thickness T 1S However, the thickness T 1B With thickness T 1S The ratio is less than 2. In other words, the thickness T 1B With thickness T 1S The ratio is in the range of 1 to 3. In some embodiments, the thickness T 1B Within the range of 4nm to 8nm, the thickness T 1S Within the range of 2nm to 4nm, and with a thickness T 1B Greater than thickness T 1S Forming a T with a thickness of less than 2 nm 1S The seed layer 98A may not be sufficient to reduce the outward diffusion of p-type dopant into the channel region 68, thereby degrading device performance. A layer with a thickness greater than 8 nm, T, is formed. 1B The seed layer 98A may not leave enough usable volume in the source / drain recess 92 for the highly doped epitaxial layer, thereby reducing device performance.

[0064] A seed layer 98A can be grown from the second nanostructure 66 and fin 62 by exposing the second nanostructure 66 and fin 62 to one or more semiconductor precursors, dopant precursors, and etching precursors. When the seed layer 98A in the p-type region 50P is formed of boron-doped silicon, the semiconductor precursor(s) can be one or more silicon precursors, the dopant precursor can be a boron precursor, and the etching precursor can be a chlorine precursor. The silicon precursor can be a silane, such as dichlorosilane (H2SiCl2), silane (SiH4), etc. The boron precursor can be diborane (B2H6), etc. The chlorine precursor can be hydrochloric acid (HCl), etc. In some embodiments, the second nanostructure 66 and fin 62 are exposed to one or more semiconductor precursors, dopant precursors, and etching precursors at a temperature in the range of 600°C to 700°C, at a pressure in the range of 20 Torr to 50 Torr, and for a duration in the range of 2 minutes to 5 minutes. Growing the seed layer 98A at these temperature and pressure ranges allows the seed layer 98A to have the desired thickness (as previously described). Growing the seed layer 98A at temperatures or pressures outside these ranges may not allow the seed layer 98A to have the desired thickness.

[0065] The impurity concentration in the seed layer 98A determines the extent to which the seed layer 98A reduces the outward diffusion of p-type dopants into the channel region 68. In some embodiments, the seed layer 98A comprises Si:B, and the boron concentration is 1 × 10⁻⁶. 19 cm -3 Up to 2×10 21 cm -3Within the range. Formation of boron concentration less than 1×10⁻⁶. 19 cm -3 The seed layer 98A may not be sufficient to reduce the outward diffusion of p-type dopant into the channel region 68, thereby degrading device performance. A boron concentration greater than 2 × 10⁻⁶ is required. 21 cm -3 The seed layer 98A will result in lower epitaxial growth quality, which will lead to higher resistance in the epitaxial source / drain region 98 and reduce device performance.

[0066] exist Figure 15 In the p-type region 50P, the liner layer 98B is epitaxially grown on the surface of the seed layer 98A. The liner layers 98B grow until they merge in each source / drain recess 92. Thus, the outer walls of the inner spacer 96 are covered by the liner layer 98B (e.g., contact liner layer 98B).

[0067] The epitaxial growth process for forming the liner layer 98B has a second bottom-up growth rate (e.g., in the Z direction) and a second lateral growth rate (e.g., in the X direction), wherein the ratio of the second bottom-up growth rate to the second lateral growth rate is small, for example, less than 4. As described above, the liner layer 98B is grown from the seed layer 98A (not from the fin 62). The second bottom-up growth rate when growth is performed from the seed layer 98A is less than the second bottom-up growth rate when growth is performed from the fin 62. Furthermore, the first bottom-up growth rate (for...) Figure 14 (As described) is less than the second bottom-up growth rate during growth from fin 62. Thus, the thickness T of the liner layer 98B at the bottom of the source / drain recess 92 is... 2B The thickness T of the liner layer 98B at the sidewall of the source / drain recess 92 2S The difference is small. In some embodiments, the thickness T... 2B Within the range of 8nm to 16nm, the thickness T 2S Within the range of 2nm to 4nm, and with a thickness T 2B Greater than thickness T 2S Forming a T with a thickness of less than 2 nm 2S The 98B liner layer may not provide sufficient adhesion for the growth of subsequent epitaxial layers, thus reducing device reliability. A layer with a thickness greater than 16 nm is formed. 2B The liner layer 98B may not leave enough usable volume in the source / drain recess 92 for the highly doped epitaxial layer, thereby reducing device performance.

[0068] The liner layer 98B can be grown from the seed layer 98A by exposing the seed layer 98A to various semiconductor-containing precursors, dopant-containing precursors, and etching precursors. When the liner layer 98B in the p-type region 50P is formed from boron-doped silicon-germanium, the semiconductor-containing precursor can include a silicon-containing precursor and a germanium-containing precursor; the dopant-containing precursor can be a boron-containing precursor; and the etching precursor can be a chlorine-containing precursor. The silicon-containing precursor can be a silane, such as dichlorosilane (H2SiCl2), silane (SiH4), etc. The germanium-containing precursor can be a germanane, such as monogermanane (GeH4), etc. The boron-containing precursor can be diborane (B2H6), etc. The chlorine-containing precursor can be hydrochloric acid (HCl), etc. In some embodiments, the seed layer 98A is exposed to a semiconductor precursor, a doped precursor, and an etch precursor at a temperature ranging from 580°C to 680°C, at a pressure ranging from 20 Torr to 50 Torr, and for a duration ranging from 2 minutes to 4 minutes. The doped precursor and / or etch precursor used to grow the liner layer 98B may be the same as the doped precursor and / or etch precursor used to grow the seed layer 98A, or may include different precursors. Growing the liner layer 98B at these temperature and pressure ranges allows the liner layer 98B to have the desired thickness (as previously described). Growing the liner layer 98B at temperatures or pressures outside these ranges may not allow the liner layer 98B to have the desired thickness.

[0069] exist Figure 16 In the p-type region 50P, the master layer 98C is epitaxially grown on the surface of the liner layer 98B. The master layers 98C grow until they fill (or overfill) each source / drain recess 92. Because the thickness of the liner layer 98B decreases at the bottom of the source / drain recess 92, the master layer 98C can occupy the increased volume of the source / drain recess 92.

[0070] The master layer 98C can be grown from the liner layer 98B by exposing the liner layer 98B to various semiconductor-containing precursors, dopant-containing precursors, and etching precursors. When the master layer 98C in the p-type region 50P is formed from boron-doped silicon-germanium, the semiconductor-containing precursor can include a silicon-containing precursor and a germanium-containing precursor; the dopant-containing precursor can be a boron-containing precursor; and the etching precursor can be a chlorine-containing precursor. The silicon-containing precursor can be a silane, such as dichlorosilane (H2SiCl2), silane (SiH4), etc. The germanium-containing precursor can be a germanane, such as monogermanane (GeH4), etc. The boron-containing precursor can be diborane (B2H6), etc. The chlorine-containing precursor can be hydrochloric acid (HCl), etc. In some embodiments, the liner layer 98B is exposed to a semiconductor-containing precursor, a doped precursor, and an etching precursor at a temperature ranging from 550°C to 650°C, at a pressure ranging from 20 Torr to 50 Torr, and for a duration ranging from 3 minutes to 7 minutes. The semiconductor-containing precursor, doped precursor, and / or etching precursor used to grow the master layer 98C may be the same as the semiconductor-containing precursor, doped precursor, and / or etching precursor used to grow the liner layer 98B and / or the seed layer 98A, or may include different precursors.

[0071] The main layer 98C is a heavily doped epitaxial layer, while the liner layer 98B is a lightly doped epitaxial layer. Specifically, the main layer 98C may have a higher germanium concentration and a higher boron concentration than the liner layer 98B. In some embodiments, the liner layer 98B is composed of layers with a density of 1 × 10⁻⁶. 20 cm -3 Up to 5×10 20 cm -3 Si with boron concentration in the range 1-x Ge x :B is formed, and the main layer 98C is composed of layers with a diameter of 4×10. 20 cm -3 Up to 10×10 20 cm -3 Si with boron concentration in the range 1-y Ge y :B is formed, wherein x is in the range of 0.1 to 0.4 and y is in the range of 0.2 to 0.9 (or more generally, x is less than y). In some embodiments, the seed layer 98A also has a greater boron concentration than the liner layer 98B.

[0072] exist Figures 17A-17CIn this configuration, the first ILD 104 is deposited on the epitaxial source / drain region 98, the gate spacer 88, and the mask 86 (if present) or dummy gate 84. The first ILD 104 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0073] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, gate spacer 88, and mask 86 (if present) or dummy gate 84. The CESL 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity relative to the etching of the first ILD 104. The CESL 102 can be formed by any suitable method, such as CVD, ALD, etc.

[0074] exist Figures 18A-18C In the process, a removal process is performed to make the top surface of the first ILD 104 flush with the top surface of the gate spacer 88 and the mask 86 (if present) or dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, and combinations thereof, may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and a portion of the gate spacer 88 along the sidewall of the mask 86. After the planarization process, the top surfaces of the gate spacer 88, the first ILD 104, CESL 102, and the mask 86 (if present) or dummy gate 84 are coplanar (within the range of process variations). Therefore, the top surface of the mask 86 (if present) or dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 flush with the top surface of the mask 86.

[0075] exist Figures 19A-19CIn the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form the recess 106. A portion of the dummy dielectric 82 within the recess 106 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 84 (relative to the first ILD 104 or gate spacer 88) at a faster rate. During removal, the dummy dielectric 82 may serve as an etch stop layer while etching the dummy gate 84. The dummy dielectric 82 is then removed. Each recess 106 exposes and / or covers a portion of the channel region 68. A portion of the second nanostructure 66 serving as the channel region 68 is disposed between and adjacent to adjacent pairs of epitaxial source / drain regions 98.

[0076] The remaining portion of the first nanostructure 64 is then removed to enlarge the recess 106, thereby forming an opening 108 between the second nanostructures 66. The remaining portion of the first nanostructure 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructure 64 (compared to the material of the second nanostructure 66) at a faster rate. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructure 66.

[0077] exist Figures 20A-20CIn this process, a gate dielectric 122 and a gate electrode 124 are formed to replace the gate structure. Each corresponding pair of gate dielectric 122 and gate electrode 124 may be collectively referred to as a "gate structure". Each gate structure extends along the sidewalls and top surface of the channel region 68 of the nanostructure 66. Some gate structures also extend along the sidewalls and / or top surface of the fin 62. The gate dielectric 122 includes one or more gate dielectric layers disposed around the nanostructure 66 and on the sidewalls of the gate spacer 88 and the internal spacer 96. The gate dielectric 122 may be formed of oxides (e.g., silicon oxide or metal oxides), silicates (e.g., metal silicates), combinations thereof, multilayers thereof, etc. Additionally or alternatively, the gate dielectric 122 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. One or more dielectric materials of the gate dielectric 122 can be formed by molecular beam deposition (MBD), ALD, PECVD, etc. Although a single-layer gate dielectric 122 is shown, the gate dielectric 122 may include any number of interface layers and any number of main layers. For example, the gate dielectric 122 may include an interface layer and an overlying high-k dielectric layer.

[0078] The gate electrode 124 includes one or more gate electrode layers disposed on the gate dielectric 122. The gate electrode 124 may be formed of a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, or multiples thereof. Although a single-layer gate electrode 124 is shown, the gate electrode 124 may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0079] As an example of forming a gate structure, one or more gate dielectric layers may be deposited in the recess 106 and the opening 108. The gate dielectric layers may also be deposited on the top surfaces of the first ILD 104, CESL 102, and gate spacer 88. Subsequently, one or more gate electrode layers may be deposited on the gate dielectric layers and in the remaining portions of the recess 106 and the opening 108. A removal process may then be performed to remove excess portions of the gate dielectric layers and gate electrode layers above the top surfaces of the first ILD 104, CESL 102, and gate spacer 88. After the removal process, the gate dielectric layers have portions remaining in the recess 106 and the opening 108 (thus forming gate dielectric 122). After the removal process, the gate electrode layers have portions remaining in the recess 106 and the opening 108 (thus forming gate electrode 124). In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, may be utilized. After the planarization process, the top surfaces of the gate spacer 88, CESL 102, first ILD 104, gate dielectric 122 and gate electrode 124 are coplanar (within the range of process variations).

[0080] The formation of the gate dielectric 122 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric 122 in each region is formed of the same (one or more) materials, and the formation of the gate electrode 124 can occur simultaneously, such that the gate electrode 124 in each region is formed of the same (one or more) materials. In some embodiments, the gate dielectric 122 in each region can be formed by different processes, such that the gate dielectric 122 may include different materials and / or have different numbers of layers, and / or the gate electrode 124 in each region can be formed by different processes, such that the gate electrode 124 may include different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0081] exist Figures 21A-21C In this configuration, the second ILD 134 is formed over the gate spacer 88, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable thin film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.), which can be deposited by any suitable method (e.g., CVD, PECVD, etc.).

[0082] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 88, ESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity relative to the etching of the second ILD 134.

[0083] exist Figures 22A-22C In this configuration, a gate contact 142 and a source / drain contact 144 are formed to contact the gate electrode 124 and the epitaxial source / drain region 98, respectively. The gate contact 142 is physically and electrically coupled to the gate electrode 124. The source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 98.

[0084] As an example of forming the gate contact 142 and the source / drain contact 144, an opening for the gate contact 142 is formed through the second ILD 134 and ESL 132, and an opening for the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown separately) (e.g., a diffusion barrier layer, adhesive layer, etc.) and a conductive material are formed within the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 within the openings. The gate contact 142 and the source / drain contact 144 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed in different cross-sections, which can avoid short circuits in the contacts.

[0085] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanide region formed from both metal silicides and metal germanides, etc. The metal-semiconductor alloy region 146 may be formed prior to one or more materials of the source / drain contact 144 by depositing metal in the opening of the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon carbide, silicon germanium, germanium, etc.) of the epitaxial source / drain region 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following a thermal annealing process, a cleaning process (e.g., wet cleaning) can be performed to remove any residual metal from the openings in the source / drain contact 144 (e.g., from the surface of the metal-semiconductor alloy region 146). One or more materials of the source / drain contact 144 can then be formed on the metal-semiconductor alloy region 146.

[0086] Subsequently, the nanoFET devices can be interconnected via a metallization layer in the overlay interconnect structure to form an integrated circuit. The overlay interconnect structure can be formed in a back-end process (BEOL) process, where the metallization layer connects to the gate contact 142 and the source / drain contact 144. In some types of devices (e.g., memory devices), the source / drain contact 144 to the source region of the device can be grounded. Additional features such as passive devices, memories (e.g., magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase-change random access memory (PCRAM), etc.) can be integrated with the interconnect structure during the BEOL process.

[0087] Figure 23 This is a view of a nanoFET according to some other embodiments. This embodiment is similar to... Figure 22A The described embodiment, except that the second nanostructure 66 has straight sidewalls. The sidewall shape of the second nanostructure 66 can be adjusted to form the sidewall recesses 92S (for...). Figure 13 The duration of the etching process (described in the text) is controlled. This is achieved by performing the etching for a longer duration (compared to the etching used to form...). Figure 22ACompared to the duration of the second nanostructure 66, the second nanostructure 66 can be formed having straight sidewalls. In some embodiments, the second nanostructure 66 is etched for a duration ranging from 25 seconds to 70 seconds.

[0088] Figure 24 This is a view of a nanoFET according to some other embodiments. This embodiment is similar to... Figure 22A The described embodiment, except that the second nanostructure 66 has convex sidewalls, is achieved by performing the formation of the sidewall recesses 92S over a longer duration (for...). Figure 13 Etching (as described) (with the method used to form) Figure 23 Compared to the duration of the second nanostructure 66, the second nanostructure 66 may be formed having convex sidewalls. In some embodiments, the second nanostructure 66 is etched for a duration ranging from 35 seconds to 80 seconds.

[0089] The embodiment offers advantages. Growing the liner layer 98B from the seed layer 98A (instead of from fin 62) allows for a reduced bottom-up growth rate of the liner layer 98B. This reduces the thickness of the liner layer 98B at the bottom of the epitaxial source / drain region 98. Consequently, the available volume for the highly doped epitaxial layer in the source / drain recess 92 can be increased. Therefore, the resistance of the epitaxial source / drain region 98 can be reduced, thereby improving device performance. Furthermore, the seed layer 98A also helps reduce the outward diffusion of p-type dopant into the channel region 68. Therefore, dopant diffusion into the channel region 68 can be reduced, lowering the resistance of the channel region 68 and further improving device performance.

[0090] In some embodiments, a device includes: a nanostructure; and a source / drain region adjacent to a channel region of the nanostructure, the source / drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer comprising a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising a germanium-containing semiconductor material and a p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer comprising a germanium-containing semiconductor material and a p-type dopant. In some embodiments, the device further includes: a gate structure surrounding the channel region of the nanostructure; and a spacer between the gate structure and the source / drain region, the sidewall of the spacer being configured to be farther from the gate structure than the sidewall of the nanostructure. In some embodiments of the device, the sidewall of the first epitaxial layer of the source / drain region is configured to be farther from the gate structure than the sidewall of the spacer. In some embodiments of the device, the second epitaxial layer of the source / drain region contacts the spacer. In some embodiments of the device, the sidewall of the nanostructure is a concave sidewall. In some embodiments of the device, the sidewalls of the nanostructure are straight. In some embodiments of the device, the sidewalls of the nanostructure are convex.

[0091] In one embodiment, a device includes: a fin extending from a substrate; a nanostructure on the fin; and a source / drain region including: a liner layer comprising boron-doped silicon-germanium; a first seed layer comprising boron-doped silicon between the liner layer and the nanostructure; and a second seed layer comprising boron-doped silicon between the liner layer and the fin. In some embodiments of the device, the first and second seed layers have a higher boron concentration than the liner layer. In some embodiments of the device, the first seed layer has a first thickness, the second seed layer has a second thickness greater than the first thickness, and the ratio of the second thickness to the first thickness is less than 2. In some embodiments of the device, the source / drain region further includes: a main layer on the liner layer, wherein the liner layer comprises Si. 1-x Ge x :B, the main layer includes Si 1-y Ge y :B, and x is less than y. In some embodiments, the device further includes: a gate structure surrounding the nanostructure; and a spacer between the gate structure and the source / drain regions, wherein the liner layer contacts the sidewall of the spacer, and the sidewall of the spacer does not contact the first seed layer and the second seed layer.

[0092] In one embodiment, a method includes: etching source / drain recesses in a nanostructure and a fin; growing a first epitaxial layer from the sidewalls of the nanostructure in the source / drain recess and the top surface of the fin; growing a second epitaxial layer from the first epitaxial layer using a growth process having a first bottom-up growth rate from the first epitaxial layer and a second bottom-up growth rate from the fin and the nanostructure, the first bottom-up growth rate being less than the second bottom-up growth rate; and growing a third epitaxial layer from the second epitaxial layer. In some embodiments of the method, the growth process has a lateral growth rate from the first epitaxial layer, the ratio of the first bottom-up growth rate to the lateral growth rate being in the range of 1 to 3. In some embodiments of the method, the first epitaxial layer comprises boron-doped silicon, the second epitaxial layer comprises boron-doped silicon-germanium, and the third epitaxial layer comprises boron-doped silicon-germanium. In some embodiments of the method, growing the first epitaxial layer includes: exposing the nanostructure and the fin to silane, diborane, and hydrochloric acid at a temperature in the range of 600°C to 700°C and a pressure in the range of 20 Torr to 50 Torr. In some embodiments of the method, growing the second epitaxial layer includes exposing the first epitaxial layer to silane, germane, diborane, and hydrochloric acid at a temperature in the range of 580°C to 680°C and a pressure in the range of 20 Torr to 50 Torr. In some embodiments of the method, the first germanium concentration of the first epitaxial layer is less than the second germanium concentration of the second epitaxial layer. In some embodiments of the method, the third germanium concentration of the third epitaxial layer is greater than the second germanium concentration of the second epitaxial layer. In some embodiments, the method further includes forming a spacer between a nanostructure and a fin in a source / drain recess, the sidewalls of the nanostructure being recessed from the sidewalls of the spacer, and the first epitaxial layer growing until the sidewalls of the first epitaxial layer extend beyond the sidewalls of the spacer.

[0093] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0094] Example 1. A semiconductor device, comprising:

[0095] Nanostructures; and

[0096] Source / drain regions, adjacent to the channel region of the nanostructure, wherein the source / drain regions include:

[0097] A first epitaxial layer is formed on the sidewall of the nanostructure, and the first epitaxial layer comprises a germanium-free semiconductor material and a p-type dopant;

[0098] A second epitaxial layer, on top of the first epitaxial layer, comprises a germanium-containing semiconductor material and the p-type dopant; and

[0099] The third epitaxial layer is located on the second epitaxial layer and includes the germanium-containing semiconductor material and the p-type dopant.

[0100] Example 2. The device according to Example 1 further includes:

[0101] Gate structure, surrounding the channel region of the nanostructure; and

[0102] A spacer, between the gate structure and the source / drain region, wherein the sidewalls of the spacer are configured to be farther from the gate structure than the sidewalls of the nanostructure.

[0103] Example 3. The device according to Example 2, wherein the sidewall of the first epitaxial layer of the source / drain region is configured to be farther from the gate structure than the sidewall of the spacer.

[0104] Example 4. The device according to Example 2, wherein the second epitaxial layer of the source / drain region contacts the spacer.

[0105] Example 5. The device according to Example 1, wherein the sidewalls of the nanostructure are concave sidewalls.

[0106] Example 6. The device according to Example 1, wherein the sidewalls of the nanostructure are straight sidewalls.

[0107] Example 7. The device according to Example 1, wherein the sidewalls of the nanostructure are convex sidewalls.

[0108] Example 8. A semiconductor device comprising:

[0109] Fins extend from the substrate;

[0110] Nanostructures, on the fins;

[0111] Source / drain regions, including:

[0112] A liner layer comprising boron-doped silicon germanium;

[0113] A first seed layer, situated between the liner layer and the nanostructure, comprises boron-doped silicon; and

[0114] A second seed layer, located between the liner layer and the fin, comprises boron-doped silicon.

[0115] Example 9. The device according to Example 8, wherein the first seed layer and the second seed layer have a greater boron concentration than the liner layer.

[0116] Example 10. The device according to Example 8, wherein the first seed layer has a first thickness, the second seed layer has a second thickness, the second thickness is greater than the first thickness, and the ratio of the second thickness to the first thickness is less than 2.

[0117] Example 11. The device according to Example 8, wherein the source / drain region further includes:

[0118] The main layer, on top of the lining layer,

[0119] The lining layer includes Si 1-x Ge x B, the main layer includes Si 1-y Ge y :B, and x is less than y.

[0120] Example 12. The device according to Example 8 further includes:

[0121] A gate structure surrounding the nanostructure; and

[0122] A spacer is provided between the gate structure and the source / drain regions, wherein the liner layer contacts the sidewall of the spacer, and the sidewall of the spacer does not contact the first seed layer and the second seed layer.

[0123] Example 13. A method of forming a semiconductor device, the method comprising:

[0124] Etching source / drain recesses in nanostructures and fins;

[0125] A first epitaxial layer is grown from the sidewalls of the nanostructure in the source / drain recess and the top surface of the fin;

[0126] A second epitaxial layer is grown from the first epitaxial layer using a growth process having a first bottom-up growth rate from the first epitaxial layer and a second bottom-up growth rate from the fins and the nanostructures, wherein the first bottom-up growth rate is less than the second bottom-up growth rate; and

[0127] A third epitaxial layer is grown from the second epitaxial layer.

[0128] Example 14. The method according to Example 13, wherein the growth process has a lateral growth rate from the first epitaxial layer, and the ratio of the first bottom-up growth rate to the lateral growth rate is in the range of 1 to 3.

[0129] Example 15. The method according to Example 13, wherein the first epitaxial layer comprises boron-doped silicon, the second epitaxial layer comprises boron-doped silicon-germanium, and the third epitaxial layer comprises boron-doped silicon-germanium.

[0130] Example 16. The method according to Example 15, wherein growing the first epitaxial layer comprises:

[0131] The nanostructure and the fin were exposed to silane, diborane and hydrochloric acid at a temperature ranging from 600°C to 700°C and a pressure ranging from 20 Torr to 50 Torr.

[0132] Example 17. The method according to Example 15, wherein growing the second epitaxial layer comprises:

[0133] The first epitaxial layer was exposed to silane, germane, diborane, and hydrochloric acid at a temperature ranging from 580°C to 680°C and a pressure ranging from 20 Torr to 50 Torr.

[0134] Example 18. The method according to Example 13, wherein the first germanium concentration of the first epitaxial layer is less than the second germanium concentration of the second epitaxial layer.

[0135] Example 19. The method according to Example 18, wherein the third germanium concentration of the third epitaxial layer is greater than the second germanium concentration of the second epitaxial layer.

[0136] Example 20. The method according to Example 13 further includes:

[0137] A spacer is formed between the nanostructure in the source / drain recess and the fin, the sidewall of the nanostructure being recessed from the sidewall of the spacer, and the first epitaxial layer is grown until the sidewall of the first epitaxial layer extends beyond the sidewall of the spacer.

Claims

1. A semiconductor device, comprising: Nanostructures, on the fins; as well as Source / drain regions, adjacent to the channel region of the nanostructure, wherein the source / drain regions include: A first epitaxial layer is formed on the sidewall of the nanostructure, and the first epitaxial layer comprises a germanium-free semiconductor material and a p-type dopant; A second epitaxial layer, on top of the first epitaxial layer, comprises a germanium-containing semiconductor material and the p-type dopant, wherein the second epitaxial layer is grown from the first epitaxial layer using a growth process having a first bottom-up growth rate from the first epitaxial layer and a second bottom-up growth rate from the fins and the nanostructures, the first bottom-up growth rate being less than the second bottom-up growth rate; and The third epitaxial layer is located on the second epitaxial layer and includes the germanium-containing semiconductor material and the p-type dopant.

2. The device according to claim 1, further comprising: A gate structure that surrounds the channel region of the nanostructure; as well as A spacer, between the gate structure and the source / drain region, wherein the sidewalls of the spacer are configured to be farther from the gate structure than the sidewalls of the nanostructure.

3. The device according to claim 2, wherein, The sidewalls of the first epitaxial layer of the source / drain region are configured to be farther from the gate structure than the sidewalls of the spacer.

4. The device according to claim 2, wherein, The second epitaxial layer of the source / drain region contacts the spacer.

5. The device according to claim 1, wherein, The sidewalls of the nanostructure are concave.

6. The device according to claim 1, wherein, The sidewalls of the nanostructure are straight.

7. The device according to claim 1, wherein, The sidewalls of the nanostructure are convex.

8. A semiconductor device, comprising: Fins extend from the substrate; Nanostructures, on the fins; Source / drain regions, including: A liner layer comprising boron-doped silicon germanium; A first seed layer, situated between the liner layer and the nanostructure, comprises boron-doped silicon; and A second seed layer, located between the liner layer and the fin, comprises boron-doped silicon. The lining layer is grown from the first seed layer and the second seed layer using a growth process having a first bottom-up growth rate from the first seed layer and the second seed layer and a second bottom-up growth rate from the fin and the nanostructure, wherein the first bottom-up growth rate is less than the second bottom-up growth rate.

9. The device according to claim 8, wherein, The first and second seed layers have a higher boron concentration compared to the lining layer.

10. The device according to claim 8, wherein, The first seed layer has a first thickness, the second seed layer has a second thickness, the second thickness is greater than the first thickness, and the ratio of the second thickness to the first thickness is less than 2.

11. The device according to claim 8, wherein, The source / drain region further includes: The main layer, on top of the lining layer, The lining layer includes Si 1-x Ge x B, the main layer includes Si 1-y Ge y :B, and x is less than y.

12. The device according to claim 8, further comprising: A gate structure surrounds the nanostructure; as well as A spacer is provided between the gate structure and the source / drain regions, wherein the liner layer contacts the sidewall of the spacer, and the sidewall of the spacer does not contact the first seed layer and the second seed layer.

13. A method of forming a semiconductor device, the method comprising: Etching source / drain recesses in nanostructures and fins; A first epitaxial layer is grown from the sidewalls of the nanostructure in the source / drain recess and the top surface of the fin; A second epitaxial layer is grown from the first epitaxial layer using a growth process having a first bottom-up growth rate from the first epitaxial layer and a second bottom-up growth rate from the fins and the nanostructures, wherein the first bottom-up growth rate is less than the second bottom-up growth rate; and A third epitaxial layer is grown from the second epitaxial layer.

14. The method according to claim 13, wherein, The growth process has a lateral growth rate from the first epitaxial layer, and the ratio of the first bottom-up growth rate to the lateral growth rate is in the range of 1 to 3.

15. The method according to claim 13, wherein, The first epitaxial layer comprises boron-doped silicon, the second epitaxial layer comprises boron-doped silicon-germanium, and the third epitaxial layer comprises boron-doped silicon-germanium.

16. The method according to claim 15, wherein, Growing the first epitaxial layer includes: The nanostructure and the fin were exposed to silane, diborane and hydrochloric acid at temperatures ranging from 600 °C to 700 °C and at pressures ranging from 20 Torr to 50 Torr.

17. The method according to claim 15, wherein, The growth of the second epitaxial layer includes: The first epitaxial layer was exposed to silane, germanane, diborane, and hydrochloric acid at a temperature ranging from 580 °C to 680 °C and a pressure ranging from 20 Torr to 50 Torr.

18. The method according to claim 13, wherein, The first germanium concentration of the first epitaxial layer is less than the second germanium concentration of the second epitaxial layer.

19. The method according to claim 18, wherein, The third germanium concentration of the third epitaxial layer is greater than the second germanium concentration of the second epitaxial layer.

20. The method of claim 13, further comprising: A spacer is formed between the nanostructure in the source / drain recess and the fin, the sidewall of the nanostructure being recessed from the sidewall of the spacer, and the first epitaxial layer is grown until the sidewall of the first epitaxial layer extends beyond the sidewall of the spacer.

Images