Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a fin on the substrate, an isolation layer on the substrate between adjacent fins, a top surface of the isolation layer being lower than a top surface of the fin, a gate structure on the substrate and across the fin, the gate structure covering a portion of a top and sidewall surface of the fin and a top surface of the isolation layer, a source / drain doped layer in the fin on both sides of the gate structure, and a spacer layer between the source / drain doped layer and the substrate. The semiconductor structure and the method for forming the same can improve the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. As the most basic semiconductor device, semiconductor devices are currently widely used. However, traditional planar devices have weakened control over channel current, resulting in short-channel effects that lead to leakage current and ultimately affect the electrical performance of semiconductor devices.

[0003] To overcome the short-channel effect and suppress leakage current, the prior art has proposed the FinFET (Fin Field-Effect Transistor). The FinFET is a common multi-gate device. The structure of the FinFET includes: a fin and an isolation structure located on the surface of a semiconductor substrate, wherein the isolation structure covers part of the sidewall of the fin and the surface of the isolation structure is lower than the top of the fin; a gate structure located on the surface of the isolation structure and on the top and sidewall surfaces of the fin; and source and drain regions located in the fin on both sides of the gate structure.

[0004] However, the performance of current fin field-effect transistors still needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; fins located on the substrate; an isolation layer located on the substrate between adjacent fins, wherein the top surface of the isolation layer is lower than the top surface of the fins; a gate structure located on the substrate and spanning the fins, wherein the gate structure covers a portion of the top and sidewall surfaces of the fins and the top surface of the isolation layer; source / drain doped layers located within the fins on both sides of the gate structure; and a spacer layer located between the source / drain doped layers and the substrate.

[0007] Optionally, it also includes: a buffer layer located on the substrate, and the fin located on the buffer layer.

[0008] Optionally, the spacer layer may include an insulating layer or an air gap layer.

[0009] Optionally, the buffer layer is made of silicon-germanium, and the molar percentage concentration of germanium in the buffer layer material is 5% to 50%.

[0010] Optionally, the insulating layer may be made of silicon oxide.

[0011] Optionally, the source / drain doped layer contains doped ions, including N-type ions or P-type ions.

[0012] Optionally, when the doped ion is a P-type ion, the material of the fin includes silicon and germanium.

[0013] Optionally, the molar percentage concentration of germanium in the material of the fin is greater than the molar percentage concentration of germanium in the material of the buffer layer, and the molar percentage concentration of germanium in the material of the fin is greater than or equal to 20%.

[0014] Optionally, when the source / drain doped layer and the substrate are an insulating layer, the system further includes a protective layer located on the surface of the source / drain doped layer.

[0015] Optionally, the material of the protective layer includes silicon.

[0016] Optionally, when the doped ion is an N-type ion, the material of the fin includes silicon.

[0017] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a buffer layer on the substrate; forming fins on the buffer layer; forming an isolation layer on the substrate between adjacent fins, the isolation layer covering the sidewall surface of the buffer layer; forming a dummy gate structure on the substrate, the dummy gate structure spanning the fins; forming source / drain doped layers in the fins on both sides of the dummy gate structure; consuming a portion of the buffer layer, and forming a spacer layer between the source / drain doped layers and the substrate.

[0018] Optionally, the spacer layer may include an insulating layer or an air gap layer.

[0019] Optionally, before forming the spacer layer, the method further includes etching a portion of the isolation layer until the sidewall surface of the buffer layer is exposed.

[0020] Optionally, the source / drain doped layer contains doped ions, which include N-type ions or P-type ions.

[0021] Optionally, when an insulating layer is formed between the source / drain doped layer and the substrate, the method for forming the insulating layer includes: oxidizing the exposed buffer layer to form an insulating layer between the source / drain doped layer and the substrate.

[0022] Optionally, the oxidation treatment furnace tube process or the rapid thermal annealing process may be used.

[0023] Optionally, when the doped ion is a P-type ion, before oxidizing the buffer layer, a protective layer is formed on the source / drain doped layer.

[0024] Optionally, the material of the protective layer includes silicon.

[0025] Optionally, when an air gap layer is formed between the source / drain doped layer and the substrate, the method of forming the air gap layer includes: removing the exposed buffer layer and forming a groove between the source / drain doped layer and the substrate, the groove serving as the air gap layer.

[0026] Optionally, the process for removing the exposed buffer layer includes a selective wet etching process, wherein the process parameters of the selective wet etching process include using a hydrochloric acid solution with a concentration of 3% to 20%.

[0027] Optionally, the buffer layer is made of silicon-germanium, and the molar percentage concentration of germanium in the buffer layer material is 5% to 50%.

[0028] Optionally, when the doped ion is a p-type ion, the material of the fin includes silicon germanium, the molar percentage concentration of germanium in the material of the fin is greater than the molar percentage concentration of germanium in the material of the buffer layer, and the molar percentage concentration of germanium in the material of the fin is greater than or equal to 20%.

[0029] Optionally, when the doped ion is an N-type ion, the material of the fin includes silicon.

[0030] Optionally, after forming the spacer layer, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the surface of the source / drain doped layer and exposing the top surface of the dummy gate structure; removing the dummy gate structure and forming a gate opening within the dielectric layer; and forming a gate structure within the gate opening.

[0031] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0032] The semiconductor structure of the present invention has a spacer layer between the source / drain doped layer and the substrate. The spacer layer can isolate the source / drain doped layer and the substrate to avoid leakage current, thereby improving the electrical performance of the semiconductor structure.

[0033] Optionally, it further includes a buffer layer located on the substrate, and the fin located on the buffer layer. The buffer layer between the fin and the substrate can improve the channel stress of the semiconductor device, thereby improving the performance of the semiconductor structure.

[0034] The method for forming the technical solution of the present invention, based on a buffer layer between the fin and the substrate, forms a spacer layer between the source / drain doped layer and the substrate by consuming part of the buffer layer. The spacer layer can isolate the source / drain doped layer and the substrate, avoiding leakage current and thus improving the electrical performance of the semiconductor structure. In addition, the spacer layer is formed after the source / drain doped layer is formed, avoiding the formation of the spacer layer from adversely affecting the formation or stress of the source / drain doped layer, thereby further improving the performance of the semiconductor structure. Attached Figure Description

[0035] Figure 1 This is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0036] Figures 2 to 24 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0037] Figures 25 to 30 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, the performance of current fin field-effect transistors still needs improvement. This will be analyzed and explained in conjunction with specific embodiments.

[0039] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure in one embodiment.

[0040] refer to Figure 1 The semiconductor structure includes: a substrate 100 having fins 101 thereon; a buffer layer 102 located between the substrate 100 and the fins 101; an isolation layer 103 located on the substrate 100 exposed by the fins 101 and also covering the sidewall surface of the buffer layer 102; a dummy gate structure 104 located on the substrate 100 and spanning the fins 101; and source / drain doped layers 105 located within the fins 101 on both sides of the dummy gate structure 104.

[0041] In the aforementioned semiconductor structure, the substrate 100 can be used to form an NMOS device, a PMOS device, or a CMOS device integrating NMOS and PMOS devices. The buffer layer 102 is made of silicon-germanium and is located between the substrate 100 and the fin 101. It acts as a strain buffer layer, reducing the tensile stress on the silicon fins in the NMOS device or the compressive stress on the silicon-germanium fins in the PMOS device, thereby improving the performance of the formed semiconductor device. However, leakage current can easily occur between the source / drain doped layer 105 and the substrate 100, affecting the electrical performance of the semiconductor structure.

[0042] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and a method for forming the semiconductor structure. A buffer layer is formed on a substrate, fins are formed on the buffer layer, a dummy gate structure and source / drain doped layers are formed, and then, based on the buffer layer, a portion of the buffer layer is consumed to form a spacer layer between the source / drain doped layers and the substrate. This spacer layer isolates the source / drain doped layers from the substrate, thereby preventing leakage current in the source / drain doped layers. Furthermore, since the spacer layer is formed after the source / drain doped layers, it does not affect the growth and stress of the source / drain doped layers, which is beneficial for improving the performance of the formed semiconductor structure.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 2 to 24 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0045] refer to Figure 2 Substrate 200 is provided.

[0046] The substrate 200 provides process planarity for the subsequent formation of semiconductor structures. The substrate 200 is used for the subsequent formation of PMOS devices or NMOS devices, or CMOS devices integrating PMOS devices and NMOS devices.

[0047] In this embodiment, the formation of an NMOS device is used as an example for explanation.

[0048] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0049] Next, a buffer layer is formed on the substrate 200, and fins are formed on the buffer layer.

[0050] In this embodiment, the method for forming the buffer layer and the fin includes:

[0051] Continue to refer to Figure 2 A buffer material layer 201 is formed on the substrate 200.

[0052] In this embodiment, the material of the buffer material layer 201 includes silicon germanium, wherein the molar percentage concentration of germanium is 5% to 50%.

[0053] In this embodiment, the buffer material layer 201 is formed using a chemical vapor deposition process; in other embodiments, the buffer material layer 201 may also be formed using an atomic layer deposition process.

[0054] In this embodiment, the buffer material layer 201 is used to form a buffer layer in the future. The buffer layer uses a low concentration of silicon-germanium material, which can increase the channel stress of the formed semiconductor structure, suppress the short-channel effect, and thus improve the performance of the semiconductor structure.

[0055] Continue to refer to Figure 2 A fin material layer 202 is formed on the buffer material layer 201.

[0056] In this embodiment, the material of the fin material layer 202 is silicon.

[0057] In other embodiments, when the substrate 200 is used to form a PMOS device, the material of the fin material layer 202 includes silicon germanium, the molar percentage concentration of germanium in the fin material is greater than the molar percentage concentration of germanium in the buffer layer material, and the molar percentage concentration of germanium in the fin material is 20% to 100%.

[0058] When forming PMOS devices, a high concentration of silicon-germanium material is used to form the fins. The enhanced hole mobility in silicon-germanium can improve the performance of PMOS devices.

[0059] refer to Figures 3 to 5 , Figure 3 This is a top view schematic diagram of a semiconductor structure. Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the AA direction. Figure 5 yes Figure 3 A cross-sectional view along the BB direction shows a mask layer (not shown) formed on the fin material layer 202. The mask layer covers a portion of the top surface of the fin material layer 202 and is used to define the position and size of the fin to be formed. Using the mask layer as a mask, the fin material layer 202 and a portion of the thickness of the buffer material layer 201 are etched to form a buffer layer 203 and a fin 204 located on the buffer layer 203 on the substrate 200.

[0060] The method of forming the fin 204 and the buffer layer 203 includes a dual patterning process or a quadruple patterning process.

[0061] Continue to refer to Figures 3 to 5 It also includes: forming an isolation layer 205 on the substrate 200, the isolation layer 205 covering the sidewall surface of the buffer layer 203.

[0062] In this embodiment, the method for forming the isolation layer 205 includes: forming an initial isolation film (not shown) on the substrate 200, the initial isolation film covering the top and sidewall surfaces of the fin 204; planarizing the initial isolation film until the top surface of the fin 204 is exposed, forming an initial isolation layer (not shown); and etching back the initial isolation layer until the top surface of the initial isolation layer is lower than the top surface of the fin 204, forming the isolation layer 205.

[0063] The insulating layer 205 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the insulating layer 205 is made of silicon oxide.

[0064] The process for forming the initial isolation membrane includes chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or thermal treatment processes.

[0065] refer to Figures 6 to 9 , Figure 6 This is a top view schematic diagram of a semiconductor structure. Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along the AA direction. Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure along the BB direction. Figure 9 yes Figure 6 A cross-sectional view along the CC direction shows that after the isolation layer 205 is formed, a pseudo-gate structure 206 is formed on the substrate 200. The pseudo-gate structure 206 spans the fin 204 and covers part of the top and sidewall surfaces of the fin 204.

[0066] The dummy gate structure 206 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) located on the dummy gate dielectric layer.

[0067] In this embodiment, the dummy gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer may also be made of silicon oxynitride.

[0068] In this embodiment, the material of the dummy gate layer is polycrystalline silicon.

[0069] The method for forming the pseudo-gate structure 206 includes: forming a pseudo-gate dielectric layer (not shown) on the substrate 200, the pseudo-gate dielectric layer spanning the fin 204 and covering part of the top surface and sidewall surface of the fin 204; forming a pseudo-gate film (not shown) on the pseudo-gate dielectric layer; forming a hard mask layer 207 on the surface of the pseudo-gate film, the hard mask layer 207 defining the pattern of the pseudo-gate structure 206 to be formed; and using the hard mask layer 207 as a mask to pattern the pseudo-gate film to form the pseudo-gate structure 206.

[0070] In this embodiment, after forming the dummy gate structure 206, the hard mask layer 207 located on top of the dummy gate structure 206 can be retained. The hard mask layer 207 is made of silicon nitride, and it serves to protect the top of the dummy gate structure 206 in subsequent processes. In other embodiments, the hard mask layer can also be made of silicon oxynitride, silicon carbide, or boron nitride.

[0071] In this embodiment, after the pseudo-gate structure 206 is formed, a sidewall 208 is formed on the sidewall of the pseudo-gate structure 206, and the top surface of the sidewall 208 is flush with the top surface of the hard mask layer 207.

[0072] In this embodiment, the sidewall 208 is made of a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.5 and less than 3.9), and the sidewall 208 is made of SiCON. In other embodiments, the sidewall 208 may also be made of other materials such as silicon nitride.

[0073] Continue to refer to Figures 6 to 9 After the pseudo-gate structure 206 is formed, source / drain doped layers 209 are formed in the fins 204 on both sides of the pseudo-gate structure 206.

[0074] The method for forming the source / drain doped layer 209 includes: using the pseudo-gate structure 206 as a mask, etching the fin 204, forming source / drain openings (not shown) in the fins 204 on both sides of the pseudo-gate structure 206; and forming the source / drain doped layer 209 in the source / drain openings.

[0075] In this embodiment, the source / drain doped layer 209 is formed using an epitaxial growth process.

[0076] The source / drain doped layer 209 contains doped ions.

[0077] When the substrate 200 is used for an NMOS device, the material of the source / drain doped layer 209 includes silicon, gallium arsenide, or indium gallium arsenide; the dopant ions are N-type ions, including phosphorus ions or arsenic ions. When the substrate 200 is used to form a PMOS device, the material of the source / drain doped layer 209 includes germanium or silicon germanium; the dopant ions are P-type ions, including boron ions and BF ions. 2- Ions or indium ions.

[0078] In this embodiment, the substrate 200 is used to form an NMOS device, and the material of the source / drain doped layer 209 includes silicon.

[0079] refer to Figures 10 to 12 , Figure 10 and Figure 7 The view orientation is consistent. Figure 11 and Figure 8 The view orientation is consistent. Figure 12 and Figure 9 With the view direction consistent, etch a portion of the isolation layer 205 until a portion of the sidewall surface of the buffer layer 203 is exposed.

[0080] In this embodiment, the etching process of the isolation layer 205 includes a dry etching process.

[0081] The thickness of the isolation layer 205 removed by etching ranges from 5 to 20 nm. Etching away a portion of the isolation layer 205 exposes a portion of the sidewalls of the buffer layer 203. The exposed buffer layer 203 will subsequently be consumed to form an insulating layer or a groove. If the thickness of the isolation layer 205 removed is too large, the parasitic capacitance between the source / drain doped layer 209 and the substrate 200 will easily increase. If the thickness of the isolation layer 205 removed is too small, the thickness of the subsequently formed insulating layer or groove will be too small, which will not be able to effectively isolate the source / drain doped layer 209 and the substrate 200, and leakage may still occur.

[0082] refer to Figures 13 to 15 , Figure 13 and Figure 10 The view orientation is consistent. Figure 14 and Figure 11 The view orientation is consistent. Figure 15 and Figure 12 With the view orientation consistent, the exposed buffer layer 203 is oxidized to form an insulating layer 210 between the source / drain doped layer 209 and the substrate 200.

[0083] In this embodiment, the spacer layer is the insulating layer 210.

[0084] The oxidation treatment includes furnace tube process or rapid thermal annealing process.

[0085] In this embodiment, the buffer layer 203 is oxidized using a furnace tube process, and the temperature of the furnace tube process is 600-1300℃.

[0086] In this embodiment, the buffer layer 203 is oxidized to form silicon oxide and germanium oxide, and the insulating layer 210 is made of silicon oxide and germanium oxide.

[0087] In this embodiment, the substrate 200 is used to form an NMOS device. The source / drain doped layer 209 is made of silicon. Since the oxidation rate of silicon-germanium material is 2 to 5 times that of silicon, the buffer layer 203 can be oxidized quickly when the buffer layer 203 is oxidized, while the silicon material of the source / drain doped layer 209 has a slow oxidation rate and is consumed less, thus minimizing damage to the source / drain doped layer 209. A larger source / drain doped layer 209 can better provide stress for the device, and when the plug that makes electrical contact with the source / drain doped layer 209 is subsequently formed, increasing the contact area can reduce the resistance, which is beneficial to improving the performance of the semiconductor device.

[0088] refer to Figures 16 to 18 , Figure 16 and Figure 13 The view orientation is consistent. Figure 17 and Figure 14 The view orientation is consistent. Figure 18 and Figure 15 With the same viewing direction, in this embodiment, after forming the insulating layer 210, the method further includes: forming a dielectric layer 211 on the substrate 200, the dielectric layer 211 covering the surface of the source / drain doped layer 209 and exposing the top surface of the dummy gate structure 206; removing the dummy gate structure 206, forming a gate opening (not shown) in the dielectric layer 211; and forming a gate structure 212 in the gate opening.

[0089] In this embodiment, the method further includes removing the hard mask layer 207.

[0090] The gate structure 212 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate layer (not shown) located on the work function layer.

[0091] The gate dielectric layer is made of a high dielectric constant material, the dielectric constant of which is greater than 3.9, and the high dielectric constant material includes alumina or hafnium oxide; the work function layer is made of one or more combinations of N-type work function materials and P-type work function materials; the gate layer is made of a metal, the metal including tungsten.

[0092] In other embodiments, when the substrate 200 is used to form a PMOS device, the material of the source / drain doped layer 209 is silicon-germanium. Before oxidizing the buffer layer 203, a protective layer needs to be formed on the surface of the source / drain doped layer 209 to prevent the source / drain doped layer 209 from being consumed.

[0093] refer to Figures 19 to 21 , Figures 19 to 21 Is Figures 7 to 9 A structural diagram based on the basic structure. Figure 19 and Figure 7 The view orientation is consistent. Figure 20 and Figure 8 The view orientation is consistent. Figure 21 and Figure 9 With the view orientation consistent, a protective layer 213 is formed on the surface of the source / drain doped layer 209 before etching the isolation layer 205 of a certain thickness.

[0094] In this embodiment, the protective layer 213 is made of silicon. The oxidation rate of silicon-germanium is greater than that of silicon, therefore the protective layer 213 can protect the source / drain doped layer 209 from oxidation.

[0095] In this embodiment, the protective layer 213 is formed using a chemical vapor deposition process; in other embodiments, the protective layer 213 may also be formed using an atomic layer deposition process.

[0096] refer to Figures 22 to 24 , Figure 22 and Figure 19 The view orientation is consistent. Figure 23 and Figure 20 The view orientation is consistent. Figure 24 and Figure 21 With the view direction consistent, after forming the protective layer 213, a portion of the thickness of the isolation layer 205 is etched away until a portion of the sidewall surface of the buffer layer 203 is exposed.

[0097] The etching process and the thickness of the etched layer 205 are the same as those disclosed in the embodiment for forming an NMOS device, and will not be repeated here.

[0098] After etching away part of the isolation layer 205, the exposed buffer layer 203 is oxidized to form an insulating layer 210 between the source / drain doped layer 209 and the substrate 200.

[0099] The oxidation process of the buffer layer 203 is the same as that disclosed in the embodiment for forming the NMOS device, and will not be described again here.

[0100] By forming a buffer layer between the fins and the substrate, the buffer layer can improve the channel stress of the semiconductor device. Then, based on the buffer layer, the buffer layer is oxidized to form an insulating layer between the source / drain doped region and the substrate. The insulating layer can isolate the source / drain doped layer and the substrate, avoiding leakage and improving the electrical performance of the semiconductor structure. Furthermore, the insulating layer is formed after the source / drain doped layer is formed, so it will not adversely affect the formation of the source / drain doped layer. It is beneficial to the performance and stress of the formed source / drain doped layer, further improving the performance of the formed semiconductor structure.

[0101] Accordingly, embodiments of the present invention also provide a semiconductor structure.

[0102] refer to Figures 16 to 18 The semiconductor structure includes: a substrate 200; a buffer layer 203 located on the substrate 200; fins 204 located on the buffer layer 203; an isolation layer 205 located on the substrate 200 between adjacent fins 204, the isolation layer 205 covering the sidewall surface of the buffer layer; a gate structure 212 located on the substrate 200 and spanning the fins 204, the gate structure 212 covering a portion of the top and sidewall surfaces of the fins 204 and the top surface of the isolation layer 205; source / drain doped layers 209 located within the fins 204 on both sides of the gate structure 212; and an insulating layer 210 located between the source / drain doped layers 209 and the substrate 200.

[0103] In this embodiment, the spacer layer is an insulating layer 210.

[0104] In this embodiment, the material of the buffer layer 203 includes silicon germanium, wherein the molar percentage concentration of germanium is 5% to 50%.

[0105] In this embodiment, the insulating layer 210 is made of silicon oxide and germanium oxide.

[0106] The source / drain doped layer 209 contains doped ions.

[0107] When the substrate 200 is used for an NMOS device, the material of the source / drain doped layer 209 includes silicon, gallium arsenide, or indium gallium arsenide; the dopant ions are N-type ions, including phosphorus ions or arsenic ions. When the substrate 200 is used to form a PMOS device, the material of the source / drain doped layer 209 includes germanium or silicon germanium; the dopant ions are P-type ions, including boron ions and BF ions. 2- Ions or indium ions.

[0108] In this embodiment, the substrate 200 is used to form an NMOS device, and the material of the source / drain doped layer 209 includes silicon.

[0109] In this embodiment, the fin 204 is made of silicon.

[0110] In this embodiment, a dielectric layer 211 is also included, located on the substrate 200, and the dielectric layer 211 covers the sidewall surface of the gate structure 212.

[0111] In this embodiment, a sidewall 208 is also included, located on the sidewall surface of the gate structure 212.

[0112] In other embodiments, when the substrate 200 is used to form a PMOS device, the source / drain doped layer 209 is made of silicon-germanium, the fin 204 is made of silicon-germanium, the molar percentage concentration of germanium in the fin material is greater than the molar percentage concentration of germanium in the buffer layer material, and the molar percentage concentration of germanium in the fin 204 material is 20% to 100%.

[0113] refer to Figures 19 to 21 When the substrate 200 is used to form a PMOS device, the semiconductor structure further includes a protective layer 213 located on the surface of the source / drain doped layer 209, which is used to protect the source / drain doped layer 209 from damage during the oxidation process of the buffer layer 203.

[0114] Figures 25 to 30 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0115] refer to Figures 25 to 27 , Figure 25 Is Figure 10 A structural diagram based on the basic structure. Figure 26 Is Figure 11 A structural diagram based on the basic structure. Figure 27 Is Figure 12 Based on the structural schematic diagram, after etching away part of the thickness of the isolation layer 205 to expose part of the thickness of the buffer layer 203, the exposed buffer layer 203 is removed, and a groove 214 is formed between the source / drain doped layer 209 and the substrate 200. The groove 214 serves as an air gap layer.

[0116] In this embodiment, the spacer layer is an air gap layer.

[0117] In this embodiment, the process for removing the buffer layer 203 includes a selective wet etching process, and the process parameters of the selective wet etching process include using a hydrochloric acid solution with a concentration of 3% to 20%.

[0118] In this embodiment, the air gap layer can also isolate the source / drain doped layer 209 and the substrate 200 to prevent leakage and improve the performance of the semiconductor structure.

[0119] refer to Figures 28 to 30 , Figure 28 and Figure 25 The view orientation is consistent. Figure 29 and Figure 26 The view orientation is consistent. Figure 30 and Figure 27 With the view consistent with the defense line, after forming the groove 214, a dielectric layer 311 is formed on the substrate 200. The dielectric layer 311 covers the surface of the source / drain doped layer 209 and exposes the top surface of the dummy gate structure 206. The dummy gate structure 206 is removed, and a gate opening (not shown) is formed in the dielectric layer 311. A gate structure 312 is formed in the gate opening.

[0120] Accordingly, another embodiment of the present invention also provides a semiconductor structure.

[0121] refer to Figures 28 to 30 The semiconductor structure includes: a substrate 200; a buffer layer 203 located on the substrate 200; a fin 204 located on the buffer layer 203; an isolation layer located on the substrate between adjacent fins, the isolation layer covering the sidewall surface of the buffer layer; a gate structure 312 located on the substrate 200 and spanning the fin 204, the gate structure 312 covering part of the top and sidewall surfaces of the fin 204 and the top surface of the isolation layer; source / drain doped layers 209 located within the fins 204 on both sides of the gate structure 312; and a recess 214 located between the source / drain doped layers 209 and the substrate 200, the recess 214 serving as an air gap layer.

[0122] In this embodiment, the spacer layer is an air gap layer.

[0123] In this embodiment, a dielectric layer 311 is also included, located on the substrate 200, and the dielectric layer 311 covers the sidewall surface of the gate structure 312.

[0124] In this embodiment, the dielectric layer 311 also fills part of the groove 214. The dielectric layer 311 in the groove 214 and the air in the groove 214 work together to isolate the source / drain doped layer 209 and the substrate 200.

[0125] In this embodiment, a sidewall 208 is also included, located on the sidewall surface of the gate structure 212.

[0126] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A buffer layer located on the substrate, the buffer layer being made of silicon-germanium; A fin, located on the buffer layer, wherein the fin material comprises silicon germanium, and the molar percentage concentration of germanium in the fin material is greater than the molar percentage concentration of germanium in the buffer layer material; An isolation layer is located on the substrate between adjacent fins, the top surface of the isolation layer being lower than the top surface of the fins; A gate structure is located on the substrate and spans the fin, the gate structure covering a portion of the top and sidewall surfaces of the fin and the top surface of the isolation layer; The source / drain doped layer is located in the fins on both sides of the gate structure, and the source / drain doped layer contains doped ions, which are P-type ions; A spacer layer is formed by oxidizing a portion of the buffer layer or by directly removing a portion of the buffer layer. The spacer layer is located between the source / drain doped layer and the substrate, while the buffer layer below the gate structure is retained.

2. The semiconductor structure as described in claim 1, characterized in that, The spacer layer includes an insulating layer or an air gap layer.

3. The semiconductor structure as described in claim 1, characterized in that, The buffer layer material has a germanium molar percentage concentration of 5% to 50%.

4. The semiconductor structure as described in claim 2, characterized in that, The insulating layer is made of silicon oxide and germanium oxide.

5. The semiconductor structure as described in claim 1, characterized in that, The molar percentage concentration of germanium in the material of the fin is greater than or equal to 20%.

6. The semiconductor structure as described in claim 2, characterized in that, When the spacer layer is an insulating layer, it further includes a protective layer located on the surface of the source / drain doped layer.

7. The semiconductor structure as described in claim 6, characterized in that, The material of the protective layer includes silicon.

8. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A buffer layer is formed on the substrate, the material of the buffer layer including silicon germanium; A fin is formed on the buffer layer, the fin material comprising silicon germanium, wherein the molar percentage concentration of germanium in the fin material is greater than the molar percentage concentration of germanium in the buffer layer material; An isolation layer is formed on the substrate between adjacent fins, the isolation layer covering the sidewall surface of the buffer layer; A pseudo-gate structure is formed on the substrate, the pseudo-gate structure spanning the fin; Source / drain doped layers are formed in the fins on both sides of the pseudo-gate structure, and the source / drain doped layers contain doped ions, which are P-type ions; A portion of the buffer layer is oxidized or a portion of the buffer layer is removed to form a spacer layer between the source / drain doped layer and the substrate, while retaining the buffer layer beneath the dummy gate structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The spacer layer includes an insulating layer or an air gap layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the spacer layer, the process further includes etching a portion of the isolation layer until the sidewall surface of the buffer layer is exposed.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, When the spacer layer is an insulating layer, the method of forming the insulating layer includes: oxidizing the exposed buffer layer to form an insulating layer between the source / drain doped layer and the substrate.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The oxidation treatment includes furnace tube process or rapid thermal annealing process.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before oxidizing the buffer layer, the method further includes forming a protective layer on the source / drain doped layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The material of the protective layer includes silicon.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, When the spacer layer is an air gap layer, the method of forming the air gap layer includes: removing the exposed buffer layer and forming a groove between the source / drain doped layer and the substrate, the groove serving as an air gap layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process for removing the exposed buffer layer includes a selective wet etching process, wherein the process parameters of the selective wet etching process include using a hydrochloric acid solution with a concentration of 3% to 20%.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, The buffer layer material has a germanium molar percentage concentration of 5% to 50%.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The molar percentage concentration of germanium in the fin material is greater than the molar percentage concentration of germanium in the buffer layer material, and the molar percentage concentration of germanium in the fin material is greater than or equal to 20%.

19. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the spacer layer, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the surface of the source / drain doped layer and exposing the top surface of the dummy gate structure; removing the dummy gate structure and forming a gate opening within the dielectric layer; and forming a gate structure within the gate opening.

Images