Semiconductor devices and manufacturing methods thereof

Abstract

The embodiments mainly provide a semiconductor device and a method for manufacturing the same, which can improve the reverse recovery characteristics and reliability of the built-in diode. According to the embodiments, the semiconductor device includes: an upper electrode; a lower electrode; a substrate located between the upper electrode and the lower electrode; a buried electrode portion located between the substrate and the upper electrode, having a gate electrode; and a silicon layer located between the substrate and the upper electrode, having a mesa portion adjacent to the buried electrode portion, a first region located between the mesa portion and the substrate, and a second region located between the buried electrode portion and the substrate, wherein the energy level density of the first region is higher than the energy level density of the second region.

Description

[0001] Related applications:

[0002] This application is based on Japanese Patent Application No. 2021-45548 (filed on March 19, 2021) and enjoys priority thereto. This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation methods mainly relate to semiconductor devices and their manufacturing methods. Background Technology

[0004] In a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), there exists an internal diode that differs from the MOSFET's operating section. Improving the reverse recovery characteristics of this internal diode can help increase circuit efficiency. One known method for improving the reverse recovery characteristics of the internal diode is irradiation with high-energy particles and control of the carrier lifetime in the drift layer. Summary of the Invention

[0005] The embodiments provide a semiconductor device and a method for manufacturing the same, which can improve the reverse recovery characteristics of the built-in diode and achieve high reliability.

[0006] According to an embodiment, a semiconductor device includes: an upper electrode; a lower electrode; a substrate located between the upper electrode and the lower electrode; a buried electrode portion located between the substrate and the upper electrode, having a gate electrode; and a silicon layer located between the substrate and the upper electrode, having a mesa portion adjacent to the buried electrode portion, a first region located between the mesa portion and the substrate, and a second region located between the buried electrode portion and the substrate, wherein the energy level density of the first region is higher than the energy level density of the second region. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0008] Figure 2 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0009] Figure 3 This is a graph showing the simulation results of the dependence of the reverse recovery charge Qrr on the width of the lifetime control region.

[0010] Figure 4A It is a graph showing the relationship between proton irradiation energy and transmission range. Figure 4BIt is a graph showing the relationship between the electron irradiation energy and the transmission range.

[0011] Figure 5 This is a graph showing the simulation results of the dependence of the reverse recovery charge Qrr on the longitudinal position of the lifetime control region. Detailed Implementation

[0012] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in each drawing, the same reference numerals will be used to label the same structures. In the following embodiments, the first conductivity type will be described as n-type and the second conductivity type as p-type, but it is also possible to describe the first conductivity type as p-type and the second conductivity type as n-type.

[0013] Figure 1 This is a schematic cross-sectional view of the semiconductor device 1 according to the embodiment.

[0014] Semiconductor device 1 includes: an upper electrode 50; a lower electrode 60; a substrate 10 located between the upper electrode 50 and the lower electrode 60; a buried electrode portion 30 located between the substrate 10 and the upper electrode 50, having a gate electrode 31; and a silicon layer 20 located between the substrate 10 and the upper electrode 50. Semiconductor device 1 is a vertical semiconductor device in which current flows in the direction (longitudinal) connecting the upper electrode 50 and the lower electrode 60 by controlling the gate electrode 31.

[0015] A silicon layer 20 is disposed on a substrate 10. A lower electrode 60 is disposed on the back side of the substrate 10. The substrate 10 is a silicon substrate. A plurality of trenches are formed in the silicon layer 20, and buried electrode portions 30 are disposed in the trenches. The silicon layer 20 has a plurality of mesa portions 11a adjacent to the buried electrode portions 30. By forming trenches in the silicon layer 20, mesa portions 11a adjacent to the trenches are also formed. The trenches do not reach the substrate 10.

[0016] The electrode portion 30 and the platform portion 11a are embedded, for example in... Figure 1 The middle part extends in a stripe pattern in the direction that runs through the paper. Alternatively, the embedded electrode part 30 (groove) can also be cylindrical or hexagonal prism shaped.

[0017] The silicon layer 20 has a drift layer 11, a base layer 12, and a source layer 13 disposed on the substrate 10. The substrate 10 and the drift layer 11 are n-type. The n-type impurity concentration of the drift layer 11 is lower than that of the substrate 10.

[0018] The platform surface 11a includes: a portion of a drift layer 11; a p-type base layer 12 disposed on the portion of the drift layer 11; and an n-type source layer 13 disposed on the surface of the base layer 12. The n-type impurity concentration of the source layer 13 is higher than that of the drift layer 11.

[0019] Furthermore, the drift layer 11 has: a first region 11b located between the mesa portion 11a and the substrate 10; and a second region 11c located between the buried electrode portion 30 and the substrate 10. The first region 11b is located below the mesa portion 11a, and the second region 11c is located below the buried electrode portion 30. The first region 11b and the second region 11c are continuous in the direction (lateral) in which the buried electrode portion 30 is adjacent to the mesa portion 11a. Figure 1 In the diagram, for ease of explanation, the boundary between the first region 11b and the second region 11c is represented by a dashed line.

[0020] For example, two gate electrodes 31 are provided in a buried electrode portion 30. The gate electrodes 31 are positioned opposite the side of the substrate 12 through a gate insulating film 42. The gate insulating film 42 is disposed between the side of the substrate 12 and the gate electrodes 31.

[0021] By applying a voltage above a threshold to the gate electrode 31, an n-type channel (inversion layer) can be formed in the portion of the substrate 12 opposite to the gate electrode 31.

[0022] Furthermore, the buried electrode portion 30 has a field plate electrode 32. The field plate electrode 32 is located approximately at the center of the width direction (lateral direction) of the buried electrode portion 30. The field plate electrode 32 extends within the buried electrode portion 30 below the gate electrode 31. The bottom of the field plate electrode 32 is located closer to the substrate 10 than the bottom of the gate electrode 31. In this embodiment, the buried electrode portion 30 has both a gate electrode 31 and a field plate electrode 32, but it may also have a gate electrode 31 without the field plate electrode 32.

[0023] An insulating film 41 is disposed between the field plate electrode 32 and the drift layer 11. An insulating film 43 is disposed between the field plate electrode 32 and the gate electrode 31.

[0024] The field plate electrode 32 is electrically connected to the upper electrode 50, for example. Alternatively, the field plate electrode 32 may also be electrically connected to the gate electrode 31. In the off state, when a voltage above a threshold is no longer applied to the gate electrode 31, the field plate electrode 32 smooths out the electric field distribution of the drift layer 11.

[0025] The upper electrode 50 is disposed above the buried electrode portion 30 and the mesa portion 11a. An insulating film 44 is disposed between the gate electrode 31 and the upper electrode 50, and between the field plate electrode 32 and the upper electrode 50. The upper electrode 50 is connected to the upper surface of the mesa portion 11a (the upper surface of the source layer 13 and the upper surface of the base layer 12). Alternatively, a portion of the upper electrode 50 may be disposed within a recess formed on the upper surface of the mesa portion 11a, and the upper electrode 50 may be connected to the side surface of the source layer 13.

[0026] The manufacturing method of semiconductor device 1 will now be described.

[0027] After forming a silicon layer 20 and a buried electrode portion 30 on the substrate 10, as Figure 2 As shown, the upper electrode 50 is formed on the embedded electrode portion 30 and the platform portion 11a. At this time, the upper electrode 50 has a first portion 51 located on the platform portion 11a and a second portion 52 located on the embedded electrode portion 30.

[0028] The thickness of the second part 52 (the shortest distance between the upper surface of the insulating film 44 embedded in the electrode portion 30 and the upper surface of the second part 52) ​​is greater than the thickness of the first part 51 (the shortest distance between the upper surface of the platform portion 11a and the upper surface of the first part 51). Undulations are formed on the upper surface of the upper electrode 50. For example, Cu is formed as the upper electrode 50 using electroplating. Alternatively, the material of the upper electrode 50 can also be Al.

[0029] Using the upper electrode 50 with this film thickness difference as a mask, energy particles 100 are irradiated from one side of the upper electrode 50. The energy particles 100 are protons or electrons.

[0030] Energy particles 100 penetrate the first portion 51 of the upper electrode 50 and the mesa 11a to reach the region below the mesa 11a in the drift layer 11. Thus, in Figure 1 Energy levels (lifetime suppression factors) are formed in the first region 11b beneath the mesa 11a shown, serving as recombination centers for electrons and holes. During reverse recovery operation of the built-in diode (a PIN diode composed of a base layer 12, a drift layer 11, and a substrate 10) of the semiconductor device 1, one type of charge carrier (electrons and holes) remaining in the drift layer 11 is captured by the energy levels formed in the first region 11b, while the other type of charge carrier encounters and recombines with it. This reduces the reverse recovery charge of the built-in diode and improves its reverse recovery characteristics. The first region 11b functions as a lifetime control region during the reverse recovery operation of the built-in diode.

[0031] On the other hand, since the second portion 52 of the upper electrode 50 above the embedded electrode portion 30 is thicker than the first portion 51, it is possible to suppress energy particles from reaching the embedded electrode portion 30. Consequently, the energy level density of the first region 11b below the mesa 11a is higher than the energy level density of the second region 11c below the embedded electrode portion 30. For example, the energy levels can be measured using the PL (photoluminescence) method. Furthermore, the silicon crystal defect density of the first region 11b is higher than that of the second region 11c. Moreover, when protons are irradiated as energy particles, the hydrogen concentration in the first region 11b is higher than that in the second region 11c.

[0032] When high-energy particles are irradiated into the insulating film, defects are formed, which can cause threshold voltage variations, withstand voltage variations, and reduced insulation reliability of the insulating film. To address this, according to this embodiment, the thickness difference of the upper electrode 50 can be used to suppress the arrival of energy particles in the buried electrode portion 30. This suppresses defects in the gate insulating film 42, insulating films 41, 43, and 44 of the buried electrode portion 30. According to this embodiment, a semiconductor device that improves the reverse recovery characteristics of the built-in diode while maintaining high reliability can be provided. Furthermore, annealing after irradiation by energy particles is unnecessary to repair defects in the insulating film of the buried electrode portion 30. This prevents characteristic variations caused by annealing and can reduce the number of processes.

[0033] Furthermore, in this embodiment, since an energy level can be locally formed in the first region 11b below the mesa 11a by having a film thickness difference in the upper electrode 50, one of the structural elements of the semiconductor device 1, the process is not complicated.

[0034] After irradiation with energy particles, it is desirable to flatten the upper surface of the upper electrode 50, from the viewpoint of facilitating the connection between the upper electrode 50 and the external circuit. This flattening can be achieved by aligning the upper surface with that of the first portion 51, or by embedding a metallic material in the recess between the second portions 52. Alternatively, the upper surface of the upper electrode 50 may not be flattened, but rather maintained in a manner similar to... Figure 2 The unevenness shown.

[0035] Figure 3 This is a graph showing the simulation results of the dependence of the reverse recovery charge Qrr on the width of the lifetime control region.

[0036] Figure 3 The horizontal axis of the chart represents the... Figure 2 The width of the distance from center C1 to center C2 in the width direction of the embedded electrode portion 30 is taken as the starting point in the width direction of the platform surface 11a. This represents the relative value when the width (distance) from center C1 to center C2 is set to 1. The reverse recovery charge Qrr on the vertical axis represents the relative value when the width of the lifetime control region is 0, that is, when no energy level is formed on the drift layer 11, Qrr is 1.0.

[0037] from Figure 2 Starting from the center C1 of the platform surface 11a shown, the width of the area not extending below the embedded electrode portion 30 is... Figure 3The diagram corresponds to a lifetime control region width of 0.5. That is, even if no energy level is formed below the embedded electrode portion 30, as long as an energy level is locally formed in the region below the platform portion 11a, Qrr can be reduced sufficiently compared to when the lifetime control region width is 0.

[0038] The film thickness of the first part 51 and the second part 52 of the upper electrode 50 are determined according to the type of metal constituting the upper electrode 50, the type of energy particles irradiated, and the irradiation energy.

[0039] Figure 4A It is a graph showing the relationship between the proton irradiation energy (horizontal axis) and the transmission range (vertical axis). Figure 4B This is a graph showing the relationship between the electron beam's irradiation energy (horizontal axis) and its transmission range (vertical axis). Figure 4A and Figure 4B In the various charts, solid lines represent the transmission range in Cu, dashed lines represent the transmission range in Si, and dashed lines represent the transmission range in Al.

[0040] The transmission ranges of protons and electrons in Si and Al are approximately the same. Therefore, when using Al as the material for the upper electrode 50, by providing a second portion 52 above the buried electrode portion 30 with a film thickness equal to the desired depth to which protons or electrons will reach in the silicon layer 20, it is possible to suppress the arrival of protons or electrons in the buried electrode portion 30.

[0041] Furthermore, the transmission range of both protons and electrons in Cu is shorter than that in Si. Therefore, when using Cu as the material for the upper electrode 50, the second portion 52, which has a smaller film thickness than the upper electrode 50 in Al, can suppress the arrival of protons or electrons in the buried electrode portion 30. For example, when it is desired that protons reach a depth of 8 μm in the silicon layer 20, it is possible to... Figure 4A The diagram shows that the thickness of the second part of Cu, 52, is set to about 4 μm.

[0042] Figure 5 This is a graph showing the simulation results illustrating the dependence of the reverse recovery charge Qrr on the longitudinal position of the lifetime control region. The width of the lifetime control region is... Figure 2 The calculation is performed under the condition of 0.5.

[0043] Figure 5 The horizontal axis of the graph shows the location of the lifetime control region relative to the boundary (0) between the substrate 10 and the drift layer 11. The positive direction is the drift layer 11 side, and the negative direction is the substrate 10 side. Furthermore, the vertical axis represents the relative value when Qrr is set to 1.0 when no energy level is formed.

[0044] exist Figure 5In the diagram, the boundary between substrate 10 and drift layer 11 is used as a reference. When a lifetime control region is formed in the positive direction, i.e., on the drift layer 11 side, the reduction effect of Qrr is confirmed. In other words, by forming an energy level (lifetime suppression factor) in the region containing drift layer 11, the reverse recovery characteristics of the built-in diode can be improved.

[0045] Furthermore, when the depletion layer extending into the drift layer 11 reaches the energy level (lifetime suppression factor), it may become a cause of leakage current in the off state of the MOSFET operating section. Therefore, it is desirable that the depth to which the energy particles in the drift layer 11 reach is a depth that the depletion layer extending into the drift layer 11 cannot reach.

[0046] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and also within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, have: Upper electrode; Lower electrode; A substrate of the first conductivity type is located between the upper electrode and the lower electrode; An embedded electrode portion is located between the substrate and the upper electrode, and has a gate electrode; as well as A silicon layer, located between the substrate and the upper electrode, has a mesa portion adjacent to the buried electrode portion and a drift layer of a first conductivity type in direct contact with the substrate of the first conductivity type. The drift layer includes a first region located between the mesa portion and the substrate, and a second region located between the buried electrode portion and the substrate. The first region and the second region are continuous in the direction in which the embedded electrode portion and the platform portion are adjacent to each other. The energy level density of the first region is higher than that of the second region, and the peak energy level density of the drift layer is located in the first region.

2. The semiconductor device according to claim 1, wherein, The crystal defect density in the first region is higher than that in the second region.

3. The semiconductor device according to claim 1, wherein, The hydrogen concentration in the first region is higher than that in the second region.

4. The semiconductor device according to claim 1, wherein, Multiple embedded electrode portions and multiple table-shaped extensions.

5. The semiconductor device according to claim 1, wherein, The embedded electrode portion has a field plate electrode, which is electrically connected to the upper electrode or the gate electrode.

6. The semiconductor device according to claim 1, wherein, The upper electrode is connected to the platform surface.

7. A method for manufacturing a semiconductor device, wherein, include: The process of forming a buried electrode portion having a gate electrode and a silicon layer on a substrate, wherein the silicon layer has a mesa portion adjacent to the buried electrode portion; In the process of forming an upper electrode on the embedded electrode portion and on the silicon layer, the upper electrode has: a first portion located on the mesa portion and a second portion located on the embedded electrode portion and thicker than the first portion; as well as The process of using the upper electrode as a mask to irradiate energy particles from one side of the upper electrode, so that the energy particles reach the region below the mesa in the silicon layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein, The energy particle is a proton.

9. The method for manufacturing a semiconductor device according to claim 7, wherein, The energy particles are electrons.

10. The method of manufacturing a semiconductor device according to claim 7, wherein, The material of the upper electrode is Cu.

11. The method of manufacturing a semiconductor device according to claim 7, wherein, The material of the upper electrode is Al.

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