Gallium nitride heterojunction bipolar phototransistor and method of manufacturing the same

Abstract

This invention discloses a gallium nitride heterojunction bipolar photonic transistor and its fabrication method, comprising: a substrate; and a nucleation layer and a buffer layer sequentially disposed on the substrate; a collector region disposed on the buffer layer; a collector electrode disposed at one end of the collector region; a lower quantum well layer disposed at the other end of the collector region; a gap exists between the collector electrode and the lower quantum well layer; a base region disposed on the lower quantum well layer; a base electrode disposed at one end of the base region; wherein the base electrode and the collector electrode are disposed on the same side; an upper quantum well layer disposed at the other end of the base region; a gap exists between the base electrode and the upper quantum well layer; an emitter region disposed on the upper quantum well layer; and an emitter electrode disposed at one end of the emitter region; the emitter electrode and the collector electrode are disposed on different sides; wherein the materials of the collector region, the lower quantum well layer, the base region, the upper quantum well layer, and the emitter region are all group III nitrides. This invention simultaneously possesses the functions of a transistor and an LED.

Description

Technical Field

[0001] This invention belongs to the field of electronic and optoelectronic device technology, specifically relating to a gallium nitride heterojunction bipolar photonic transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), representing wide bandgap materials, is the third generation of semiconductor materials after silicon (Si) and gallium arsenide (GaAs). It possesses superior properties such as high frequency, high efficiency, high power, high voltage resistance, high temperature resistance, and strong radiation resistance, meeting the major national strategic needs of energy conservation and emission reduction, intelligent manufacturing, and information security. It is a key core material and electronic component supporting the independent innovation and transformation and upgrading of industries such as next-generation mobile communications, new energy vehicles, high-speed rail, and the energy internet, and has become a focal point of global semiconductor technology and industry competition. Compared with Si and GaAs, gallium nitride (GaN) has a wider bandgap (3.4 eV), a stronger critical breakdown field, and a higher electron mobility, thus attracting widespread attention from researchers both domestically and internationally. It has significant advantages and potential in power electronic devices and high-frequency power devices, and can be widely used in the fabrication of LEDs and chips containing these LEDs.

[0003] The most significant difference between heterojunction bipolar transistors (HBTs) and homojunction transistors (HBTs) is the wide emitter bandgap. The emitter region uses a semiconductor with a wider bandgap than the base region, creating different energy barriers for electrons and holes. This suppresses minority carrier injection from the base to the emitter, improving the injection efficiency and resulting in higher gain. Due to the different bandgap widths of the emitter and base materials, HBTs exhibit conduction band and valence band discontinuities at the heterojunction interface. The valence band discontinuity blocks reverse injection of holes from the base to the emitter, significantly increasing the electron injection efficiency and current gain of the HBT. HBTs primarily use compound semiconductor materials, which have a wider bandgap and higher electron mobility and saturation velocity. Therefore, HBTs have high switching speeds and cutoff frequencies. Furthermore, the large bandgap of the collector material in HBTs increases the reverse breakdown voltage, thereby increasing output power.

[0004] The light-emitting mechanism of an LED is to convert electrical energy into light energy, making it an electroluminescent solid-state device. Its core structure is a PN junction chip, which consists of electrodes (pins) and an optical system. The light-emitting mechanism can be summarized as follows: charge carriers recombine under forward voltage conditions, resulting in radiation and light energy transfer. When a forward voltage is applied across the PN junction, the potential barrier decreases, causing positive charges (holes) in the P-region to diffuse into the N-region, and negative charges (electrons) in the N-region to diffuse into the P-region. This results in an accumulation of unbalanced charges in both regions. For the PN junction, these partially unstable charge carriers caused by the injected current cause holes in the valence band to recombine with electrons in the conduction band. The energy generated by this recombination is radiated outwards as photons, thus emitting light.

[0005] Transistor current amplification principle: Transistors have three operating states: amplification state, saturation state, and cutoff state. In analog circuits, the amplification state is mainly used. In digital logic circuits, the saturation and cutoff states are primarily used. The operating state of a transistor is closely related to external conditions. If the emitter junction is forward biased and the collector junction is reverse biased, the transistor is in the amplification state, or in other words, it operates in the amplification region. If both the emitter and collector junctions are forward biased, the transistor is in the saturation state, or in other words, it operates in the saturation region. If the emitter junction is reverse biased, the transistor is in the cutoff state regardless of the collector junction bias, and it operates in the cutoff region. Let's take an NPN transistor as an example to illustrate the characteristics of the amplification state. First, with the emitter as the potential reference point, a forward bias is applied to the emitter junction. Since the emitter region contains a large number of charge carriers—free electrons—under the action of a forward voltage, a large number of electrons will flow from the emitter region to the base region, forming a current. Because the collector junction is reverse-biased, it becomes thicker, bringing it closer to the emitter junction. Therefore, a situation arises where, under the forward bias of the emitter junction, a large number of electrons traveling from the emitter region to the base region are attracted by the reverse bias of the collector junction, crossing the base region to reach the collector region, forming the collector current. Only a small number of electrons recombine with holes in the base region (because the number of holes in the base region is very small), forming the base current. The greater the forward bias applied to the emitter junction, the more electrons travel from the emitter region to the base region per unit time, and the more electrons cross the base region to reach the collector region under the reverse bias of the collector junction. Furthermore, numerous experiments have shown that once a transistor is manufactured, under amplification conditions, the number of electrons crossing the base region to reach the collector region is always in a certain proportion to the number of electrons recombinating with holes in the base region. Moreover, the collector current is much larger than the base current.

[0006] It is evident that while gallium nitride materials, heterojunction bipolar transistors (HBTs), LEDs, and transistors all play important roles in their respective fields, research combining them is scarce. Therefore, how to combine their structural advantages to fabricate photonic transistors that simultaneously function as transistors and LEDs has become a current research hotspot. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a gallium nitride heterojunction bipolar photonic transistor and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0008] In a first aspect, embodiments of the present invention provide a gallium nitride heterojunction bipolar photonic transistor, comprising:

[0009] A substrate; and a nucleation layer and a buffer layer sequentially disposed on the upper surface of the substrate;

[0010] A current collection area is disposed on the upper surface of the buffer layer;

[0011] A collector electrode is disposed at one end of the upper surface of the collector region;

[0012] A lower multiple quantum well layer is disposed at the other end of the upper surface of the current collector region; there is a gap between the current collector and the lower multiple quantum well layer;

[0013] The base region is disposed on the upper surface of the lower multi-quantum well layer;

[0014] A base electrode is disposed at one end of the upper surface of the base region; wherein the base electrode and the collector electrode are disposed on the same side;

[0015] An upper quantum well layer is disposed at the other end of the upper surface of the base region; there is a gap between the base and the upper quantum well layer;

[0016] The emission region is located on the upper surface of the upper multi-quantum-well layer;

[0017] An emitter is disposed at one end of the upper surface of the emitter region; the emitter and the collector are disposed on different sides.

[0018] The materials of the current collector region, the lower multi-quantum well layer, the base region, the upper multi-quantum well layer, and the emitter region are all group III nitrides.

[0019] In one embodiment of the present invention, the material used for the collector region includes gallium nitride or indium gallium nitride; the doping type of the collector region is N-type, and the thickness is 30nm to 2000nm.

[0020] In one embodiment of the present invention, the base region is made of gallium nitride or indium gallium nitride; the base region is p-type doped and has a thickness of 10 nm to 300 nm.

[0021] In one embodiment of the present invention, the material used for the emission region includes gallium nitride or aluminum gallium nitride; the doping type of the emission region is N-type, and the thickness is 50nm to 1000nm.

[0022] In one embodiment of the present invention, the lower multiple quantum well layer includes a plurality of spaced lower barrier layers and lower well layers; the thickness of each lower barrier layer is 3nm to 20nm, the thickness of each lower well layer is 1nm to 5nm, and the doping type of the lower barrier layer and the lower well layer is P-type.

[0023] In one embodiment of the present invention, the material of the lower barrier layer is aluminum gallium nitride with an aluminum content of 0.05 to 0.15, and the material of the lower potential well layer is gallium nitride; or, the material of the lower barrier layer is gallium nitride, and the material of the lower potential well layer is indium gallium nitride with an indium content of 0.05 to 0.25; or, the material of the lower barrier layer is indium gallium nitride, the material of the lower potential well layer is indium gallium nitride, and the indium content of the lower barrier layer is lower than that of the lower potential well layer.

[0024] In one embodiment of the present invention, the upper multiple quantum well layer includes several spaced upper barrier layers and upper well layers; the thickness of each upper barrier layer is 3nm to 20nm, the thickness of each upper well layer is 1nm to 5nm, and the doping type of the upper barrier layer and the upper well layer is P-type.

[0025] In one embodiment of the present invention, the upper barrier layer is made of aluminum gallium nitride with an aluminum content of 0.05 to 0.15, and the upper well layer is made of gallium nitride; or, the upper barrier layer is made of gallium nitride, and the upper well layer is made of indium gallium nitride with an indium content of 0.05 to 0.25; or, the upper barrier layer is made of indium gallium nitride, the upper well layer is made of indium gallium nitride, and the indium content of the upper barrier layer is lower than that of the upper well layer.

[0026] Secondly, embodiments of the present invention provide a method for fabricating a gallium nitride heterojunction bipolar photonic transistor, comprising:

[0027] Select a substrate;

[0028] A core layer and a buffer layer are sequentially grown on the substrate;

[0029] A current collector region, a lower multi-quantum well layer, a base region, an upper multi-quantum well layer, and an emitter region are sequentially grown on the buffer layer.

[0030] Etch away part of the emitter region and the upper multi-quantum-well layer until the base region is exposed;

[0031] On the exposed base region, a portion of the emitter region, the lower quantum well layer, the base region, and the lower quantum well layer are etched away until the collector region is exposed;

[0032] Emitter metal and collector metal are deposited in the emitter region and the collector region, respectively, to form the emitter and the collector.

[0033] A base metal is deposited in the base region to form the base electrode.

[0034] In one embodiment of the present invention, the materials of the current collector region, the lower multiple quantum well layer, the base region, the upper multiple quantum well layer and the emitter region are all group III nitrides.

[0035] The beneficial effects of this invention are:

[0036] The gallium nitride heterojunction bipolar photonic transistor proposed in this invention is a novel transistor that combines the functions of a transistor and an LED. The base can be used to control the transistor's on-state current and the LED's brightness. Since the transistor has current amplification capability when operating in the linear region, the current flowing into the transistor's collector and emitter can be controlled by controlling the magnitude of the current flowing into the transistor's base, thereby regulating the brightness of the two LEDs formed by the two multi-quantum-well layers, provided that the emitter junction is forward biased and the collector junction is reverse biased. Furthermore, the heterojunction structure suppresses minority carrier injection from the base region to the emitter region, improving the emitter injection efficiency and achieving higher gain.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a gallium nitride heterojunction bipolar photonic transistor provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the structure of the lower multi-quantum well layer provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the structure of the multiple quantum well layer provided in the embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the fabrication process of a gallium nitride heterojunction bipolar photonic transistor provided in an embodiment of the present invention;

[0042] Figures 5(a) to 5(g) This is a schematic diagram of the structure corresponding to the fabrication process of a gallium nitride heterojunction bipolar photonic transistor provided in an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1-Substrate; 2-Nucleation layer; 3-Buffer layer; 4-Collector region; 5-Lower multiple quantum well layer; 6-Base region; 7-Upper multiple quantum well layer; 8-Emitter region; 9-Collector; 10-Emitter; 11-Base; 51-Lower barrier layer; 52-Lower potential well layer; 71-Upper barrier layer; 72-Upper potential well layer. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0046] Existing devices typically involve the separate fabrication of transistors and LEDs, with limited research combining them. Through research, the inventors, aiming to expand the application of heterojunction bipolar transistors (HBTs) in photonic crystallography and extend their application to the field of photonic transistors, proposed a novel approach. This invention leverages the inherent advantages of gallium nitride (GaN) materials and HBTs, combined with the light-emitting mechanism of LEDs and the current amplification principle of transistors. Specifically, it proposes a new structure for a GaN HBT photonic transistor. Based on the amplification principle of transistors, it aims to control the current flowing into the collector and emitter by controlling the base current, thereby modulating the brightness of the LED and enabling its application in the field of photonic transistors. This provides researchers with a new direction for consideration. For details, please refer to [link to relevant documentation]. Figure 1 This invention provides a gallium nitride heterojunction bipolar photonic transistor, comprising:

[0047] Substrate 1; and nucleation layer 2 and buffer layer 3 sequentially disposed on the upper surface of substrate 1;

[0048] The collector area 4 is located on the upper surface of the buffer layer 3;

[0049] Collector 9 is disposed at one end of the upper surface of collector region 4;

[0050] The lower quantum well layer 5 is disposed at the other end of the upper surface of the collector region 4; there is a gap between the collector electrode 9 and the lower quantum well layer 5.

[0051] Base region 6 is located on the upper surface of the lower multi-quantum well layer 5;

[0052] The base 11 is disposed at one end of the upper surface of the base region 6; wherein the base 11 and the collector 9 are disposed on the same side;

[0053] The upper quantum well layer 7 is disposed at the other end of the upper surface of the base region 6; there is a gap between the base 11 and the upper quantum well layer 7;

[0054] The emission region 8 is located on the upper surface of the upper multi-quantum well layer 7;

[0055] The emitter 10 is disposed at one end of the upper surface of the emitter region 8; the emitter 10 and the collector 9 are disposed on different sides;

[0056] Among them, the materials of collector region 4, lower multi-quantum well layer 5, base region 6, upper multi-quantum well layer 7 and emitter region 8 are all group III nitrides.

[0057] In one embodiment of the present invention, the substrate 1 is preferably made of sapphire, silicon, or silicon carbide, specifically selected based on a combination of cost and performance requirements, and its thickness is 100 μm to 1000 μm. More preferably, the substrate 1 is made of sapphire with a thickness of 100 μm.

[0058] In one embodiment of the present invention, the nucleation layer 2 is made of aluminum nitride or low-temperature (500°C to 650°C) gallium nitride, specifically selected based on a combination of cost and performance requirements, and its thickness is 20nm to 300nm. More preferably, the nucleation layer 2 is made of gallium nitride with a thickness of 30nm.

[0059] In one embodiment of the present invention, the buffer layer 3 preferably uses aluminum gallium nitride, gallium nitride, or a combination of aluminum gallium nitride and gallium nitride as the material, specifically selected based on a comprehensive consideration of cost and performance requirements, and its thickness is 100nm to 3000nm. More preferably, the buffer layer 3 uses gallium nitride with a thickness of 80nm.

[0060] By introducing a nucleation layer 2, this embodiment of the invention can provide nucleation centers with the same q orientation for the subsequent growth of gallium nitride layers, release the mismatch stress caused by the lattice mismatch between gallium nitride and substrate 1, and the thermal stress caused by the mismatch of thermal expansion coefficients, thus providing a flat nucleation surface for further epitaxial layer growth.

[0061] In one embodiment of the present invention, the collector region 4 is preferably made of gallium nitride or indium gallium nitride; the doping type of the collector region 4 is N-type, and the thickness is 30 nm to 2000 nm. More preferably, the collector region 4 is made of N-doped gallium nitride with a thickness of 850 nm, the dopant is Si, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 Ohmic contact is achieved in collector region 4.

[0062] In one embodiment of the present invention, the base region 6 preferably uses gallium nitride or indium gallium nitride as its material; the base region 6 is p-type doped and has a thickness of 10 nm to 300 nm. More preferably, the base region 6 uses p-doped gallium nitride with a thickness of 100 nm, the dopant being Mg, and the doping concentration being 1 × 10⁻⁶. 19 ~5×10 19 cm-3 Ohmic contact is achieved in base region 4.

[0063] In one embodiment of the present invention, the emitter region 8 is preferably made of gallium nitride or aluminum gallium nitride; the doping type of the emitter region 8 is N-type, and the thickness is 50 nm to 1000 nm. More preferably, the emitter region 8 is an N-doped aluminum gallium nitride with a thickness of 100 nm, the dopant being Si, and the doping concentration being 1 × 10⁻⁶. 19 cm -3 Ohmic contact is achieved in launch zone 4.

[0064] To enhance the ohmic contact of the collector region 4, the emitter region 8 further includes an N-type heavily doped gallium nitride cap layer with a thickness of 50 nm to 100 nm. More preferably, a 100 nm thick gallium nitride cap layer is used, with Si as the dopant impurity and a doping concentration of 1 × 10⁻⁶. 20 cm -3 .

[0065] In one embodiment of the present invention, please refer to Figure 2 The lower quantum well layer 5 includes several spaced lower barrier layers 51 and lower well layers 52. Preferably, the thickness of each lower barrier layer 51 is 3 nm to 20 nm, and the thickness of each lower well layer 52 is 1 nm to 5 nm. Both the lower barrier layer 51 and the lower well layer 52 are p-type doped. More preferably, the thickness of each lower barrier layer 51 is 5 nm, and the thickness of each lower well layer 52 is 2 nm.

[0066] In one embodiment of the present invention, the lower barrier layer 51 is preferably made of aluminum gallium nitride with an aluminum content of 0.05 to 0.15% (percentage), and the lower well layer 52 is made of gallium nitride; or, the lower barrier layer 51 is made of gallium nitride, and the lower well layer 52 is made of indium gallium nitride with an indium content of 0.05 to 0.25%; or, the lower barrier layer 51 is made of indium gallium nitride, the lower well layer 52 is made of indium gallium nitride, and the indium content of the lower barrier layer 51 is lower than that of the lower well layer 52. More preferably, the lower well layer 52 is made of p-doped gallium nitride, and the lower well layer 52 is made of indium gallium nitride with an indium content of 0.15% (15%).

[0067] correspond Figure 2 The lower quantum well layer 5 is formed by eight alternating periods of a 2 nm thick P-doped indium gallium nitride lower potential well layer 52 (indium composition of 0.15) and a 5 nm thick P-doped gallium nitride lower barrier layer 51.

[0068] In one embodiment of the present invention, please refer to Figure 3The upper quantum well layer 7 includes several spaced upper barrier layers 71 and upper well layers 72; the thickness of each upper barrier layer 71 is 3 nm to 20 nm, and the thickness of each upper well layer 72 is 1 nm to 5 nm. Both the upper barrier layer 71 and the upper well layer 72 are p-type doped. More preferably, the thickness of each upper barrier layer 71 is 8 nm, and the thickness of each upper well layer 72 is 2.5 nm.

[0069] In one embodiment of the present invention, the upper barrier layer 71 is preferably made of aluminum gallium nitride with an aluminum content of 0.05 to 0.15, and the upper well layer 72 is made of gallium nitride; or, the upper barrier layer 71 is made of gallium nitride, and the upper well layer 72 is made of indium gallium nitride with an indium content of 0.05 to 0.25; or, the upper barrier layer 71 is made of indium gallium nitride, and the upper well layer 72 is made of indium gallium nitride, wherein the indium content of the upper barrier layer 71 is lower than that of the upper well layer 72. More preferably, the upper barrier layer 71 is made of p-doped gallium nitride, and the upper well layer 72 is made of p-doped indium gallium nitride with an indium content of 0.15.

[0070] correspond Figure 3 The upper quantum well layer 7 is formed by eight alternating growths of a 2.5 nm thick P-doped indium gallium nitride upper potential well layer 72 (indium composition of 0.15) and an 8 nm thick P-doped gallium nitride upper barrier layer 71.

[0071] In this invention, the preferred embodiment employs a multi-quantum-well structure composed of indium gallium nitride (IGaN) and gallium nitride (GaN). This structure plays an irreplaceable role in the development of semiconductor light-emitting diodes (LEDs) and short-wavelength lasers, and is of great significance for the realization of semiconductor short-wavelength light-emitting devices. The IGaN alloy, formed from indium nitride and gallium nitride, has a direct bandgap, which continuously changes from 0.7 eV to 3.4 eV with variations in the indium composition, thereby extending the emission wavelength of the semiconductor light-emitting device from far-infrared light to the entire visible light range, and even the near-ultraviolet range.

[0072] In summary, the gallium nitride heterojunction bipolar photonic transistor provided in this embodiment of the invention is a novel transistor that simultaneously functions as a transistor and an LED. The base 11 can be used to control the transistor's conduction current and also to control the LED's brightness. Since the transistor has current amplification capability when operating in the linear region, under the premise of ensuring that the emitter junction is forward biased and the collector junction is reverse biased, the magnitude of the current flowing into the transistor's collector 9 and emitter 10 is controlled by controlling the magnitude of the current flowing into the transistor's base 11, thereby regulating the brightness of the two LEDs formed by the two multi-quantum well layers (lower multi-quantum well layer 5 and upper multi-quantum well layer 7). Furthermore, the heterojunction structure suppresses minority carrier injection from the base region 6 to the emitter region 8, improving the injection efficiency of the emitter 10 and achieving higher gain.

[0073] Meanwhile, the gallium nitride heterojunction photonic transistor provided in this embodiment of the invention uses heterojunction compound semiconductor material, which has a larger bandgap and higher electron mobility and electron saturation velocity. Therefore, the heterojunction has a high switching speed and cutoff frequency. Moreover, the heterojunction collector region 4 material has a large bandgap, which can improve the reverse breakdown voltage and thus increase the output power.

[0074] In the embodiments of the present invention, both the upper quantum well layer 7 and the lower quantum well layer 5 are P-doped indium gallium nitride / gallium nitride quantum well structures. The selection of P-type doped lower well barrier layer 52 and upper well barrier layer 72 plays a positive role in regulating the light emission characteristics of dual-wavelength LEDs. Reasonably selecting the number of doped layers of lower well barrier layer 52 and upper well barrier layer 72 and an appropriate number of quantum wells can effectively improve the light emission characteristics and increase the light emission efficiency.

[0075] Secondly, please see Figure 4 This invention provides a method for fabricating a gallium nitride heterojunction bipolar photonic transistor. In this embodiment, the materials of the collector region 4, the lower multi-quantum well layer 5, the base region 6, the upper multi-quantum well layer 7, and the emitter region 8 are all group III nitrides. The method includes the following steps:

[0076] S10, Select substrate 1.

[0077] Specifically, please refer to Figure 5(a). In this embodiment of the invention, the substrate 1 is made of sapphire Al2O3. The selected substrate 1 is first cleaned, which generally involves two steps: the first step is chemical cleaning of the substrate 1, and the second step is in-situ cleaning of the substrate 1. Specifically:

[0078] Substrate 1 was chemically cleaned using organic reagents and other methods. Immediately after chemical cleaning, substrate 1 was placed in a reactor for in-situ cleaning at approximately 1100°C. Substrate 1 was then incinerated for about 10 minutes in an H2 atmosphere. After in-situ cleaning, the temperature of substrate 1 was lowered, and a certain amount of NH3 was introduced to nitride substrate 1.

[0079] It should be noted that, in the embodiments of the present invention, the substrate 1 can be placed in a growth apparatus such as various reactors. The reactor can be a metal-organic chemical vapor deposition (MOCVD) apparatus, a molecular beam epitaxy (MBE) apparatus, or a hydride vapor phase epitaxy (HVPE) apparatus. More preferably, subsequent operations can be performed using an MOCVD reactor.

[0080] S20. A core layer 2 and a buffer layer 3 are sequentially grown on substrate 1.

[0081] Specifically, as shown in Figure 5(b), the temperature inside the reactor is raised to 950°C, and the substrate 1 is nitrided at 950°C for about 7 minutes to form AlN molecules on the surface of the sapphire substrate 1, i.e., the nucleation layer 2, so as to improve the quality of GaN epitaxial growth on the sapphire substrate 1.

[0082] The substrate 1 with the nucleation layer 2 is nitrided, specifically by growing a GaN buffer layer 3 on the nucleation layer 2 at 480℃ to 550℃ using NH3, TMGa, or TEGa. Although the GaN buffer layer 3 grown at low temperatures has poor quality, it can effectively improve the quality of subsequent high-temperature grown GaN.

[0083] After the buffer layer 3 has grown, the substrate 1 is heated to 1000℃~1050℃ and stabilized for several minutes. This process is usually called the recrystallization process of the buffer layer 3. During this process, on the one hand, the crystal quality of the GaN buffer layer 3 is improved, and on the other hand, the buffer layer 3 decomposes to form GaN island-like grains, providing nuclei for subsequent high-temperature GaN growth. After the buffer layer 3 recrystallizes, high-temperature nitride growth can be carried out.

[0084] S30. On the buffer layer 3, the collector region 4, the lower multi-quantum well layer 5, the base region 6, the upper multi-quantum well layer 7, and the emitter region 8 are grown sequentially.

[0085] Specifically, please refer to Figure 5(c). An N-doped gallium nitride collector region 4 is grown on the buffer layer 3. The specific process conditions are as follows: growth time is 40 minutes, furnace temperature is 920℃, H2 is the carrier gas, 2442.1 sccm of NH3, 177.7 sccm of TEG, and 13.7 sccm of SiH4.

[0086] A P-doped lower multiple quantum well layer 5, as shown in Figure 2, is grown on collector region 4. The lower multiple quantum well layer 5 includes a P-doped gallium nitride lower barrier layer 51 and a P-doped indium gallium nitride lower well layer 52 grown in 8 cycles. The indium composition is 0.15. The specific process conditions are as follows: trimethylgallium, trimethylindium, and ammonia are used as Ga source, In source, and N source, respectively. During the growth process, nitrogen is used as the carrier gas for the growth of the lower multiple quantum well layer 5. The growth temperature of the indium gallium nitride lower well layer 52 is 790℃, the thickness of each layer is 2nm, and the in composition is 0.15. The growth temperature of the gallium nitride lower barrier layer 51 is 890℃, and the thickness of each layer is 5nm.

[0087] In this embodiment of the invention, the gallium nitride (GaN) lower barrier layer 51 of the multi-quantum well layer 5 can be grown at the same temperature as the indium gallium nitride (IGaN) lower barrier layer 52, or at a higher temperature. IGaN growth is generally performed at 650°C to 800°C. Growing the GaN lower barrier layer 51 of the multi-quantum well layer 5 at the same temperature as the IGaN lower barrier layer 52, or at a higher temperature, reduces the decomposition of the IGaN lower barrier layer 52. However, due to the lower growth temperature of the GaN lower barrier layer 51, its quality is poor because the epitaxial wafer surface is prone to blackening at excessively low growth temperatures. Increasing the growth temperature of the GaN lower barrier layer 51 can improve its quality, but this will lead to the decomposition of the IGaN lower barrier layer 52, thus reducing its quality. Therefore, when growing photonic transistors in this embodiment of the invention, the effects of growth temperature on the indium gallium nitride lower well layer 52 and the gallium nitride lower barrier layer 51 should be comprehensively considered.

[0088] P-doped gallium nitride-based region 6 was grown on the lower multi-quantum well layer 5. The specific process conditions were as follows: growth time was 20 minutes, furnace temperature was 876℃, H2 was used as carrier gas, 2436.3 sccm of NH3, 72.9 sccm of TEG, and 149.4 sccm of (CP)2Mg.

[0089] Growing on basal region 6 as... Figure 3 The p-doped upper multiple quantum well layer 7 shown includes a p-doped gallium nitride upper barrier layer 71 and a p-doped indium gallium nitride upper well layer 72 grown in 8 cycles. The indium composition is 0.15. The specific process conditions are as follows: trimethylgallium, trimethylindium, and ammonia are used as Ga source, In source, and N source, respectively. During the growth process, nitrogen is used as the carrier gas for the growth of the upper multiple quantum well layer 7. The growth temperature of the indium gallium nitride upper well layer 72 is 790℃, the thickness of each layer is 2.5nm, and the inin composition is 0.15. The growth temperature of the gallium nitride upper barrier layer 71 is 890℃, and the thickness of each layer is 8nm.

[0090] N-doped aluminum gallium nitride emitter regions 8 were grown on the upper quantum well layer 7. The specific process conditions were as follows: growth time was 15 minutes, furnace temperature was 920℃, H2 was used as carrier gas, 2447.9 sccm of NH3, 57.9 sccm of TEG, and 4.9 sccm of TMA.

[0091] S40, etch away part of the emitter region 8, add multiple quantum well layers 7 until the base region 6 is exposed.

[0092] Specifically, as shown in Figure 5(d), etching is performed on the grown crystal surface using photoresist as a mask. Reactive ion etching (RIE) is employed to etch the mesa, removing part of the emitter region 8 and the upper quantum well layer 7. The etching depth is the sum of the thicknesses of the emitter region 8 and the upper quantum well layer 7, until the base region 6 is exposed. The etched mesa should have neat edges and steep sidewalls, as shown in Figure 5(d).

[0093] S50. On the exposed base region 6, etch away part of the emitter region 8, the lower quantum well layer 5, the base region 6, and the lower quantum well layer 5 until the collector region 4 is exposed.

[0094] Specifically, as shown in Figure 5(e), etching is performed on the surface of the base region 6 completed in S40. Using photoresist as a mask, the mesa is etched using RIE equipment and technology to remove part of the base region 6 and the lower multi-quantum well layer 5. That is, the etching depth is the sum of the thicknesses of the base region 6 and the lower multi-quantum well layer 5, until the collector region 4 is exposed. The etched mesa should have neat edges and steep sidewalls, as shown in Figure 5(e).

[0095] S60, emitter metal and collector metal are deposited in emitter region 8 and collector region 4 respectively to form emitter 10 and collector 9.

[0096] Specifically, as shown in Figure 5(f), the emitter 10 and collector 9 are fabricated by combining photolithography and metal lift-off techniques and using vacuum evaporation or electron beam evaporation. Specifically, Ti / Al / Ni / Au metals with thicknesses of 20nm / 100nm / 40nm / 50nm are deposited in the emitter region 8 and the collector region 4, respectively. After deposition, the metals are annealed in a nitrogen atmosphere at 850℃ for 30s to achieve ohmic contact between the emitter 10 and the collector 9.

[0097] S70, deposit base metal in base region 6 to form base 11.

[0098] Specifically, as shown in Figure 5(g), the base 11 is prepared by combining photolithography and metal lift-off techniques and using vacuum evaporation or electron beam evaporation. Specifically, a Ni / Au metal with a thickness of 10nm / 20nm is deposited in the base region 6. After deposition, it is annealed for 5 minutes in an oxygen atmosphere at 550°C to achieve the ohmic contact of the base 11.

[0099] This completes the fabrication of the gallium nitride heterojunction bipolar photonic transistor.

[0100] It should be noted that during the fabrication process, the materials for each layer can be other materials used in the transistor structure embodiments, and the process is similar. The process conditions are selected and designed according to the actual situation, and will not be explained in detail here.

[0101] The method for fabricating a gallium nitride heterojunction bipolar photonic transistor provided in this invention produces a novel transistor that functions as both a transistor and an LED. The base 11 can control both the transistor's on-state current and the LED's brightness. Since the transistor has current amplification capability when operating in the linear region, the current flowing into the collector 9 and emitter 10 is controlled by adjusting the current flowing into the base 11, thus regulating the brightness of the two LEDs formed by the two multi-quantum-well layers. Furthermore, the heterojunction structure suppresses minority carrier injection from the base region 6 to the emitter region 8, improving the injection efficiency of the emitter 10 and achieving higher gain. This invention features a simple fabrication process with low cost, is compatible with conventional semiconductor fabrication processes, and possesses excellent performance characteristics, thus offering broad application prospects in photonic crystallography and providing new ideas for the application of transistors in optics.

[0102] As the method embodiments are basically similar to the structural embodiments, the description is relatively simple, and relevant parts can be found in the description of the structural embodiments.

[0103] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0104] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0105] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gallium nitride heterojunction bipolar phototransistor, comprising: include: Substrate; And a nucleation layer and a buffer layer are sequentially disposed on the upper surface of the substrate; A current collection area is disposed on the upper surface of the buffer layer; A collector electrode is disposed at one end of the upper surface of the collector region; A lower multiple quantum well layer is disposed at the other end of the upper surface of the current collector region; there is a gap between the current collector and the lower multiple quantum well layer; The base region is disposed on the upper surface of the lower multi-quantum well layer; A base electrode is disposed at one end of the upper surface of the base region; wherein the base electrode and the collector electrode are disposed on the same side; An upper quantum well layer is disposed at the other end of the upper surface of the base region; there is a gap between the base and the upper quantum well layer; The emission region is located on the upper surface of the upper multi-quantum-well layer; An emitter is disposed at one end of the upper surface of the emitter region and partially covers the upper surface of the emitter region; the emitter and the collector are disposed on different sides. The materials of the current collector region, the base region, and the emitter region are all group III nitrides; The lower multiple quantum well layer comprises several spaced lower barrier layers and lower well layers, both of which are p-type doped. The thickness of each lower barrier layer is 3 nm to 20 nm, and the thickness of each lower well layer is 1 nm to 5 nm. The material of the lower barrier layer is aluminum gallium nitride (AlGaN) with an aluminum content of 0.05 to 0.15, and the material of the lower well layer is gallium nitride (GaN); or, the material of the lower barrier layer is GaN, and the material of the lower well layer is indium gallium nitride (InGaN) with an indium content of 0.05 to 0.25; or, the material of both the lower barrier layer and the lower well layer is InGaN, and the indium content of the lower barrier layer is lower than that of the lower well layer. The upper multiple quantum well layer includes several spaced upper barrier layers and upper well layers, both of which are p-type doped. The thickness of each upper barrier layer is 3 nm to 20 nm, and the thickness of each upper well layer is 1 nm to 5 nm. The material of the upper barrier layer is aluminum gallium nitride with an aluminum content of 0.05 to 0.15, and the material of the upper well layer is gallium nitride; or, the material of the upper barrier layer is gallium nitride, and the material of the upper well layer is indium gallium nitride with an indium content of 0.05 to 0.25; or, the material of the upper barrier layer is indium gallium nitride, and the material of the upper well layer is indium gallium nitride, wherein the indium content of the upper barrier layer is lower than that of the upper well layer.

2. The GaN heterojunction bipolar phototransistor of claim 1, wherein The material used in the collector region includes gallium nitride or indium gallium nitride; the doping type of the collector region is N-type, and the thickness is 30nm~2000nm.

3. The GaN heterojunction bipolar phototransistor of claim 1, wherein The base region is made of materials including gallium nitride or indium gallium nitride; the base region is p-type doped and has a thickness of 10 nm to 300 nm.

4. The GaN heterojunction bipolar phototransistor of claim 1, wherein The material used in the emission region includes gallium nitride or aluminum gallium nitride; the doping type of the emission region is N-type, and the thickness is 50nm~1000nm.

5. A method of fabricating a gallium nitride heterojunction bipolar phototransistor, comprising: The method for fabricating the gallium nitride heterojunction bipolar photonic transistor according to any one of claims 1 to 4 includes: Select a substrate; A core layer and a buffer layer are sequentially grown on the substrate; A current collector region, a lower multi-quantum well layer, a base region, an upper multi-quantum well layer, and an emitter region are sequentially grown on the buffer layer. Etch away part of the emitter region and the upper multi-quantum-well layer until the base region is exposed; On the exposed base region, a portion of the emitter region, the lower quantum well layer, the base region, and the lower quantum well layer are etched away until the collector region is exposed; Emitter metal and collector metal are deposited in the emitter region and the collector region, respectively, to form the emitter and the collector. A base metal is deposited in the base region to form the base electrode.

6. The method of claim 5, wherein the method further comprises: The materials of the current collector region, the lower multi-quantum well layer, the base region, the upper multi-quantum well layer, and the emitter region are all group III nitrides.

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