Gate driver communication system

Abstract

A gate driver communication system includes a core transformer including a primary coil and a secondary coil configured to receive a power signal and an uplink data signal from the primary coil, a primary-side power signal generator coupled to the primary coil and configured to generate the power signal having a first frequency, a primary-side data transmitter coupled to the primary coil and configured to generate the uplink data signal having a second frequency different from the first frequency, and a primary-side controller configured to allocate the power signal and the uplink data signal to the primary coil according to a plurality of time slots, wherein the power signal is allocated to a first time slot of the plurality of time slots and the uplink data signal is allocated to a second time slot of the plurality of time slots.

Description

Technical Field

[0001] This invention relates to the field of electronics, and more particularly to a current-isolated gate driver communication system based on a transformer for both power transmission and data transmission from the primary coil to the secondary coil. Background Technology

[0002] Many modern electronic circuits, such as switched-capacitor converters and motor drivers, utilize power switches to control the flow of high current levels. Power switches typically require driver circuitry for supplying and drawing current from the control terminals (e.g., gates) of the power switch. Drivers for power switches with load terminals (e.g., sources) directly coupled to ground may be relatively simple, as the circuitry of such drivers may be ground-referenced. However, power switches are typically not directly coupled to ground. For example, a half-bridge configuration may include a low-side power switch coupled between ground and the switching node, and a high-side power switch coupled between the positive voltage rail and the switching node. In other examples, switched-capacitor converters or multi-stage Class-D amplifiers may include a series of cascaded power switches between ground and the positive voltage rail, where the voltage at the load terminals (e.g., sources) of intermediate power switches typically falls between ground and the positive voltage rail.

[0003] Therefore, a gate driver system can include a low-voltage (LV) gate driver for driving a low-side transistor switch and a high-voltage (HV) gate driver for driving a high-side transistor switch. The LV gate driver can be located in the low-voltage domain on the low-side input chip, while the HV gate driver can be located in the high-voltage domain on the high-side output chip, which is current-isolated from the low-voltage domain (i.e., from the low-side input chip). The power switches can also be located in other voltage domains, such as an intermediate voltage domain between the LV and HV domains. Typically, the HV gate driver receives control signals and possibly other communication signals from circuitry located in the low-voltage domain. Therefore, a method for transmitting signals between the LV and HV domains is required.

[0004] Power switches not coupled to ground, such as high-side or other floating power switches, present unique challenges for driving, including transmitting control signals (e.g., drive signals) across voltage domains to the HV gate driver. Consider, for example, an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) power switch with a source, drain, and gate (control terminal). The turn-on voltage driving the MOSFET gate references the source voltage, which may be floating. The HV driver typically has a reference terminal for coupling to the MOSFET source and must be equipped with a power supply that provides power at a positive voltage, such as 5V, higher than the reference (source) voltage. Therefore, a floating power supply referenced to the MOSFET source voltage is required. Furthermore, the HV driver input, typically a digital signal alternating between, for example, ground and 3V, generally needs to be level-shifted according to the MOSFET source voltage.

[0005] Coreless transformers or optocouplers can be used in current-isolated gate drivers to enable bidirectional communication across voltage domains (e.g., between input and output chips). Signal transmission can be used to provide control signals and other communication signals.

[0006] While coreless transformers ensure good general performance, they exhibit at least two weaknesses. First, on-chip HV current isolation is required to electrically isolate the low-side coil in the LV domain from the high-side coil in the HV domain. Therefore, specialized techniques are needed to ensure isolation, increasing manufacturing costs. Second, an external isolated power supply is required to power the floating output circuitry, including the HV gate driver. Qualifying on-chip HV current isolation is tricky and problematic. Furthermore, the standards for ensuring proper and safe operation of HV current isolation are becoming increasingly stringent.

[0007] A major drawback of optocouplers is that their performance degrades with age. Like coreless transformers, they also require an external isolated power supply to power the floating output circuitry.

[0008] Therefore, coreless transformers and optocouplers used for transmitting communication signals between voltage domains require robust, isolated power supplies, typically made of external discrete transformers, to power the floating output circuitry. Thus, the signal transmission path and the floating power supply path are implemented using two different structures.

[0009] Therefore, an improved device may be desired that utilizes a shared structure to transmit both communication signals and power between the low-side and high-side chips. Summary of the Invention

[0010] An embodiment provides a gate driver communication system, comprising: a core transformer including a primary coil disposed on a primary side, a secondary coil disposed on a secondary side, and a core associating the primary coil to the secondary coil, wherein the secondary coil is configured to receive a power signal and an uplink data signal from the primary coil; a primary-side power signal generator coupled to the primary coil and configured to generate a power signal having a first frequency; a primary-side data transmitter coupled to the primary coil and configured to generate an uplink data signal having a second frequency different from the first frequency; and a primary-side controller configured to distribute the power signal and the uplink data signal to the primary coil according to a plurality of time slots, wherein the power signal is distributed to a first time slot of the plurality of time slots, and the uplink data signal is distributed to a second time slot of the plurality of time slots.

[0011] The embodiment also provides a gate driver communication system, including: a core transformer comprising a primary coil disposed on a primary side, a secondary coil disposed on a secondary side, and a core relating the primary coil to the secondary coil, wherein the secondary coil is configured to receive a data-encoded power signal; a primary-side power signal generator coupled to the primary coil and configured to generate a data-encoded power signal having a fixed frequency and a phase varying based on encoded bit values; and a power transport carrier generator disposed on the primary side and configured to generate a zero-phase power carrier signal having a fixed frequency and a fixed phase. The circuit includes: an inverter configured to invert a zero-phase power carrier signal to generate a phase-shifted power carrier signal; and a shunt configured to selectively couple the zero-phase power carrier signal to a primary-side power signal generator to encode a first bit value onto a data-encoded power signal, and selectively couple the phase-shifted power carrier signal to the primary-side power signal generator to encode a second bit value onto the data-encoded power signal, wherein the primary-side power signal generator is configured to generate a data-encoded power signal with encoded bits thereon based on receiving either the zero-phase power carrier signal or the phase-shifted power carrier signal.

[0012] The embodiment also provides a gate driver communication system, including: a core transformer including a primary coil disposed on a primary side, a secondary coil disposed on a secondary side, and a core associating the primary coil to the secondary coil, wherein the secondary coil is configured to receive a data-encoded power signal; and a phase-locked loop (PLL) based receiver coupled to the secondary coil and configured to receive and decode the data-encoded power signal to extract encoded bits therefrom. The PLL-based receiver includes: a PLL configured to generate a PLL signal locked to a reference signal in frequency and phase; a dual-phase discriminator circuit configured to receive the PLL signal and determine the phase of the data-encoded power signal received at the secondary coil based on the PLL signal; and a bit decoder configured to extract encoded bits based on the determined phase of the data-encoded power signal relative to the PLL signal. Attached Figure Description

[0013] The embodiments are described herein with reference to the accompanying drawings.

[0014] Figure 1 It is a schematic block diagram of a multi-voltage domain system according to one or more implementation methods;

[0015] Figure 2 This is a schematic diagram of a bidirectional communication system based on one or more implementations of a multi-voltage domain system;

[0016] Figure 3 It is a timing diagram of the main communication signals and power transmission from the primary side to the secondary side according to one or more embodiments of a multi-voltage domain system;

[0017] Figure 4 A schematic diagram of a high-side circuit according to one or more embodiments is shown;

[0018] Figure 5 This is a schematic diagram of a data transmission system disposed on the primary side of a core transformer as part of a phase-locked loop (PLL) based communication system, according to one or more embodiments.

[0019] Figure 6 This is a schematic diagram of another data receiving system disposed on the secondary side of a core transformer as part of a PLL-based communication system, according to one or more embodiments.

[0020] Figure 7 It is a signal diagram of signals located at various nodes along a portion of a two-phase discriminator of a data receiving system, according to one or more embodiments.

[0021] Figure 8It is a signal diagram of signals at various stages of a PLL-based communication system according to one or more implementations. Detailed Implementation

[0022] In the following sections, details are set forth to provide a more comprehensive explanation of exemplary embodiments. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In other instances, to avoid obscuring the embodiments, well-known structures and apparatuses are shown in block diagrams or schematic representations rather than in detail. Furthermore, unless otherwise specifically stated, features of the different embodiments described below may be combined with each other.

[0023] Furthermore, equivalent or similar elements, or elements having equivalent or similar functions, are indicated by equivalent or similar reference numerals in the following description. Since identical elements or elements with equivalent functions are given the same reference numerals in the drawings, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals are interchangeable.

[0024] In this regard, directional terms such as "top," "bottom," "below," "above," "front," "back," "rear," "front part," and "tail" may be used with reference to the orientation of the described drawings. Because components of an embodiment can be positioned in multiple different orientations, directional terms are used for illustrative purposes. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description should not be considered limiting. The directional terms used in the claims help define the spatial or positional relationship between one element and another element or feature, and are not limited to a specific orientation.

[0025] It will be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as being “directly connected” or “directly coupled” to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent” vs. “directly adjacent”, etc.).

[0026] In the embodiments described herein or shown in the accompanying drawings, any direct electrical connection or coupling—i.e., any connection or coupling without additional intermediate elements—can also be achieved through an indirect connection or coupling—i.e., a connection or coupling with one or more additional intermediate elements—and vice versa, as long as the general purpose of the connection or coupling is substantially maintained, such as transmitting a signal or transmitting information. Features from different embodiments can be combined to form other embodiments. For example, unless otherwise stated, variations or modifications described with respect to one embodiment may also apply to other embodiments.

[0027] Without departing from aspects of the embodiments described herein, the terms "substantially" and "approximately" may be used herein to interpret small manufacturing tolerances (e.g., within 5%) that are considered industrially acceptable. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of that approximate resistance value.

[0028] In this disclosure, the use of ordinal expressions such as "first," "second," etc., can modify various elements. However, such elements are not limited by the above expressions. For example, the above expressions do not limit the order and / or importance of elements. The above expressions are used only for the purpose of distinguishing elements from other elements. For example, a first box and a second box indicate different boxes, although they are both boxes. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving motors or electric machines, rely on power semiconductor devices. For example, to name just a few, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a wide range of applications, including but not limited to switches in power supplies and power converters.

[0030] Power semiconductor devices typically include semiconductor structures configured to conduct load current along a load current path between two load terminal structures or load electrodes (e.g., source / emitter and drain / collector) of the device. Furthermore, the load current path can be controlled by means of a control electrode (sometimes referred to as a gate electrode). For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of an on or off state. The control signal can be a voltage signal or a current signal with a controlled value.

[0031] A power transistor (also known as a power switch or transistor switch) is a power semiconductor device that can be used to drive load current. For example, an IGBT is turned on or off by activating and deactivating its gate terminal. Applying a positive input voltage signal across the gate and emitter will keep the device in its "on" state, while making the input gate signal zero or slightly negative will turn the device "off". There are turn-on and turn-off processes for turning a power transistor on and off.

[0032] During the conduction process, a gate driver integrated circuit (IC) can be used to provide a (source) gate current (i.e., on-state current) to the gate of the power transistor to charge the gate to a sufficient voltage to turn the device on. Specifically, the current Io+ is the gate driver output current used to raise (i.e., charge) the gate of the power transistor during the on-state transient. Therefore, the current Io+ is used to turn the power transistor on.

[0033] In contrast, during the turn-off process, the gate driver IC draws (drains) gate current (i.e., the turn-off current) from the gate of the power transistor to fully discharge the gate and turn off the device. The current Io- is the gate driver output current used to discharge the gate of the power transistor during the turn-off transient. Therefore, Io- is used to turn off the power transistor.

[0034] According to the pulse width modulation (PWM) scheme, a voltage pulse can be output from the gate driver IC as a control signal. Therefore, during the PWM cycle used to control the power transistor, the control signal can be switched between the on-state voltage level and the off-state voltage level. This, in turn, charges and discharges the gate voltage to turn the power transistor on and off, respectively.

[0035] Specifically, the gate of the power transistor is a capacitive load, and upon initiating a switching event, the on-current (i.e., gate-source current) and the off-current (i.e., gate-drain current) are designated as initial currents. During the off-event, after a short period of time (smaller than the PWM cycle), the gate current decreases and reaches zero when the gate reaches 0V. During the on-event, after a short period of time (smaller than the PWM cycle), the gate current decreases and reaches zero when the gate reaches the high-side supply level.

[0036] Transistors can include insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., silicon MOSFETs or silicon carbide MOSFETs). Although IGBTs may be used as examples in the embodiments described below, it should be understood that MOSFETs can replace IGBTs, and vice versa. In this case, in any of the examples described herein, when a MOSFET is used instead of an IGBT, the drain of the MOSFET can replace the collector of the IGBT, the source of the MOSFET can replace the emitter of the IGBT, and the drain-source voltage VDS of the MOSFET can replace the collector-emitter voltage VCE of the IGBT. Therefore, any IGBT module can be replaced by a MOSFET module, and vice versa.

[0037] The specific embodiments described in this specification pertain to, but are not limited to, power semiconductor devices that can be used within power converters or power supplies. Therefore, in these embodiments, the power semiconductor device can be configured to carry load currents to be supplied to a load and / or supplied by a power supply. For example, the semiconductor device may include one or more power semiconductor units, such as monolithically integrated diode units and / or monolithically integrated transistor units. Such diode units and / or such transistor units may be integrated within a power semiconductor module.

[0038] Power semiconductor devices, including transistors appropriately connected to form a half-bridge, are commonly used in the field of power electronics. For example, a half-bridge can be used to drive a motor or a switch-mode power supply.

[0039] For example, multiphase inverters are configured to provide multiphase power by supplying multiphase loads, such as three-phase motors. Three-phase power, for instance, consists of three symmetrical sine waves, each 120 electrical degrees out of phase with the others. In a symmetrical three-phase power system, each of the three conductors carries an alternating current (AC) with the same frequency and voltage amplitude relative to a common reference, but with a phase difference of one-third of a cycle. Due to this phase difference, the voltage on any conductor reaches its peak at one-third of a cycle after one of the other conductors and one-third of a cycle before the remaining conductors. This phase delay provides constant power delivery for balanced linear loads. This also makes it possible to generate a rotating magnetic field in the motor.

[0040] In a three-phase system with a balanced feed and linear load, the sum of the instantaneous currents in the three conductors is zero. In other words, the current in each conductor is equal in magnitude to the sum of the currents in the other two conductors, but with opposite signs. The return path of the current in any phase conductor is through the other two phase conductors. Instantaneous currents produce a current space vector.

[0041] A three-phase inverter comprises three inverter branches, one for each of the three phases, and each inverter branch is connected in parallel to a direct current (DC) voltage source. Each inverter branch includes a pair of power transistors, arranged, for example, in a half-bridge configuration, for converting DC to AC. In other words, each inverter branch includes two complementary transistors connected in series (i.e., a high-side transistor and a low-side transistor), which complementaryly turn on and off to drive the phase load.

[0042] The implementation relates to a current-isolated gate driver system comprising a single discrete core transformer for transmitting communication signals (including control signals) and power between the low-side and high-side chips of the gate driver system. In this sense, the core transformer can be considered as providing a single transmit / receive channel (i.e., a TX / RX channel) through which communication and power signals are transmitted. Power transmission can be considered unidirectional, from the low-side chip to the high-side chip. However, communication signal transmission can be considered bidirectional and can be performed between chips in both directions, although not simultaneously.

[0043] Communication signals and power signals are assigned different time slots to transmit these different signal types on a single core transformer. In particular, Time Division Multiple Access (TDMA) is an example allocation scheme (i.e., transmission protocol) used to allocate different time slots to communication signals and power signals.

[0044] According to the following implementation, a cored transformer is configured to generate an isolated power supply for providing power from the low-side chip to the high-side chip. Furthermore, the control circuitry in the low-side chip is configured to stop or interrupt power transmission to allow for rapid data transmission bursts between the low-side and high-side chips. Typically, in a master / slave configuration, the low-side chip is configured as the master chip, and the high-side chip is configured as the slave chip. As the master chip, the low-side chip located on the ground primary side (LV domain) is configured to stop power transmission to the high-side chip to utilize the cored transformer for communication signal transmission. When it is desired to transmit a communication signal from the low-side chip to the high-side chip, the control circuitry of the low-side chip can interrupt the power transmission. However, the high-side chip can also be configured with an interrupt function to transmit an interrupt to the control circuitry of the low-side chip. In response to receiving this interrupt, the control circuitry of the low-side chip can interrupt the power transmission to allow the communication signal to be transmitted from the high-side chip to the low-side chip.

[0045] Therefore, by using a core transformer between two current-isolated gate driver chips, all high-voltage isolation issues are moved to the system level and outside the integrated circuit IC (i.e., chip), which would otherwise be problematic and expensive to manage.

[0046] The principle of using a single discrete core transformer to transmit both communication signals and power between two current-isolated chips can also be extended more generally to any system that exchanges a limited amount of digital data to / from an isolated (floating) voltage domain, which also requires an isolated power supply. For example, the described implementation can also be used for phase current sensors that include floating analog-to-digital converters. A transformer with multiple secondary coils can also be used by introducing a handshake into the transmission protocol.

[0047] Figure 1 This is a schematic block diagram of a multi-voltage domain system 100 according to one or more embodiments. Specifically, the multi-voltage domain system 100 includes two current isolation chips 10 and 20 with a core transformer 30 between them for transmitting communication signals and power between the two chips 10 and 20. The multi-voltage domain system 100 also includes two current isolation chips 10 and 40 with a core transformer 50 between them for transmitting communication signals and power between the two chips 10 and 40.

[0048] The cored transformer 30 includes two coils—a primary coil 31 and a secondary coil 32—connected by a ferromagnetic core 33, such that magnetic flux from one coil passes through the core 33 to the other coil. The cored transformer 30 provides a high-voltage barrier between chips 10 and 20. When the magnetic flux generated by one coil changes, the magnetic flux through the other coil changes, inducing a voltage in the second coil. The primary coil 31 includes two terminals E1 and A1 coupled to the input chip 10, where the voltage across coil 31 is represented by Ve1-Va1. Similarly, the secondary coil 32 includes two terminals F1 and H1 coupled to the high-side chip 20 (i.e., the output chip), where the voltage across coil 32 is represented by Vf1-Vh1. With AC power supplied to terminals E1 and A1, the voltage Vf1-Vh1 induced in the second coil will also be AC.

[0049] Similarly, the cored transformer 50 includes two coils—a primary coil 51 and a secondary coil 52—connected by a ferromagnetic core 53, such that magnetic flux from one coil passes through the core 53 to the other coil. The cored transformer 50 provides a high voltage barrier between chips 10 and 40. When the magnetic flux generated by one coil changes, the magnetic flux through the other coil will change, thus inducing a voltage in the second coil. The primary coil 51 includes two terminals E2 and A2 coupled to the input chip 10, where the voltage across coil 51 is represented by Ve2-Va2. Similarly, the secondary coil 52 includes two terminals F2 and H2 coupled to the low-side chip 40 (i.e., the output chip), where the voltage across coil 52 is represented by Vf2-Vh2. With AC power supplied to terminals E2 and A2, the voltage Vf2-Vh2 induced in the second coil will also be AC.

[0050] The multi-voltage-domain system 100 includes a low-side transistor 1 and a high-side transistor 2, which are controlled to supply load current ILOAD to one phase of the load (not shown). The low-side transistor 1 is controlled by a low-side device 41, which includes a low-side (LS) gate driver for driving the low-side transistor switch 1. The high-side transistor 2 is controlled by a high-side device 21, which includes a high-side (HS) gate driver for driving the high-side transistor switch 2. Chips 10 and 20 are located in different voltage domains, for example, a low-voltage domain and a high-voltage domain. Typically, the low-side device 41 may be referred to as a low-side gate driver, and the high-side device 21 may be referred to as a high-side gate driver.

[0051] Chips 10 and 40 can have the same voltage domain or different voltage domains. For example, chips 10 and 40 can both be powered by the same voltage domain (i.e., the same voltage potential) or by different voltage domains (i.e., one or two different voltage potentials). However, to maintain current isolation between chips 10 and 20, chips 10 and 40 also need to be isolated from each other by a core transformer 50. It should be understood that the structure of chip 40 and core transformer 50 replicates the structure of chip 20 and core transformer 30, except for different power supply voltage levels. Therefore, the description of chip 20 and core transformer 30 also applies to chip 40 and core transformer 50.

[0052] Both the low-side device 41 (e.g., LS gate driver) and the high-side device 21 (e.g., HS gate driver) perform gate driving of their respective power transistors 1 and 2 based on digital PWM signals LIN and HIN received from the microcontroller unit (MCU) 3. The PWM signals are control signals received from the MCU 3 at the low-voltage device 11. The low-voltage device 11 includes PWM logic that receives the LIN and HIN signals from the MCU 3 and ensures a minimum dead time to prevent bridge breakdown. Finally, the corresponding PWM control signals are passed to the respective low-side and high-side gate drivers, with the PWM signal HIN sent to the high-side gate driver and LIN sent to the low-side gate driver. The low-side and high-side gate drivers then perform gate driving.

[0053] Gate drivers 41 and 21 each include separate pre-driver circuitry and buffers. The pre-driver circuitry is configured to receive a PWM signal and, based on the PWM signal, control the on / off state of a corresponding first current source (e.g., a source-type FET) for generating the current Io+. Additionally, the pre-driver circuitry is configured to receive a PWM signal and, based on the PWM signal, control the on / off state of a corresponding second current source (e.g., a drain-type FET) for generating the current Io-. The corresponding current sources are housed in buffers. Thus, each buffer may include a pair of complementary FETs for generating on-current Io+ and off-current Io- for its respective power transistors 1 and 2. Each of the pre-driver circuits may also command its respective buffer to use a certain current capability.

[0054] Low-voltage device 11 can be configured to receive PWM control signals HIN and LIN from MCU 3, and to turn on or off the corresponding transistors 1 and 2 according to the received PWM control signals. For example, during the turn-on process of the corresponding transistor 1 or 2, low-voltage device 11 can be used to provide a (source) gate current Io+ to the gate of the corresponding transistor 1 or 2 to charge the gate. In contrast, during the turn-off process, low-voltage device 11 can be used to draw a (drain) gate current Io- from the gate of transistor 1 or 2 to discharge the gate. Of course, when controlling high-side transistor 2, the control signal is sent from low-voltage device 11 to high-side device 21 via core transformer 30, and when controlling low-side transistor 1, the control signal is sent from low-voltage device 11 to low-voltage device 41 via core transformer 50.

[0055] Therefore, MCU 3 is electrically coupled to low-voltage device 11 for the transmission of information signals and control signals HIN and LIN therebetween, and the gate driver system is electrically coupled to inverter branch for driving its power transistors 1 and 2.

[0056] Specifically, MCU 3 is configured to generate PWM control signals LIN and HIN for controlling transistors 1 and 2, respectively, and send these control signals to low-voltage device 11. For example, low-voltage device 11 is configured to receive instructions from MCU 3 to use the PWM control signals to drive the load phase (i.e., the inverter branch) connected to voltage VS. These PWM control signals are received by low-voltage device 11 in the LV domain (i.e., at input pins HIN and LIN) and passed to the corresponding pre-driver circuits via appropriate logic. The buffer for each gate driver is configured to receive the PWM control signals and drive the corresponding power transistors 1 and 2 via the output terminals HO and LO of the gate driver system.

[0057] exist Figure 1 In the example shown, at least three regions exist: a high-side region defined by the HV domain, a low-side region defined by the LV domain, and an isolation region defined by core transformers 30 and 50. The LV domain includes low-voltage devices, and the HV domain includes high-voltage devices. For example, low-voltage devices can be supplied from 0V to 5V, while high-voltage devices can be supplied above 100V (e.g., 120V to 160V). The voltage domains are not limited to these voltage ranges but are instead intended to provide an example of an implementation. However, the general principle of different voltage domain levels at different voltage levels remains unchanged. The LV and HV regions are located on separate current-isolated dies (i.e., ICs).

[0058] Transformer 30 is configured to transmit electrical signals (e.g., PWM control signals) from low-voltage device 11 to high-side device 21 (i.e., from a first voltage domain to a second voltage domain), or vice versa. Additionally, transformer 30 is configured to transmit power from low-voltage device 11 to high-side device 21 (i.e., from a first voltage domain to a second voltage domain). Different time slots are allocated for transmitting communication signals and power according to, for example, a TDMA protocol.

[0059] Transformer 50 is configured to transmit electrical signals (e.g., PWM control signals) from low-voltage device 11 to low-side device 41 (i.e., from a first voltage domain to the same or a different voltage domain), or vice versa. Additionally, transformer 50 is configured to transmit power from low-voltage device 11 to high-side device 41 (i.e., from the first voltage domain to the same or a different voltage domain). Different time slots are allocated for transmitting communication signals and power according to, for example, a TDMA protocol.

[0060] Additionally, VB refers to the high-side floating supply voltage; VS refers to the high-side floating ground voltage; VDD or VCC refers to the low-side and logic fixed supply voltage; VSS or VEE refers to the low-side ground voltage; HO refers to the high-side floating output voltage; LO refers to the low-side output voltage; DC+ refers to the positive terminal of the DC link; DC- refers to the negative terminal of the DC link; and HIN and LIN refer to the logic input voltage (i.e., control signal) received from MCU 3. VCC1 and VCC2 can be used to distinguish between two isolated low-side potentials. Similarly, VSS1 and VSS2 can be used to distinguish between two isolated low-side ground voltages.

[0061] Similarly, similar terminals and voltages are intended for similar purposes (e.g., E1 / E2, A1 / A2, F1 / F2, H1 / H2, Ve1 / Ve2, Va1 / Va2, Vf1 / Vf2, Vh1 / Vh2).

[0062] The high-side chip 20 includes a diode bridge 22 connected to and spanning the Fl and Hl terminals of the secondary coil 32. The diode bridge 22 rectifies the AC voltage Vfl-Vhl into a DC voltage VB-VS, with energy stored in a storage capacitor Ctank 23 located "off-chip" or outside the chip 20. The diode bridge 22 and the storage capacitor Ctank 23 form a power supply circuit on the secondary side, which receives and stores power received from the primary side and supplies the stored power to components of the chip 20. Specifically, the power supply circuit receives a power signal, converts the power signal into stored energy, and supplies the stored energy to components of the chip 20.

[0063] The low-side chip 40 includes a diode bridge 42 connected to and spanning the Fl and Hl terminals of the secondary coil 52. The diode bridge 42 rectifies the AC voltages Vf2-Vh2 into DC voltages VCC2-VSS2, with energy stored in a storage capacitor Ctank 43 located "off-chip" or outside the chip 40. The diode bridge 42 and the storage capacitor Ctank 43 form a power supply circuit on the secondary side, which receives and stores power received from the primary side and supplies the stored power to components of the chip 40. Specifically, the power supply circuit receives a power signal, converts the power signal into stored energy, and supplies the stored energy to components of the chip 40.

[0064] The energy storage capacitor Ctank 23 is configured to supply the high-side floating supply voltage VB and the high-side floating ground voltage VS to the high-side device 21, particularly to the high-side gate driver, for turning on the high-side transistor switch 2. Specifically, when the high-side transistor switch 2 is off and its source is grounded, for example during the interval when the low-side transistor switch 1 is on, the energy storage capacitor Ctank 23 is charged by the low-voltage device 11 via the transformer 30 and the diode bridge 22. Once the source of the high-side transistor switch 2 is disconnected from ground, for example when the low-side transistor switch 1 is off, the energy storage capacitor 23 supplies power to the high-side gate driver as needed to turn on the high-side transistor switch 2.

[0065] The energy storage capacitor Ctank 43 is configured to supply the low-side fixed supply voltage VCC2 and the low-side ground voltage VSS2 to the low-side device 42, particularly to the low-side gate driver, to turn on the low-side transistor switch 1. Specifically, the energy storage capacitor Ctank 43 is charged by the low-voltage device 11 via the transformer 50 and the diode bridge 42. The energy storage capacitor Ctank 43 provides the fixed supply voltage VCC2-VSS2 to the low-side device 41. VSS2 can be coupled to DC-.

[0066] The high-side device 21 is further (directly) coupled to two terminals F1 and H1 of the secondary coil 32 for receiving communication signals, including PWM control signals, from it. The high-side device 21 can also be configured to use terminals F1 and H1 to transmit communication signals, such as diagnostic or fault signals, to it, for transmission to the primary coil 31 and ultimately to the low-voltage device 11, and possibly further to the MCU 3 coupled to the low-voltage device 11.

[0067] The low-side device 41 is further (directly) coupled to two terminals F2 and H2 of the secondary coil 52 for receiving communication signals, including PWM control signals, from it. The low-side device 41 can also be configured to transmit communication signals, such as diagnostic or fault signals, to it using terminals F2 and H2, for transmission to the primary coil 51 and ultimately to the low-voltage device 11, and possibly further to the MCU 3 coupled to the low-voltage device 11.

[0068] As will be explained in more detail below, the high-side device 21 can also trigger an interrupt to enable the transmission of communication signals, such as diagnostic or fault signals, to the low-voltage device 11 and possibly further to the MCU 3 coupled to the low-voltage device 11. For example, the low-voltage device 11 can be configured to relay diagnostic or fault signals to the MCU 3 via the feedback terminal FB. Based on the received diagnostic or fault signal, the MCU 3 can adjust its PWM control signals HIN and LIN. For example, the MCU 3 can change the duty cycle, period, etc., of the PWM control signals HIN and LIN. In the event of a fault, the MCU 3 can turn off the high-side transistor switch 2 by driving the PWM control signal HIN low until the fault is resolved.

[0069] Similarly, the low-side device 41 can also trigger an interrupt to enable the transmission of communication signals, such as diagnostic or fault signals, to the low-voltage device 11, and possibly further to the MCU 3 coupled to the low-voltage device 11. For example, the low-voltage device 11 can be configured to relay diagnostic or fault signals to the MCU 3 via the feedback terminal FB. Based on the received diagnostic or fault signal, the MCU 3 can adjust its PWM control signals HIN and LIN. For example, the MCU 3 can change the duty cycle, period, etc., of the PWM control signals HIN and LIN. In the event of a fault, the MCU 3 can turn off the low-side transistor switch 1 by driving the PWM control signal LIN low until the fault is resolved.

[0070] The high-side device 21 can trigger an interruption by closing an interrupt switch 24 connected across terminals F1 and H1 of the secondary coil 32. The high-side device 11 can control the state of the interrupt switch 24 via a control signal SW1. A closed interrupt switch 24 short-circuits terminals F1 and H1 together to the same potential (e.g., ground). The low-voltage device 11 may include a short-circuit detector that detects such a short circuit on the primary side, which the low-voltage device 11 interprets as a transmission request from the secondary side (i.e., from the high-side device 21). In response to the transmission request, the low-voltage device 11 can interrupt any primary-to-secondary transmission (communication signals or power) to allow the high-side device 21 to send its communication signals.

[0071] Similarly, the low-side device 41 can trigger an interruption by closing an interrupt switch 44 connected across terminals F2 and H2 of the secondary coil 52. The high-side device 11 can control the state of the interrupt switch 44 via a control signal SW2. A closed interrupt switch 44 short-circuits terminals F2 and H2 together to the same potential (e.g., ground). The low-voltage device 11 may include a short-circuit detector that detects such a short circuit on the primary side, which the low-voltage device 11 interprets as a transmission request from the secondary side (i.e., from the low-side device 41). In response to the transmission request, the low-voltage device 11 can interrupt any primary-to-secondary transmission (communication signals or power) to allow the low-side device 41 to send its communication signals.

[0072] In one example, the multi-voltage domain system 100 can operate in common-mode at 130V with a floating supply having a maximum operating range of 30V. In this example, VB operates at a maximum of 160V, VS at a maximum of 130V, VCC at 30V, and VSS at 0V. Specifically, VS equals DC+ when transistor 2 is on (and transistor 1 is off), and VS equals DC- when transistor 1 is on (and transistor 2 is off). In both cases, VB remains substantially 30V higher than VS due to the energy storage capacitor 23. Therefore, with DC+ equal to the common-mode voltage of 130V, the low-side (external) supply voltage to VCC can be set to 30V, and the high-side supply voltage VB can operate at a maximum voltage of 160V. DC- is connected to ground / VSS, but this is not mandatory.

[0073] In another example, the multi-voltage domain system 100 can operate in common-mode at 1500V with a floating supply having a maximum operating range of 35V. In this example, VB operates at a maximum of 1535V, VS operates at a maximum of 1500V, VCC2 operates at 35V, and VSS operates at 0V. Specifically, when transistor 2 is on (and transistor 1 is off), VS equals DC+, and when transistor 1 is on (and transistor 2 is off), VS equals DC-. In both cases, VB remains substantially 35V higher than VS due to the energy storage capacitor 23. Therefore, with DC+ equal to the common-mode voltage of 1500V, the low-side supply voltage supplying VCC2 can be set to 35V, and the high-side supply voltage VB can operate at its maximum voltage of 1535V. DC- is connected to ground / VSS, but this is not mandatory.

[0074] It will be understood that the common-mode voltage and maximum operating range of the floating power supply are configurable and can be set to different voltages provided in the two examples above, including common-mode voltages between 130V and 1500V, less than 30V, or greater than 1500V. These voltages are set to allow the high-side voltage domain to operate at a higher voltage or power domain compared to the low-side voltage domain.

[0075] Figure 2 This is a schematic diagram of a bidirectional communication system of a multi-voltage domain system 100 according to one or more embodiments. However, it should be understood that the use of the bidirectional communication system can be extended more generally to any system exchanging a limited amount of digital data with an isolated (floating) voltage domain that also requires isolated power supplies. Furthermore, although... Figure 2 The transmission to / from the high-side chip 20 uses transformer 30, but the disclosed transmission principle can be similarly applied to the transmission to / from the low-side chip 40 using transformer 50.

[0076] Low-side to high-side transmission can be called primary-side to secondary-side transmission or uplink transmission, while high-side to low-side transmission can be called secondary-side to primary-side transmission or downlink transmission.

[0077] exist Figure 2 The diagram illustrates a circuit used to explain the transmission of communication signals and power between two chips 10 and 20 using a core transformer 30. The LV field is defined by a power supply voltage V1 (e.g., VCC1) and a reference voltage Ref1 (e.g., ground or VSS1), and the HV field is defined by a floating power supply voltage V2 (e.g., VB) and a floating reference voltage Ref2 (e.g., VS).

[0078] Figure 3 This is a timing diagram based on the main communication signals (i.e., those communication signals transmitted from the low-voltage device 11 to the high-side device 21) and power transmission of the multi-voltage domain system 100. Figure 2 The description is as follows. Multiple bits can be transmitted during a data transmission cycle.

[0079] As described above, input chip 10 acts as the master device, while high-voltage high-side chip 20 acts as the slave device. Both chips 10 and 20 share a common structure for signal management, but differ in their energy transfer functions. Specifically, the master device is configured to transfer energy to the secondary side of transformer 30, while the slave device has the function of appropriately storing this energy in energy storage capacitor Ctank 23, as described above.

[0080] The energy management block and its presence in the low-side chip 10 / high-side chip 20 include: a power transmission bridge 12 in the input chip 10, a data transmission bridge 13 (i.e., the master transmitter) in the low-voltage chip 10, a data transmission bridge 25 (i.e., the slave transistor) in the high-side chip 20, a data transmission receiver 14 (i.e., the master receiver) in the input chip 10, a data transmission receiver 26 (i.e., the slave receiver) in the high-side chip 20, a digital core 16 in the input chip 10 including processing and / or control circuitry, a digital core 28 in the high-side chip 20 including processing and / or control circuitry, and a high-side gate driver 29 in the high-side chip 20 that drives the power transistor 2 based on control signals received from the digital core 28. A diode bridge 22 including four diodes D1 to D4, an energy storage capacitor Ctank 23, and an interrupt switch 24 are also shown according to the above description.

[0081] Circuits 12, 13, and 14 can be integrated into Figure 1 In the low-voltage device 11 shown, circuits 22, 24, 25, and 26 can be integrated into Figure 1 In the high-side device 12 shown, a storage capacitor Ctank 23 is connected to the high-side chip 20, but is disposed externally thereon. The storage capacitor Ctank 23 is connected to the output of the diode bridge 22, stores the energy provided by the diode bridge 22, and further provides voltages V2 and Vref2 to the circuitry of the high-side chip 20.

[0082] Note that bridges 12, 13, and 25 are full-bridge circuits, each including four transistors. Specifically, power transmission bridge 12 is a full bridge including transistors Q1, Q2, Q3, and Q4; data transmission bridge 13 is a full bridge including transistors TX1, TX2, TX3, and TW4; and data transmission bridge 25 is a full bridge including transistors TX21, TX22, TX23, and TW24.

[0083] Furthermore, the data transmission receiver 14 includes two input terminals coupled to the two terminals E1 and A1 of the primary coil for receiving voltage potentials from them, the difference of which can be decoded into a data signal. Similarly, the data transmission receiver 26 includes two input terminals coupled to the two terminals F1 and H1 of the secondary coil for receiving voltage potentials from them, the difference of which can be decoded into a data signal.

[0084] The power transmission bridge 12 provides power transmission, and the data transmission bridge 13 provides data transmission. They operate in a complementary manner according to, for example, a TDMA protocol, and they are never simultaneously active. The purpose of the power transmission bridge 12 is to transfer energy from the primary power source V1 to the energy storage capacitor Ctank 23. The purpose of the data transmission bridge 13 is to transfer digital information from the input chip 10 to the high-side chip 20, or more generally, to the secondary side of the transformer 30. The data transmission bridge 25 has the same purpose for data transmission in the opposite direction, particularly for sending digital information from the high-side chip 20 to the input chip 10.

[0085] Data transmission bridges 13 and 25 can use smaller output switches (e.g., MOSFETs) than power transmission bridge 12. This will help increase the transmission frequency of data transmission while maintaining reduced power consumption during data transmission.

[0086] Figure 3 The timing diagram shows the voltage signals Ve1-Va1 across the primary coil 31. The voltage signals Ve1-Va1 are rectangular waves that switch between low and high states with a period of Tpwr. Data and power signals originating from the input chip 10 are also shown, each with a transmission time interval and a high impedance (Hi-Z) time interval during which transmission is blocked. Specifically, bridges 12, 13, and 25 remain in a high impedance state when they are not switching. The high impedance (Hi-Z) time intervals are complementary to the data and power signals, allowing the data and power signals to be allocated different time slots for transmission through the channel formed by transformer 30.

[0087] During the power transmission interval, the power signal has a frequency Fpwr = 1 / Tpwr. Therefore, the frequency of the power signal matches the frequency of the voltage signal Ve1-Va1. On the other hand, during data transmission, the data signal has a frequency Fsig = 1 / Tsig, where the period of the data signal Tsig is less than the period Tpwr. Therefore, the frequency Fsig of the data signal is higher than the frequency Fpwr of the power signal. Furthermore, the data transmission bridge 13 communicates with the data transmission receiver 26 at a frequency Fdrive = 1 / Tdrive, where Tdrive is the drive cycle or interval that spans the start of the data transmission interval and the end of the adjacent high-impedance (Hi-Z) interval. In other words, Tdrive is the time interval that spans the start of the data transmission interval and the start of the next data transmission interval. To ensure correct functioning, the following relationship should be observed:

[0088] Fdrive <Fpwr<Fsig(1)

[0089] For example, Fdrive can be set to 25kHz, Fpwr can be set to 250kHz, and Fsig can be set to 2.5MHz; this is just one example.

[0090] In other words, the length of the time slot allocated to the power signal is longer than the length of the time slot allocated to the data signal, and the frequency (Hz) of the data signal is higher than the frequency (Hz) of the power signal. The time slots allocated to the power signal and the time slots allocated to the data signal are interleaved. The drive period, defined by the length of two consecutive time slots (one allocated to the power signal and one allocated to the data signal), is longer than the period of the power signal (Tpwr = 1 / Fpwr), and the period of the power signal is longer than the period of the data signal (Tsig = 1 / Fsig).

[0091] Data receivers 14 and 26 are each composed of a high-pass filter, which includes two filter capacitors Cf and a filter resistor Rf. The high-pass filter is tuned to suppress the power transmission frequency Fpwr and sense the data transmission frequency Fsig (e.g., in the range of 1MHz to 10MHz, depending on the transformer bandwidth). Therefore, the respective frequencies are set according to equation (1) so that the high-pass filter can distinguish between the power signal and the data signal, allowing the data signal to pass while attenuating the power signal. Receiver 14 is configured to demodulate the digital signal received at pins E1 and A1, while receiver 26 is configured to demodulate the digital signal received at pins F1 and H1.

[0092] Each data receiver 14 and 26 also includes comparators 15 and 27, respectively, which demodulate the received data signal by converting a signal defined at the output of the high-pass filter (or at the input of comparators 15, 27) into a digital (differential) signal representing the bit value of the data signal.

[0093] The data signal is output from the comparator 15 at receiver 14 (data output) and provided to the digital core 16. The digital core 16 can provide the data decoded from the digital signal as feedback information FB to the microcontroller 3.

[0094] Similarly, the data signal is output from the output (data output) terminal of the differential amplifier 27 at receiver 26 and provided to the digital core 28. The data signal can be a control signal representation of the PWM control signal HIN used to turn the power transistor 2 on / off. The data signal may also include other information, including but not limited to, the strength of the current to be supplied to the gate (i.e., the amplitudes of currents IO+ and IO-), the bias configuration, and the undervoltage lockout (UVLO) detection voltage (i.e., the voltage value to be used as the threshold for UVLO detection).

[0095] When data transfer from the low-voltage side to the high-voltage side is required (e.g., in the gate driver, to control the change of the state of the high-side transistor switch 2), the power transfer bridge 12 is turned off (high impedance), and after a delay period, the data transfer bridge 13 is activated to perform serial communication using the transmission protocol. Data transfer receivers 14 and 26 are always active. Due to the nature of the input chip 10, which manages the transfer of energy from the input chip 10 to the high-side chip 20, data transfer must use a master-slave configuration.

[0096] High-side to low-side data transfer (i.e., secondary-side to primary-side transfer) may occur only after low-side to high-side (i.e., primary-side to secondary-side transfer) data transfer, or when an interrupt is triggered by the control signal SW1 using interrupt switch 24. This does not imply an impact on characteristics, as high-side to low-side data is typically represented by diagnostic signals that can be delayed (e.g., undervoltage lockout (UVLO) and desaturation (DESAT)).

[0097] In cases where more critical diagnostic or fault signals need to be sent (e.g., rapid diagnostic detection), the interrupt provides the option to send high-side to low-side data transmission without waiting for low-side to high-side data transmission. Digital core 28, for example, generates a control signal SW1 in response to a detected fault condition to control the state of interrupt switch 24. When interrupt switch 24 is closed, it short-circuits the F1 and H1 terminals of secondary coil 32 to the same potential (e.g., ground). This can trigger a short-circuit detection on the primary side, which is then interpreted by the main receiver 14 as a transmission request. Specifically, comparator 15 detects a short circuit via terminals E1 and A1 and outputs a short-circuit detection signal to digital core 16. Digital core 16 then interrupts current transmission (i.e., power transmission bridge 12 and data transmission bridge 13 are both turned off (high impedance)) to allow data transmission from high-side chip 20 to input chip 10.

[0098] The high-side to low-side data signal can also be used to generate a closed-loop (discrete-time) secondary power supply. In practice, the high-side chip 20 on the secondary floating side can sense, digitally convert, and feed back the voltage level of its power supply to the input chip 10 on the primary side. The power transmission bridge 12 can then be controlled by the digital core 16 to adapt its power transmission frequency to the charging state of the energy storage capacitor Ctank 23, thereby limiting power consumption and improving electromagnetic interference (EMI) performance.

[0099] Therefore, the core transformer 30 serves both as a source of floating voltage for the high-side chip 20 by transferring energy from the input chip 10 to the high-side chip 20, and as a bidirectional digital data transmission channel for data transmission between chips 10 and 20 in the isolated gate driver. Thus, instead of integrating a high-voltage isolation barrier within the chip, such isolation can be provided at the system level between the two chips. This results in a simpler design, fewer external components, and lower manufacturing costs due to the avoidance of costly on-chip isolation processes.

[0100] Figure 4 A schematic diagram of a high-side circuit 200 according to one or more embodiments is shown. Specifically, the high-side circuit 200 is... Figure 1 and Figure 2 An alternative configuration of the high-side circuitry is shown. The high-side circuitry 200 includes a bipolar power supply for supplying power to the gate driver 29.

[0101] Here, the secondary side (i.e., the high-side chip 20) is configured to ensure bipolar bias (e.g., +15, -5V) for the high-side gate driver, as is common in high-power IGBTs, GaN, and SiC power switches. In this case, since one of the terminals of the secondary coil 32 (i.e., terminal H1) is fixed as “center ground” HVGND, only the half-bridge transmitter 25hb can be used as a high-side to low-side data transmitter to transmit data to the input chip 10. The center ground voltage HVGND is 0V. Diodes D5 and D6 are configured to rectify the voltage received at terminals F1 and H1 of the secondary coil 32. Energy storage capacitors C1 and C2 are configured as a voltage divider to generate supply voltages V2 and Ref2, and to maintain the center ground voltage HVGND at 0V.

[0102] This particular arrangement can be used when voltage V2 is applied to the gate of transistor 2, with the emitter of transistor 2 serving as a reference for turning on transistor 2, and voltage Ref2 is applied to the gate of transistor 2, with the emitter of transistor 2 serving as a reference for turning off transistor 2. In other words, the gate of transistor 2 is driven by a negative voltage (Ref2) compared to its emitter to turn off transistor 2.

[0103] The high-side to low-side data signal can also be used to generate a closed-loop (discrete-time) secondary power supply. In practice, the high-side chip 20 on the secondary floating side can sense, digitally convert, and feed back the voltage level of its power supply to the input chip 10 on the primary side. The power transmission bridge 12 can then be controlled by the digital core 16 to adapt its power transmission frequency to the charging states of the energy storage capacitors C1 and C2, thereby limiting power consumption and improving electromagnetic interference (EMI) performance.

[0104] In a gate driver system, there is a small delay (e.g., 100 ns or more) between the time it takes for the PWM control signal HIN or LIN to be received at input chip 10 and the time it takes for the information to be transmitted via the core transformer to the appropriate gate driver for turning the power transistor on / off (e.g., gate driver 29 for high-side switch 2). For example, there is a delay between the time it takes for input chip 10 to receive the external command HIN from MCU 3 and the time it takes for high-side transistor switch 2 to effectively turn on or off in response to the command HIN. Once power transmission stops to allow data transmission of the control signal, the transformer current of transformer 30 needs some time to drop to zero, mainly due to parasitic leakage inductance. During this period, the secondary-side diodes D1 and D3 or diodes D2 and D4 (these two diodes depend on the configuration of the primary side and on the energy in the leakage inductance) remain conducting, thus shorting any transmitted signal to a low-impedance signal short (energy storage capacitor Ctank 23). In this case, data transmission may be affected due to the damping effect of energy storage capacitor Ctank 23. This delay can be so small as to be negligible. However, if this delay becomes too large, or if a reduction in transmission delay is desired, three additional solutions are provided.

[0105] First, once digital core 16 detects an interrupt command triggered by the closing of interrupt switch 24, it shuts down power transmission bridge 12 to stop power transmission. When the interrupt command is triggered at interrupt switch 24, the high-side digital core 28 is configured to wait a predetermined amount of time before using transmitter 25 to begin its data transmission. This predetermined amount of time is at least set to the maximum time period required for the leakage inductance of secondary coil 32 to discharge. In this case, the delay is accepted and known.

[0106] Secondly, the digital core 16 can utilize predictive signal action to compensate for leakage inductance delay by prematurely stopping power transmission through the power transmission bridge 12. Typically, the signal delay is known (e.g., 1 μs). Therefore, the digital core 16 can, for example, stop power transmission 1 μs (prematurely) to address the delay.

[0107] Third, during the data transmission idle time when transmitters 13 and 25 are set to high impedance, input chip 10 transmits power only using a square wave of fixed frequency Fpwr. A phase-locked loop (PLL) in high-side chip 20 can be implemented to generate an exact copy of the frequency and phase of the square wave used to transmit power to high-side chip 20. During power-on in high-side chip 20, the locking of this PLL should occur before the effective switching of the high-side gate driver. Other embodiments will describe in detail the PLL arrangement for performing fast data transmission across a core transformer implemented in a gate driver system.

[0108] Figure 5This is a schematic diagram of another data transmission system 300 disposed on the primary side of a cored transformer according to one or more embodiments. Figure 6 This is a schematic diagram of another data receiving system 400 disposed on the secondary side of a cored transformer, according to one or more embodiments. A data transmitting system 300 is configured to work in conjunction with the data receiving system 400 to transmit information to the data receiving system 400. Specifically, systems 300 and 400 form a PLL-based communication system.

[0109] The data transmission system 300 is configured to transmit information from the LV domain (i.e., from the input chip 10) to a chip connected to the secondary side of the core transformer via a core transformer. The data transmission system 300 is configured to rapidly transmit single bits by changing the phase of the power line carrier signal.

[0110] The data transmission system 300 includes: a stable power carrier generator 60 (i.e., an oscillator with a fixed frequency (typically in the range of 50 kHz to 700 kHz)) that generates a square wave as a reference power carrier signal with a reference phase (defined here as 0°). An inverter 61 with negligible delay (e.g., a complementary metal-oxide-semiconductor (CMOS) inverter or NOT gate) generates a 180° phase-shifted power carrier signal with a (out-of-phase) 180° phase relative to the reference power carrier signal. Both the reference power carrier signal and the phase-shifted power carrier signal are provided to a diverter 62, which further receives a PWM control signal HIN from the microcontroller 3. Note that the PWM control signal LIN will be used for transmission to the low-side chip 40.

[0111] Shunt 62 is configured to couple a reference power line carrier signal or a phase-shifted power line carrier signal to power transmission bridge 12 (see PWM control signal HIN) based on the PWM control signal HIN. Figure 2 For example, when the PWM control signal HIN is high, shunt 62 selectively couples the phase-shifted power line carrier signal to the power transmission bridge 12 to turn on the power transistor 2. Alternatively, when the PWM control signal HIN is low, shunt 62 selectively couples the reference power line carrier signal to the power transmission bridge 12 to turn off the power transistor 2. Thus, shunt 62 is configured to encode data (e.g., a single data bit) onto the power signal coupled to the primary coil 31 based on whether the reference power line carrier signal or the phase-shifted power line carrier signal is selected.

[0112] A coupled carrier signal is provided to the gates of transistors Q1 to Q4 of the power transmission bridge 12, and the power transmission bridge 12 generates a power signal based on the coupled carrier signal (i.e., based on either a reference power carrier signal or a phase-shifted power carrier signal). The data receiving system 400 is configured to detect the phase of the coupled power carrier signal to determine whether a turn-on command (i.e., an on bit) or a turn-off command (i.e., a turn-off bit) is sent by the power transmission bridge 12. The power transistors 2 can then be turned on / off according to the received command, while power is still transmitted to the secondary side of the core transformer 30.

[0113] The power transmission bridge 12 is driven by a 0° phase carrier when the input is low (meaning the power switch is off on the high side) and by a 180° phase carrier when the input is high (meaning the power switch is on). During a fixed period of time during system startup (i.e., the initialization period), the power transmission bridge 12 is driven only by the 0° reference power carrier signal, regardless of the HIN input state. That is, the shunt 62 is locked to the reference power carrier signal during the initialization period and does not respond to the PWM control signal HIN. This fixed period is determined by the need to establish a stable power supply for the high-side chip 20 plus the time interval used by the PLL in the high-side chip 20 to obtain a precise and stable locking condition with the 0° reference power carrier signal. Once the initialization period has passed, the shunt 62 responds to the PWM control signal HIN by selectively coupling either the reference power carrier signal or a phase-shifted power carrier signal to the power transmission bridge 12.

[0114] Note that the power transmission carrier generator 60 can also be used in... Figure 2 The input chip 10 shown is used to generate a square wave power transmission signal as a direct coupling to the power transmission bridge 12 transistors Q1 to Q4.

[0115] Figure 6 The data receiving system 400 shown is configured to receive information from the LV domain (i.e., from the input chip 10) via a power transmission signal. The data receiving system 400 can be used in conjunction with the power transmission section of system 100, which uses the power transmission signal to generate power supply voltages V2 and Ref2. Specifically, although not shown, the diode bridge 22 and the energy storage capacitor Ctank 23 can be coupled to terminals E1 and H1 of the secondary coil 32, as previously described. Figure 2 As described, power supply voltages V2 and Ref2 are used to supply power to the components of the high-side chip 20. In this case, a reference power line carrier signal and a phase-shifted power line carrier signal are used for power transmission signals, both of which charge the energy storage capacitor Ctank 23. The difference here is that the power transmission signals are used synchronously to transmit data bits to control the state of the power transistor 2.

[0116] The transformer outputs F1 and H1 of the secondary coil 32 are converted into square waves by a low-delay comparator 70. The output Cout of the low-delay comparator 70 is a copy of the power transmission carrier frequency of the received power transmission carrier signal. Specifically, the output Cout of comparator 70 is more like a square wave, while the input of comparator 70 is noisy and has no explicitly defined high or low levels. Comparator 70 sets the signal to an appropriate digital level that changes (alternates) according to the power transmission carrier frequency. The comparator output Cout has the same phase (0° or 180°) as the power transmission carrier signal coupled in by shunt 62 to drive the primary side of the transformer (i.e., the same phase as the reference power transmission carrier signal or the phase-shifted power transmission carrier signal).

[0117] The data receiving system 400 includes a flip-flop 82 for storing the state (on-off) of the power transistor 2 driven by the gate driver 29. When a phase-shifted power line carrier signal is received at the secondary coil 32, the output (Q) of the flip-flop 82 is set high (logic state 1) via the SET (S) input, and when a reference power line carrier signal is received at the secondary coil 32, the output (Q) of the flip-flop 82 is set low (logic state 0) via the RESET (R) input. This memory cell is RESET-dominated. In other words, if both the SET and RESET commands are present, the flip-flop 82 is in the RESET state. The flip-flop 82 is initialized during system startup by a power-on reset (POR) circuit during the initialization cycle in the 0 logic state (i.e., transistor 2 is off), which provides a high POR signal to an OR gate 81. The OR gate 81 generates a high signal in response to the high POR signal, which pulses the RESET input of the flip-flop 82 and keeps transistor 2 off. Once the initialization cycle has passed, the POR circuit provides a low POR signal to OR gate 81, thereby allowing the output of OR gate 81 to be controlled by its other input terminal.

[0118] The data receiving system 400 further includes an inverter 71 (e.g., a CMOS inverter or NOT gate) and a shunt 72 that selectively switches between two inputs based on the output (Q) of a flip-flop 82. The inverter 71 receives the comparator output Cout and inverts it to generate Cout(NOT). Therefore, Cout(NOT) always has an out-of-phase (180°) phase relative to the power transmission carrier signal. When the output (Q) of the flip-flop 82 is low, the shunt 72 is selectively coupled to the comparator output Cout, and when the output (Q) of the flip-flop 82 is high, the shunt 72 is selectively coupled to Cout(NOT).

[0119] During initialization, flip-flop 82 is in the RESET state, and shunt 72 connects the comparator output Cout to the input of PLL 73, enabling PLL 73 to achieve stable locking with the 0° reference power line carrier signal.

[0120] Based on the input selection made by shunt 72, the output of shunt 72 always has a 0° phase. For example, when transistor 2 is about to turn off, a 0° reference power line carrier signal is provided to the secondary side, meaning the output of flip-flop 82 is low, and the comparator output Cout, with a 0° phase copy of the 0° reference power line carrier signal, is coupled to PLL 73. Conversely, when transistor 2 is about to turn on, a 180° phase-shifted power line carrier signal is provided to the secondary side, meaning the output of flip-flop 82 is high, and the inverted comparator output Cout(NOT), with a 180° phase-shifted power line carrier signal, is coupled to PLL 73. 180° inversion is 0°. Therefore, in this case, Cout(NOT) with a 0° phase is coupled to PLL 73. Thus, PLL 73 remains locked to the 0° power line carrier signal and outputs a 0° phase carrier copy signal PLLout.

[0121] Inverter 74 (e.g., a CMOS inverter or NOT gate) is connected to the PLL output PLLout to generate an inverted (180° phase copy) of PLLout in the form of PLLout(NOT).

[0122] The PLL outputs PLLout (0° phase copy) and inverted (180° phase copy) PLLout (NOT) are provided as inputs to a two-phase discriminator, which includes an XOR gate 75, an inverter 76 (e.g., a CMOS inverter NOR gate), a deglitch filter 77, an XOR gate 78, an inverter 79 (e.g., a CMOS inverter NOR gate), and a deglitch filter 80. The XOR and NOT gates (inverters) can also be replaced by XNOR gates. The two-phase discriminator is configured to discriminate the phase of the comparator output Cout and set the state of flip-flop 82 accordingly (Q is set high if Cout has a 0° phase, and low if Cout has a 180° phase). Flip-flop 82 decodes the determined phase of the electrical signal received at secondary coil 32 into the corresponding bit value—logic 1 or logic 0. Therefore, the flip-flop is a bit decoder configured to extract encoded bits based on the determined phase of the electrical signal relative to the phase of the PLL output signal PLLout.

[0123] XOR generates a low (logic 0) output when its two inputs are the same and a high (logic 1) output when its two inputs are different. Therefore, when the phase of Cout is 180°, XOR 75 generates a low output, indicating that a phase-shifted power line carrier signal has been transmitted to turn on transistor 2. Inverter 76 converts this low output to a high output (logic 1) to set flip-flop 82. Conversely, when the phase of Cout is 0°, XOR 78 generates a low output, indicating that a reference power line carrier signal has been transmitted to turn off transistor 2. Inverter 79 converts this low output to a high output (logic 1) to reset flip-flop 82. Thus, the two-phase discriminator can determine whether the power line carrier received from the low side is in phase with the 0° phase PLL output PLLout, or in phase with the 180° carrier copy PLLout (NOT) generated by the low-delay inverter 74 applied to the PLL output PLLout. Flip-flop 82 decodes the determined phase of the power signal received at secondary coil 32 into the corresponding bit value—logic 1 or logic 0. Therefore, the trigger is a bit decoder configured to extract coded bits based on the phase of the determined power signal relative to the phase of the PLL output signal PLLout.

[0124] The system is fully synchronized, so only 0° and 180° phase are possible. However, slight misalignment may occur on the rising and falling edges of PLLout and PLLout(NOT), resulting in glitches at the outputs of XOR 75 and XOR 78. These glitches can be removed at the cost of a few nanoseconds of delay by low-pass de-glitches 77 and 80. Each of the de-glitches 77 and 80 includes a resistor (R1 or R2) and a capacitor (C1 or C2) coupled in a low-pass filter configuration. De-glitcher 77 filters out sharp glitches caused by brief misalignment of the falling and / or rising edges of Cout and PLLout(NOT). De-glitcher 80 filters out sharp glitches caused by brief misalignment of the falling and / or rising edges of Cout and PLLout.

[0125] Figure 7 It is located along Figure 6 The signal diagrams at the various nodes of a portion of the two-phase discriminator are shown. Specifically, the signals at nodes V, W, X, Y, and Z are shown, where the signal at node V is Cout and the signal at node W is PLLout (NOT). SET is activated at flip-flop 82 if the carrier phase from the low-voltage side is 180°. De-glitch filter 77 removes any glitches that may occur due to brief misalignment of the falling and / or rising edges of Cout and PLLout (NOT).

[0126] Circuit elements XOR 78, inverter 79, and de-glitch filter 80 operate in a similar manner, where the signal at node V is Cout and the signal at node W is PLLout. In that case, if the transmitted carrier has a 0° phase, the RESET of flip-flop 82 is active (set high via OR gate 81). As described above, shunt 72 is driven by the flip-flop state such that the PLL input of PLL 73 always receives a 0° phase.

[0127] Figure 8 This is a signal diagram of the signals at each stage of the PLL-based communication system, including the PWM control signal HIN, the carrier power signal at the primary coil of the core transformer, the output signal PLLout of PLL 73, and the on / off state of the power transistor 2 controlled by the gate driver 29.

[0128] The secondary-side PLL 73 generates an exact copy of the reference power carrier signal (square wave) in terms of phase and frequency, generated by the primary-side power transmission carrier generator 60. Locking of the PLL 73 occurs during high-side power-on and before the gate driver 29 effectively switches transistor 2. The copied reference power carrier signal is then used by a two-phase discriminator to determine the value of the transmission bit (i.e., 0 or 1) to control the on / off state of transistor 2, where 0 bits turn off transistor 2 and 1 bit turns it on. A similar transmission scheme can also be used to control transistor 1 via the core transformer 50.

[0129] according to Figure 8 The phase of the carrier power signal at the primary coil is reversed relative to PLLout by shunt 62, thus ideally transmitting the on state (HIN = high). When the off state (HIN = low) is desired, the phase of the carrier power signal at the primary coil is switched by shunt 62 to be in phase with PLLout. Of course, out-of-phase and in-phase can be configured to have opposite meanings; with minor adjustments to the programming and circuitry, out-of-phase indicates the on state, and in-phase indicates the off state.

[0130] Figure 5 and Figure 6 The PLL-based communication system described in [the document] inherently exhibits [better characteristics] than [other systems]. Figure 2 The bidirectional communication system shown has low performance. The PLL-based communication system transmits only a single bit in one direction. If the PLL lock condition is lost for any reason, the communication system fails and it is not easy to send back the fault condition. On the other hand, compared to the bidirectional communication system, the PLL-based communication system can transmit faster to reduce communication delays caused by the on / off states of transistor 2.

[0131] Therefore, the two communication systems (i.e., the PLL-based communication system and the bidirectional communication system) can be combined to take advantage of their respective strengths. Both communication systems can be coupled to the terminals of the core transformer and provide communication for their respective digital cores. In particular, the combined communication system implements bidirectional communication in addition to the fast transmission based on the PLL. The fast power switching commutation is performed by the PLL-based communication system, but immediately after the commutation, the high-side chip 20 can expect serial communication from the bidirectional communication system to confirm the new switching state of transistor 2. If no serial communication occurs within a given short delay period, the digital core 28 turns off transistor 2 and generates a fault signal to be sent to the digital core 16 via the bidirectional communication system.

[0132] Therefore, digital core 28 monitors data transmission received by the PLL-based communication system (i.e., by the data receiving system 400), detects the reception of data bits used to control the state of transistor 2, and starts a timer to further monitor data transmission received by the bidirectional communication system (i.e., by the receiver 26). If the timer reaches or exceeds a predetermined threshold before the receiver 26 receives data transmission, a fault signal is generated and sent by transmitter 25. If the receiver 26 receives data transmission within the predetermined threshold, no fault signal is generated.

[0133] Additional implementation methods include:

[0134] 1. A gate driver communication system, comprising:

[0135] A cored transformer includes a primary coil disposed on the primary side, a secondary coil disposed on the secondary side, and a core connecting the primary coil to the secondary coil, wherein the secondary coil is configured to receive data-encoded power signals.

[0136] A primary-side power signal generator, coupled to a primary coil, is configured to generate a data-coded power signal with a fixed frequency and a phase that varies based on the coded bit value;

[0137] A power transmission carrier generator is arranged on the primary side and configured to generate a zero-phase power carrier signal with a fixed frequency and a fixed phase;

[0138] An inverter configured to invert a zero-phase power carrier signal to generate a phase-shifted power carrier signal; and

[0139] A shunt is configured to selectively couple a zero-phase power line carrier signal to a primary-side power signal generator to encode bits with the first bit value onto a data-encoded power signal, and selectively couple a phase-shifted power line carrier signal to the primary-side power signal generator to encode bits with the second bit value onto a data-encoded power signal.

[0140] The primary-side power signal generator is configured to generate a data-coded power signal with coded bits based on a received zero-phase power carrier signal or a phase-shifted power carrier signal.

[0141] 2. The gate driver communication system according to embodiment 1 further includes:

[0142] A power transistor, disposed on the secondary side, and configured to conduct load current based on the on / off state of the power transistor; and

[0143] A gate driver, disposed on the secondary side, is configured to drive the on / off state of the power transistor based on coded bits extracted by a PLL-based receiver, wherein the gate driver is configured to turn on the power transistor in response to encoding a data-coded power signal with a first bit value, and the gate driver is configured to turn off the power transistor in response to encoding the data-coded power signal with a second bit value.

[0144] 3. The gate driver communication system according to Embodiment 2, wherein:

[0145] When the shunt couples the phase-shifted power carrier signal to the primary-side power signal generator, the first bit value is used to encode the data-encoded power signal, and

[0146] When the shunt couples the zero-phase power carrier signal to the primary-side power signal generator, the data-encoded power signal is encoded using the second bit value.

[0147] 4. The gate driver communication system according to embodiment 1 further includes:

[0148] A phase-locked loop (PLL) based receiver, coupled to a secondary coil and configured to receive and decode data-encoded electrical signals to extract encoded bits therefrom, wherein the PLL-based receiver includes:

[0149] PLL, which is configured to generate a PLL signal that is locked to a zero-phase power line carrier signal in both frequency and phase;

[0150] A dual-phase discriminator circuit is configured to receive a PLL signal and determine the phase of the data-encoded power signal received at the secondary coil based on the PLL signal; and

[0151] A bit decoder is configured to extract coded bits based on the phase of the determined data-coded power signal relative to the PLL signal.

[0152] 5. The gate driver communication system according to embodiment 4 further includes:

[0153] A power supply circuit, coupled to a secondary coil, is configured to: receive a data-encoded electrical signal, convert the data-encoded electrical signal into stored energy, and supply the stored energy to a PLL-based receiver.

[0154] 6. The gate driver communication system according to embodiment 5 further includes:

[0155] A power transistor, disposed on the secondary side, and configured to conduct load current based on the on / off state of the power transistor; and

[0156] A gate driver, disposed on the secondary side, is configured to drive the on / off state of the power transistor based on coded bits extracted by a PLL-based receiver.

[0157] The power supply circuit is configured to supply the stored energy to the gate driver so that the gate driver can drive the power transistor to the on / off state.

[0158] 7. A gate driver communication system, comprising:

[0159] A cored transformer includes a primary coil disposed on the primary side, a secondary coil disposed on the secondary side, and a core connecting the primary coil to the secondary coil, wherein the secondary coil is configured to receive data-encoded power signals; and

[0160] A phase-locked loop (PLL) based receiver, coupled to a secondary coil and configured to receive and decode data-encoded electrical signals to extract coded bits therefrom, wherein the PLL-based receiver includes:

[0161] PLL, which is configured to generate a PLL signal that is locked to the reference signal in both frequency and phase;

[0162] A dual-phase discriminator circuit is configured to receive a PLL signal and determine the phase of the data-encoded power signal received at the secondary coil based on the PLL signal; and

[0163] A bit decoder is configured to extract coded bits based on the phase of the determined data-coded power signal relative to the PLL signal.

[0164] 8. The gate driver communication system according to embodiment 7, wherein the bit decoder is a flip-flop.

[0165] 9. The gate driver communication system according to embodiment 7 further includes:

[0166] A power supply circuit, coupled to a secondary coil, is configured to: receive a data-encoded electrical signal, convert the data-encoded electrical signal into stored energy, and supply the stored energy to a PLL-based receiver.

[0167] 10. The gate driver communication system according to embodiment 9, wherein:

[0168] The power supply circuit includes a diode bridge and an energy storage capacitor, as well as

[0169] A diode bridge is configured to rectify a power signal into a DC voltage stored in an energy storage capacitor.

[0170] 11. The gate driver communication system according to embodiment 10 further includes:

[0171] A power transistor, disposed on the secondary side, and configured to conduct load current based on the on / off state of the power transistor; and

[0172] A gate driver, disposed on the secondary side, is configured to drive the on / off state of the power transistor based on coded bits extracted by a PLL-based receiver.

[0173] The power supply circuit is configured to supply the stored energy to the gate driver so that the gate driver can drive the power transistor to the on / off state.

[0174] While various embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made to achieve some of the advantages of the concepts disclosed herein without departing from the spirit and scope of the invention. It should be understood that other embodiments can be utilized, and structural or logical changes can be made, without departing from the scope of the invention. It should be mentioned that features illustrated with reference to specific figures can be combined with features of other figures, even if not explicitly stated. Such modifications to the general inventive concept are intended to be covered by the appended claims and their legal equivalents.

[0175] Furthermore, the appended claims are thus incorporated into the detailed description, wherein each claim may stand alone as a separate exemplary embodiment. While each claim may stand alone as a separate exemplary embodiment, it should be noted that although a dependent claim may refer in the claim to a specific combination of one or more other claims, other exemplary embodiments may also include combinations of dependent claims with the subject matter of each of the other dependent or independent claims. Such combinations are presented herein unless the description is not intended to suggest any particular combination. Moreover, even if a claim is not directly dependent on an independent claim, it is intended to include the features of the claim in any other independent claim.

[0176] It should also be noted that the methods disclosed in the specification or claims can be implemented by means having means for performing each of the corresponding actions of these methods. For example, the techniques described in this disclosure can be implemented at least in part in hardware, software, firmware, or any combination thereof—including any combination of computer programs on non-transitory computer-readable recording media, computing systems, and integrated circuits. For example, aspects of the described techniques can be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuits, and any combination of such components.

[0177] Furthermore, it should be understood that the disclosure of multiple actions or functions in the specification or claims is not necessarily construed as being in a specified order. Therefore, unless such actions or functions are technically incomparable, the disclosure of multiple actions or functions does not limit these actions or functions to a particular order. Additionally, in some embodiments, a single action may include or be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of that single action.

Claims

1. A gate driver communication system, comprising: A cored transformer includes a primary coil disposed on the primary side, a secondary coil disposed on the secondary side, and a core connecting the primary coil to the secondary coil, wherein the secondary coil is configured to receive power signals and uplink data signals from the primary coil. A primary-side power signal generator is coupled to the primary coil and configured to generate a power signal having a first frequency. A primary-side data transmitter, coupled to the primary coil, and configured to generate an uplink data signal having a second frequency different from the first frequency; and A primary-side controller is configured to distribute the power signal and the uplink data signal to the primary coil according to a plurality of time slots, wherein the power signal is distributed to a first time slot of the plurality of time slots, and the uplink data signal is distributed to a second time slot of the plurality of time slots. The primary-side controller is further configured to: During the first time slot, the primary-side power signal generator is activated and the primary-side data transmitter is deactivated. During the second time slot, the primary-side data transmitter is activated and the primary-side power signal generator is deactivated.

2. The gate driver communication system according to claim 1, wherein, The primary-side controller is configured to distribute the power signal and the uplink data signal to the primary coil using time division multiple access and according to multiple time slots.

3. The gate driver communication system according to claim 1, wherein, Each uplink data signal is a multi-bit data signal.

4. The gate driver communication system according to claim 1, wherein, The first frequency is less than the second frequency.

5. The gate driver communication system according to claim 1, wherein, Each of the first time slots has a first length, and each of the second time slots has a second length that is smaller than the first length.

6. The gate driver communication system according to claim 1, wherein, The primary side is configured to operate in a first voltage domain, and the secondary side is configured to operate in a second voltage domain isolated from the current in the first voltage domain.

7. The gate driver communication system according to claim 1, further comprising: A secondary receiver, coupled to the secondary coil, is configured to demodulate the uplink data signal to extract data therefrom; A secondary-side controller is configured to process data extracted by the secondary-side receiver; as well as A power supply circuit coupled to the secondary coil and configured to receive the power signal, convert the power signal into stored energy, and supply the stored energy to the secondary-side receiver and the secondary-side controller.

8. The gate driver communication system according to claim 7, wherein: The power supply circuit includes a diode bridge and an energy storage capacitor, and The diode bridge is configured to rectify the power signal into a DC voltage stored by the energy storage capacitor.

9. The gate driver communication system according to claim 7, further comprising: A power transistor is disposed on the secondary side and configured to conduct load current based on the on / off state of the power transistor. as well as A gate driver, disposed on the secondary side, is configured to drive the on / off state of the power transistor based on data extracted by the secondary-side receiver. The power supply circuit is configured to supply the stored energy to the gate driver so that the gate driver can drive the power transistor to the on / off state.

10. The gate driver communication system according to claim 1, further comprising: A secondary-side data transmitter, coupled to the secondary coil and configured to transmit downlink data signals, wherein the primary coil is configured to receive downlink data signals from the secondary coil; and A primary-side data receiver, coupled to the primary coil, is configured to demodulate the downlink data signal to extract data therefrom; The primary-side controller is configured to process data extracted by the primary-side data receiver.

11. The gate driver communication system of claim 10, further comprising: A secondary-side controller is configured to detect faults on the secondary side and generate a fault signal indicating the detected fault, wherein the downlink data signal includes the fault signal.

12. The gate driver communication system of claim 11, further comprising: A switch, coupled to two terminals of the secondary coil, is configured such that, when closed, it triggers an interrupt signal on the secondary coil by short-circuiting the two terminals to the same potential. The secondary-side controller is configured to control the switch, including closing the switch in response to a detected fault. The primary-side data receiver is configured to receive the interrupt signal at the primary coil, and The primary-side controller is configured to interrupt the transmission of the uplink data signal or the power signal in response to a received interrupt signal, so that the secondary-side data transmitter can send the fault signal to the primary-side data receiver.

13. The gate driver communication system according to claim 1, further comprising: A power transmission carrier generator is arranged on the primary side and configured to generate a zero-phase power transmission carrier signal having the first frequency; An inverter configured to invert the zero-phase power carrier signal to generate a phase-shifted power carrier signal; A shunt is configured to selectively couple the zero-phase power line carrier signal to the primary-side power signal generator to encode a first bit value onto one of the power signals, and selectively couple the phase-shifted power line carrier signal to the primary-side power signal generator to encode a second bit value onto one of the power signals. The primary-side power signal generator is configured to generate a power signal with coded bits based on receiving the zero-phase power carrier signal or the phase-shifted power carrier signal. as well as A phase-locked loop-based receiver, coupled to the secondary coil, is configured to receive and decode the power signal to extract the encoded bits.

14. The gate driver communication system of claim 13, further comprising: A power supply circuit, coupled to the secondary coil, is configured to: receive the power signal, convert the power signal into stored energy, and supply the stored energy to the phase-locked loop-based receiver.

15. The gate driver communication system according to claim 14, wherein: The power supply circuit includes a diode bridge and an energy storage capacitor, and The diode bridge is configured to rectify the power signal into a DC voltage stored by the energy storage capacitor.

16. The gate driver communication system of claim 14, further comprising: A power transistor is disposed on the secondary side and configured to conduct load current based on the on / off state of the power transistor; as well as A gate driver, disposed on the secondary side, is configured to drive the on / off state of the power transistor based on coded bits extracted by the phase-locked loop-based receiver. The power supply circuit is configured to supply the stored energy to the gate driver so that the gate driver can drive the power transistor to the on / off state.

17. The gate driver communication system according to claim 13, wherein, The phase-locked loop-based receiver includes: A phase-locked loop, configured to generate a phase-locked loop signal, the phase-locked loop signal being locked to the frequency and phase of the zero-phase power line carrier signal; A dual-phase discriminator circuit is configured to receive the phase-locked loop (PLL) signal and determine the phase of the power signal received at the secondary coil based on the PLL signal; and A bit decoder is configured to extract the encoded bits based on a determined phase of the power signal relative to the phase-locked loop signal.

18. The gate driver communication system according to claim 1, further comprising: A power transmission carrier generator is arranged on the primary side and configured to generate a zero-phase power transmission carrier signal having the first frequency; An inverter is arranged on the primary side and configured to invert the zero-phase power carrier signal to generate a phase-shifted power carrier signal; A shunt, disposed on the primary side, is configured to selectively couple the zero-phase power line carrier signal to the primary-side power signal generator to encode a first bit value onto one of the power signals, and selectively couple the phase-shifted power line carrier signal to the primary-side power signal generator to encode a second bit value onto one of the power signals. The primary-side power signal generator is configured to generate a power signal with coded bits based on receiving the zero-phase power carrier signal or the phase-shifted power carrier signal. A secondary receiver, coupled to the secondary coil, is configured to demodulate the uplink data signal to extract data therefrom; A phase-locked loop-based receiver, coupled to the secondary coil, is configured to receive and decode the power signal to extract the coded bits; The secondary-side controller is configured to process data extracted by the secondary-side receiver and coded bits extracted by the phase-locked loop-based receiver; A power transistor, disposed on the secondary side, and configured to conduct load current based on the on / off state of the power transistor; and A gate driver, disposed on the secondary side, is configured to drive the on / off state of the power transistor based on data extracted by the secondary-side receiver and coded bits extracted by the phase-locked loop-based receiver.

19. The gate driver communication system of claim 18, further comprising: A power supply circuit, coupled to the secondary coil, is configured to: receive the power signal, convert the power signal into stored energy, and supply the stored energy to the secondary-side receiver, the secondary-side controller, the phase-locked loop-based receiver, and the gate driver, such that the gate driver can drive the power transistor to the on / off state.

20. The gate driver communication system according to claim 1, wherein, When the primary-side data transmitter is activated, it transmits the uplink data signal and the primary-side power signal generator is configured in a high-impedance state; when the primary-side power signal generator is activated, it transmits the power signal and the primary-side data transmitter is configured in a high-impedance state.

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