shunt regulator

Abstract

This invention provides a shunt regulator that can quickly and stably transition to high-precision normal operation when the output voltage is low, such as during power-on. The shunt regulator of this invention includes: multiple resistors connected in series between an output terminal and a ground terminal to form a voltage divider circuit; an output transistor connected between the output terminal and the ground terminal; a first driving circuit including a first reference voltage circuit that outputs a first reference voltage and an error amplifier, controlling the output transistor based on the voltage at the first output terminal of the voltage divider circuit; a second driving circuit that controls the output transistor based on the voltage at the second output terminal of the voltage divider circuit; and a startup control circuit that switches the operation of the first driving circuit and the second driving circuit based on the first reference voltage, wherein the startup time of the second driving circuit is shorter than that of the first driving circuit.

Description

Technical Field

[0001] This invention relates to a shunt regulator, and more specifically to a stabilizing operation under low voltage conditions. Background Technology

[0002] Figure 4 This is a circuit diagram representing a conventional shunt regulator.

[0003] Figure 4 The shunt regulator includes a reference voltage circuit 101, an error amplifier 102, an N-channel metal-oxide-semiconductor (NMOS) transistor 103, and voltage divider resistors R1 and R2.

[0004] If the shunt regulator has a power supply voltage Vin at input, a current flows through the external resistor 110, and the resulting output voltage Vout drives the load 111. If the current flowing through the external resistor 110 with resistance value R is set as Ir, the current flowing through the load 111 is set as Io, and the current flowing through the shunt regulator IC is set as Ic, then the output voltage Vout is expressed by the following formula.

[0005] Vout=Vin-Ir / R=Vin-(Io+Ic) / R

[0006] In the shunt regulator, the NMOS transistor 103 adjusts the current Ic to obtain the desired output voltage Vout. That is, in the shunt regulator, there is always a current Io flowing to the load 111 and a current Ic flowing in the shunt regulator IC, thus consuming a lot of current. However, since the power supply voltage Vin is input through the external resistor 110, the power supply voltage Vin is not limited and is not affected by fluctuations. Therefore, the shunt regulator has the characteristic of good accuracy of the output voltage Vout (for example, see Patent Document 1).

[0007] Therefore, shunt regulators can be used in applications where the output current Io can be low but the accuracy of the output voltage Vout is required.

[0008] [Existing Technical Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] US Patent No. 8085006 Specification Summary of the Invention

[0011] [The problem the invention aims to solve]

[0012] However, the operating voltage of the shunt regulator circuit is based on the output voltage Vout. Therefore, when the output voltage Vout decreases, the reference voltage output by the reference voltage circuit 101 also decreases. Consequently, there is a problem that the time it takes for the output voltage Vout to reach the desired voltage becomes longer.

[0013] The present invention was made in view of the aforementioned problem, and its object is to provide a shunt regulator that can shorten the time it takes for the output voltage to rise from a low state to the desired voltage.

[0014] [Technical means to solve the problem]

[0015] An embodiment of the shunt regulator of the present invention includes: an output terminal connected to a power supply terminal via an external resistor; a plurality of resistors connected in series between the output terminal and a ground terminal to form a voltage divider circuit; an output transistor connected between the output terminal and the ground terminal; a first driving circuit including a first reference voltage circuit that outputs a first reference voltage and an error amplifier, which controls the output transistor based on the voltage of the first output terminal of the voltage divider circuit; a second driving circuit that controls the output transistor based on the voltage of the second output terminal of the voltage divider circuit; and a startup control circuit that switches the operation of the first driving circuit and the second driving circuit based on the first reference voltage, wherein the startup time of the second driving circuit is shorter than that of the first driving circuit.

[0016] [The effects of the invention]

[0017] The shunt regulator according to the present invention includes a first driving circuit and a second driving circuit for controlling the output transistor, and a start control circuit for switching the operation of the first driving circuit and the second driving circuit, thereby shortening the time for the output voltage to go from a low state to the required voltage. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating the shunt regulator of this embodiment.

[0019] Figure 2 This is a circuit diagram illustrating an example of the start-up control circuit of this embodiment.

[0020] Figure 3 This is a circuit diagram illustrating another example of the second drive circuit in this embodiment.

[0021] Figure 4 This is a block diagram representing an existing shunt regulator.

[0022] [Explanation of Symbols]

[0023] 10: First driving circuit

[0024] 11: First reference voltage circuit

[0025] 12: First Error Amplifier

[0026] 13, 14, 15: Resistors

[0027] 16, 23, 31: NMOS transistors

[0028] 20: Second drive circuit

[0029] 21: Second reference voltage circuit

[0030] 22: Second Error Amplifier

[0031] 24, 32: Constant current circuit

[0032] 25: Inverting amplifier circuit

[0033] 30: Start-up control circuit

[0034] 33: Inverting circuit

[0035] 100: Shunt regulator Detailed Implementation

[0036] The shunt regulator of the present invention will now be described with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating the shunt regulator 100 of this embodiment.

[0038] Figure 1 The shunt regulator 100 includes a first reference voltage circuit 11, a first error amplifier 12, resistors 13, 14, and 15 forming a voltage divider circuit, an NMOS transistor 16, a second reference voltage circuit 21, a second error amplifier 22, and a startup control circuit 30. The first reference voltage circuit 11 and the first error amplifier 12 constitute a first drive circuit 10. The second reference voltage circuit 21 and the second error amplifier 22 constitute a second drive circuit 20.

[0039] Resistors 13, 14, and 15 are connected in series between the output terminal and the ground terminal. The first error amplifier 12 has its output terminal of the first reference voltage circuit 11 connected to its inverting input terminal - and its first output terminal FB1 (the junction of resistors 13 and 14) connected to its non-inverting input terminal +. Its output terminal is connected to the gate of the NMOS transistor 16. The second error amplifier 22 has its output terminal of the second reference voltage circuit 21 connected to its inverting input terminal - and its second output terminal FB2 (the junction of resistors 14 and 15) connected to its non-inverting input terminal +. Its output terminal is connected to the gate of the NMOS transistor 16. The start-up control circuit 30 has its input terminal connected to the output terminal of the first reference voltage circuit 11, its first output terminal S1 connected to the control terminal of the first error amplifier 12, and its second output terminal S2 connected to the control terminal of the second error amplifier 22.

[0040] The first drive circuit 10 operates under normal conditions, thus requiring high precision and stability. Therefore, for example, a low-pass filter is incorporated into the first reference voltage circuit 11, resulting in a relatively long startup time. Here, the second drive circuit 20 operates when the shunt regulator starts up or when the output voltage Vout decreases; therefore, compared to the first drive circuit 10, precision and stability are less critical, resulting in a shorter startup time. Furthermore, the minimum operating voltage of the second reference voltage circuit 21 is set lower than that of the first reference voltage circuit 11. Consequently, the output voltage Vout of the second drive circuit 20 is set to be at least higher than the minimum operating voltage of the first reference voltage circuit 11.

[0041] Figure 2 This is a circuit diagram illustrating an example of the start-up control circuit 30 in this embodiment.

[0042] The startup control circuit 30 includes an NMOS transistor 31, a constant current circuit 32, and an inverter circuit 33. The startup control circuit 30 outputs a control signal by comparing the drain current of the NMOS transistor 31 with the current of the constant current circuit 32.

[0043] The source of NMOS transistor 31 is connected to the ground terminal, the gate is connected to the input terminal of the startup control circuit 30, and the drain is connected to the second output terminal S2. One terminal of the constant current circuit 32 is connected to the output terminal of the shunt regulator, and the other terminal is connected to the second output terminal S2. The input terminal of the inverter circuit 33 is connected to the second output terminal S2, and the output terminal is connected to the first output terminal S1.

[0044] The shunt regulator 100 configured as described herein operates as follows.

[0045] If a power supply voltage Vin is input, current flows through the external resistor 110, resulting in an output voltage Vout at the output terminal. Regarding the output voltage Vout, charge is generated by the capacitor of the load 111 connected to the output terminal or the internal capacitor of the shunt regulator 100, thus gradually increasing the voltage from below the minimum operating voltage of the first reference voltage circuit 11. At this time, the first reference voltage circuit 11 outputs a voltage lower than the predetermined reference voltage Vref1, which gradually increases as the output voltage Vout rises. The drain current of the NMOS transistor 31 in the start-up control circuit 30 gradually increases as the gate voltage of the input reference voltage Vref1 rises.

[0046] When the drain current of NMOS transistor 31 is less than the current of constant current circuit 32, the startup control circuit 30 outputs a high (Hi) level control signal to the second output terminal S2 and a low (Lo) level control signal to the first output terminal S1. That is, during startup, when the output voltage Vout is low and the reference voltage Vref1 is low, the second drive circuit 20 operates according to the Hi level control signal, and the first drive circuit 10 stops according to the Lo level control signal.

[0047] Here, the first drive circuit 10 and the second drive circuit 20 are controlled by, for example, switching the operating current of the error amplifier on / off, or switching a switch located at the output terminal on / off. Furthermore, the output of the stopped drive circuit is designed to have high impedance.

[0048] The gate voltage of the NMOS transistor 16 is controlled by the output voltage V2 of the second drive circuit 20, which has a relatively short startup time. Moreover, the output voltage Vout can be quickly raised above the minimum operating voltage of the first reference voltage circuit 11 by the second drive circuit 20.

[0049] If the first reference voltage circuit 11 outputs a specified reference voltage Vref1, the drain current of the NMOS transistor 31 is greater than the current of the constant current circuit 32, triggering the control circuit 30 to output a Lo-level control signal to the second output terminal S2 and a Hi-level control signal to the first output terminal S1. That is, the first drive circuit 10 operates according to the Hi-level control signal, and the second drive circuit 20 stops according to the Lo-level control signal. Therefore, the shunt regulator 100 operates with the output voltage V1 of the first drive circuit 10 via the NMOS transistor 16, transitioning to high-precision normal operation with a stable output voltage Vout. Here, the gate voltage of the NMOS transistor 31, whose signals are inverted at the first output terminal S1 and the second output terminal S2, is considered to be a voltage where the reference voltage Vref1 is lower than the specified voltage, and the first reference voltage circuit 11 operates sufficiently stably.

[0050] As explained above, the shunt regulator 100 of this embodiment includes a second drive circuit 20 with lower accuracy or stability than the first drive circuit 10, but with a shorter start-up time, and a start-up control circuit 30 that switches between the first drive circuit 10 and the second drive circuit 20. Therefore, it can quickly and stably switch to high-precision normal operation when the output voltage Vout is low during power-on.

[0051] Figure 3 This is a circuit diagram showing another example of the second drive circuit 20 in this embodiment.

[0052] The second driving circuit 20 includes an NMOS transistor 23, a constant current circuit 24, and an inverting amplifier circuit 25. The inverting amplifier circuit 25 is, for example, a source-grounded amplifier circuit.

[0053] The source of NMOS transistor 23 is connected to the ground terminal, the gate is connected to the second output terminal FB2 of the voltage divider circuit, and the drain is connected to the input terminal of the inverting amplifier circuit 25. One terminal of the constant current circuit 24 is connected to the output terminal of the shunt regulator, and the other terminal is connected to the input terminal of the inverting amplifier circuit 25. The control terminal of the inverting amplifier circuit 25 is connected to the second output terminal S2, and the output terminal is connected to the output terminal of the second drive circuit 20.

[0054] Figure 3 The second drive circuit 20 controls the voltage at the second output terminal FB2 of the voltage divider circuit input to the gate, so that the drain current of the NMOS transistor 23 is equal to the current of the constant current circuit 24. The current of the constant current circuit 24 or the size of the NMOS transistor 23 is adjusted so that the voltage at the second output terminal FB2 of the voltage divider circuit is equal to... Figure 1 The reference voltage Vref2 is equal.

[0055] Figure 3 The second driving circuit 20 and Figure 1 Similarly, the operation is controlled by switching the operating current on / off or by switching a switch located at the output terminal on / off. Furthermore, the output is designed to have high impedance when stopped.

[0056] Figure 3 The second driving circuit 20 and Figure 1 Compared to the first driving circuit 10, the second driving circuit 20 does not include the second error amplifier 22 and the second reference voltage circuit 21. While its accuracy and stability are inferior, it still meets the requirement of a short circuit startup time, thus serving the same purpose as the first driving circuit 10. Figure 1 The second drive circuit 20 has the same effect.

[0057] The embodiments of the present invention have been described above, but the present invention is not limited to the described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, Figure 2 The start-up control circuit 30 shown can output a control signal based on the reference voltage Vref1 of the first reference voltage circuit 11, and is therefore not limited to this circuit as long as it meets the functional requirements. Furthermore, for example, it is explained that the control signals of the first drive circuit 10 and the second drive circuit 20 operate at a Hi level and stop at a Lo level, but the logic can be freely designed. For example, the control signal output from the start-up control circuit 30 can be replaced or can be the same signal. If the control signal of the start-up control circuit 30 is the same signal, the inverter circuit 33 may not be necessary.

Claims

1. A current-sharing voltage regulator, comprising: include: The output terminal is connected to the power supply terminal via an external resistor; Multiple resistors are connected in series between the output terminal and the ground terminal to form a voltage divider circuit; An output transistor is connected between the output terminal and the ground terminal; The first driving circuit includes a first reference voltage circuit that outputs a first reference voltage and a first error amplifier, and controls the output transistor based on the voltage of the first output terminal of the voltage divider circuit; The second driving circuit controls the output transistor based on the voltage at the second output terminal of the voltage divider circuit; as well as The start-up control circuit switches the operation of the first drive circuit and the second drive circuit based on the first reference voltage, wherein... The startup time of the second driving circuit is shorter than that of the first driving circuit. The second driving circuit includes: A constant current circuit, wherein one terminal is connected to the output terminal; An N-type metal-oxide-semiconductor transistor has its drain connected to the other terminal of the constant current circuit, its gate connected to the second output terminal of the voltage divider circuit, and its source connected to the ground terminal; and The inverting amplifier circuit has its input terminal connected to the other terminal of the constant current circuit, and its control terminal connected to the second output terminal of the start-up control circuit, using the output voltage to control the output transistor.

2. The shunt regulator of claim 1, wherein, The second driving circuit includes a second reference voltage circuit that outputs a second reference voltage and a second error amplifier.

3. The shunt voltage regulator according to claim 1 or 2, characterized in that, The start-up control circuit includes: A constant current circuit, wherein one terminal is connected to the output terminal; and The N-type metal-oxide-semiconductor transistor has its drain connected to the other terminal of the constant current circuit, its gate connected to the first reference voltage circuit, and its source connected to the ground terminal.

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