Method and apparatus for optimizing data caching

Abstract

Embodiments of the present disclosure provide a computer-implemented method. The method comprises caching data in a persistent storage device in a cache. The method also comprises caching a physical address and a logical address of the data in the persistent storage device in the cache. The method further comprises, in response to receiving an access request for the data, using at least one of the physical address and the logical address to access the cached data in the cache. Embodiments of the present disclosure also provide an electronic apparatus and a computer program product.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on April 17, 2017, with application number 201710250599.8 and entitled "Method and apparatus for optimizing data caching". Technical Field

[0002] This disclosure generally relates to the technical field of computer systems or storage systems, and more particularly to a computer-implemented method and electronic device. Background Technology

[0003] In computer or storage systems, the management of cached data entries typically focuses on reading and writing data using its physical address and indexing data using offsets from that physical address. Therefore, when a system provides a read / write request for data using its logical address or logical address offset, the cache cannot determine whether data with that given logical address or offset is already cached.

[0004] In this scenario, read / write requests originating from the logical address of data must be mapped to the physical address via a mapping function, which typically requires several access steps to the persistent storage device. To address this, traditional solutions can further provide a write buffer, which allows read / write requests originating from the logical address to potentially be found directly in the "write buffer record" maintained within the write buffer (also known as a hit), without requiring an "immediate" mapping from logical to physical address, and avoiding the redundancy of creating a separate cache space for logical addresses. Subsequently, the write buffer will perform the mapping from logical to physical address in the background during idle periods; this can also be referred to as background renaming. Summary of the Invention

[0005] Embodiments of this disclosure provide a computer-implemented method, electronic device, and computer program product.

[0006] In a first aspect of this disclosure, a computer-implemented method is provided. The method includes: caching data in a persistent storage device in a cache; caching the physical address and logical address of the data in the persistent storage device in the cache; and, in response to receiving an access request for the data, accessing the cached data in the cache using at least one of the physical address and the logical address.

[0007] In some embodiments, caching physical addresses and logical addresses in a cache may include using a two-dimensional hash table to cache the physical addresses and logical addresses. In some embodiments, the two-dimensional hash table may include: a first-dimensional hash table for using physical addresses as keys and mapping them to logical addresses and data; and a second-dimensional hash table for using logical addresses as keys and mapping them to physical addresses. In some embodiments, a logical address may correspond to a physical address or may not correspond to any physical address; and a physical address may correspond to at least one logical address or may not correspond to any logical address.

[0008] In some embodiments, the method may further include: caching an indicator in a cache; and setting the indicator to a positive or negative state to indicate whether the data in the cache is directly writable. In some embodiments, setting the indicator may include: setting the indicator to a positive state if the physical address corresponds only to the logical address; and setting the indicator to a negative state if the physical address corresponds to multiple logical addresses, or if it is uncertain whether the physical address corresponds only to the logical address. In some embodiments, setting the indicator may further include: setting the indicator to a negative state in response to at least one of a snapshot operation or a deduplication operation on the data in the storage device.

[0009] In some embodiments, caching data in a storage device may include: determining whether the data is already cached in the cache in response to a request to read the data; copying the data from the storage device to the cache in response to determining that the data is not cached in the cache; and setting an indicator to a negative state.

[0010] In some embodiments, accessing cached data may include: determining the state of an indicator in response to an access request being a rewrite request; performing a rewrite operation on the data directly in the cache in response to determining the indicator to be positive; caching the data to be rewritten in another location in the cache in response to determining the indicator to be negative; and setting an indicator indicating whether the data to be rewritten is directly rewriteable to a positive state.

[0011] In a second aspect of this disclosure, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer instructions. The at least one memory and the computer instructions are configured, together with the processor, to cause the electronic device to: cache data in a persistent storage device in a cache; cache the physical address and logical address of the data in the persistent storage device in the cache; and, in response to receiving an access request for the data, access the cached data in the cache using at least one of the physical address and the logical address.

[0012] In a third aspect of this disclosure, a computer program product is provided. The computer program product is tangibly stored on a non-volatile computer-readable medium and includes machine-executable instructions. When executed, the machine-executable instructions cause a machine to perform the steps of the method of the first aspect. Attached Figure Description

[0013] The above and other objects, features, and advantages of embodiments of the present disclosure will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated in the drawings by way of example and not limitation, in which:

[0014] Figure 1 A schematic diagram of a storage system according to an embodiment of the present disclosure is shown.

[0015] Figure 2 A flowchart of a method according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A schematic diagram of a two-dimensional hash table according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A schematic diagram of the structure of a data entry in a cache according to an embodiment of the present disclosure is shown.

[0018] Figure 5 A state transition diagram of the operation process according to an embodiment of the present disclosure is shown.

[0019] Figure 6 A block diagram of an apparatus according to an embodiment of the present disclosure is shown.

[0020] Figure 7 A block diagram of an apparatus that can be used to implement embodiments of the present disclosure is shown.

[0021] Throughout all the accompanying drawings, the same or similar reference numerals are used to denote the same or similar elements. Detailed Implementation

[0022] The principles and spirit of this disclosure will now be described with reference to several exemplary embodiments illustrated in the accompanying drawings. It should be understood that these specific embodiments are described only to enable those skilled in the art to better understand and implement this disclosure, and are not intended to limit the scope of this disclosure in any way.

[0023] It should be noted that, for ease of discussion in the context of this disclosure, certain specific terms may be used to describe some embodiments of this disclosure. However, those skilled in the art will understand that such description is not intended to limit the embodiments of this disclosure to a particular system or technical environment. The embodiments of this disclosure are equivalently applicable to other computer systems or storage systems.

[0024] As mentioned above, in traditional schemes, the space for write buffer records is limited. Here, a write buffer record refers to the space reserved by the write buffer to temporarily store write requests that haven't yet been mapped from logical addresses to physical addresses. Therefore, based on advanced file system features such as snapshots, inline compression, data redundancy elimination, and write buffering, a key consideration in this traditional scheme is how frequently the write buffer should rename data entries in the write buffer record. In fact, only data entries in the write buffer record may be hit, but they cannot remain in the record for too long; once renamed, they must be removed from the write buffer record.

[0025] To further explain background renaming, consider two hypothetical scenarios. One scenario is that if the write buffer performs renaming for an extended period, it will have a good hit rate for recent read / write operations because most data entries are held in the write buffer record. However, in this case, the write buffer record will become full, and subsequent new write requests will struggle to benefit from the "write buffer." Therefore, the performance of new requests will become very poor, even worse than when write buffering is disabled. Another hypothetical scenario is that the write buffer performs renaming quickly when it is idle. In this way, the write buffer record will contain very few data entries that are likely to be hit, also resulting in a poor hit rate.

[0026] In practice, as shown in the table below, regardless of whether the renaming frequency is short or long, the write buffer function must be selected. In the table, recent R / W refers to logical read / write requests that satisfy good spatial locality, while non-recent R / W refers to requests whose addresses are not in the recent cache entry list, thus making them less likely to hit. Here, logical read / write refers to I / O requests from the client-side storage system via logical addresses, which are, for example, composed of <file system number, root index number, offset address>. Correspondingly, physical read / write refers to I / O requests for persistent data on the physical disk after the mapping from logical address to physical address is completed, which may, for example, consist of physical address offsets.

[0027] Short (difficult to choose) Difference good Long (difficult to choose) good Difference

[0028] Table 1

[0029] The reason why traditional solutions have the above problems is that data entries in the cache are organized using a traditional hash table indexed by physical addresses. Therefore, if a physical address is provided, it can be queried and quickly answered whether data with that physical address is contained. However, if a data entry in the cache is accessed via a logical address, it cannot determine whether data with that logical address is cached.

[0030] To at least partially address the aforementioned and other potential problems, embodiments of this disclosure provide a computer-implemented method, electronic device, and computer program product that improves upon the various situations described above and makes cached data easier to manage. As shown in the table below, by using embodiments of this disclosure, in the specific technical scenarios discussed above, renaming can always be recommended without negatively impacting recent R / W.

[0031] Short (Recommended) good good Long (not recommended) good Difference

[0032] Table 2

[0033] Specifically, embodiments of this disclosure extend the logical address information of the data for each data entry in the cache, and in some embodiments, also extend the shared indicator information. In some embodiments, by organizing the data and its related information into a special two-dimensional hash table, data content can be looked up by both physical and logical addresses without increasing time and space complexity. This improvement made using embodiments of this disclosure allows the cache to look up data not only by physical address but also by logical address, while the shared state of the indicator determines whether write operations can be optimized.

[0034] Furthermore, in embodiments where a shared indicator is configured, the shared indicator helps the cache distinguish whether a physical address uniquely maps to a logical address. This further prevents new rewrite requests from performing more redundant mappings from logical addresses to physical addresses. The following section combines... Figure 1 The general concept of embodiments of this disclosure is described below.

[0035] Figure 1 A schematic diagram of a storage system 100 according to an embodiment of the present disclosure is shown. Figure 1 As shown, storage system 100 may include persistent storage device 110 and cache 120. In operation of storage system 100, data 130 stored in persistent storage device 110 may be copied to cache 120 so that data 130 can be accessed more quickly in cache 120 in subsequent operations without repeatedly locating data 130 in persistent storage device 110 by resolving the index.

[0036] To enable access to data 130 in cache 120, according to embodiments of this disclosure, the physical address 131 and logical address 132 of data 130 in persistent storage device 110 are also cached together with data 130 in cache 120. Therefore, storage system 100 can access data 130 in cache 120 through at least one of the physical address 131 and logical address 132 of data 130.

[0037] It should be understood that Figure 1 This is a highly simplified schematic diagram, which only briefly illustrates the units or components closely related to this disclosure. Its purpose is to provide a general explanation of the technical environment of the embodiments of this disclosure, and it is not intended to limit the scope of this disclosure in any way. In other embodiments, the storage system 100 may also include or involve more units or components, the data organization in the cache 120 may have more complex data structures, the persistent storage device 110 and the cache 120 may have more complex interaction mechanisms, and so on. The following is in conjunction with... Figure 2-5 The method according to embodiments of the present disclosure will be described in detail below.

[0038] Figure 2 A flowchart of a method 200 according to an embodiment of the present disclosure is shown. In some embodiments, method 200 may be performed by... Figure 1 The execution can be performed by the storage system 100 depicted herein, for example, by one or more units or modules in the storage system 100.

[0039] At 210, storage system 100 caches data 130 from persistent storage device 110 in cache 120. Those skilled in the art will understand that data 130 may be cached in cache 120 for various reasons or various interaction mechanisms between persistent storage device 110 and cache 120, and embodiments of this disclosure are not limited in this respect.

[0040] For example, a user of storage system 100 might send a read request for data 130 to storage system 100 via a client. In this case, in response to the request to read data 130, storage system 100 can determine whether data 130 is already cached in cache 120. On one hand, if it is determined that data 130 is cached in cache 120, storage system 100 can directly read data 130 from cache 120. On the other hand, if it is determined that data 130 is not cached in cache 120, storage system 100 can copy data 130 from persistent storage device 110 to cache 120.

[0041] Continue to refer to Figure 2 At 220, storage system 100 caches the physical address 131 and logical address 132 of data 130 in persistent storage device 110 in cache 120. Those skilled in the art will understand that storage system 100 can use a variety of data organization methods to cache the physical address 131 and logical address 132 of data 130 together with data 130 in cache 120, and the embodiments of this disclosure are not limited in this respect. The following is in conjunction with… Figure 3To describe the organizational manner in which this functionality is implemented according to embodiments of the present disclosure.

[0042] Figure 3 A schematic diagram of a two-dimensional hash table 300 according to an embodiment of the present disclosure is shown. Those skilled in the art will understand that, in a relatively simple manner, cache 120 can use the physical address 131 of data 130 as an index to form a hash table, which can perform operations such as inserting / finding / removing data entries with a time complexity of approximately O(1). Building upon this, according to an embodiment of the present disclosure, cache 120 can construct a two-dimensional hash table 300 to further extend the logical address 132 of data 130 as an index to each data entry.

[0043] Specifically, such as Figure 3 As shown, cache 120 can implement a two-dimensional hash table 300 using a pair of hash tables 310 and 320 to cache data 130 and its physical address 131 and logical address 132. Specifically, the two-dimensional hash table 300 can include a first-dimensional hash table 310 and a second-dimensional hash table 320. The first-dimensional hash table 310 can be used to use the physical address 131 as a key and map it to the logical address 132 and the data 130. The second-dimensional hash table 320 can be used to use the logical address 132 as a key and map it to the physical address 131. Figure 3 The dashed arrows in the diagram depict this mapping relationship between physical address 131 and logical address 132.

[0044] For example, in Figure 3 The diagram schematically depicts two entries in the first-dimensional hash table 310. Each entry stores data 1, the physical address of data 1 (denoted by key K1), and the logical address of data 1 (denoted by @K2). Figure 3 As indicated by the dashed arrow, K1 maps to the entry in the second-dimensional hash table 320 with the logical address K2 of data 1 as the key value. Furthermore, this entry K2 in the second-dimensional hash table 320 also maps to the aforementioned entry in the first-dimensional hash table 310. Through this mapping relationship, data 130 can be accessed via either physical address 131 or logical address 132.

[0045] It will be understood that the two-dimensional hash table 300 does not add any additional time or space complexity. Compared to a regular one-dimensional hash table, the two-dimensional hash table 300 only doubles the space used to store the key, but this still does not increase the space complexity because the size of the logical address 132 used as the index is much smaller than the data 130 of the binary large object (e.g., 8K).

[0046] In some embodiments, such as those based on a single storage layout, the mapping relationship between physical address 131 and logical address 132 may follow these rules. In one aspect, logical address 132 may correspond to only one physical address 131 to ensure that logical address 132 can be uniquely mapped to physical address 131, thereby enabling access to data 130. Furthermore, in some cases, logical address 132 may not correspond to any physical address or may be prevented from being located to any physical address, for example, in some storage systems where inline compression is enabled. In this case, it is equivalent to logical address 132 not being usable to access data 130 in cache 120, but only data 130 in cache 120 being accessible via physical address 131.

[0047] In another aspect, physical address 131 may correspond to at least one logical address 132. In other words, physical address 131 may correspond to multiple logical addresses, including logical address 132. In this document, this situation may be referred to as data 130 or physical address 131 being shared. If multiple logical addresses map to the same physical address 131, storage system 100 may consider special complexity and only record one of them. However, it should be understood that storing all or part of the logical addresses is also feasible, albeit at a slightly higher storage cost and implementation complexity. Furthermore, in some cases, physical address 131 may not correspond to any logical address. For example, in situations where logical addresses are not enabled, such as those mentioned above where inline compression is enabled in some storage systems.

[0048] Based on the mapping rules above, it can be expected that there are two forms of data entries in an effective two-dimensional hash map. One type of data entry is in the form of (key1, key2, data value), which indicates both key1 in the first-dimensional hash table 310 and key2 in the second-dimensional hash table 320 for that data value. For example, Figure 3 The entry for data 1 in the first-dimensional hash table 310 shown. Another data entry, such as (key1, empty, data value), simply indicates key1 in the first-dimensional hash table 310 pointing to that data value. For example, Figure 3 The first dimension hash table 310 contains the entry for data 2. The logical address of data 2 is set to null, which means that the mapping from logical address to physical address is blocked, and it can only be accessed through physical address K3.

[0049] Figure 4 A schematic diagram of the structure of a data entry 400 in a cache 120 according to an embodiment of the present disclosure is shown. Figure 4As shown, a data entry 400 in cache 120 may include data 130, a physical address 131 of data 130, a logical address 132 of data 130, an overwrite bit 410, and a share bit 420. The overwrite bit 410 indicates whether data 130 in cache 120 has been overwritten and has not yet been updated in persistent storage device 110. Furthermore, the share bit 420 indicates whether the physical address 131 of data 130 is shared by multiple logical addresses, including logical address 132. In this document, the share bit 420 may also be referred to as share indicator 420 or simply indicator 420.

[0050] Will understand, although Figure 4 The overwrite bit 410 and the shared bit 420 are depicted as a single bit, but in other embodiments, they may be set to other lengths, and embodiments of this disclosure are not limited thereto. Furthermore, although Figure 4 The data 130 is schematically depicted as an 8K binary data block, but in other embodiments, the data 130 may be of other sizes, and the embodiments of this disclosure are not limited thereto.

[0051] As explained further below, storage system 100 can indicate whether data 130 is directly writable in cache 120 by caching indicator 420 and setting indicator 420 to a positive or negative state. Therefore, compared to conventional solutions, setting indicator 420 can avoid a large amount of unnecessary mapping from logical address to physical address and background renaming.

[0052] In some embodiments, indicator 420 is set to indicate that the data is not shared only when it is certain that logical address 132 uniquely maps to physical address 131. For example, this applies to data generated by a new write split operation, i.e., data intended for rewriting that is stored in another location in cache 120 because it cannot be rewritten directly in cache 120.

[0053] Furthermore, indicator 420 should be set to indicate sharing in any other situation, including when it is uncertain whether the physical address 131 of data 130 is shared. For data copied from persistent storage device 110 to cache 120, since it is unknown whether they are shared due to a lack of information provided by persistent storage device 110, storage system 100 can set their indicator 420 to indicate sharing.

[0054] In embodiments involving both snapshot and deduplication operations on data 130, in response to at least one of the snapshot or deduplication operations on data 130 in persistent storage device 110, storage system 100 may set indicator 420 of data 130 to indicate that it is shared.

[0055] Specifically, after taking a snapshot on, for example, a storage disk in storage system 100, the indicator 420 of the existing data entries belonging to that storage disk in cache 120 should be set to indicate that they are shared. It will be understood that this process is fast because the number of data entries in cache 120 is finite and all data to be accessed is done in memory. For example, in the case of 512MB of memory and 8KB of data in cache 120, we can calculate 512MB / 8KB = 64KB = 6 * 10^6. 4 Therefore, the time cost is only about 0.6 microseconds.

[0056] Furthermore, in deduplication operations, whether online or background, the deduplication process merges two physical addresses into a single physical address shared by multiple logical addresses. Therefore, it is only necessary to set the indicator 420 of the data involved in deduplication to indicate sharing after deduplication. For example, in a specific implementation, only the following few lines of code are needed for management. Here, the MCC cache refers to a single-dimensional cache originally dedicated to physical addresses. By extending the logical addresses and sharing indicators, and rewriting the indicators, it is made to support bidirectional positioning using both physical and logical addresses.

[0057]

[0058] Return to reference Figure 2 When data 130 and its physical address 131 and logical address 132 are both cached in cache 120, at 230, in response to receiving an access request for data 130, storage system 100 uses at least one of the physical address 131 and logical address 132 to access data 130 cached in cache 120.

[0059] In some embodiments, if the access request is a read request for data 130, the storage system 100 can directly read data 130 from the cache 120. When the indicator 420 is set, whether the indicator 420 is in a positive or negative state will not affect the storage system 100 from directly reading data 130 from the cache 120.

[0060] In some embodiments, when indicator 420 is set, in response to an access request being a rewrite request, storage system 100 can determine the state of indicator 420. Further, in response to determining that indicator 420 is in a positive state (i.e., not shared), storage system 100 can directly rewrite data 130 in cache 120. Otherwise, in response to determining that indicator 420 is in a negative state (i.e., shared), storage system 100 can cache the data to be rewritten in another location of cache 120, and set indicator 420, which indicates whether the data to be rewritten is directly writable, to a positive state (i.e., not shared).

[0061] In other words, according to some embodiments of this disclosure, data 130 in cache 120 is directly readable regardless of whether the entries are shared or not. Furthermore, data 130 in cache 120 is directly writable only when the entries are not shared. That is, if a write request is directed to "non-shared" cached data 130, a direct write operation to the physical cache 120 can be performed solely through logical address 132.

[0062] In practical application, the access operation according to the embodiments of this disclosure can be described using pseudocode as follows, where "la" represents the logical address 132 of data 130 and "pa" represents the physical address 131 of data 130. Furthermore, in embodiments where the overwrite bit 410 is set and the Least Recently Used (LRU) algorithm is utilized, if a direct overwrite is performed, the LRU needs to be updated and the overwrite bit 410 set, as clarified in the pseudocode.

[0063] Read function:

[0064]

[0065]

[0066] Rewrite the function:

[0067]

[0068] Figure 5 A state transition diagram 500 illustrating an operational process according to an embodiment of the present disclosure is shown. (As...) Figure 5 As shown, the data 130 cached in cache 120 may have four states: "unique overwrite" 510, "unique synchronization" 520, "shared overwrite" 530, and "shared synchronization" 540. In these states 510-540, "unique" means that the physical address 131 of data 130 is uniquely mapped to logical address 132, while "shared" means that the physical address 131 of data 130 may be mapped to other logical addresses besides logical address 132.

[0069] Furthermore, in these states 510-540, "overwrite" means that data 130 has been overwritten in cache 120 but the overwrite has not yet been synchronized to persistent storage device 110, and is inconsistent with the data 130 recorded in persistent storage device 110. In contrast, "synchronize" means that the data 130 in cache 120 is consistent with the data 130 recorded in persistent storage device 110.

[0070] As shown, in response to, for example, a write operation miss from a client, storage system 100 can cache data 130 used to modify certain data in a location in cache 120. Since it can be determined at this time that data 130 is not shared, the state of data 130 is "unique rewrite 510". If data 130 is flushed, it means that the modification of the data in cache 120 is synchronized to persistent storage device 110, so data 130 changes from state "unique rewrite 510" to state "unique synchronization 520". Conversely, in response to, for example, a write operation hit in cache 120, storage system 100 can directly modify data 130 in cache 120, so data 130 changes from state "unique synchronization 520" to "unique rewrite 510".

[0071] Similarly, if cache 120 is flushed, data 130 in the "Shared Overwrite 530" state can be changed to the "Shared Synchronization 540" state. In addition, in response to operations such as snapshotting, deduplication, or ILC on data 130, the states "Unique Overwrite 510" and "Unique Synchronization 520" can be changed to "Shared Overwrite 530" and "Shared Synchronization 540" respectively.

[0072] Additionally, in response to, for example, a read operation miss from a client, storage system 100 can copy data 130 from persistent storage device 110 to cache 120. Since it is uncertain whether data 130 is shared, storage system 100 can set the state of data 130 to "shared synchronization 540". Finally, data 130 in either "unique synchronization 520" or "shared synchronization 540" state can be deleted from cache 120, for example, based on the Least Recently Used (LRU) algorithm.

[0073] The effectiveness of the methods in the embodiments of this disclosure is demonstrated below through a simple analysis. First, as will be further explained, the embodiments of this disclosure have a higher hit rate in more situations compared to conventional solutions. A higher hit rate not only allows for faster return of results to the user (meaning better performance), but it also enables the consumption of fewer write buffer records, less stress, and many other benefits.

[0074] For example, in some embodiments, embodiments of the present disclosure have more direct read / write hits after renaming of the write buffer function. A direct read / write hit means that there is no need to perform a logical address to physical address mapping to process read / write operations and retain entries of the write buffer function, but rather to directly query or modify the data in the cache. For a traditional "write buffer" scheme, renaming at a certain interval frequency is required to reclaim the space of the write buffer. Once the renaming of the write buffer function is completed, all data entries are necessarily not hittable in terms of both reading and writing, because the logical address mapping is cleared to free up more space for write buffer records. However, embodiments of the present disclosure make it possible for both reading and writing to still be hittable because the cache 120 (e.g., MCC cache) contains the mapping of the logical address 131 both before and after the renaming of the write buffer function.

[0075] For another example, embodiments of the present disclosure can achieve more direct rewrite hits. For a traditional scheme, if a rewrite request is not within the write buffer records of the write buffer function, it will always retain the space of the write buffer records for write splitting, even if it is actually non-shared. Therefore, both the mapping from the logical address to the physical address for the new address and the deallocation for the old address are inevitable. In contrast, embodiments of the present disclosure can easily handle all non-shared cases.

[0076] Furthermore, as can be seen from the following discussion, non-shared data entries will be common in the data entry list of the cache 120 (e.g., MCC cache), which plays an important role in increasing direct rewrite hits.

[0077] Specifically, if a rewrite request for the logical address 132 is reported as shared, the first write on this logical address will not be hittable, so write splitting is required. However, write splitting causes the logical address 132 to map to another physical address that is determined not to be shared, so for all subsequent write requests on this logical address 132, it will continuously meet the conditions for write-through.

[0078] For a simple quantitative analysis, it can be assumed that there are a total of A write requests at a fixed logical address, and B snapshots are executed during them. In a realistic scenario, B will be significantly smaller than A, so it can be assumed that B << A. In this case, only (B + 1) write requests are not directly rewritable, and the remaining A - (B + 1) write requests can be directly rewritten.

[0079] In summary, as shown in the following table, embodiments of the present disclosure make logical read operations hittable in all cases, and make logical write operations hittable when the data entries are non-shared, and non-shared data entries will be a common situation.

[0080] Direct Read Hit Hit Direct rewrite Miss Hit

[0081] Table 3

[0082] Figure 6 A block diagram of an apparatus 600 according to an embodiment of the present disclosure is shown schematically. Those skilled in the art will understand that... Figure 6 Only the units or components closely related to this disclosure are shown in the apparatus 600. In some embodiments, the apparatus 600 may also include other functional units or components that enable it to function properly.

[0083] also, Figure 6 The various units or components shown may have necessary connections, but for the sake of simplicity, Figure 6 These connections are not described in the text. In some embodiments, device 600 may be configured to implement the above-described connections. Figure 2 Method 200 is described. In Figure 6 In the diagram, optional units or components are depicted using dashed boxes.

[0084] like Figure 6 As shown, the apparatus 600 includes a cache unit 610 and an access unit 620. The cache unit 610 is configured to cache data 130 from persistent storage device 110 in cache 120. The cache unit 610 is also configured to cache the physical address 131 and logical address 132 of data 130 in persistent storage device 110 in cache 120. The access unit 620 is configured to, in response to receiving an access request for data 130, access the cached data 130 in cache 120 using at least one of the physical address 131 and logical address 132.

[0085] In some embodiments, the cache unit 610 may also be configured to use a two-dimensional hash table 300 to cache physical address 131 and logical address 132. In some embodiments, the two-dimensional hash table 300 may include: a first-dimensional hash table 310 for using physical address 131 as key K1 and mapping it to logical address 132 and data 130; and a second-dimensional hash table 320 for using logical address 132 as key K2 and mapping it to physical address 131. In some embodiments, logical address 132 may correspond to a physical address or may not correspond to any physical address; and physical address 131 may correspond to at least one logical address or may not correspond to any logical address.

[0086] In some embodiments, cache unit 610 may also be configured to cache indicator 420 in cache 120; and to set indicator 420 to a positive or negative state to indicate whether data 130 is directly writable in cache 120. In some embodiments, cache unit 610 may also be configured to set indicator 420 to a positive state if physical address 131 corresponds only to logical address 132; and to set indicator 420 to a negative state if physical address 131 corresponds to multiple logical addresses, or if it is uncertain whether physical address 131 corresponds only to logical address 132.

[0087] In some embodiments, the apparatus 600 may further include a setting unit 630. The setting unit 630 is configured to set the indicator 420 to a negative state in response to at least one operation, namely a snapshot operation or a deduplication operation, on the data 130 in the persistent storage device 110.

[0088] In some embodiments, the cache unit 610 may also be configured to, in response to a request to read data 130, determine whether data 130 has been cached in cache 120; in response to determining that data 130 is not cached in cache 120, copy data 130 from persistent storage device 110 to cache 120; and set indicator 420 to a negative state.

[0089] In some embodiments, the cache unit 610 may also be configured to: determine the state of indicator 420 in response to an access request being a rewrite request; directly rewrite the data 130 in cache 120 in response to determining that indicator 420 is in a positive state; cache the data to be rewritten in another location of cache 120 in response to determining that indicator 420 is in a negative state; and set an indicator indicating whether the data to be rewritten is directly rewriteable to a positive state.

[0090] Figure 7 A block diagram schematically illustrates a device 700 that can be used to implement embodiments of the present disclosure. Figure 7 As shown, device 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes according to computer program instructions stored in read-only storage device (ROM) 702 or loaded from storage unit 708 into random access storage device (RAM) 703. The RAM 703 may also store various programs and data required for the operation of device 700. CPU 701, ROM 702, and RAM 703 are interconnected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0091] Multiple components in device 700 are connected to I / O interface 705, including: input unit 706, such as keyboard, mouse, etc.; output unit 707, such as various types of monitors, speakers, etc.; storage unit 708, such as disk, optical disk, etc.; and communication unit 709, such as network card, modem, wireless transceiver, etc. Communication unit 709 allows device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0092] The various processes and procedures described above, such as method 200, can be executed by processing unit 701. For example, in some embodiments, method 200 can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by CPU 701, one or more steps of method 200 described above can be performed.

[0093] Embodiments of this disclosure provide a computer-implemented method, electronic device, and computer program product. In some embodiments, a data structure is proposed that can optimize cache hit rates not only for read operations but also for write operations. Embodiments of this disclosure offer the following advantages compared to existing cache data structures (e.g., the MCC model).

[0094] First, embodiments of this disclosure improve read hit rates, for example, regardless of whether renaming of the write buffer clears the cache. Furthermore, embodiments of this disclosure improve write hit rates, supporting direct rewriting in more cases without the need for slow mapping from logical to physical addresses. Additionally, embodiments of this disclosure can handle less pressure during background flushing of the write buffer, as more write operations can be intelligently analyzed and no longer reserved in the write buffer records.

[0095] Furthermore, embodiments of this disclosure can easily work with inline compression, snapshot functionality, and deduplication functionality. Moreover, all operations of embodiments of this disclosure remain O(1) in both time and space complexity, and the order in which data is written can also meet consistency requirements. Furthermore, embodiments of this disclosure do not require changes to the layout of persistent storage devices, making them easy to implement on existing products. Finally, embodiments of this disclosure are also suitable for B-tree-based architectures, such as Cyclone.

[0096] As used herein, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The terms "an embodiment" or "the embodiment" should be understood as "at least one embodiment". As used herein, the term "determine" covers a wide variety of actions. For example, "determine" can include calculation, computation, processing, derivation, investigation, search (e.g., searching in a table, database, or other data structure), ascertainment, etc. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. In addition, "determine" can include parsing, selecting, choosing, building, etc.

[0097] It should be noted that the embodiments of this disclosure can be implemented using hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, code provided on programmable memory or a data carrier such as an optical or electronic signal carrier.

[0098] Furthermore, although the operation of the methods of this disclosure is described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowcharts may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. It should also be noted that the features and functions of two or more devices according to this disclosure may be embodied in one device. Conversely, the features and functions of one device described above may be further divided and embodied by multiple devices.

[0099] While this disclosure has been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the specific embodiments disclosed. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A computer-implemented method, comprising: Data entries are cached in a cache. The data entries include data from a persistent storage device, the physical address of the data, the logical address of the data, and access status information. The data is accessible to a requester who issues an access request using the physical address or the logical address. as well as Managing the use and status of the data entries based on the access status information includes: After the flushing operation, the data entry is changed from the overwrite state to the synchronization state. The data entry in the overwrite state is directly writable. The synchronization state indicates that the data in the cache is consistent with the data recorded in the persistent storage device. The data entry in the synchronization state is later deleted to make room for the new data entry in the cache. as well as After performing snapshot, deduplication, and / or compression operations, the data entry is transitioned from a unique state to a shared state. The unique state means that the physical address of the data is uniquely mapped to the logical address. The data entry in the shared state is associated with multiple different logical addresses, and the data entry in the unique state is writable. After being written to while in a unique synchronization state, the data entry transitions from the unique synchronization state to a unique overwrite state. The unique synchronization state indicates that the data entry is in the unique state and in the synchronization state, and the unique overwrite state indicates that the data entry is in the unique state and in the overwrite state.

2. The computer-implemented method according to claim 1, wherein the access state information identifies two access state dimensions as unique / shared and overwrite / synchronized, thereby generating four access states, the four access states being unique overwrite, unique synchronization, shared overwrite, and shared synchronization.

3. The computer-implemented method of claim 2, wherein the unique overwrite state is entered in response to both of the following: (1) causing a write miss that caches the data entry in the cache, and (2) a write hit that occurs when the data entry is in the unique synchronization state in the cache.

4. The computer-implemented method of claim 2, wherein the data entry is cached in the cache in response to either: (1) a write miss, the write miss setting the access state to the unique overwrite state; and (2) a read miss, the read miss setting the access state to the shared synchronization state.

5. The computer-implemented method according to claim 1, wherein caching the physical address and the logical address in the cache comprises: A two-dimensional hash table is used to cache the physical address and the logical address. The two-dimensional hash table includes a first-dimensional hash table and a second-dimensional hash table. The first-dimensional hash table is used to map the physical address to the logical address and the data by using the physical address as a key. The second-dimensional hash table is used to map the logical address to the physical address by using the logical address as a key.

6. The computer-implemented method according to claim 1, wherein the access status information provides corresponding conditions, in which: The logical address corresponds to a physical address or is prevented from corresponding to any physical address; and The physical address corresponds to at least one logical address or is prevented from corresponding to any logical address.

7. The computer-implemented method of claim 6, wherein the access status information includes a unique / shared indicator, and: If the physical address corresponds only to the logical address, then the unique / shared indicator is set to a unique state; and If the physical address corresponds to multiple logical addresses, or it is uncertain whether the physical address corresponds to only the logical address, then the unique / shared indicator is set to a shared state.

8. The computer-implemented method according to claim 7, wherein: In response to at least one of a snapshot operation and a deduplication operation on the data in the storage device, the unique / shared indicator is set to the shared state.

9. The computer-implemented method of claim 7, wherein caching the data in the storage device in the cache comprises: In response to a request to read the data, determine whether the data has been cached in the cache; as well as In response to determining that the data is missing in the cache: Copy the data from the storage device to the cache; as well as Set the unique / shared indicator to the shared state.

10. The computer-implemented method of claim 7, wherein accessing the data cached in the cache comprises: In response to the access request being a rewrite request, determine whether the unique / shared indicator is in the unique state or in the shared state; In response to determining that the unique / shared indicator is in the unique state, the data is directly rewritten in the cache; as well as In response to determining that the unique / shared indicator is in the shared state, The data to be rewritten is cached in another location within the cache, and Set a separate indicator to an affirmative state, the separate indicator indicating whether the data to be rewritten is directly writable.

11. An electronic device comprising: At least one processor; as well as At least one memory including computer instructions, the at least one memory and the computer instructions being configured, together with the processor, to cause the electronic device to: Data entries are cached in a cache. The data entries include data from a persistent storage device, the physical address of the data, the logical address of the data, and access status information. The data is accessible to a requester who issues an access request using the physical address or the logical address. as well as Managing the use and status of the data entries based on the access status information includes: After the flushing operation, the data entry is changed from the overwrite state to the synchronization state. The data entry in the overwrite state is directly writable. The synchronization state indicates that the data in the cache is consistent with the data recorded in the persistent storage device. The data entry in the synchronization state is later deleted to make room for the new data entry in the cache. as well as After performing snapshot, deduplication, and / or compression operations, the data entry is transitioned from a unique state to a shared state. The unique state means that the physical address of the data is uniquely mapped to the logical address. The data entry in the shared state is associated with multiple different logical addresses, and the data entry in the unique state is writable. After being written to while in a unique synchronization state, the data entry transitions from the unique synchronization state to a unique overwrite state. The unique synchronization state indicates that the data entry is in the unique state and in the synchronization state, and the unique overwrite state indicates that the data entry is in the unique state and in the overwrite state.

12. The electronic device of claim 11, wherein the access state information identifies two access state dimensions as unique / shared and overwrite / synchronized, thereby generating four access states, the four access states being unique overwrite, unique synchronization, shared overwrite, and shared synchronization.

13. The electronic device of claim 12, wherein the unique overwrite state is entered in response to both of the following: (1) causing a write miss that caches the data entry in the cache, and (2) a write hit that occurs when the data entry is in the unique synchronization state in the cache.

14. The electronic device of claim 12, wherein the data entry is cached in response to either: (1) a write miss, the write miss setting the access state to the unique overwrite state; and (2) a read miss, the read miss setting the access state to the shared synchronization state.

15. The electronic device of claim 11, wherein caching the physical address and the logical address in the cache comprises: A two-dimensional hash table is used to cache the physical address and the logical address. The two-dimensional hash table includes a first-dimensional hash table and a second-dimensional hash table. The first-dimensional hash table is used to map the physical address to the logical address and the data by using the physical address as a key. The second-dimensional hash table is used to map the logical address to the physical address by using the logical address as a key.

16. The electronic device of claim 11, wherein the access status information provides corresponding conditions, in which: The logical address corresponds to a physical address or is prevented from corresponding to any physical address; and The physical address corresponds to at least one logical address or is prevented from corresponding to any logical address.

17. The electronic device of claim 16, wherein the access status information includes a unique / shared indicator, and: If the physical address corresponds only to the logical address, then the unique / shared indicator is set to a unique state; and If the physical address corresponds to multiple logical addresses, or it is uncertain whether the physical address corresponds to only the logical address, then the unique / shared indicator is set to a shared state.

18. The electronic device according to claim 17, wherein: In response to at least one of a snapshot operation and a deduplication operation on the data in the storage device, the unique / shared indicator is set to the shared state.

19. The electronic device of claim 17, wherein caching the data in the storage device in the cache comprises: In response to a request to read the data, determine whether the data has been cached in the cache; as well as In response to determining that the data is missing in the cache: Copy the data from the storage device to the cache; as well as Set the unique / shared indicator to the shared state.

20. The electronic device of claim 17, wherein accessing the data cached in the cache comprises: In response to the access request being a rewrite request, determine whether the unique / shared indicator is in the unique state or in the shared state; In response to determining that the unique / shared indicator is in the unique state, the data is directly rewritten in the cache; as well as In response to determining that the unique / shared indicator is in the shared state, The data to be rewritten is cached in another location within the cache, and Set a separate indicator to an affirmative state, the separate indicator indicating whether the data to be rewritten is directly writable.

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