Method for partitioning a simulation model between a processor and an FPGA

Abstract

The invention relates to a method for dividing a simulation model of a graph into a first submodel and a second submodel, the function of the simulation model being modeled in the form of modules connected by signals, each module of the simulation model being provided with a sampling time, the first submodel being executed on a first computing unit and the second submodel being executed on a second computing unit, the method comprising: identifying at least one first module as belonging to the first submodel and at least one second module as belonging to the second submodel; finding cyclic groups consisting of modules, the modules of the cyclic groups all having the same sampling time; the cyclic groups being considered indivisible; identifying acyclic groups consisting of modules; assigning each module of these groups to the first submodel or to the second submodel; generating code for the first computing unit from the first submodel; and generating code for the second computing unit from the second submodel.

Description

Technical Field

[0001] The present invention relates to a method for partitioning a simulation model, the simulation model being executed jointly on a processor and a programmable logic component. Background Technology

[0002] Such simulation models are applied, for example, to hardware-in-the-loop (HIL) simulations, in which controllers, particularly those for motor vehicles, undergo testing of their specific functions. For this purpose, the controller to be tested is connected to electronic circuitry, also known as I / O circuitry, which has input and / or output channels to apply signals to the controller and / or acquire signals generated by the controller.

[0003] The signals output by the I / O circuits are determined by running a software model of the test environment in a simulation environment, for example, simulating driving in the case of a motor vehicle. Simulated events are transmitted to output channels, such as pins or registers of the circuit's output channels, via electrical signals representing the events. These electrical signals are then transmitted to the controller, and / or from the controller to input channels, such as pins or registers of the circuit's input channels, so that the signals can be acquired and processed in the simulation environment. Therefore, the controller can operate in the simulated environment as if it were actually operating in a real environment.

[0004] The simulation environment, or simulator for short, is formed, for example, by a real-time computer system having at least one processor executing a software model. For example, the model can be provided by real-time software or multiple cooperating software tools, preferably having a graphical user interface and particularly preferably programmed using software objects. The software may include MATLAB, Simulink, or the applicant's RTI (Real-Time Interface), for example, forming a link to Simulink. The software objects are, in the aforementioned cases, programmed graphically, particularly hierarchically, as modules. However, the simulation environment is not limited to using the software specifically mentioned. The software model is either runnable in the simulation environment directly after programming or after generating and compiling the code.

[0005] In addition to the processor circuitry including the at least one processor, the simulation environment typically includes at least one I / O circuitry connected to the processor circuitry, the I / O circuitry having the aforementioned input / output channels. These input / output channels are used to output electrical signals to pins of the output channels and / or acquire electrical signals present on pins of the input channels, for example, through analog-to-digital conversion, to direct the acquired signals for further processing, either on the aforementioned electronic circuitry or on other electronic devices connected to the circuitry. It may also be specified that at least one I / O circuitry including input and / or output channels is connected to a circuitry including programmable logic components, particularly a field-programmable gate array (FPGA), to obtain signals from or provide signals to the circuitry. The FPGA circuitry itself may be connected to the processor circuitry, so that the simulation model can be executed partly on the FPGA circuitry and partly on the processor circuitry.

[0006] The key difference between real-time computer systems and commercially available computer systems lies in the fact that, for example, the time between a changed sensor signal input and the resulting response, such as a changed control signal output, does not exceed a predetermined delay. Here, depending on the system to be simulated, the maximum delay may, for example, be 1 millisecond or less. In particular, the simulation of electric vehicle (E-Drive) drives or power electronics places high demands on the speed of control loops, especially with the maximum permissible delay in the microsecond range. Therefore, real-time simulation often cannot be satisfied by a pure processor model and processor-controlled I / O channels, but rather by executing time-critical model portions on freely programmable FPGA circuits. Preferably, the FPGA circuit is configured such that different I / O circuits can be modularly connected to the FPGA circuit.

[0007] Therefore, particularly for complex real-time simulations in the fields of e-Mobility, ADAS, or power electronics, real-time computer systems with different types of computing units are used, such as one or more processors and one or more programmable logic components. Until now, users had to manually determine and model the partitioning of which part of the model they wanted to execute in which domain (processor, FPGA). EP1971944B1 provides a method for automatically transferring sub-models to another domain, but only through exploratory trial-and-error schemes, iterating until determined performance criteria, such as predetermined timing characteristics, are met.

[0008] To date, in the following typical application scenarios, it is necessary to manually identify and move model boundaries between the processor section and the FPGA section, in which each model section must be assigned to a different domain:

[0009] • Divide the model during the conceptualization process.

[0010] • Further extend the FPGA model beyond the resources of the FPGA already in use.

[0011] • Migrate the project to another FPGA platform with more / fewer resources.

[0012] • Distribute large FPGA applications across multiple FPGAs. Summary of the Invention

[0013] In this context, the objective of the present invention is to provide a method and an apparatus that further extend the prior art and preferably enable the automatic or computer-aided division of a simulation model into a processor portion and an FPGA portion.

[0014] The task is solved by a method for dividing a graphical simulation model into a first sub-model and a second sub-model, and by a computer system.

[0015] Therefore, a method is provided for dividing a graphical simulation model into a first sub-model and a second sub-model, wherein the functionality of the simulation model is modeled in modules, each module being at least partially connected by signals, each module is executed periodically, and each module of the simulation model is assigned a sampling time. The first sub-model is determined to be executed on a first computing unit, particularly a processor, while the second sub-model is determined to be executed on a second computing unit, particularly a programmable logic component. The method includes the following steps:

[0016] a. Identify at least one first module as belonging to a first sub-model and at least one second module as belonging to a second sub-model, wherein the attribution is determined by means of sampling time and / or resource configuration;

[0017] b. Identify cyclic groups consisting of multiple modules, where all modules in the cyclic group share the same sampling time; such cyclic groups are considered indivisible.

[0018] c. Identify acyclic groups composed of modules.

[0019] d. Assign each module in these groups to the first or second sub-model, wherein all modules of an indivisible cyclic group are assigned to the same sub-model.

[0020] e. The first sub-model generates code, specifically program code, for the first computational unit, and

[0021] f. The code generated by the second sub-model for the second computational unit, particularly the configuration bitstream.

[0022] A loop group comprises two or more modules connected by at least one signal. A first module in the loop group outputs a signal to a second module in the group and at least indirectly receives the output signal of the second module. If the loop group comprises three or more modules, the output signal of the second module can first be the input signal of the third module, and the output signal of the third module can be connected to the first module; the first module therefore does not directly receive the output signal of the second module, but performs an intermediate operation within the third module. Correspondingly, other modules can be connected intermediately in a larger loop group.

[0023] In a non-cyclic group consisting of multiple modules, there is no feedback between the modules, where the output signal of a module located downstream in the signal path is connected to the first module in the signal path.

[0024] The sampling time can be explicitly assigned to a module or derived through inheritance or propagation. The simulation model can, for example, be designed hierarchically, where multiple lower-level modules implement the functionality of a higher-level module, and the sampling time of the higher-level module is accepted by all lower-level modules. In modules modeled for accessing hardware interfaces (such as I / O ports), the sampling time can be determined by the characteristics of the hardware. In multiple modules connected via a single signal line, it can also be specified that the sampling time of one of the modules is propagated or accepted by all modules connected by the signal line.

[0025] This invention provides a deterministic, rule-based method that proposes boundaries between processor and FPGA sections and / or provides suggestions for boundaries of movement at appropriate locations for all signal paths by transforming and analyzing the entire model. To this end, the model is subdivided into partitions that are either suitable for implementation on an FPGA or suitable for implementation on either a processor or an FPGA.

[0026] Preferably, the suggested boundaries can be moved by the modeler in the model view (which displays partitions, for example, by coloring) towards the FPGA or processor respectively. This invention has the advantage that it is suitable for cycle-accurate, i.e., clock-precise modeling, which enables the implementation of high-precision control loops, for example, in the E-Drive field. The method according to this invention can, in principle, be applied to different types of computing units, such as CPUs, GPUs, and FPGAs. Furthermore, it can, in principle, be used for a large number of sub-models.

[0027] For a hierarchical simulation model, wherein the simulation model includes at least one module in a first structural level and at least one module in a second structural level, it is preferable to group the modules of the simulation model into a common structural level before further steps. This simplifies and accelerates the partitioning of the model.

[0028] If the simulation model includes input ports, output ports, and / or buses, the step of grouping the modules of the simulation model into a common structural hierarchy preferably includes at least removing some of the input ports, output ports, and / or buses and adding corresponding signals. Here, input ports and output ports primarily refer to internal model communication modules that connect different regions or structural levels of the model. A pair of Goto and From modules indicating a data connection between two modules or parts of the model can also be treated as a pair of input and output ports and removed or replaced by a single signal line. I / O ports are fixedly assigned to a hardware resource, such as an I / O pin of an FPGA or a conversion component of an I / O board, and these I / O ports are retained in the model.

[0029] Preferably, a module is identified as belonging to the second sub-model if one or more of the following conditions are met:

[0030] I. The module is equipped with a sampling time below a predetermined sampling threshold;

[0031] II. The module is equipped with a delay below a predetermined delay threshold;

[0032] III. The module is equipped with resources for programmable logic components, such as, in particular, I / O pins for programmable logic components.

[0033] Modules with particularly high requirements for timing characteristics (such as frequent sampling and / or short delays) are configured in a manner appropriate to the purpose of the second sub-model, which executes on a programmable logic component or FPGA. In modules with direct hardware access, the model is configured with hardware units that directly follow the response.

[0034] Preferably, a module is identified as belonging to the first sub-model if one or more of the following conditions are met:

[0035] I. The module describes function calls, particularly operating system functions and / or access to network interfaces;

[0036] II. The module is equipped with processor resources, such as, in particular, processor registers.

[0037] The modules that model the software interface or require (ansprechen) processor hardware resources are configured to the first sub-model in a manner that suits the purpose.

[0038] Advantageously, the step of finding cyclic groups includes recursive subdivision, wherein for each found cyclic group, the following checks are performed: whether all modules have the same sampling time, in which case the cyclic group is considered indivisible and retained; and otherwise, the cyclic group is subdivided into new cyclic or non-cyclic subgroups among modules with different sampling times, until no further subdivisible cyclic groups exist. Counters can also preferably be processed as cyclic groups including adders and registers. Indivisible cyclic groups are configured as a whole only for the first or second submodel in a manner appropriate to the purpose.

[0039] According to a preferred embodiment of the invention, the step of configuring the modules in these groups to a first sub-model or a second sub-model is performed using predetermined rules. The rule series (Regelsatz) can also be predetermined by multiple nested conditions. By executing rules that verify one or more conditions, the configuration of modules can be performed quickly and reproducibly.

[0040] Particularly preferably, according to the aforementioned rules, all modules that do not need to be executed on the programmable logic components are allocated to the first sub-model. Thus, only particularly time-critical modules are executed on the FPGA, taking into account the typically scarce resources of the programmable logic components.

[0041] Specifically, it can be specified that if a module is connected to a module identified as belonging to a second sub-model via a signal, and the signal has a bit width higher than a width threshold and / or a change frequency higher than a change threshold and / or a delay shorter than a signal delay threshold, then the module must also be executed on a programmable logic component. Bandwidth can also be considered as the product of signal width and change frequency, wherein if the bandwidth exceeds a predetermined bandwidth threshold, the module is executed on an FPGA. It can be specified that multiple signals are considered as a single signal with a cumulative or accumulated bit width. If multiple data points must be transferred between two modules, then the two modules are positioned on the same computing unit, particularly a programmable logic component, in a manner appropriate to the purpose. If signal transmission between two modules is only permitted to be performed with low latency, it is advantageous to execute or implement these modules on a programmable logic component.

[0042] Preferably, after the step of assigning the various modules in these groups to the first sub-model or the second sub-model, a graphical representation of the divided model is displayed via a user interface. Changes in the division are received via the user interface in a manner appropriate to the intended purpose.

[0043] Particularly preferably, additional rules are used to identify modules that can be configured not only for the first sub-model but also for the second sub-model, wherein these modules are prominently displayed in the user interface. The configuration of these modules is performed via user input. In particular, additional rules can be used to identify modules that can be arbitrarily configured, based on the lack of resource configuration. For example, the user can pre-select a portion of the model via a slider, which is executed on a programmable logic component; alternatively or additionally, it can be specified that desired limits can be added to the graphical representation of the model. In particular, desired limits can be received via mouse movement. The user-defined limits are stored in a manner appropriate to the purpose in the model properties or in modules set for this purpose within the model, particularly in that the changing configurations are stored as module parameters. Alternatively, it can be specified that the user-defined limits are stored in a separate file or database. This allows for the parallel existence of multiple different partitioning methods, wherein, in particular, the effective partitioning method can be pre-adjusted.

[0044] Preferably, after the step of assigning each module in these groups to the first sub-model or the second sub-model, an additional step of adding communication modules is performed, wherein for two modules connected by a signal, it is checked whether these modules are assigned to different sub-models, and in this case, a pair of communication modules are added that enable data exchange between the processor and the programmable logic components.

[0045] In a preferred embodiment of the present invention, the method includes the following additional steps:

[0046] g. Transmitting program code and configuration bitstreams to a real-time computer system, said real-time computer system including a processor and programmable logic components, and

[0047] h. Perform a simulation, wherein the processor executes program code and the functionality of the programmable logic components is determined by configuring a bitstream.

[0048] Applications generated from simulation models according to the present invention include program code for processors and configuration for programmable logic components, and these applications can be executed directly. Simulations can be implemented using the corresponding program code or a real-time computer configured to run bitstreams, or any functionality specified in the simulation model can be generally provided.

[0049] The present invention also relates to a computer system comprising an operating computer with an user interface and a real-time computer having a processor, programmable logic components, and I / O circuitry. Instructions for implementing the method according to the present invention are stored in the non-volatile memory of the computer system.

[0050] The present invention also relates to a non-volatile data carrier having a computer-readable storage medium on which commands are embedded, the commands being triggered when executed by a processor configured to perform the method according to the invention. Typically, the operating computer of a real-time computer system has a modeling environment and is therefore particularly well-suited for implementing the model partitioning according to the invention. Furthermore, program code or FPGA configurations can be automatically created and executed on the real-time computer system, resulting in high operational comfort. Attached Figure Description

[0051] The invention is described in more detail below with reference to the accompanying drawings. Here, the same parts are labeled with the same reference numerals. The embodiments shown are strongly simplified, i.e., the distances and the lateral and vertical dimensions are not to scale and do not have deducible geometric relationships unless otherwise stated.

[0052] In the picture:

[0053] Figure 1 A schematic diagram of an exemplary hardware-in-the-loop test environment is shown.

[0054] Figure 2 The diagram shows a simulator that executes a first sub-model on a processor and a second sub-model on an FPGA.

[0055] Figure 3 A hierarchical simulation model is shown.

[0056] Figure 4 This shows a simulation model aggregated on one level.

[0057] Figure 5 A schematic flowchart of the method according to the present invention is shown.

[0058] Figure 6 A schematic diagram of a model with two fixed points and an indivisible cyclic group is shown.

[0059] Figure 7 A schematic diagram of subdivisible cyclic groups is shown, comprising indivisible cyclic groups with high sampling rates and acyclic groups with slow sampling rates.

[0060] Figure 8 A schematic diagram of a model with multiple cyclic and acyclic groups is shown.

[0061] Figure 9 This diagram illustrates a method for fine-tuning or determining boundaries within a non-cyclic portion of a model, where multiple possible boundaries are exemplarily represented.

[0062] Figure 10aA schematic diagram of a simple model with a boundary is shown.

[0063] Figure 10b A schematic diagram of the simplified model is shown, in which additional boundaries are added to the signal path by moving the boundary, and

[0064] Figure 10c A schematic diagram of the simplified model is shown, in which the moved boundaries are retained, but the number of other boundaries is reduced. Detailed Implementation

[0065] exist Figure 1 The diagram schematically illustrates an exemplary hardware-in-the-loop test environment, which includes an operating computer (PC), an emulator (ES), and a controller (DUT) to be tested. The operating computer (PC) can be configured as a commercially available personal computer, having a screen, input devices, and one or more network interfaces.

[0066] The real-time emulator ES includes a computing node CN, which is connected to an operating computer PC via a network interface NET. The computing node CN has at least one processor CPU, particularly a multi-core processor, working memory RAM, and non-volatile memory NVM, on which the operating system and / or bootloader are preferably stored. A logic board with a programmable logic component FPGA, two I / O circuits ADC, DAC, and an error simulation circuit FIU is connected to the computing node via a high-speed bus SBC or a corresponding controller. The programmable logic component FPGA is preferably freely programmable and can be configured according to the present invention. Alternatively, the emulator ES may have multiple logic boards or multiple programmable logic components FPGA on a single logic board. The logic board preferably has one or more slots for I / O modules. An I / O module IOM is shown, which is connected to the controller DUT to be tested and, for example, can exchange digital input and output signals with the controller. The I / O circuit ADC has one or more analog-to-digital converters that receive analog signals from the controller DUT to be tested. The emulator ES can output analog signals from the controller DUT to the controller DUT via an I / O circuit DAC with one or more digital-to-analog converters. The error emulation circuit FIU can impose defined electrical errors, such as a short circuit between two channels, on the connected devices.

[0067] Programmable logic components (FPGAs) are particularly used in applications such as E-Drive and power electronics, where particularly fast regulation loops are required. In a purpose-appropriate manner, logic boards with such FPGAs have multiple slots for I / O modules; for example, dSPACE offers the DS6601 FPGA board with five slots, which can be equipped with different I / O modules. Existing test environments can be expanded, for example, by incorporating new I / O modules for high-resolution analog-to-digital conversion.

[0068] Figure 2 A schematic diagram of a simulator is shown, which executes a first sub-model on a processor and a second sub-model on an FPGA. The first sub-model RTA is stored on a compute node CN, and is executed as a real-time application by the compute node's processor. The programmable logic component FPGA#1 is configured such that the second sub-model CNF is implemented in a portion of the region, while the control module CTL is implemented in other portions of the region. The control module CTL is connected to the I / O module IOM via a component IOF, the I / O module having analog-to-digital converters ADC#1, ADC#n and digital-to-analog converters DAC#1, DAC#n. The compute node and the programmable logic component are connected via a high-speed bus SBC. The programmable logic component FPGA#1 is connected to the second programmable logic component FPGA#n via an internal FPGA bus.

[0069] The method according to the present invention can also optionally be used to divide the system into multiple sub-models, such as a third sub-model, which is implemented on a second programmable logic component FPGA#n. In addition to the processor and programmable logic component, other components of different types of computing systems, such as GPUs or KI cores, can be supported; here, the steps are simulated, wherein each module is configured onto each sub-model using a corresponding rule framework adapted to different architectures.

[0070] In principle, the method according to the present invention can be extended to the boundaries between arbitrary domains, such as...

[0071] Programmable logic components

[0072] Programmable logic components—graphics card or GPU,

[0073] Processors and processors / microcontrollers

[0074] Processor and graphics card or GPU

[0075] First graphics card and second graphics card

[0076] Or each model may have more than two domains.

[0077] exist Figure 3 The diagram schematically illustrates a hierarchical simulation model. In the first structural level E1, multiple modules B1, B2, B3, B4, and B5 are arranged. These modules implement the model's functions and are connected via signals. Module B4 is a subsystem, and its functions are implemented through lower-level modules in the second structural level. The second structural level E2 includes input port P11, modules B21, B22, and B23, and output port P22.

[0078] Figure 4 The simulation model is shown after the modules are grouped into a common structural hierarchy. Modules B1, B2, B3, and B5 still exist. Subsystem B4 is replaced by lower-level modules B21, B22, and B23. Input port P11 and output port P22, used for internal model communication and not connected to hardware resources, are removed and replaced with direct signal connections to modules B2 and B3.

[0079] exist Figure 5 The diagram shows a schematic flowchart of a method according to a preferred embodiment of the invention.

[0080] The starting point of the method according to the invention, in a manner consistent with the purpose, is an entire model with multiple sampling times, that is, each module is explicitly or implicitly (e.g., by default setting or by inheritance) configured with an entire model of a sampling time. The sampling time should be understood in particular as the time after which a module re-executes or re-reads its input signals and / or a new output value of the module becomes available. Furthermore, in a manner consistent with the purpose, the modules are indivisible, and any resulting partitions therefore cannot traverse the modules, but are always only between the modules. The method preferably operates with the following steps:

[0081] In step S1 (removing the hierarchical structure), as in Figure 3 and 4As shown, the modules of a hierarchical model are grouped together on a common structural hierarchy. Analyzing a hierarchical, structured Simulink model with a data bus is complex and time-consuming; therefore, in a purposeful manner, structural components such as subsystems and buses are removed during the preparation step, or replaced with individual signals. This enables high-performance graph-based analysis, where all input / output ports of a node and its source are directly known, and connected to its source and destination via edges. This step is optional and can be implemented using methods known per se. For example, Xilinx's Vivado development environment provides such a method in netlist optimization using "flatten_hierarchy".

[0082] In step S2 (identifying fixed modules), at least one first module is identified as belonging to a first sub-model and at least one second module is identified as belonging to a second sub-model. Additional conditions imposed by the architecture necessitate that some modules be implemented on an FPGA, while others must be implemented on a processor. The module assignments (processor or FPGA) are therefore determined from the outset, hence these fixed points are identified in the first step. For example, modules must be implemented on an FPGA with low latency, while modules that interact complexly with the operating system (e.g., network protocols) must execute on a processor. Furthermore, modules with sampling times below a given threshold are assigned to the FPGA. Specialized I / O modules are typically explicitly assigned to a domain.

[0083] In step S3 (finding cyclic groups), groups of modules whose output values ​​are cyclically correlated with each other are sought. If the model has such cyclic groups or cycles, these cycles are configured in one of two types. Such cycles, where all nodes have the same sampling time, are considered indivisible and are no longer partitioned. That is, these cycles are implemented entirely on the FPGA or entirely on the processor and can only move across the hardware / software boundary as a whole. I / O modules are not considered part of the cycles here for the purpose of this discussion. Figure 6 A schematic diagram of a model with two fixed points and an indivisible cyclic group is shown, where all modules have the same sampling time.

[0084] In step S4 (Group Separability?), it is checked whether the cyclic group can be further subdivided. If the cyclic nodes have different sampling times, these nodes are considered separable and can be further subdivided. This occurs in step S5 (Segmenting the Cyclic Group). Subdivision here takes place at the transition between the parts with different sampling times. This results in new non-cyclic and cyclic subregions, which are then iteratively further processed according to this method. This iteration is currently represented by reimplementing step S3. Figure 7A schematic diagram of a subdivisible cyclic group is shown, which has a portion with a fast sampling time or high sampling rate and a portion with a slow sampling time or low sampling rate, and can therefore be divided into two parts: an indivisible cyclic group and a non-cyclic group.

[0085] In step S6 (identifying groups), acyclic groups consisting of the modules are identified. In this step, all acyclic (feedforward) portions of the model are identified. These portions are, in principle, located before (fan-in) or after (fan-out) the fixed point and the cycle. Within these model portions, the possible partition boundaries between the FPGA and the processor, i.e., between the modules in the acyclic groups, can be freely chosen as the boundaries between the first and second sub-models.

[0086] In step S7 (assigning modules), each module in the acyclic group or all modules in the cyclic group are assigned to the first sub-model or the second sub-model. After identifying the correlation between fixed points, cycles, and acyclic elements, the entire model is divided according to a predetermined rule framework.

[0087] The rules for determining where a given model should be implemented can be made taking into account the overall performance of the model, available resources, communication nodes, and sampling time. It can be specified that the parameters are selected via user input; however, it can also be specified that values ​​are predetermined heuristically or determined by exploring the design space for meaningful parameters.

[0088] In a manner consistent with the objective, first determine for each indivisible cycle where the indivisible cycle should be implemented. Figure 8 This diagram illustrates the configuration of a loop group of an exemplary simulation model to a first sub-model or a second sub-model; the upper loop group (white-filled circle) is configured to the first sub-model and executed on the processor, and the lower loop group (black-filled circle) is configured to the second sub-model and executed on the FPGA.

[0089] After the configuration cycle, it is preferable to fine-tune the hardware-software boundaries between modules in the non-cyclic group, wherein these boundaries can now be moved towards the FPGA or processor within the non-cyclic portion. The same criteria as for the configuration cycle can be applied to the configuration of modules in the non-cyclic group. The main difference is that the boundaries can be moved module by module here, which provides a finer granularity. Alternatively, the cycle of slower domains can also be moved to faster domains (e.g., from the processor to the FPGA) if their configuration is determined solely by sampling time. Figure 9 A schematic diagram is shown for fine-tuning or determining the boundaries between non-cyclic parts of the model, wherein five possible boundaries are illustrated by way of example.

[0090] The method according to the present invention can be used to partition an entire model that has not yet been subdivided into processor and FPGA parts, or to re-perform the subdivision of an entire model that has already been subdivided into processor and FPGA parts. Here, the following steps are preferably performed:

[0091] 1. Partitioning

[0092] 2. Automatically suggests the boundary between the processor and FPGA.

[0093] 3. Interactive movement boundaries

[0094] Preferably, the method according to the invention is used in conjunction with conversion tools, such as MathWorks' HDL Coder or Xilinx System Generator. Thus, model modules or all subsystems can be used in a simple manner not only in the processor model but also in the FPGA model, by using these tools to generate source code for the processor or HDL code for the FPGA for each module.

[0095] Automatic suggestions are provided to define the boundaries between the processor and the FPGA: for partitioning the entire model, which does not yet have fixed module configurations and consists only of processor or FPGA portions; or for repartitioning the entire model, which already has defined partitions for the processor and FPGA. Both cases can be handled identically by ignoring the possible affiliation of modules to a domain.

[0096] According to a preferred embodiment of the present invention, the model is divided into domains using the following two rules:

[0097] Rule 1: Model portions that do not need to run on the FPGA should be moved to the processor. Rule 2 should be considered here.

[0098] Rule 2: Because data transfer often offsets time gains when computation is moved to a faster computing device if necessary, data transfer should be minimized. Therefore, in the model graph, the data width will be bounded by the least possible segmentation while considering Rule 1. This minimizes the duration of data transfer.

[0099] Additionally or alternatively, criteria such as the task turnaround time of a processor model, the maximum available logic resources, the number of flip-flops, LUTs, DSPs, RAM, AI cores, or predetermined clock speeds for programmable logic components in an FPGA model can be considered. These values ​​can be determined based on the integration of the entire model, even if the model as a whole is much larger for the FPGA. In this integration, a “virtual” netlist is generated in a purposeful manner, from which resources for each model module / subsystem are determined and approximate achievable clock speeds are identified and used as the basis for determining model limits. It is preferable to abandon subsequent steps, placement, and routing to the specific FPGA in the normal construction of a programmable logic device.

[0100] After the automatic subdivision model, it is preferable to be able to interactively move the boundary between the processor and the FPGA.

[0101] Starting with subdividing the model into partitions for the FPGA and partitions for the processor, the different partitions are preferably graphically highlighted in the model or in a graphical user interface. Additionally, it is preferable to draw all actual or proposed model boundaries in the model. Alternatively or supplementarily, these partitions and boundaries can also be displayed in the model's graphics, which have been created using the method according to the invention. The actual drawn boundaries can also extend within a partition (instead of between two partition boundaries), as discussed below. Importantly, an FPGA model is typically represented not by individual, continuous graphics, but by multiple island-shaped graphics. This is because an FPGA often implements multiple self-contained functions that do not communicate with each other, but rather provide a fixed function connected only via I / O pins or communicate only with their respective processor portions. Therefore, there are typically boundaries not only between the processor and the FPGA, but also boundaries for each island-shaped graphic, i.e., boundaries for completely independent functions.

[0102] Users now preferably have the possibility of interactively moving a boundary, for example by using a slider or moving it directly in the model or its graph, further toward the processor or FPGA after clicking on a boundary in the model or its graph. Additionally, the granularity of the model representation can be reduced by integrating parts that can only be moved as a whole (such as indivisible cyclic groups) into individual subsystems / nodes.

[0103] Here, one or more of the following descriptions are preferably displayed interactively and updated:

[0104] - The bit-level interface width between the processor and the FPGA, and the communication duration for transmitting that bit at a predetermined maximum data transfer rate (e.g., 2.5 Gbit / s). This allows the user to know the minimum achievable task cycle time based on the value of the communication. In one embodiment, the variation in the corresponding value for existing / suggested limits can also be shown.

[0105] - Required logic resources in an FPGA. The resources and approximate achievable clock speeds of each model module / subsystem can be determined based on the integration of the entire model, preferably interrupted after the creation of the unimplemented netlist. Therefore, it can be determined in advance whether the model for a given partition can be executed on a real-time computer system.

[0106] The following discussion addresses the significance of partitioning for boundary movement. A partition view with drawn boundaries provides the user with a wealth of information at a glance, allowing them to immediately see whether a boundary is on a partition boundary or within a partition. If a boundary is within a partition suitable for a processor or FPGA, it can be easily moved in the direction of the two partition boundaries, i.e., towards the processor or FPGA, thereby changing the interface width for data communication if necessary.

[0107] Figure 10a This diagram illustrates a simple model with a boundary. On the left is a fixed module to be executed on the FPGA (FPGA fixed point), and on the right is a fixed module to be executed on the processor (processor fixed point). Multiple modules exist, each connected by a single signal line. Modules to be executed on the FPGA are shown in black, modules to be executed on the processor in white, and flexibly configurable modules in gray. Within the shown partition, the user can expand their FPGA portion (second sub-model) by moving the boundary to the right. Thus, a pure FPGA model exists, excluding the shown processor fixed point.

[0108] From Figure 10a Starting from the boundary shown, the user can alternatively expand the processor portion of the model, and the boundary may even move across multiple partitions if necessary. In the case of the boundary moving to the left, the module to be executed on the FPGA will initially be positioned after the boundary for the processor model (the black circle on the right). If the user does not change the module to be executed on the FPGA and the boundary, additional boundaries are automatically added to the signal path in a preferred embodiment of the invention. Figure 10bA schematic diagram of the simplified model is shown, in which additional boundaries are automatically added to the signal path. These boundaries require communication between the processor and the FPGA and thus increase communication overhead, where such communication may be congested. Congested communication here specifically refers to a situation where further computation can only proceed after data transfer between the processor and the FPGA has ended.

[0109] If the user adapts the modeling of the FPGA partition or the corresponding module (the black circle on the right) to the FPGA partition, and can configure the module to the processor partition, then communication costs will be reduced. Figure 10c A schematic diagram of the simplified model is shown, where the moved boundaries are preserved, but the number of other boundaries is reduced by varying the intermediate modules. The model partitioning is graphically represented in a partitioned view to facilitate user observation that the modified modeling results in a reduction in the number of boundaries or transitions between the processor and the FPGA. Due to reduced communication overhead, this modified modeling allows for faster implementation of the entire model.

[0110] Alternative embodiments of the invention can also achieve the determination of a large number of boundaries between the processor and FPGA sections, particularly two boundaries between each section. By defining appropriate rules, additional sections can be defined at the boundaries between the FPGA and the processor, allowing for flexible determination of the execution of these additional sections. If, for example, not one but two boundaries are defined for each input and output boundary between each section of the model, either throughout the model or in the model graph of the entire model, then a region is obtained between each section of the model. Modules within these regions can then, for example, be executed on the processor, while the remainder of the model is implemented on the FPGA.

[0111] This invention enables the automatic or computer-aided decomposition of models for implementation on different types of simulators, which can significantly reduce the time required for design simulations.

Claims

1. A method for dividing a graphical simulation model into a first sub-model and a second sub-model, wherein, The simulation model is modeled in a modular fashion, with each module at least partially connected by signals. Each module is executed periodically, and a sampling time is assigned to each module of the simulation model. The first sub-model is determined to execute on a first computing unit, and the second sub-model is determined to execute on a second computing unit. The method includes the following sequential steps: a. Identify at least one first module as belonging to a first sub-model and at least one second module as belonging to a second sub-model, wherein the attribution is determined by means of sampling time and / or resource configuration; b. Identify cyclic groups consisting of modules, where each cyclic group comprises two or more modules connected by at least one signal. The first module of the cyclic group outputs a signal to the second module within the cyclic group and at least indirectly receives the output signal from the second module. Cyclic groups in which all modules share the same sampling time are considered indivisible. c. Identify acyclic groups composed of modules. d. Assign each module in these groups to the first or second sub-model, wherein all modules of an indivisible cyclic group are assigned to the same sub-model. e. The first sub-model generates code for the first computational unit, and f. Code generated from the second sub-model for use in the second computational unit.

2. The method according to claim 1, characterized in that, The first computing unit is a processor, and / or the second computing unit is a programmable logic component.

3. The method according to claim 1, characterized in that, The code used for the first computing unit is program code, and / or the code used for the second computing unit is a configuration bitstream.

4. The method according to claim 1, characterized in that, The simulation model includes at least one module in a first structural level and at least one module in a second structural level, and the modules of the simulation model are grouped together in a common structural level before further steps.

5. The method according to claim 4, characterized in that, The simulation model includes input ports, output ports, and / or buses, and the step of bringing together the modules of the simulation model in a common structural hierarchy includes removing at least some of the input ports, output ports, and / or buses and adding corresponding signals.

6. The method according to any one of claims 1 to 5, characterized in that, A module is identified as belonging to the second sub-model if one or more of the following conditions are met: I. The module is equipped with a sampling time below a predetermined sampling threshold; II. The module is equipped with a delay below a predetermined delay threshold; III. The module is equipped with FPGA resources.

7. The method according to claim 6, characterized in that, The resources of the FPGA are its I / O pins.

8. The method according to any one of claims 1 to 5, characterized in that, A module is identified as belonging to the first sub-model if one or more of the following conditions are met: I. The module describes the function call; II. The module is equipped with processor resources.

9. The method according to claim 8, characterized in that, The module describes the functions of the operating system and / or access to network interfaces.

10. The method according to claim 8, characterized in that, The module is equipped with a processor register.

11. The method according to any one of claims 1 to 5, characterized in that, The steps for finding cyclic groups include recursive subdivision, wherein for a found cyclic group, the following checks are performed: whether all modules have the same sampling time, in which case the cyclic group is considered indivisible and is retained, and otherwise the cyclic group is subdivided into new cyclic or non-cyclic subgroups among modules with different sampling times, until no more cyclic groups can be subdivided.

12. The method according to any one of claims 1 to 5, characterized in that, The process of assigning each module in these groups to the first or second sub-model is carried out using predetermined rules.

13. The method according to claim 12, characterized in that, According to the rules, all modules that do not need to be executed on programmable logic components are assigned to the first sub-model.

14. The method according to claim 13, characterized in that, If a module is connected to a module identified as belonging to a second sub-model via a signal, and the signal has a bit width higher than a width threshold and / or a change frequency higher than a change threshold and / or a delay shorter than a signal delay threshold, then the module must also be executed on a programmable logic component.

15. The method according to any one of claims 1 to 5, characterized in that, After configuring the modules in these groups to the first or second sub-model, a graphical representation of the divided model is displayed through the user interface, and changes to the division are received through the user interface.

16. The method according to claim 15, characterized in that, Additional rules are used to identify modules that can be configured not only for a first sub-model but also for a second sub-model, wherein the modules are prominently displayed on the user interface and the configuration of these modules is performed by user input.

17. The method according to claim 15, characterized in that, The following modules are identified by leveraging the lack of resource configuration: these modules can be configured not only for the first sub-model but also for the second sub-model, wherein the modules are prominently displayed on the user interface and the configuration of these modules is performed by user input.

18. The method according to any one of claims 1 to 5, characterized in that, After the step of assigning the individual modules in these groups to the first sub-model or the second sub-model, an additional step of adding communication modules is performed, wherein for two modules connected by a signal, it is checked whether these modules are assigned to different sub-models, and in this case, a pair of communication modules are added to enable data exchange between the processor and the programmable logic components.

19. The method according to any one of claims 1 to 5, characterized in that... Additional steps: g. Transmitting program code and configuration bitstreams to a real-time computer system, said real-time computer system including a processor and programmable logic components, and h. Perform a simulation, wherein the processor executes program code and the functionality of the programmable logic components is determined by configuring a bitstream.

20. A computer system, said computer system comprising an operating computer with an operating interface and a real-time computer having a processor, programmable logic components and I / O circuitry, characterized in that, The computer system stores instructions for implementing the method according to any one of claims 1 to 19 in its non-volatile memory.

21. A non-volatile data carrier having a computer-readable storage medium on which a command is embedded, the command being triggered when executed by a processor, the processor being configured to perform the method according to any one of claims 1 to 19.

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