A method and device for designing parameterized memory

Abstract

The present invention discloses a design method and device for parameterized memory, and relates to the field of reconfigurable compilation technology of FPGA. The method comprises: selecting a data width that satisfies the bit width ratio of a port according to the data bit width types supported by an optional memory element, and performing approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero; determining an address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result; determining a memory unit instance that needs to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance; and instantiating a memory element instance according to the capacity of the memory unit instance and the optional memory element. The present invention does not need to modify the code, but only needs to reload the bit width and depth parameters of the port to meet various specification requirements, and can achieve the purpose of building a memory with necessary and minimum memory resources, thereby optimizing resource utilization.

Description

Technical Field

[0001] The present invention relates to the field of reconfigurable compilation technology of FPGA, and in particular to a design method and device for a parameterized memory. Background Art

[0002] HDL (Hardware Description Language) is a language for describing the behavior, structure, and data flow of electronic system hardware. It is widely used in ASIC (Application Specific Integrated Circuit) and FPGA (Field Programmable Gate Array) design. In hardware description languages, the calculation of constants is completed during the compilation process and does not consume FPGA logic resources.

[0003] There are two types of FPGA memory, distributed RAM and block RAM, and the corresponding basic units are: Configurable Logic Block (CLB) and Block RAM. Block RAM is fixed and suitable for large-scale RAM applications, with good timing convergence. Configurable logic units are not fixed and suitable for small-scale applications, with relatively poor timing convergence.

[0004] The block type has basic unit specifications, which are different for different manufacturers and different device families, and the supported (data bit width, address depth) combinations are also different. For example, the minimum unit capacity supported by Xilinx's VIRTEX5 is 18Kb, and the supported combinations are: (1, 16k), (2, 8k), (3-4, 4k), (5-9, 2k), (10-18, 1k), and the minimum unit capacity supported by Altera's arria2 is 9k, and the supported combinations are: (1, 8k), (2, 4k), (3-4, 2k), (5-9, 1k). The capacity is the product of the data bit width and the address depth. The capacity of the basic unit may be wasted under different (data bit width, address depth) combinations. The unit of data bit width and capacity is bit. The data bit width ratio supported by Xilinx and Altera is a power of 2, and the supported ones are 1, 2, 4, 8, 16, and 32.

[0005] The actual memory specifications vary greatly. A large one may require dozens or even hundreds of block connections, while a small one may only require a few CLBs. There are the following ways to generate the actual memory to be used:

[0006] The first is to use IP provided by the manufacturer. In the compiler interface (designed in a high-level language) provided by the FPGA manufacturer, enter the specification value, and the compiler will generate IP of the specified specification.

[0007] The second method is to use the template code provided by the compiler to generate a parameterized one-dimensional array. After the compiler recognizes this code, it generates a RAM with the required data bit width and address depth.

[0008] The third method is to call the macros provided by the compiler, namely the basic elements of RAM, and perform address splicing.

[0009] However, the first approach has the following limitations:

[0010] For example, if you need a dual-port RAM: one side is 40 bits wide * 4K deep, and the other side is 20 bits wide * 8K deep.

[0011] When using Xilinx products, 4 36K+1 18K Block RAMs can be used for implementation, and IP must be generated in the compiler. When using Altera products (taking quartus15 and Arria10 as examples), 20 M10K Block RAMs can be used for implementation, and the bit width and depth parameter values ​​of the IP source file generated by the compiler can be overloaded, and the compiler does not need to generate them, but 40Kb is wasted.

[0012] If the requirements change, the above RAM specifications need to be changed to: 48bit width * 4k depth on one side, and 24bit width * 8K depth on the other side.

[0013] When using Xilinx products, 5 36K + 1 18K Block RAMs will be used, but a new IP must be regenerated in the compiler. When using Altera products, Quartus 13 will report: unsupported bit width. In other words, when using Xilinx products, there will be problems with IP not being universal and different specifications will require a new IP to be generated. When using Altera products, there will be problems with no resource optimization and limited supported bit widths.

[0014] The second approach has the limitations of parameterized one-dimensional arrays:

[0015] The compiler cannot control whether to use distributed / register or block RAM during implementation. If it thinks that it cannot match the (bit width, depth) and read / write strategy template of the RAM element it supports, it will synthesize it into a register, which consumes a lot of resources;

[0016] In addition, asymmetric bit width is not supported, and there is no supported (bit width, depth) template, so synthesis cannot be passed at this time;

[0017] At the same time, there is also the problem of no resource optimization.

[0018] The third method has the limitation of calling the RAM components provided by the manufacturer and splicing the addresses: because the maximum bit width of the components is limited, for example, the maximum bit width of 18k is 18, and the maximum bit width of 36k is 36, and there is also the problem of no resource optimization. Summary of the invention

[0019] In view of the defects existing in the prior art, the first aspect of the present invention provides a design method for a parameterized memory implemented using a hardware description language, which does not require code modification, but only requires overloading the bit width and depth parameters of the two ports to meet various specifications and achieve the purpose of using the necessary and minimum memory resources to build a memory of the required bit width, thereby optimizing resource utilization.

[0020] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0021] A method for designing a parameterized memory, the method comprising the following steps:

[0022] According to the data bit width types supported by the optional memory element, a data bit width that satisfies the bit width ratio of the port is selected, and approximation iteration is performed on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero;

[0023] Determine the address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result;

[0024] Determine the memory unit instance that needs to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance;

[0025] The memory element instance is instantiated according to the capacity of the memory cell instance and the optional memory element.

[0026] In some embodiments, selecting a data bit width that satisfies the bit width ratio of a port according to the data bit width types supported by the optional memory element, and performing approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero includes:

[0027] Count the upper limit of the data bit width supported by the optional memory element at various address depths, the power of 2 value in the supported data bit width, and the bit width ratio supported by each value;

[0028] Compare the data bit widths of the two ports, select the data bit width of the larger port as the initial value of the remaining data bit width, and the required capacity as the initial value of the remaining capacity;

[0029] If the remaining data bit width does not exceed the maximum value in the statistics, and the remaining capacity does not exceed the maximum memory element capacity value, the remaining data bit width is used as the data bit width of this iteration; otherwise, the maximum data bit width value that does not exceed the remaining data bit width and whose supported bit width ratio value contains the bit width ratio value of the port is selected as the data bit width of this iteration;

[0030] The remaining data bit width and the remaining capacity are iterated using the obtained data bit width until the remaining data bit width and the remaining capacity return to zero.

[0031] In some embodiments, determining the address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result includes:

[0032] Determine the number of address concatenation instances of the port according to the number of iterations;

[0033] Determine the data bit width value and data bit starting sequence number of the larger port of the address splicing instance according to the data bit width selected in each iteration;

[0034] The data bit width value and the data bit starting sequence number of another port of the address splicing instance are determined according to the data bit width selected in each iteration and the bit width ratio of the port.

[0035] In some embodiments, when the bit width ratio of the port is not 1, it also includes:

[0036] The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

[0037] In some embodiments, when a check bit of a memory element is used, the method further includes:

[0038] The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

[0039] In some embodiments, when the remaining data bit width is less than the upper limit of the data bit width corresponding to the address depth, the steps of writing data for filling and reading data for deleting are also included.

[0040] In some embodiments, determining the memory unit instance to be instantiated when performing address splicing according to the address splicing instance includes:

[0041] When the capacity of the designed memory is not greater than the maximum capacity supported by the optional memory element, a memory unit instance is instantiated;

[0042] When the capacity of the designed memory is larger than the maximum capacity supported by the optional memory element, determine the address depth bit width of the largest memory element at the required data bit width, subtract the address depth bit width from the required address bit width, and use the power of 2 obtained as the number of instantiations of the memory unit instance.

[0043] The second aspect of the present invention provides a method for designing a parameterized memory, which does not require code modification, but only requires overloading the bit width and depth parameters of the two ports to meet various specification requirements, and can achieve the purpose of using the necessary and minimum memory resources to build a memory of the required bit width, thereby optimizing resource utilization.

[0044] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0045] A design device for parameterized memory, comprising:

[0046] A bit width splicing module, which selects a data bit width that satisfies the bit width ratio of the port according to the data bit width types supported by the optional memory element, performs approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero, and determines the address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result;

[0047] An address splicing module, which determines a memory unit instance to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance;

[0048] A memory cell module instantiates a memory element instance according to the capacity of the memory cell instance and an optional memory element.

[0049] In some embodiments, the bit width splicing module selects a data bit width that satisfies the bit width ratio of the port according to the data bit width types supported by the optional memory element, and performs approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero, including:

[0050] Count the upper limit of the data bit width supported by the optional memory element at various address depths, the power of 2 value in the supported data bit width, and the bit width ratio supported by each value;

[0051] Compare the data bit widths of the two ports, select the data bit width of the larger port as the initial value of the remaining data bit width, and the required capacity as the initial value of the remaining capacity;

[0052] If the remaining data bit width does not exceed the maximum value in the statistics, and the remaining capacity does not exceed the maximum memory element capacity value, the remaining data bit width is used as the data bit width of this iteration; otherwise, the maximum data bit width value that does not exceed the remaining data bit width and whose supported bit width ratio value contains the bit width ratio value of the port is selected as the data bit width of this iteration;

[0053] The remaining data bit width and the remaining capacity are iterated using the obtained data bit width until the remaining data bit width and the remaining capacity return to zero.

[0054] In some embodiments, the bit width splicing module determines, according to the iteration result, an address splicing instance that needs to be instantiated when performing data bit width and address splicing, including:

[0055] Determine the number of address concatenation instances of the port according to the number of iterations;

[0056] Determine the data bit width value and data bit starting sequence number of the larger port of the address splicing instance according to the data bit width selected in each iteration;

[0057] The data bit width value and the data bit starting sequence number of another port of the address splicing instance are determined according to the data bit width selected in each iteration and the bit width ratio of the port.

[0058] Compared with the prior art, the advantages of the present invention are:

[0059] The design method of parameterized memory in the present invention can calculate and analyze the bit width, automatically instantiate and splice memory elements of appropriate specifications and quantities, and support arbitrary bit width; there is no need to modify the code, just reload the bit width and depth parameters of the two ports to meet various specification requirements; the bit width splicing and address splicing are realized through the code, and the component template provided by the compiler is strictly matched, so the realized component type is highly controllable, and a memory built with a large number of registers will not be synthesized. Using bit width and capacity, it is approximated and iterated in order from large to small, so as to achieve the purpose of using necessary and minimum memory resources to build a memory of the required bit width, thereby optimizing resource utilization; using hardware description language, it is seamlessly connected with the functional design of FPGA, without relying on compilers and compilation tools, and no need to use other high-level languages ​​for design. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a flow chart of a method for designing a parameterized memory in an embodiment of the present invention;

[0061] Figure 2 is a flow chart of step S1 in an embodiment of the present invention;

[0062] Figure 3 4 is a flow chart of step S2 in an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The technical solution of the present invention (including the preferred technical solution) is further described in detail below by means of the accompanying drawings and by listing some optional embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] See also Figure 1 As shown, the present invention discloses a design method for parameterized memory, the method comprising the following steps:

[0065] S1. According to the data bit width types supported by the optional memory element, select the data bit width that meets the bit width ratio of the port, and iterate the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero.

[0066] It is worth noting that the embodiment of the present invention mainly uses two variables, the remaining data width and the remaining capacity, during calculation, and uses the larger data width value and the data width ratio at both ends for calculation. That is, if the remaining data width does not exceed the maximum value in the statistical value, and the remaining capacity does not exceed the maximum memory element capacity value in each iteration, the remaining data width is used as the data width value of this iteration, otherwise the remaining data width and the port width ratio value are compared with the template value of the memory element, and the maximum data width value in the template that is not greater than the remaining data width and can meet the data width ratio is taken.

[0067] Each iteration obtains the data width of an address splicing module, and subtracts the data width from the remaining data width, and subtracts the capacity corresponding to this iteration from the remaining capacity, until the remaining data width and the remaining capacity are 0, where the result of each iteration is defined from low to high.

[0068] Specifically, step S1 includes:

[0069] S11. Count the upper limit values ​​of the data bit widths supported by the optional memory elements at various address depths, the values ​​of powers of 2 in the supported data bit widths, and the bit width ratios supported by each value.

[0070] S12. Compare the data widths of the two ports, select the data width of the larger port as the initial value of the remaining data width, and the required capacity as the initial value of the remaining capacity.

[0071] It can be understood that if the data bit widths of the two ports are equal, then the data bit width of one port can be arbitrarily selected as the initial value of the remaining data bit width.

[0072] S13. If the remaining data bit width does not exceed the maximum value in the statistics, and the remaining capacity does not exceed the maximum memory element capacity value, the remaining data bit width is used as the data bit width of this iteration; otherwise, the maximum data bit width value that does not exceed the remaining data bit width and the supported bit width ratio value contains the bit width ratio value of the port is selected as the data bit width of this iteration;

[0073] S14. Use the obtained data bit width to iterate the remaining data bit width and the remaining capacity until the remaining data bit width and the remaining capacity return to zero.

[0074] The following is a specific example to further illustrate:

[0075] In this example, Verilog language and Xilinx devices are used as examples. Xilinx devices support two types of memory components, with capacities of 18kb and 36kb respectively.

[0076] Among them, the {bit width, depth} supported by 18kb are:

[0077] (1,16k),(2,8k),(3-4,4k),(5-9,2k),(10-18,1k);

[0078] 36kb supports {bit width, depth}:

[0079] (1,32k),(2,16k),(3-4,8k),(5-9,4k),(10-18,2k),(19-36,1k).

[0080] Supported data width ratios are 1, 2, 4, 8, 16, and 32.

[0081] The data bit widths of 9bit, 18bit, and 36bit are extended by 1bit, 2bit, and 4bit check bits as data bits. In the ISE compiler, all check bits are gathered together in the high bit, and the data bits are all in the low bit. Bit mapping of the check bits is required. In Vivado, the check bits are adjacent to the corresponding data bits, so it is not necessary. When the data bit width is 19-36, the write enable is 4 bits, 2 bits when 0-18, and 1 bit for the rest.

[0082] At this time, the capacity Q1 = 18k, Q2 = 36k. The upper limit values ​​of the bit width supported by all components of a specific depth and the values ​​of the powers of 2 in the supported bit width are arranged from large to small to obtain a list WU = {36, 32, 18, 16, 9, 8, 4, 2, 1}. The bit width wid_WU of each element in the list is set to 6 bits. Elements wu1 = 36, wu9 = 1.

[0083] Each element is divisible by a power of 2, that is, the data bit width ratio supported by each element is: wu1rt={1,2,4}, wu2rt={1,2,4,8,16,32}, wu3rt=wu8rt={1,2}, wu4rt={1,2,4,8,16}, wu5rt=wu9rt={1}, wu6rt={1,2,4,8}, wu7rt={1,2,4}, wu8rt={1,2}, wu9rt={1};

[0084] The list of upper bit width values ​​supported for a particular depth is {36,18,9,4,2,1}. The supported bit width values ​​that are powers of 2 are {32,16,8,4,2,1}.

[0085] In this embodiment, the function for calculating the data bit width value set is merge, the maximum number of iterative calculations MAX_ITR is set to 32, wid_WU is set to 6, and the same below. The bit width of this function is set to 192. The input w is the bit width to be calculated. The constants are: q capacity, depth d. The variables are: the number of iterations of a specific data bit width value, including: wany of any data bit width, wn1 of data bit width wu1, wn2 of data bit width wu2, ... wnn of data bit width wun. The above constants and variable data types can all be integer integers.

[0086] Initially: merge is reset to zero, wany, wn1, wn2, ...wnn are all reset to zero, quantity is assigned to q, d = quantity / w;

[0087] Iteration: As long as w>0, iterative calculation is performed continuously:

[0088] (1) For data bit width w

[0089] If w is not greater than 36 and q is not greater than 36k, then merge=merge<<6|w, w=0, and wany is incremented by 1;

[0090] Otherwise if w is not less than 36 and RATIO is 4 or 2 or 1,

[0091] Then merge=merge<<6|36,w=w-36,wn36 is incremented by 1;

[0092] Otherwise, if w is not less than 32 and RATIO is 32 or 16 or 8 or 4 or 2 or 1, then merge = merge << 6|32, w = w-32, wn32 is incremented by 1;

[0093] Otherwise, if w is not less than 18 and RATIO is 2 or 1,

[0094] Then merge=merge<<6|18,w=w-18,wn18 is incremented by 1;

[0095] Otherwise if w is not less than 16 and RATIO is 16 or 8 or 4 or 2 or 1,

[0096] Then merge=merge<<6|16,w=w-16,wn16 is incremented by 1;

[0097] Otherwise, if w is not less than 9, then merge = merge << 6|9, w = w-9, wn9 increases by 1;

[0098] Otherwise if w is not less than 8 and RATIO is 8 or 4 or 2 or 1,

[0099] Then merge=merge<<6|8,w=w-8,wn8 is incremented by 1;

[0100] Otherwise if w is not less than 4 and RATIO is 4 or 2 or 1,

[0101] Then merge=merge<<6|4,w=w-4,wn4 is incremented by 1;

[0102] Otherwise if w is not less than 2 and RATIO is 2 or 1,

[0103] Then merge=merge<<6|2,w=w-2,wn2 increases by 1;

[0104] Otherwise, if RATIO is 1, then merge=merge<<6|1, w=w-1, wn1 is incremented by 1.

[0105] (2) Capacity q=quantity-(wn36*6'd36+wn18*6'd18+wn16*6'd16+wn9*6'd9+wn8*6'd8+wn4*6'd4+wn2*6'd2+wn1*6'd1)*d.

[0106] It is worth noting that when the port width ratio is not 1, it also includes:

[0107] The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

[0108] Specifically, if you want to generate a memory with port A and port B data width of 20 / 5 bits respectively, there will be two address splicing instances spliced ​​together. Assuming port A is the larger port, the data widths of the two address splicing instances A / B ports are 16 / 4 and 4 / 1 respectively. As shown in the following table:

[0109] Table 1. Arrangement of calculated values ​​of data bit range of port A

[0110] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

[0111] Table 2. Port B data bit range calculation value arrangement

[0112] 4 3 2 1 0 2 1 1 1 1

[0113] Table 3. Arrangement of calculated values ​​of actual data bit range of ports A and B

[0114] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 2 1 1 1 1 2 1 1 1 1 2 1 1 1 1 2 1 1 1 1 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 0 0 0 0 0

[0115] The first row of Tables 1, 2, and 3 represents the data bit sequence number, with a value range of 19 to 0, for a total of 20 bits.

[0116] The 1,2 in the second row of Table 1 represent the arrangement order of the data bit range calculation values ​​of the 0th and 1st address splicing instances of port A;

[0117] 1,2 in the second row of Table 2 represents the data bit arrangement of the 0th and 1st address concatenation instances of port B and the arrangement order of the data bit range calculation value;

[0118] As shown in the second and third rows of Table 3, the data of port A is formed by connecting the data in the four address splicing instances of port B. The 3, 2, 1, 0 in the fourth row of Table 3 represent the sequence numbers of the four address splicing instances. The 1, 2 in the third row of Table 3 represent the data bit arrangement of the 0th and 1st address splicing module instances of port A.

[0119] Observe that the values ​​of the second row of Table 1 and the third row of Table 3 are different, and bit mapping is required. That is, the write data and read data of the A (larger) port need to be bit mapped from Table 1 -> Table 3, and Table 3 -> Table 1 respectively. The B (smaller) port does not need it.

[0120] In addition, when using the parity bit of the memory element, it also includes:

[0121] The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

[0122] Specifically, for example, a port A has a bit width of 18 and a port B is a 9-bit memory element, as shown in the following table, RATIO=2.

[0123] Table 4 Data / check bit allocation for port A:

[0124] 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1 p2 d1 d1 d1 d1 d1 d1 d1 d1 d2 d2 d2 d2 d2 d2 d2 d2

[0125] Table 5 Data / check bit allocation for port B

[0126] 8 7 6 5 4 3 2 1 0 p d d d d d d d d

[0127] Table 6 Data / check bit allocation for port A

[0128] 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1 d1 d1 d1 d1 d1 d1 d1 d1 p2 d2 d2 d2 d2 d2 d2 d2 d2

[0129] The first row of Tables 4, 5, and 6 indicates the data bit sequence number. Port A has 18 bits from 0 to 17, and Port B has 8 bits from 0 to 7.

[0130] In the second row of Table 4, d1 and d2 represent the data bits of port A of the memory element, p1 and p2 represent the check bits of port A of the memory element, and 1 and 2 represent the high and low bit groups in the mapping of port A data to port B data 2 groups.

[0131] In the second row of Table 5, d represents the data bit in the port B of the memory element / unit, and p represents the check bit therein;

[0132] As shown in Table 6, the data of port A is the data in two B port address units connected. In the second row of Table 6, d1, d2 represent the data bit ranking of the memory element in the read and write data bits of the memory unit, and p1, p2 represent the parity bit ranking of the memory element in the read and write data bits of the memory unit.

[0133] The write data of the larger port is mapped from Table 4 -> Table 6, and the read data is mapped from Table 6 -> Table 4. The smaller port does not need this.

[0134] Furthermore, when the remaining data bit width is smaller than the upper limit of the data bit width corresponding to the address depth, the steps of writing data for filling and reading data for deleting are also included.

[0135] Specifically, if you want to generate a memory with port A and port B bit widths of 10 / 5 bits respectively, and the currently supported data bit widths are 18, 9, 4, 2, and 1, then the closest value is 18 / 9.

[0136] Therefore, for port A, the data bit width is 18, and only 10 bits are used; for port B, the data bit width is 9, and only 5 bits are used.

[0137] The wasted bits need to be supplemented in the extra places (other variable signals in FPGA besides constants need to declare the bit width).

[0138] Port B is at [8:5], 4 bits need to be added when writing, and 4 bits need to be deleted when reading.

[0139] The bits to be supplemented at port A are [9*0+8:9*0+5],[9*1+8:9*1+5], that is, [17:14],[8:5].

[0140] S2. Determine the address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result.

[0141] Specifically, step S2 includes:

[0142] S21. Determine the number of address concatenation instances of the port according to the number of iterations.

[0143] According to step S1, the total number of iterations can be obtained. In this embodiment, the number of address concatenation instances is equal to the number of iterations.

[0144] S22. Determine the data bit width value and the data bit starting sequence number of the address splicing instance according to the data bit width selected in each iteration.

[0145] It can be understood that the data bit start bit number of the i-th address splicing instance is the accumulation of the data bit width values ​​of the 0th to i-1th instances.

[0146] S23. Determine the data bit width value and data bit starting sequence number of another port address splicing instance according to the maximum data bit width selected in each iteration and the port bit width ratio.

[0147] Specifically, according to the calculated data bit width value of the address splicing instance of the larger port, the smaller bit width is obtained by dividing the former by RATIO (bit width ratio of the port).

[0148] S3. Determine the memory unit instance that needs to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance.

[0149] Specifically, when the capacity of the designed memory is not greater than the maximum capacity supported by the optional memory element, a memory unit instance is instantiated;

[0150] When the capacity of the designed memory is larger than the maximum capacity supported by the optional memory element, determine the address depth bit width of the largest memory element at the required data bit width, subtract the address depth bit width from the required address bit width, and use the power of 2 obtained as the number of instantiations of the memory unit instance.

[0151] Refer to Q1=18k, Q2=36k in the above example; if the designed memory capacity quantity<=Q2, then directly instantiate one memory unit instance, otherwise instantiate multiple memory unit instances (the specific number can be calculated through the above steps) and perform address splicing.

[0152] S4. Instantiate a memory element instance according to the capacity of the memory unit instance and the optional memory element.

[0153] Specifically, in this embodiment, the required capacity is obtained by multiplying the required data bit width and the required address, and the one closest to and not less than the required capacity is selected from the memory elements. If the required capacity is less than 18K, the element corresponding to Q1 is used, and if the required capacity is between 18K and 36K, the element corresponding to Q2 is used.

[0154] Calculate the actual occupied address depth and data bit width, and determine whether check bit mapping and padding and deletion of invalid bits are required based on the data bit width and address depth parameters.

[0155] According to the calculation results, a memory element is instantiated, the address is padded with zeros when necessary, the data is bit mapped or filled to delete invalid bits or not processed when necessary, and the corresponding parameters and interfaces of the memory element are connected together with the actual occupied data bit width and depth parameters, and the remaining parameters and signals are directly connected.

[0156] In summary, the design method of the parameterized memory in the present invention selects the data bit width that meets the bit width ratio of the port according to the data bit width types supported by the optional memory elements, and performs approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero; determines the address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result; determines the memory unit instance that needs to be instantiated when performing address splicing according to the data bit width and address depth value of the address splicing instance; and instantiates the memory element instance according to the capacity of the memory unit instance and the optional memory element.

[0157] Therefore, the data width can be calculated and analyzed, and the memory elements of appropriate specifications and quantities can be automatically instantiated and spliced ​​to support any data width. There is no need to modify the code, just reload the data width and address depth parameters of the two ports to meet various specifications. Data width splicing and address splicing are implemented through code, and the component template provided by the compiler is strictly matched, so the implemented component type is highly controllable and will not synthesize a large number of registers to build the memory. Using data width and capacity, it is approximated and iterated in order from large to small, so as to achieve the purpose of using the necessary and minimum memory resources to build the memory of the required width, thus optimizing resource utilization. Using hardware description language, it is seamlessly connected with the functional design of FPGA, without relying on compilers and compilation tools, and no need to use other high-level languages ​​for design.

[0158] The embodiment of the present invention also provides a design device for a parameterized memory, which uses a hardware description language to implement all functions. According to the data bit width and address depth parameter (constant) values ​​of the input two end ports, the processing steps of bit width first and then depth are followed. The data bit width and capacity are matched with the maximum bit width value in the template of the element (data bit width, address depth, bit width ratio) that meets the conditions each time by the remaining value until it returns to zero and is continuously iterated. The address bit width is divided into high and low bits, and the high bit is used as a chip selection method. The number of lower-level modules that need to be instantiated, and the data bit width and address depth parameters at both ends of the modules, the data bit width and address bit width range of the corresponding ports are calculated, and the calculation results are arranged in sequence; according to the calculation results, the memory is instantiated step by step and in sequence, and the corresponding data bit mapping is performed according to the characteristics of the device and the compiler and the data bit width ratio. The lower-level module parameters are overloaded and their signals are connected to realize the splicing of data bit width and address.

[0159] Specifically, the design device of the parameterized memory includes a bit width splicing module, an address splicing module and a memory unit module. The bit width splicing module instantiates one or more address splicing modules according to its calculation results, the address splicing module instantiates one or more memory unit modules according to its own calculation results, and the memory unit module calls several memory elements supported by compilers and devices and instantiates one of them according to its calculation results.

[0160] Among them, the bit width splicing module selects the data bit width that meets the bit width ratio of the port according to the data bit width types supported by the optional memory element, and iterates the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero, and determines the address splicing instance that needs to be instantiated when performing data bit width and address splicing according to the iteration result. The address splicing module determines the memory unit instance that needs to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance. The memory unit module instantiates the memory element instance according to the capacity of the memory unit instance and the optional memory element.

[0161] In some embodiments, the bit width splicing module selects a data bit width that satisfies the bit width ratio of the port according to the data bit width types supported by the optional memory element, and performs approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero, including:

[0162] Statistics are collected on the upper limit of the data bit width supported by the optional memory elements at various address depths, the values ​​of powers of 2 in the supported data bit width, and the bit width ratios supported by each value.

[0163] Compare the data bit widths of the two ports, select the data bit width of the larger port as the initial value of the remaining data bit width, and the required capacity as the initial value of the remaining capacity;

[0164] If the remaining data bit width does not exceed the maximum value in the statistics, and the remaining capacity does not exceed the maximum memory element capacity value, the remaining data bit width is used as the data bit width of this iteration; otherwise, the maximum data bit width value that does not exceed the remaining data bit width and whose supported bit width ratio value contains the bit width ratio value of the port is selected as the data bit width of this iteration;

[0165] The remaining data bit width and the remaining capacity are iterated using the obtained data bit width until the remaining data bit width and the remaining capacity return to zero.

[0166] In some embodiments, the bit width splicing module determines, according to the iteration result, an address splicing instance that needs to be instantiated when performing data bit width and address splicing, including:

[0167] Determine the number of address concatenation instances of the port according to the number of iterations;

[0168] Determine the data bit width value and data bit starting sequence number of the larger port of the address splicing instance according to the data bit width selected in each iteration;

[0169] The data bit width value and the data bit starting sequence number of another port of the address splicing instance are determined according to the maximum data bit width selected in each iteration and the bit width ratio of the port.

[0170] In some embodiments, when the bit width ratio of the port is not 1, the bit width splicing module is further used to implement:

[0171] The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

[0172] In some embodiments, when the parity bit of the memory element is used, the bit width splicing module is further used to implement:

[0173] The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

[0174] In some embodiments, when the selected remaining data bit width is smaller than the upper limit value of the data bit width corresponding to the address depth, the bit width splicing module is further used to implement the steps of writing data for filling and reading data for deletion.

[0175] In some embodiments, the address splicing module determines the memory unit instance that needs to be instantiated when performing address splicing according to the address splicing instance, including:

[0176] When the capacity of the designed memory is not greater than the maximum capacity supported by the optional memory element, a memory unit instance is instantiated;

[0177] When the capacity of the designed memory is larger than the maximum capacity supported by the optional memory element, determine the address depth bit width of the largest memory element at the required data bit width, subtract the address depth bit width from the required address bit width, and use the power of 2 obtained as the number of instantiations of the memory unit instance.

[0178] In summary, the design device of parameterized memory in the present invention can calculate and analyze the bit width, automatically instantiate and splice memory elements of appropriate specifications and quantities, and support arbitrary bit width; there is no need to modify the code, just reload the data bit width and depth parameters of the two ports to meet various specification requirements; bit width splicing and address splicing are realized through code, and the component template provided by the compiler is strictly matched, so the realized component type is highly controllable, and a memory built with a large number of registers will not be synthesized. Using data bit width and capacity, it is approximated and iterated in order from large to small, so as to achieve the purpose of using necessary and minimum memory resources to build a memory of the required bit width, thereby optimizing resource utilization; using hardware description language, it is seamlessly connected with the functional design of FPGA, without relying on compilers and compilation tools, and no need to use other high-level languages ​​for design.

[0179] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A method for designing a parameterized memory, characterized in that: The method comprises the following steps: According to the data bit width types supported by the optional memory element, a data bit width that satisfies the bit width ratio of the port is selected, and approximation iteration is performed on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero; Determine the address splicing instance that needs to be instantiated when performing data width splicing and address splicing according to the iteration result; Determine the memory unit instance that needs to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance; Instantiate a memory element instance according to the capacity of the memory unit instance and the optional memory element; The method of selecting a data bit width that satisfies the bit width ratio of a port according to the data bit width types supported by the optional memory element, and performing approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero includes: Count the upper limit of the data bit width supported by the optional memory element at various address depths, the power of 2 value in the supported data bit width, and the bit width ratio supported by each value; Compare the data bit widths of the two ports, select the data bit width of the larger port as the initial value of the remaining data bit width, and the required capacity as the initial value of the remaining capacity; If the remaining data bit width does not exceed the maximum value in the statistics, and the remaining capacity does not exceed the maximum memory element capacity value, the remaining data bit width is used as the data bit width of this iteration; otherwise, the maximum data bit width value that does not exceed the remaining data bit width and whose supported bit width ratio value contains the bit width ratio value of the port is selected as the data bit width of this iteration; The remaining data bit width and the remaining capacity are iterated using the obtained data bit width until the remaining data bit width and the remaining capacity return to zero.

2. The method for designing a parameterized memory according to claim 1, characterized in that: The address splicing instance that needs to be instantiated when performing data bit width splicing and address splicing according to the iteration result includes: Determine the number of address concatenation instances of the port according to the number of iterations; Determine the data bit width value and data bit starting sequence number of the larger port of the address splicing instance according to the data bit width selected in each iteration; The data bit width value and the data bit starting sequence number of another port of the address splicing instance are determined according to the data bit width selected in each iteration and the bit width ratio of the port.

3. A method for designing a parameterized memory according to claim 2, characterized in that: When the port width ratio is not 1, it also includes: The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

4. The method for designing a parameterized memory according to claim 2, characterized in that: When using the parity bit of the memory element, it also includes: The step of bit mapping the write data and read data of the port with a larger bit width value according to the data bit arrangement of the address splicing instance of the two ports.

5. The method for designing a parameterized memory according to claim 2, characterized in that: When the remaining data bit width of the port bit width is less than the upper limit value of the data bit width corresponding to the address depth, the method further includes the steps of writing data for filling and reading data for deletion.

6. A method for designing a parameterized memory according to claim 2, characterized in that: The determining, according to the address splicing instance, a memory unit instance that needs to be instantiated when performing address splicing includes: When the capacity of the designed memory is not greater than the maximum capacity supported by the optional memory element, a memory unit instance is instantiated; When the capacity of the designed memory is larger than the maximum capacity supported by the optional memory element, determine the address depth bit width of the largest memory element at the required data bit width, subtract the address depth bit width from the required address bit width, and use the power of 2 obtained as the number of instantiations of the memory unit instance.

7. A design device for parameterized memory, characterized in that: include: A bit width splicing module, which selects a data bit width that satisfies the bit width ratio of the port according to the data bit width types supported by the optional memory element, performs approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero, and determines the address splicing instance that needs to be instantiated when performing data bit width splicing and address splicing according to the iteration result; An address splicing module, which determines a memory unit instance to be instantiated when performing address splicing according to the data bit width and address depth of the address splicing instance; A memory cell module that instantiates a memory element instance according to the capacity of the memory cell instance and an optional memory element; The bit width splicing module selects a data bit width that satisfies the bit width ratio of the port according to the data bit width types supported by the optional memory element, and performs approximation iteration on the remaining capacity of the required memory and the remaining data bit width of a port until the remaining data bit width and the remaining capacity return to zero, including: Count the upper limit of the data bit width supported by the optional memory element at various address depths, the power of 2 value in the supported data bit width, and the bit width ratio supported by each value; Compare the data bit widths of the two ports, select the data bit width of the larger port as the initial value of the remaining data bit width, and the required capacity as the initial value of the remaining capacity; If the remaining data bit width does not exceed the maximum value in the statistics, and the remaining capacity does not exceed the maximum memory element capacity value, the remaining data bit width is used as the data bit width of this iteration; otherwise, the maximum data bit width value that does not exceed the remaining data bit width and whose supported bit width ratio value contains the bit width ratio value of the port is selected as the data bit width of this iteration; The remaining data bit width and the remaining capacity are iterated using the obtained data bit width until the remaining data bit width and the remaining capacity return to zero.

8. The device for designing a parameterized memory according to claim 7, characterized in that: The bit width splicing module determines the address splicing instance that needs to be instantiated when performing data bit width splicing and address splicing according to the iteration result, including: Determine the number of address concatenation instances of the port according to the number of iterations; Determine the data bit width value and data bit starting sequence number of the larger port of the address splicing instance according to the data bit width selected in each iteration; The data bit width value and the data bit starting sequence number of another port of the address splicing instance are determined according to the data bit width selected in each iteration and the bit width ratio of the port.

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