A three-dimensional memory data refresh method, device, system, and medium

Abstract

The application provides a three-dimensional memory data refresh method, device, system and medium, the method comprises the following steps: determining the data refresh period of a weak storage page according to the storage page with the maximum error rate in a flash block; performing data refresh on the weak storage page according to the data refresh period of the weak storage page; when the error rate of a strong storage page is greater than a preset threshold, updating the strong storage page with the error rate greater than the preset threshold to a weak storage page and performing data refresh; determining the data refresh period of the strong storage page according to the storage page with the maximum error rate in the strong storage page; and performing data refresh on the strong storage page according to the data refresh period of the strong storage page. Thus, the data refresh of the same flash block is divided into two parts, i.e., weak storage page data refresh and strong storage page data refresh, so that the overall refresh frequency can be reduced, the system overhead can be reduced, the label of the strong storage page is dynamically modified, and the strong storage page can be refreshed before the error exceeds the upper limit of error correction code correction after experiencing multiple refresh periods.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a three-dimensional memory data refresh method, apparatus, system and medium. Background Technology

[0002] Semiconductor memory devices can be volatile or non-volatile. While volatile semiconductor memory devices can perform read and write operations at high speeds, the data stored in them is lost when power is off. Conversely, non-volatile semiconductor memory devices retain their stored data regardless of whether power is applied. Flash memory is a typical example of a non-volatile semiconductor memory device, and therefore, it is widely used as a data storage medium.

[0003] In NAND Flash memory devices, data storage is achieved by injecting different amounts of charge into the floating gate of the flash memory cell or storing different amounts of charge in the charge trapping layer. However, electrons stored in the floating gate or charge trapping layer leak out over time. This phenomenon becomes increasingly pronounced with the increase in the number of wear cycles of the flash memory cell. After experiencing a large number of wear cycles, i.e., after multiple program / erase cycles, the charge leakage of the flash memory cell accelerates. This cumulative error caused by the continuous loss of charge over time is called data retention error. Retention time is defined as the time that a flash memory cell can store data before exceeding the error correction capability of ECC (Error Correcting Code).

[0004] The commonly used solution to address data retention errors in flash memory systems is a refresh operation. This involves reading the data before the flash memory block's data storage time exceeds its retention time, performing ECC error correction, and then rewriting the error-free data to a new flash memory page, thus extending the time that the data can be correctly stored in the flash memory.

[0005] While refresh operations can fundamentally solve data retention errors and extend data retention time, the additional read and write operations they introduce can impact system performance and reduce the response speed of read and write requests. Furthermore, refresh operations involve additional writes, and a large number of refresh operations also lead to more erase operations, increasing flash memory wear. Therefore, reducing the number of flash memory refresh operations while ensuring data integrity is a key technical problem that needs to be solved in this field. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a three-dimensional memory data refresh method, apparatus, system and medium that can reduce the number of data refreshes, reduce flash memory wear and improve system performance.

[0007] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] To achieve the above objectives, this application provides the following technical solution:

[0009] In a first aspect, embodiments of this application provide a three-dimensional memory data refresh method, including:

[0010] Memory pages with a bit error rate greater than a preset threshold are marked as weak memory pages;

[0011] Memory pages with a bit error rate less than or equal to the preset threshold are marked as strong memory pages;

[0012] The data refresh cycle of the weak storage page is determined based on the storage page with the highest bit error rate among the weak storage pages, and the data of the weak storage page is refreshed according to the data refresh cycle of the weak storage page;

[0013] Periodically check whether the bit error rate of the strong storage page is greater than the preset threshold. When the bit error rate of the strong storage page is greater than the preset threshold, update the strong storage page with the bit error rate greater than the preset threshold as a weak storage page and refresh the data.

[0014] The data refresh cycle of the strong storage page is determined based on the storage page with the highest bit error rate among the strong storage pages, and the data of the strong storage page is refreshed according to the data refresh cycle of the strong storage page.

[0015] In one possible implementation, determining the data refresh cycle of the weak storage page based on the storage page with the highest bit error rate among the weak storage pages includes:

[0016] The data refresh cycle of the weak storage page is equal to the first data retention time of the storage page with the highest bit error rate among the weak storage pages; the first data retention time is the time that the storage page with the highest bit error rate among the weak storage pages stores data before it exceeds the error correction code's error correction capability.

[0017] In one possible implementation, determining the data refresh cycle of the strong storage page based on the storage page with the highest bit error rate among the strong storage pages includes:

[0018] The data refresh cycle of the strong storage page is equal to the second data retention time of the storage page with the highest bit error rate among the strong storage pages; the second data retention time is the time that the storage page with the highest bit error rate among the strong storage pages stores data before it exceeds the error correction code's error correction capability.

[0019] In one possible implementation, the data refresh cycle of the weak storage page is less than the periodic refresh cycle of the strong storage page.

[0020] Secondly, embodiments of this application provide a three-dimensional memory data refresh device, comprising:

[0021] The weak storage page marking unit is used to mark storage pages with a bit error rate greater than a preset threshold as weak storage pages;

[0022] A strong storage page marking unit is used to mark storage pages with a bit error rate less than or equal to the preset threshold as strong storage pages;

[0023] A weak storage page data refresh unit is used to determine the data refresh cycle of the weak storage page based on the storage page with the highest bit error rate among the weak storage pages, and to refresh the data of the weak storage page according to the data refresh cycle of the weak storage page;

[0024] A periodic detection unit is used to periodically detect whether the bit error rate of the strong storage page is greater than the preset threshold. When the bit error rate of the strong storage page is greater than the preset threshold, the strong storage page with the bit error rate greater than the preset threshold is updated and marked as a weak storage page, and the data is refreshed.

[0025] A strong storage page data refresh unit is used to determine the data refresh cycle of the strong storage page based on the storage page with the highest bit error rate among the strong storage pages, and to refresh the data of the strong storage page according to the data refresh cycle of the strong storage page.

[0026] In one possible implementation, the weak storage page data refresh unit is specifically used for:

[0027] The data refresh cycle of the weak storage page is equal to the first data retention time of the storage page with the highest bit error rate among the weak storage pages; the first data retention time is the time that the storage page with the highest bit error rate among the weak storage pages stores data before it exceeds the error correction code's error correction capability.

[0028] In one possible implementation, the strong storage page data refresh unit is specifically used for:

[0029] The data refresh cycle of the strong storage page is equal to the second data retention time of the storage page with the highest bit error rate among the strong storage pages; the second data retention time is the time that the storage page with the highest bit error rate among the strong storage pages stores data before it exceeds the error correction code's error correction capability.

[0030] In one possible implementation, the data refresh cycle of the weak storage page is less than the periodic refresh cycle of the strong storage page.

[0031] Thirdly, embodiments of this application provide a three-dimensional memory data refresh system, including:

[0032] Memory, used to store computer programs;

[0033] A processor is configured to implement the steps of the three-dimensional memory data refresh method as described above when executing the computer program.

[0034] Fourthly, embodiments of this application provide a computer-readable medium storing a computer program, which, when processed and executed, implements the steps of the three-dimensional memory data refresh method described above.

[0035] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0036] This application provides a three-dimensional memory data refresh method, apparatus, system, and medium. The method includes: marking memory pages with a bit error rate (BER) greater than a preset threshold as weak memory pages, marking memory pages with a BER less than or equal to the preset threshold as strong memory pages, determining the data refresh cycle of weak memory pages based on the memory page with the highest BER among the weak memory pages, refreshing the weak memory pages according to the data refresh cycle, periodically detecting whether the BER of strong memory pages is greater than the preset threshold, and when the BER of strong memory pages is greater than the preset threshold, remarking the strong memory pages with BER greater than the preset threshold as weak memory pages and refreshing their data; determining the data refresh cycle of strong memory pages based on the memory page with the highest BER among the strong memory pages, and refreshing the strong memory pages according to the data refresh cycle. This method divides the data refresh of the same flash memory block into two parts: weak memory page data refresh and strong memory page data refresh. This reduces the overall refresh frequency, reduces system overhead, and allows for dynamic modification of the marking of strong memory pages, preventing strong memory pages from exceeding the error correction code upper limit after multiple refresh cycles without being refreshed. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 This illustration shows a schematic diagram of the distribution of the threshold voltage of a memory under normal conditions, according to an embodiment of this application.

[0040] Figure 2 This application provides a schematic diagram illustrating the location and composition of an FTL (Functional Tolerancing Module).

[0041] Figure 3 This illustration shows a schematic diagram of the data retention time corresponding to a P / E Cycle provided in an embodiment of this application;

[0042] Figure 4 This illustration shows a refresh interval for flash memory blocks of different numbers and different retention durations, as provided in an embodiment of this application.

[0043] Figure 5 This illustration shows a schematic diagram of ECC performing flash memory block error correction according to an embodiment of this application;

[0044] Figure 6 A flowchart of a three-dimensional memory data refresh method provided in an embodiment of this application is shown;

[0045] Figure 7 This illustration shows a schematic diagram of different storage pages corresponding to different tags and states, provided in an embodiment of this application.

[0046] Figure 8 A schematic diagram of the flow of a three-dimensional memory data refresh method provided in an embodiment of this application is shown;

[0047] Figure 9 A schematic diagram of a three-dimensional memory data refresh device provided in an embodiment of this application is shown. Detailed Implementation

[0048] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0050] As described in the background section, the applicant has discovered that semiconductor memory devices can be volatile or non-volatile. While volatile semiconductor memory devices can perform read and write operations at high speeds, the content stored in them is lost when power is off. Conversely, non-volatile semiconductor memory devices retain their stored content regardless of whether power is applied. Flash memory is a typical example of a non-volatile semiconductor memory device; therefore, flash memory devices can be widely used as data storage media.

[0051] In NAND Flash memory devices, data storage is achieved by injecting different amounts of charge into the floating gate of the flash memory cell or storing different amounts of charge in the charge trapping layer. However, electrons stored in the floating gate or charge trapping layer leak out over time. This phenomenon becomes increasingly pronounced with the increase in the number of wear cycles of the flash memory cell. After experiencing a large number of wear cycles, i.e., after multiple program / erase cycles, the charge leakage of the flash memory cell accelerates. This cumulative error caused by the continuous loss of charge over time is called data retention error. Retention time is defined as the time that a flash memory cell can store data before exceeding the error correction capability of ECC (Error Correcting Code).

[0052] ECC is an electronic method used to verify the overall data stored in a storage device. It can not only detect multiple data errors, but also specify and correct the erroneous bits.

[0053] The commonly used solution to address data retention errors in flash memory systems is a refresh operation. This involves reading the data before the flash memory block's data storage time exceeds its retention time, performing ECC error correction, and then rewriting the error-free data to a new flash memory page, thus extending the time that the data can be correctly stored in the flash memory.

[0054] See Figure 1The figure shows the threshold voltage distribution and the number of electrons in a flash cell. The memory cell exists in four storage states: "00", "01", "10", and "11", separated by REF1, REF2, and REF3 respectively. (See also...) Figure 1 As shown in (a), the threshold voltage distribution is under normal conditions. When a data retention error occurs, the threshold voltage will shift to the left. It will only return to normal after the data is refreshed.

[0055] The specific data refresh operation refers to designing a refresh algorithm in the FTL (Flash Translation Layer).

[0056] FTL is a firmware layer in a NAND storage system, located in the flash memory system as follows: Figure 2 As shown, the Host is the host computer. The host computer communicates with the SSD Controller (Solid State Disk) via PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard). The SSD Controller communicates with the NAND flash memory via the Open NAND Flash Interface (ONFI).

[0057] The SSD controller includes a host interface, FTL, flash interface, and DRAM (Dynamic Random Access Memory). The FTL layer further includes an address mapping block, a wear leveling block, and a garbage collection block.

[0058] Flash memory cannot be updated in-situ, and its page-based read / write, block-based erase, and wear leveling cycles are limited. These characteristics negatively impact flash memory performance. The File Transfer Layer (FTL), a software layer, can significantly overcome these problems and improve flash memory block performance. The FTL layer is responsible for scheduling flash memory requests, address mapping management, garbage collection management, and wear leveling algorithms. Currently, FTL layer algorithms are a major research direction in NAND systems.

[0059] While refresh operations can fundamentally solve data retention errors and extend data retention time, the additional read and write operations they introduce can impact system performance and reduce the response speed of read and write requests. Furthermore, refresh operations involve additional writes, and a large number of refresh operations also lead to more erase operations, increasing flash memory wear. Therefore, reducing the number of flash memory refresh operations while ensuring data integrity is a key technical problem that needs to be solved in this field.

[0060] There are three main existing algorithms for reducing data refresh operations:

[0061] (1) Dynamically adjust refresh rate based on P / E Cycle, see [link / reference] Figure 3 As shown, when the P / E Cycle is between [0, 3K], the Minimum Block Retention Time is 3 years (1095 days); between [3K, 8K], the Minimum Block Retention Time is 3 months (90 days); between [8K, 20K], the Minimum Block Retention Time is 3 weeks (21 days); between [20K, 150K], the Minimum Block Retention Time is 3 days; and when it is greater than 150K, the Minimum Block Retention Time is only 3 days.

[0062] (2) The reason why NAND flash memory pages cannot be updated in-situ based on reprogramming operations is that the programming operation of flash memory cells can only achieve low-state to high-state programming, and cannot be programmed from high-state to low-state. The data retention error is caused by charge leakage, which shifts the threshold voltage to the left, i.e., from high state to low state. Therefore, the data can be restored to its original state by reprogramming.

[0063] (3) Enhance ECC error correction capabilities

[0064] Enhancing ECC error correction capabilities can relax the upper limit of data errors, increase data retention time, and reduce refresh operations.

[0065] Data refresh frequency and overhead are primarily influenced by two factors: the retention time supported by the flash memory blocks and the amount of valid data in the flash memory blocks during refresh. Based on the retention time of the flash memory blocks, they are divided into different refresh frequency groups. The refresh interval T / N for each group can be obtained by considering the retention time T supported by each group and the number of flash memory blocks N in each group. See also... Figure 4 As shown, the retention time for group 1 is T1, the number of flash memory blocks is M, and the refresh interval is T1 / M; the retention time for group 2 is T2, the number of flash memory blocks is N, and the refresh interval is T2 / N; the retention time for group 3 is T3, the number of flash memory blocks is X, and the refresh interval is T3 / X; the retention time for group 4 is T4, the number of flash memory blocks is Y, and the refresh interval is T4 / Y.

[0066] For each flash memory block, after one refresh cycle, when the refresh begins, the valid data in the flash memory block is copied to other physical free pages. This process involves many read and write operations within the flash memory. For example... Figure 5 As shown, flash memory block Blk (Block) M is about to reach its retention time limit, triggering a refresh. Valid pages are read and corrected, written to the free pages of flash memory block N, and the previously valid pages become invalid. Valid page reads and writes consume a significant amount of system time.

[0067] Traditional data refresh operations use the physical page with the shortest retention time in a flash memory block as the standard for flash block retention time, grouping flash memory blocks according to their retention time. Data in each flash memory block is then periodically refreshed based on these groups to maintain data accuracy.

[0068] In existing methods, reprogramming leads to the accumulation of programming errors, and reprogramming can cause significant differences in the rate of error growth between pages.

[0069] Enhancing the error correction capability of ECC will result in significant decoding delay and higher system overhead.

[0070] Based on the retention time supported by the flash memory blocks, grouping flash memory blocks and fixing the refresh frequency requires ensuring that all data pages within a flash memory block will not have errors. Therefore, previous work has used the flash page with the highest bit error rate under the same retention time as the retention time standard for that block, in order to ensure that some flash pages in the flash memory block will not have bit errors exceeding the ECC error correction capability at that refresh frequency. This will lead to many unnecessary flash page refreshes, resulting in system overhead that could have been avoided.

[0071] To address the above technical problems, embodiments of this application provide a three-dimensional memory data refresh method, apparatus, system, and medium. The method includes: marking memory pages with a bit error rate (BER) greater than a preset threshold as weak memory pages; marking memory pages with a BER less than or equal to the preset threshold as strong memory pages; determining a data refresh cycle for weak memory pages based on the memory page with the highest BER among the weak memory pages; refreshing the data of weak memory pages according to the data refresh cycle; periodically detecting whether the BER of strong memory pages is greater than a preset threshold; when the BER of strong memory pages is greater than the preset threshold, updating the marking of strong memory pages with BER greater than the preset threshold as weak memory pages and refreshing their data; determining a data refresh cycle for strong memory pages based on the memory page with the highest BER among the strong memory pages; and refreshing the data of strong memory pages according to the data refresh cycle. This allows the data refresh of the same flash memory block to be completed in two parts: weak memory page data refresh and strong memory page data refresh. This reduces the overall refresh frequency, reduces system overhead, and allows for dynamic modification of the strong memory page markers. It also prevents strong memory pages from exceeding the error correction code upper limit after multiple refresh cycles without being refreshed.

[0072] Exemplary method

[0073] See Figure 6 The diagram shown is a flowchart of a three-dimensional memory data refresh method provided in an embodiment of this application, including:

[0074] S101: Mark storage pages with a bit error rate greater than a preset threshold as weak storage pages.

[0075] S102: Mark storage pages with a bit error rate less than or equal to the preset threshold as strong storage pages.

[0076] In this embodiment of the application, taking advantage of the large difference in bit error rate between different word lines of the same flash memory block in the three-dimensional memory, some flash pages with high bit error rate can be excluded from the refresh cycle of the flash memory block. The refresh of these pages is not at the same frequency as the refresh of the flash memory block. In this way, the retention time of the flash memory block can be extended to more than three times the original, which greatly reduces the refresh frequency.

[0077] Specifically, in the past, data refresh grouping of flash memory blocks used the retention time of the physical page with the worst characteristics as the retention time of the entire flash memory block. However, in 3D TLC (Trinary-Level Cell) flash memory, due to process variation (PV), the endurance characteristics of different flash memory pages vary greatly. The characteristic differences between word lines within the same flash memory block can be utilized in 3D Charge Trap TLC NAND to reduce the refresh rate.

[0078] Therefore, lower-performing flash pages can be refreshed individually, reducing the overall refresh frequency of the flash block. This avoids the refresh cycle of the entire flash block being determined by the worst-performing flash page, thus reducing refresh operations. Within the same flash block, lower-performing flash pages are recorded as "Weak Pages" in the mapping table.

[0079] For example, see Figure 7 As shown, storage pages with a bit error rate greater than a preset threshold can be marked as weak storage pages. That is, storage pages with LPN (logical page number) of 1 and 3 and PPN (physical page number) of 23 and 863 can be marked as weak storage pages.

[0080] Similarly, in the embodiments of this application, storage pages with a bit error rate less than or equal to a preset threshold can be marked as strong storage pages. For example, see [link to relevant documentation]. Figure 7 As shown, memory pages with LPN of 0, 2, and 4, and PPN of 10, 562, and 665 can be marked as strong memory pages.

[0081] S102: Determine the data refresh cycle of the weak storage page based on the storage page with the highest bit error rate among the weak storage pages, and refresh the data of the weak storage page according to the data refresh cycle of the weak storage page.

[0082] S103: Periodically check whether the bit error rate of the strong storage page is greater than the preset threshold. When the bit error rate of the strong storage page is greater than the preset threshold, update the strong storage page with the bit error rate greater than the preset threshold as a weak storage page and refresh the data.

[0083] S104: Determine the data refresh cycle of the strong storage page based on the storage page with the highest bit error rate among the strong storage pages, and refresh the data of the strong storage page according to the data refresh cycle of the strong storage page.

[0084] In this embodiment, the data refresh cycle of a weak storage page can be determined based on the storage page with the highest bit error rate among the weak storage pages, and the data of the weak storage page can be refreshed according to the data refresh cycle of the weak storage page.

[0085] In order to ensure the accuracy of the data refresh cycle of weak storage pages, the storage page with the highest error rate among the weak storage pages can be used as the standard, that is, the physical page with the shortest retention time. In other words, the refresh interval is determined according to the retention time supported by the weak storage page.

[0086] In one possible implementation, the data refresh cycle of a weak storage page can be equal to the first data retention time of the storage page with the highest bit error rate among the weak storage pages. The first data retention time is the time that the storage page with the highest bit error rate among the weak storage pages stores data before it exceeds the error correction capability of the error correction code.

[0087] For example, see Figure 8 As shown, Tweak is the Weak Page refresh cycle. Based on Tweak, the PPN102 storage page marked as weak is refreshed, and the state changes from Valid to Invalid accordingly.

[0088] Furthermore, in this embodiment of the application, in order to prevent strong storage pages from exceeding the ECC limit after multiple refresh cycles without being refreshed, the bit error rate of strong storage pages can be periodically detected to see if it is greater than a preset threshold. When the bit error rate of strong storage pages is greater than the preset threshold, the strong storage pages with bit error rates greater than the preset threshold are updated and marked as weak storage pages, and the data is refreshed, so as to dynamically modify the flash memory page marking during the periodic refresh process.

[0089] For example, see Figure 8As shown, Tcheck is a periodic process. When the bit error rate of the PPN103 storage page is detected to be greater than the preset threshold, the PPN103 can be marked as a weak storage page, the data can be refreshed, and the status can be changed from valid to invalid.

[0090] Similarly, the data refresh cycle of a strong storage page can be determined based on the storage page with the highest bit error rate among the strong storage pages, and the data of the strong storage page can be refreshed according to the data refresh cycle of the strong storage page.

[0091] In one possible implementation, the data refresh cycle of a strong storage page can be equal to the second data retention time of the storage page with the highest bit error rate among the strong storage pages. The second data retention time is the time that the storage page with the highest bit error rate among the strong storage pages stores data before it exceeds the error correction capability of the error correction code.

[0092] In this embodiment of the application, the storage page with the highest bit error rate is the storage page with the shortest data retention time. If refreshed at this frequency, the bit error rate of other storage pages with longer data retention times will not exceed the error correction limit of ECC.

[0093] For example, see Figure 8 As shown, Tstrong represents the data refresh cycle of the strong storage page. It can refresh the contents of the strong storage page in the storage block to complete the refresh of the entire storage block. That is, PPN100, 101, 104 and 105 can be refreshed, and their status changes from valid to invalid. Thus, a flash memory block completes the entire refresh process after undergoing two refreshes: one for the weak storage page and one for the strong storage page.

[0094] In one possible implementation, the data refresh cycle of weak storage pages can be set to be less than the periodic refresh cycle of strong storage pages. This means that storage pages with higher error rates can be refreshed more frequently, thus differentiating storage pages with different error rates, reducing the number of refreshes, and lowering system overhead.

[0095] It should be noted that the three-dimensional memory data refresh method provided in this application can be applied to any number of layers of 3D Charge Trap TLC NAND Flash, and this application does not impose any specific limitations on it.

[0096] This application provides a three-dimensional memory data refresh method, which includes: marking memory pages with a bit error rate (BER) greater than a preset threshold as weak memory pages, marking memory pages with a BER less than or equal to the preset threshold as strong memory pages, determining the data refresh cycle of weak memory pages based on the memory page with the highest BER among the weak memory pages, refreshing the weak memory pages according to the data refresh cycle, periodically detecting whether the BER of strong memory pages is greater than the preset threshold, and when the BER of strong memory pages is greater than the preset threshold, updating the marking of strong memory pages with BER greater than the preset threshold as weak memory pages and refreshing their data; determining the data refresh cycle of strong memory pages based on the memory page with the highest BER among the strong memory pages, and refreshing the strong memory pages according to the data refresh cycle. This method divides the data refresh of the same flash memory block into two parts: weak memory page data refresh and strong memory page data refresh, which can reduce the overall refresh frequency, reduce system overhead, and dynamically modify the marking of strong memory pages, preventing strong memory pages from exceeding the error correction code upper limit after multiple refresh cycles without being refreshed.

[0097] Exemplary apparatus

[0098] See Figure 9 The diagram shown is a schematic of a three-dimensional memory data refresh device provided in an embodiment of this application, comprising:

[0099] The weak storage page marking unit 201 is used to mark storage pages with a bit error rate greater than a preset threshold as weak storage pages;

[0100] The strong storage page marking unit 202 is used to mark storage pages with a bit error rate less than or equal to the preset threshold as strong storage pages;

[0101] The weak storage page data refresh unit 203 is used to determine the data refresh cycle of the weak storage page based on the storage page with the highest bit error rate among the weak storage pages, and to refresh the data of the weak storage page according to the data refresh cycle of the weak storage page;

[0102] The periodic detection unit 204 is used to periodically detect whether the bit error rate of the strong storage page is greater than the preset threshold. When the bit error rate of the strong storage page is greater than the preset threshold, the strong storage page with the bit error rate greater than the preset threshold is updated and marked as a weak storage page, and the data is refreshed.

[0103] The strong storage page data refresh unit 205 is used to determine the data refresh cycle of the strong storage page based on the storage page with the highest bit error rate among the strong storage pages, and to refresh the data of the strong storage page according to the data refresh cycle of the strong storage page.

[0104] In one possible implementation, the weak storage page data refresh unit is specifically used for:

[0105] The data refresh cycle of the weak storage page is equal to the first data retention time of the storage page with the highest bit error rate among the weak storage pages; the first data retention time is the time that the storage page with the highest bit error rate among the weak storage pages stores data before it exceeds the error correction code's error correction capability.

[0106] In one possible implementation, the strong storage page data refresh unit is specifically used for:

[0107] The data refresh cycle of the strong storage page is equal to the second data retention time of the storage page with the highest bit error rate among the strong storage pages; the second data retention time is the time that the storage page with the highest bit error rate among the strong storage pages stores data before it exceeds the error correction code's error correction capability.

[0108] In one possible implementation, the data refresh cycle of the weak storage page is less than the periodic refresh cycle of the strong storage page.

[0109] This application provides a three-dimensional memory data refresh device. The method using this device includes: marking memory pages with a bit error rate (BER) greater than a preset threshold as weak memory pages, marking memory pages with a BER less than or equal to the preset threshold as strong memory pages, determining the data refresh cycle of weak memory pages based on the memory page with the highest BER among the weak memory pages, refreshing the weak memory pages according to the data refresh cycle, periodically detecting whether the BER of strong memory pages is greater than the preset threshold, and when the BER of strong memory pages is greater than the preset threshold, updating the marking of strong memory pages with BER greater than the preset threshold as weak memory pages and refreshing their data; determining the data refresh cycle of strong memory pages based on the memory page with the highest BER among the strong memory pages, and refreshing the strong memory pages according to the data refresh cycle. This divides the data refresh of the same flash memory block into two parts: weak memory page data refresh and strong memory page data refresh, which can reduce the overall refresh frequency, reduce system overhead, and dynamically modify the marking of strong memory pages, preventing strong memory pages from exceeding the error correction code upper limit after multiple refresh cycles without being refreshed.

[0110] Based on the above embodiments, this application provides a three-dimensional memory data refresh system, including:

[0111] Memory, used to store computer programs;

[0112] A processor is configured to implement the steps of the three-dimensional memory data refresh method described above when executing the computer program.

[0113] Based on the above embodiments, this application also provides a computer-readable medium storing a computer program, which, when processed and executed, implements the steps of the three-dimensional memory data refresh method described above.

[0114] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0115] The aforementioned computer-readable medium may be included in the aforementioned system, or it may exist independently and not assembled into the system.

[0116] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts.

[0117] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0118] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A three-dimensional memory data refresh method, characterized in that, include: Memory pages with a bit error rate greater than a preset threshold are marked as weak memory pages; Memory pages with a bit error rate less than or equal to the preset threshold are marked as strong memory pages; The data refresh cycle of the weak storage page is determined based on the storage page with the highest bit error rate among the weak storage pages, and the data of the weak storage page is refreshed according to the data refresh cycle of the weak storage page; Specifically, the data refresh cycle of the weak storage page is equal to the first data retention time of the storage page with the highest bit error rate among the weak storage pages; The first data retention period is the duration for which the storage page with the highest bit error rate among the weak storage pages stores data before it exceeds the error correction capability of the error correction code. Periodically check whether the bit error rate of the strong storage page is greater than the preset threshold. When the bit error rate of the strong storage page is greater than the preset threshold, update the strong storage page with the bit error rate greater than the preset threshold as a weak storage page and refresh the data. The data refresh cycle of the strong storage page is determined based on the storage page with the highest bit error rate among the strong storage pages, and the data of the strong storage page is refreshed according to the data refresh cycle of the strong storage page; Specifically, the data refresh cycle of the strong storage page is equal to the second data retention time of the storage page with the highest error rate among the strong storage pages; The second data retention period is the duration for which the storage page with the highest bit error rate among the strong storage pages stores data before it exceeds the error correction code's error correction capability; the data refresh cycle of the weak storage page is less than the periodic refresh cycle of the strong storage page.

2. A three-dimensional memory data refresh device, characterized in that, include: The weak storage page marking unit is used to mark storage pages with a bit error rate greater than a preset threshold as weak storage pages; A strong storage page marking unit is used to mark storage pages with a bit error rate less than or equal to the preset threshold as strong storage pages; A weak storage page data refresh unit is used to determine the data refresh cycle of the weak storage page based on the storage page with the highest bit error rate among the weak storage pages, and to refresh the data of the weak storage page according to the data refresh cycle of the weak storage page; specifically, it is used to: set the data refresh cycle of the weak storage page to be equal to the first data retention time of the storage page with the highest bit error rate among the weak storage pages. The first data retention period is the duration for which the storage page with the highest bit error rate among the weak storage pages stores data before it exceeds the error correction capability of the error correction code. A periodic detection unit is used to periodically detect whether the bit error rate of the strong storage page is greater than the preset threshold. When the bit error rate of the strong storage page is greater than the preset threshold, the strong storage page with the bit error rate greater than the preset threshold is updated and marked as a weak storage page, and the data is refreshed. A strong storage page data refresh unit is used to determine the data refresh cycle of the strong storage page based on the storage page with the highest bit error rate among the strong storage pages, and to refresh the data of the strong storage page according to the data refresh cycle of the strong storage page; specifically, it is used to: set the data refresh cycle of the strong storage page to be equal to the second data retention time of the storage page with the highest bit error rate among the strong storage pages; the second data retention time is the duration for which the storage page with the highest bit error rate among the strong storage pages stores data before the error correction code exceeds the error correction capability of the storage page with the highest bit error rate; the data refresh cycle of the weak storage page < the periodic < the data refresh cycle of the strong storage page.

3. A three-dimensional memory data refresh system, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the three-dimensional memory data refresh method as described in claim 1 when executing the computer program.

4. A computer-readable medium, characterized in that, The computer-readable medium stores a computer program that, when processed and executed, implements the steps of the three-dimensional memory data refresh method as described in claim 1.

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