Integrated assembly and method of forming an integrated assembly

Abstract

The present disclosure relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include an integrated transistor having an active region comprising a semiconductor material. A conductive gate structure is adjacent to the active region. The conductive gate structure includes an inner region proximate to the active region, and includes an outer region distal from the active region. The inner region includes a first material comprising titanium and nitrogen, and the outer region includes a second material comprising a metal. The second material has a higher electrical conductivity than the first material. Some embodiments include an integrated assembly. Some embodiments include a method of forming an integrated assembly.

Description

Technical Field

[0001] Integrated assemblies (e.g., integrated memory). Methods for forming integrated assemblies. Background Technology

[0002] Transistors are used in a variety of semiconductor devices. A field-effect transistor (FET) has an active region that may be contained within a channel region between a pair of source / drain regions. An FET may include one or more gates configured to electrically connect the source / drain regions to each other through the channel region.

[0003] A vertical FET (VFET) has an active region that is generally perpendicular to the main surface of the substrate on which the transistor is formed.

[0004] Transistors can be incorporated into a memory array and used as access devices for memory cells in the memory array.

[0005] New methods for forming integrated transistors and integrated memories need to be developed. New transistor configurations and new assemblies utilizing these configurations (e.g., memory assemblies) also need to be developed.

[0006] Dynamic random access memory (DRAM) can utilize memory cells that individually include access transistors combined with capacitors.

[0007] Ferroelectric random access memory (FeRAM) can be configured similarly to DRAM, except that FeRAM utilizes ferroelectric capacitors instead of the non-ferroelectric capacitors of conventional DRAM. Ferroelectric capacitors can be understood as capacitors that utilize ferroelectric insulating material between conductive memory nodes within a capacitor configuration, while non-ferroelectric capacitors can be understood as capacitors that utilize only non-ferroelectric insulating material between conductive memory nodes within a capacitor configuration.

[0008] There is a need to develop improved memory architectures and improved methods for forming memory architectures. Summary of the Invention

[0009] In one aspect, this disclosure relates to an integrated transistor comprising: an active region comprising a semiconductor material; and a conductive gating structure operatively adjacent to the active region; the conductive gating structure comprising an inner region adjacent to the active region and an outer region distant from the active region; the inner region comprising a first material comprising titanium and nitrogen, and the outer region comprising a second material comprising a metal; the second material having a higher conductivity than the first material.

[0010] On the other hand, this disclosure relates to a memory array that includes an integrated transistor as one of many substantially identical access devices described in this application, wherein the access devices are coupled to memory elements.

[0011] In another aspect, this disclosure relates to a method of forming an integrated assembly, comprising: forming a configuration of semiconductor material pillars including a first linear structure and contained above the first linear structure; the first linear structure extending along a first direction; each of the pillars including an active region; a lower portion of the active region coupled to the first linear structure; forming an insulating material along a sidewall of the pillar; forming a template structure adjacent to the insulating material; the template structure including a template material and patterned to extend only along the center segment of the pillar rather than along the entire vertical length of the pillar; the template structure configured as a second linear structure extending along a second direction intersecting the first direction; selectively forming a conductive material on the template material relative to any other exposed material of the configuration; the conductive material being more conductive than the template material; and forming a memory element coupled to an upper portion of the active region.

[0012] In another aspect, this disclosure relates to a method of forming an integrated assembly, comprising: forming a configuration including a first linear structure and a semiconductor material pillar contained above the first linear structure; the first linear structure extending along a first direction; each of the pillars including an active region; a lower portion of the active region coupled to the first linear structure; the pillar having a top surface and sidewall surfaces extending downward from the top surface; forming an insulating material along the sidewall surfaces and the top surface; forming a template structure adjacent to the insulating material; the template structure being patterned to extend only along the center segment of the pillar rather than along the entire vertical length of the pillar; the template structure being configured to extend along a second direction. A second linear structure extending in the direction; the second direction intersects the first direction; after forming the template structure, the structure has a first exposed surface corresponding to the surface of the template structure and a second exposed surface corresponding to the surface of the insulating material; the second exposed surface is modified to prevent the formation of conductive material along the second exposed surface and / or the first exposed surface is modified to promote the formation of the conductive material along the first exposed surface; after the modification of the second exposed surface and / or the modification of the first exposed surface, the conductive material is selectively formed along the first exposed surface relative to the second exposed surface; and a memory element coupled to the upper portion of the active region is formed. Attached Figure Description

[0013] Figures 1 to 5 This is a schematic cross-sectional side view of the area of ​​the instance integration assembly at the instance sequential processing stage of the instance method.

[0014] Figures 6 to 9 This is a schematic cross-sectional side view of the area of ​​the instance integration assembly at the instance sequential processing stage of another instance method. Figure 6 The process stages can be followed Figure 3 The process stages.

[0015] Figure 10 This is a schematic diagram of a region in an instance memory array. Detailed Implementation

[0016] Some embodiments include methods of forming transistors, wherein a template material is used to pattern a highly conductive metallic material. The template material may, for example, include titanium nitride, be primarily composed of titanium nitride, or be composed of titanium nitride. Titanium nitride may be represented as TiN, where the chemical formula indicates the major component rather than a specific stoichiometry. The term "highly conductive" means more conductive than the template material, and in some embodiments means more conductive than TiN. The highly conductive metallic material may include one or more of, for example, ruthenium (Ru), molybdenum (Mo), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), tantalum (Ta), cobalt (Co), rhodium (Rh), nickel (Ni), conductive metal nitrides (e.g., TaN; where the chemical formula indicates the major component rather than a specific stoichiometry), etc. The patterned highly conductive metallic material can be used to form a conductive gating structure for the transistor. The transistor may be incorporated into an integrated memory, and the conductive gating structure may be incorporated into the word lines of such memory.

[0017] Some embodiments include transistors having a conductive gating material comprising TiN combined with one or more highly conductive metallic materials. Some embodiments include integrated assemblies (e.g., integrated memory) including such transistors.

[0018] refer to Figures 1 to 10 Describe an example implementation.

[0019] refer to Figure 1 The construction (integration assemblies, integration architecture, etc.) is shown at the instance process stage of the instance method.

[0020] Construction 10 includes a linear conductive structure 14 above the insulating material 16. The linear structure can be, for example, a digital line (bit line, sensing line, etc.) and can be represented in... Figure 1 Numerous digital lines are formed at the processing stage. The linear structure 14 extends in a first horizontal direction (the illustrated y-axis direction). Structure 14 includes a conductive material 18. The conductive material 18 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0021] The insulating material 16 may include any suitable composition, such as one or more of silicon dioxide, silicon nitride, etc.

[0022] Semiconductor material 12 is placed above the linear conductive structure 14 and patterned into a series of pillars 20. The pillars 20 extend in a vertical direction (the illustrated z-axis direction). Although the pillars 20 are shown extending orthogonally to the horizontal direction relative to the linear structure 14, in other embodiments, the pillars 20 may extend substantially vertically without being precisely orthogonal to the horizontal direction relative to the linear structure 14. For example, the pillars may extend in a vertical direction within ±10° of being precisely orthogonal to the horizontal direction relative to the linear structure 14.

[0023] Semiconductor material 12 may comprise any suitable composition, and in some embodiments may comprise one or more of the following, either primarily or entirely: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides (e.g., materials comprising indium, gallium, zinc, and oxygen), etc. It should be understood that the term III / V semiconductor material refers to semiconductor materials comprising elements selected from Group III and Group V of the periodic table (where Group III and Group V are older nomenclature and are now referred to as Group 13 and Group 15).

[0024] The pillar 20 may include an active region 22 (only one of which is labeled). In some embodiments (e.g., in embodiments where the semiconductor material 12 comprises silicon), such an active region may include a channel region vertically sandwiched between a conductive-doped upper source / drain region and a conductive-doped lower source / drain region, or may include any other suitable configuration. The lower portion of the active region is electrically coupled to the linear structure 14.

[0025] The insulating material 24 is formed to extend along the semiconductor material 12. In the illustrated embodiment, the insulating material 24 extends along the sidewall 21 of the pillar 20 and along the upper surface 23 of the pillar.

[0026] The insulating material 24 may correspond to the gate dielectric material and may include any suitable composition. For example, the insulating material 24 may include one or more of the following, or be mainly composed of or composed of: silicon dioxide, hafnium oxide, zirconium oxide, tantalum oxide, aluminum oxide, etc.

[0027] An insulating step 26 is formed along the bottom region of the pillar 20. The insulating step can be used to calibrate the height of the bottom surface of the transistor gate in subsequent processing. The insulating step includes an insulating material 28. The insulating material 28 may or may not include the same composition as the gate dielectric material 24. In some exemplary embodiments, both the insulating material 28 and the gate dielectric material 24 may include silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide.

[0028] refer to Figure 2 The template material layer 30 is deposited to extend across the step 26, along the sidewall 21 of the pillar, and above the top 23 of the pillar. The template material 30 may comprise titanium and nitrogen, be primarily composed of titanium and nitrogen, or be composed of titanium and nitrogen, and may be referred to as titanium nitride. In some embodiments, the template material may be referred to as including TiN, where the chemical formula indicates the major component rather than a specific stoichiometry. In the illustrated embodiment, the template material 30 is deposited above and directly abuts the insulating material (gate dielectric material) 24.

[0029] The advantage of using titanium nitride as template material 30 is that this material can be easily deposited and patterned. A disadvantage of titanium nitride in highly integrated circuits is that its conductivity may be too low for applications where it is extremely thin (e.g., less than or equal to about 15 nanometers (nm), and in some applications less than or equal to about 10 nm). Therefore, the embodiments described herein utilize the patternability of titanium nitride by selectively depositing a more highly conductive material using it as a template.

[0030] refer to Figure 3 The template material 30 is etched using, for example, dry etching conditions. This removes the template material from above the top 23 of the pillar 20 and from above the step 26, while leaving a portion of the template material 30 along the sidewall 21 of the pillar 20.

[0031] In the illustrated embodiment, spacer 26 blocks template material 30 along the bottom region of pillar 20, and etching causes the template material to be recessed from the upper region of the pillar, so that the remaining template material 30 is segmented only along the center of pillar 20 rather than along the entire vertical length of the pillar.

[0032] Etching of the template material 30 patterns the material into a template structure 32. In the illustrated embodiment, the template structure is adjacent to the insulating material (gate dielectric material) 24. The template structure 32 may be relative to... Figure 3 The cross-sectional view extends into and out of the page (i.e., along the horizontal x-axis direction orthogonal to the described horizontal y-axis direction). Figure 3 (Extended, not shown in the diagram). The template structure can be considered as a template for a second linear structure extending along a second direction intersecting the first direction of the first linear structure 14. This second direction may be orthogonal to the first direction (i.e., the second direction may be along the x-axis direction orthogonal to the described y-axis direction of the linear structure 14), or not orthogonal.

[0033] The template structure 32 can be formed to be extremely thin, and in some embodiments may have a lateral thickness T of less than or equal to about 2 nm.

[0034] refer to Figure 4Conductive metallic material 34 is selectively formed on template material 30 relative to insulating materials 28 and 24. Materials 30 and 34 may be referred to as first and second conductive materials, respectively. Conductive material 34 differs in composition from template material 30. It may be necessary for conductive material 34 to have a higher conductivity than template material 30. This enables conductive material 34 to be used in highly integrated applications because conductive material 34 can still conduct electricity sufficiently even when formed extremely thin (e.g., less than or equal to about 15 nm, less than or equal to about 12 nm, less than or equal to about 10 nm, etc.). In some embodiments, conductive material 34 may have a lateral thickness T1 of less than or equal to about 50 nm, less than or equal to about 12 nm, less than or equal to about 10 nm, less than or equal to about 5 nm, etc.; and may, for example, have a lateral thickness T1 in the range of about 2 nm to about 15 nm.

[0035] In some embodiments, where the conductive material 34 is to be oxidized, the conductive material 34 may also be more oxidation-resistant than the template material 30 and / or may have higher conductivity than the template material 30.

[0036] The conductive material 34 and the template material 30 can be considered together to form a conductive gating structure 36. This gating structure includes an inner region 38 corresponding to the template structure 32 and an outer region 40 corresponding to the conductive material 34. The inner region 38 can be considered relatively close to the active region 22 of the pillar 20, and the outer region 40 can be considered relatively far from such an active region. The gating structure can be considered as a second linear structure extending along a second direction intersecting a first direction of the first linear structure 14 (wherein this second direction is relative to...). Figure 4 (Cross-section view on page).

[0037] The metallic material 34 may include one or more of Ru, Mo, Cu, Pt, Pd, W, Ta, Co, Rh and Ni; and in some embodiments may include one or more metal nitrides (e.g., TaN, where the chemical formula indicates the main component rather than a specific stoichiometry), one or more metal oxides (e.g., RuO, where the chemical formula indicates the main component rather than a specific stoichiometry), etc.

[0038] The conductive material 34 can be selectively formed on the template material 30 by any suitable method. In some embodiments, the conductive material 34 can be selectively formed on the template material 30 using atomic layer deposition (ALD). The conductive material 34 is a metal-containing material (e.g., including a metal), and the ALD can utilize the metal including the conductive material 34 and one or more precursors selected from carbon, nitrogen, halogens, and oxygen. For example, the precursor can be a metal-organic compound. In a particular application, the metal containing the metal material 34 can be ruthenium, and the precursor can be bis(ethylcyclopentadienyl)ruthenium. As another example, the precursor can be a metal halide, which includes the metal containing the metal material 34 and one or more selected from chlorine, fluorine, and bromine.

[0039] The gating structure 36 can be considered as operatively approaching the active region 22 of the pillar 20 such that a sufficient voltage applied to the gating structure will induce an electric field that causes current to flow vertically through the vertically extending active region. If the voltage to the gating structure is below a threshold level, no current will flow through the active region. In some embodiments, the gating structure 36 may correspond to a... Figure 4 The cross-sectional view extends into and out of the page's word lines, and selective control of the current flowing through the active area can be achieved by turning selected word lines on or off.

[0040] refer to Figure 5 The insulating material 24 is removed from above the upper surface of the pillar 20, and a conductive cap 42 is formed directly against the semiconductor material 12 of the pillar 20. The conductive cap 42 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0041] Insulating material 44 is formed between the supports 20. The insulating material 44 may include any suitable composition, and in some embodiments may include one or more of the following, or be mainly composed of or composed of: silicon dioxide, silicon nitride, etc.

[0042] The active region 22 and the gate structure 36 together form an integrated transistor 46. This transistor can be an access device within the memory array 50 and can be coupled to a storage element 48. The storage element can be any suitable device having at least two detectable states; and in some embodiments, it can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase-change memory (PCM) device, a programmable metallization cell (PMC), etc. If the storage element is a capacitor, it can be a ferroelectric capacitor or a non-ferroelectric capacitor.

[0043] The access device 46 and the storage element 48 together form the memory cell 52 of the memory array 50. The described memory cell 52 may represent a large number of memory cells formed within the memory array 50. For example, in some embodiments, the memory array may have thousands, hundreds of thousands, millions, hundreds of millions, etc. of memory cells.

[0044] In the illustrated embodiment, the stepped structure 26 is removed from the memory array 50. Figure 4 In other embodiments, the stepped structure 26 may be retained within the memory array.

[0045] Figure 5 The configuration can be viewed as corresponding to a region of an integrated assembly including a memory array. In other embodiments, similar integrated assemblies can be formed through other processes. (See reference...) Figures 6 to 9 Examples of other embodiments of this kind are described.

[0046] Figure 6 Shown in followable Figure 3 Assembly 10 at the process stage. Return to reference. Figure 3 The described configuration can be considered as having a first exposed surface 53 corresponding to the surface of the template structure 32, a second exposed surface 55 corresponding to the surface of the insulating material 24, and a third exposed surface 57 corresponding to the surface of the insulating material 28 of the stepped structure 26. In some embodiments, the insulating materials 24 and 28 may comprise the same composition as each other (e.g., both may comprise silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide), and therefore the second surface 55 and the third surface 57 may comprise the same composition as each other.

[0047] The first exposed surface 53 is modified (e.g., the surface of the template structure 32). This is illustrated by the color variations of the structure (e.g., from...). Figure 3 The crosshairs become Figure 6 The modification is illustrated by the variation (indicated by a pure dark color) throughout the structure 32. The modification of surface 53 may be primarily along the surface of structure 32, or it may extend throughout structure 32.

[0048] In some embodiments, the modification of surface 53 can be achieved by exposing structure 10 to a reducing agent. The reducing agent may, for example, comprise a synthesis gas (i.e., a mixture of H2 and N2). The modified surface 53 of template structure 32 can facilitate modification in subsequent process stages (see below). Figure 8 A conductive material is formed along surface 53 at the location described.

[0049] refer to Figure 7The modification of the second exposed surface 55 and the third exposed surface 57 is illustrated by forming material 56 over surfaces 55 and 57. Modification of surfaces 55 and 57 may include exposing the silica of such surfaces to a silane (e.g., dimethylaminotrimethylsilane). Such modification can prevent [further damage] in subsequent process stages (see below). Figure 8 Conductive material is formed along surfaces 55 and 57 at the location described.

[0050] refer to Figure 8 This illustrates a conductive metal-containing material 34 selectively deposited along the modified surface 53 relative to modified surfaces 55 and 57. In some embodiments, the deposition of the conductive material 34 may utilize one or both of atomic layer deposition and chemical vapor deposition, and may utilize a metal comprising the conductive material 34 and one or more precursors selected from carbon, nitrogen, halogens, and oxygen. Such precursors may be, for example, organometallic compounds, and in some embodiments may include one or more carbonyl moieties. For example, in some exemplary embodiments, the metal of the conductive material 34 may be ruthenium, and is used in... Figure 8 The precursor that forms the conductive material 34 at the process stage may include ruthenium and one or more carbonyl groups.

[0051] although Figures 6 to 8 The embodiments illustrate treating the surface of such a template structure by a process that promotes the formation of conductive material 34 along the surface of the template structure 32, and treating the surface of such insulating materials by a process that prevents the formation of conductive material 34 along the surfaces of insulating materials 24 and 28. However, it should be understood that in other embodiments, only one of these processes may be utilized. In other words, they may be used together or alternately with respect to each other. Figure 6 and 7 The treatment (i.e., the surface of the modified template structure 32) Figure 6 ) and the surfaces of modified insulating materials 24 and 28 ( Figure 7 In any case, conductive material 34 is selectively formed on template structure 32 rather than on insulating materials 24 and 28.

[0052] The conductive material 34 and the template structure 32 together form a structure similar to the one described above. Figure 4 The gated structures described are 36.

[0053] refer to Figure 9 Construction 10 undergoes similar conditions to those described in the reference above. Figure 5 The described process is used to form a memory array 50 including memory cells 52.

[0054] Figure 5 and 9 The memory array 50 can have any suitable configuration. Figure 10An example configuration in which the storage element 48 is a capacitor is shown. The capacitor may be a nonferroelectric capacitor, and therefore the memory array 50 may be a dynamic random access memory (DRAM) array. Alternatively, the capacitor may be a ferroelectric capacitor, and therefore the memory array 50 may be a ferroelectric random access memory (FeRAM) array.

[0055] The capacitor 48 described has an electrical node coupled to the access transistor 46 and another electrical node coupled to a reference 60. The reference 60 may correspond to any suitable reference voltage, including ground, VCC / 2, etc.

[0056] Word line 36 is shown extending along the x-axis and coupled to word line driver circuitry 70. Digital line 14 is shown extending along the y-axis and coupled to sense amplifier circuitry 72. Access transistor 46 and memory element 48 together form memory cell 52, wherein each memory cell is uniquely addressed by a combination of one of the digital lines 14 and one of the word lines 36.

[0057] In some embodiments, the relatively simple patterning of a highly conductive thin linear structure (word line) 36 achieved using the process described herein can be implemented at a lower cost compared to similar patterning achieved using conventional processes.

[0058] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0059] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0060] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others is used within this disclosure to provide linguistic variation to simplify the premises of the following claims, and not to indicate any significant chemical or electrical differences.

[0061] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the following claims.

[0062] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in the specific orientation of the figures or rotated relative to such an orientation.

[0063] Unless otherwise indicated, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the drawings.

[0064] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0065] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend generally orthogonally relative to the upper surface of the substrate.

[0066] Some embodiments include an integrated transistor having an active region comprising a semiconductor material. A conductive gating structure is operatively located close to the active region. The conductive gating structure includes an inner region close to the active region and an outer region distant from the active region. The inner region comprises a first material containing titanium and nitrogen, and the outer region comprises a second material containing a metal. The second material has a higher conductivity than the first material.

[0067] Some embodiments include a method of forming an integrated assembly. A configuration is formed including a first linear structure and a semiconductor material pillar comprising a first linear structure above the first linear structure. The first linear structure extends along a first direction. Each of the pillars includes an active region. A lower portion of the active region is coupled to the first linear structure. An insulating material is formed along the sidewalls of the pillar. A template structure is formed adjacent to the insulating material. The template structure includes a template material and is patterned to extend only along the center segment of the pillar, rather than along the entire vertical length of the pillar. The template structure is configured as a second linear structure extending along a second direction intersecting the first direction. A conductive material is selectively formed on the template material relative to any other exposed material of the configuration. The conductive material is more conductive than the template material. A memory element is formed to be coupled to the upper portion of the active region.

[0068] Some embodiments include a method of forming an integrated assembly. A semiconductor material pillar is constructed to include a first linear structure and is located above the first linear structure. The first linear structure extends along a first direction. Each pillar includes an active region. The lower portion of the active region is coupled to the first linear structure. The pillar has a top surface and sidewall surfaces extending downward from the top surface. An insulating material is formed along the sidewall surfaces and along the top surface. A template structure is formed adjacent to the insulating material. The template structure is patterned to extend only along the center segment of the pillar, rather than along the entire vertical length of the pillar. The template structure is configured as a second linear structure extending along a second direction. The second direction intersects the first direction. After forming the template structure, a first exposed surface having a surface corresponding to the template structure and a second exposed surface having a surface corresponding to the insulating material are constructed. The second exposed surface is modified to prevent the formation of conductive material along the second exposed surface and / or the first exposed surface is modified to promote the formation of conductive material along the first exposed surface. After the modification of the second exposed surface and / or the modification of the first exposed surface, conductive material is selectively formed along the first exposed surface relative to the second exposed surface. The storage element is formed to be coupled to the upper portion of the active region.

[0069] As per the provisions, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated transistor comprising: An active region pillar is located on a substrate, the active region pillar comprising a semiconductor material having opposing sidewalls; An insulating material that covers the entire surface of the opposite sidewalls of the active area pillar and extends over the substrate adjacent to the active area pillar; An insulating step-like structure extending along the insulating material and close to the bottom of the active region support; as well as A conductive gated structure, operatively close to the active region and spaced apart from the substrate by the insulating material and the insulating steps; The conductive gating structure includes an inner region close to the active region and an outer region away from the active region; the inner region includes a first material comprising titanium and nitrogen, and the outer region includes a second material containing metal. The second material has higher conductivity than the first material, and the second material is present along the entire outer surface of the inner region and at least a portion of the upper surface of the inner region.

2. The integrated transistor of claim 1, wherein the internal region has a thickness of less than or equal to 2 nm.

3. The integrated transistor of claim 1, wherein the outer region has a thickness in the range of 2 nm to 15 nm.

4. The integrated transistor of claim 1, wherein the second material comprises one or more of Ru, Mo, Cu, Pt, Pd, W, Ta, Co, Rh and Ni.

5. The integrated transistor of claim 1, wherein the second material comprises one or more metal nitrides.

6. The integrated transistor of claim 5, wherein the second material comprises TaN, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

7. The integrated transistor of claim 1, wherein the second material comprises one or more metal oxides.

8. A memory array comprising an integrated transistor according to claim 1 as one of a plurality of substantially identical access devices, wherein the access device is coupled to a memory element.

9. The memory array of claim 8, wherein the memory element comprises a capacitor.

10. The memory array of claim 9, wherein the capacitor is a ferroelectric capacitor.

11. The memory array of claim 9, wherein the capacitor is a nonferroelectric capacitor.

12. A method of forming an integrated assembly, comprising: A structure is formed that includes a first linear structure and a semiconductor material pillar contained above the first linear structure; The first linear structure extends along a first direction; Each of the pillars includes an active region; the lower portion of the active region is coupled to the first linear structure; An insulating material is formed along the sidewall of the support column; A template structure is formed adjacent to the insulating material; the template structure includes template material and is patterned to extend only along the center segment of the pillar rather than along the entire vertical length of the pillar; the template structure is configured as a second linear structure extending along a second direction intersecting the first direction; A conductive material is selectively formed on the template material relative to any other exposed material of the aforementioned structure; The conductive material is more conductive than the template material, and the conductive material is present along the entire outer surface of the template structure and at least a portion of the upper surface of the template structure; as well as A storage element is formed that is coupled to the upper portion of the active region.

13. The method of claim 12, wherein the conductive material comprises one or more of Ru, Mo, Cu, Pt, Pd, W, Ta, Co, Rh and Ni.

14. The method of claim 12, wherein the template material comprises titanium and nitrogen.

15. The method of claim 12, wherein the selective formation of the conductive material utilizes atomic layer deposition.

16. The method of claim 15, wherein the conductive material comprises a metal, and wherein the atomic layer deposition utilizes a precursor comprising the metal and one or more of carbon, nitrogen, halogens and oxygen.

17. The method of claim 16, wherein the precursor is a metal-organic compound.

18. The method of claim 17, wherein the metal is Ru, and wherein the precursor is bis(ethylcyclopentadienyl)ruthenium.

19. The method of claim 16, wherein the precursor is a metal halide and includes the metal and one or more of chlorine, fluorine and bromine.

20. The method of claim 12, further comprising forming an insulating step along the bottom region of the pillar prior to forming the template structure, wherein the formation of the template structure comprises: The template material is deposited in layers that extend across the steps, along the sidewalls, and above the top of the pillar; as well as The layers of the template material are etched to remove areas of the layer from above the top of the pillar and from above the step, thereby patterning the layers into the template structure.

21. The method of claim 20, wherein the template structure has a lateral thickness of less than or equal to 2 nm.

22. A method of forming an integrated assembly, comprising: A structure comprising a first linear structure and a semiconductor material pillar contained above the first linear structure is formed; The first linear structure extends along a first direction; Each of the pillars includes an active region; the lower portion of the active region is coupled to the first linear structure; The support has a top surface and sidewall surfaces extending downward from the top surface; An insulating material is formed along the sidewall surface and the top surface; A template structure is formed adjacent to the insulating material; the template structure is patterned to extend only along the center segment of the pillar rather than along the entire vertical length of the pillar; the template structure is configured as a second linear structure extending along a second direction; the second direction intersects the first direction; After the template structure is formed, the structure has a first exposed surface corresponding to the surface of the template structure and a second exposed surface corresponding to the surface of the insulating material; Modify the second exposed surface to prevent the formation of conductive material along the second exposed surface and / or modify the first exposed surface to promote the formation of the conductive material along the first exposed surface; Following the modification of the second exposed surface and / or the modification of the first exposed surface, the conductive material is selectively formed along the first exposed surface relative to the second exposed surface; as well as A storage element is formed coupled to the upper portion of the active region, wherein the conductive material is present along the entire outer surface of the template structure and at least a portion of the upper surface of the template structure.

23. The method of claim 22, wherein the modification comprises modifying the first exposed surface using a reducing agent.

24. The method of claim 22, wherein the second exposed surface comprises silicon dioxide, and wherein the modification comprises modifying the second exposed surface with a silane.

25. The method of claim 24, further comprising forming an insulating step along the bottom region of the pillar prior to forming the template structure; wherein the formation of the template structure comprises depositing a template material layer across the step and extending along the sidewall, and etching the layer of the template material to remove a region of the layer from above the step; wherein a third exposed surface is constructed having a surface corresponding to the step; and wherein the third exposed surface comprises silica and is modified by the silane during the modification of the second exposed surface.

26. The method of claim 22, wherein the modification comprises both the modification of the second exposed surface and the modification of the first exposed surface.

27. The method of claim 22, wherein the modification comprises only the modification of the first exposed surface.

28. The method of claim 22, wherein the modification comprises only the modification of the second exposed surface.

29. The method of claim 22, wherein the conductive material comprises one or more of Ru, Mo, Cu, Pt, Pd, W, Ta, Co, Rh and Ni.

30. The method of claim 22, wherein the template structure comprises titanium and nitrogen.

31. The method of claim 22, wherein the selective formation of the conductive material utilizes one or both of atomic layer deposition and chemical vapor deposition.

32. The method of claim 31, wherein the conductive material comprises a metal, and wherein the deposition utilizes a precursor comprising the metal and one or more of carbon, nitrogen, halogens and oxygen.

33. The method according to claim 32, wherein the precursor is a metal-organic compound.

34. The method of claim 33, wherein the metal is Ru, and wherein the precursor comprises one or more carbonyl moieties.

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