Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the thickness of a first floating gate structure formed is greater than or equal to the sum of the thickness of a second floating gate structure, a gate dielectric layer subsequently formed on the second floating gate structure, and a first control gate layer located on the gate dielectric layer, so that a chemical mechanical polishing process can be performed on the first control gate material layer and the gate dielectric material layer with the top surface of the first floating gate structure as a stop position to expose the top surface of the first floating gate structure, so that the second control gate material layer subsequently formed can contact the first floating gate structure, and damage to the first floating gate structure caused by the penetration of plasma ions used in the plasma etching process into the first floating gate structure during the process of using a plasma etching process to form an opening to expose the first floating gate structure can be avoided, thereby improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of semiconductor process technology, flash memory with faster access speed has been developed in storage devices. Flash memory is also called flash memory. The main feature of flash memory is that it can retain stored information for a long time without power supply. It has the advantages of high integration, fast access speed, easy erasing and reading and writing, so it has become the mainstream memory of non-volatile memory (NVM).

[0003] The main feature of flash memory is that it can keep the stored information for a long time without power supply, and it has the advantages of high integration, fast access speed, easy erasure and rewrite, etc., so it has been widely used in many fields such as microcomputers and automatic control. According to different structures, flash memory can be divided into two types: Nor Flash and NAND Flash. NAND flash memory devices have advantages such as high cell density, high storage density, fast writing and erasing speed, etc., and have gradually become a more commonly used structure in flash memory. At present, they are mainly used in flash memory cards and MP3 players of digital cameras. Among them, an existing NAND flash memory device uses gaps as air side walls. Compared with the side wall material, the dielectric constant of air is smaller, so the setting of air side walls can reduce the capacitance between adjacent word lines in the NAND flash memory device, thereby improving the crosstalk problem of the NAND flash memory device during the programming process and the repeated reading and writing ability of the NAND flash memory device.

[0004] However, the performance of current NAND flash memory devices still needs to be improved. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of a NAND flash memory device.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, the method comprising:

[0007] A substrate is provided, the substrate comprising a peripheral region and a storage region; the peripheral region has a plurality of discrete first floating gate structures, the storage region has a plurality of discrete second floating gate structures, the thickness of the first floating gate structure is greater than or equal to the sum of the thickness of the second floating gate structure, a gate dielectric layer subsequently formed on the second floating gate structure, and a first control gate layer located on the gate dielectric layer;

[0008] forming a gate dielectric material layer conformally covering the first floating gate structure, the second floating gate structure, and the exposed portions of the first floating gate structure and the second floating gate structure;

[0009] forming a first control gate material layer covering the gate dielectric material layer;

[0010] Taking the top surface of the first floating gate structure as a stop position, performing a chemical mechanical polishing process on the first control gate material layer and the gate dielectric material layer, so that the first control gate material layer and the gate dielectric material layer form the first control gate layer and the gate dielectric layer respectively;

[0011] After performing the chemical mechanical polishing process, a second control gate material layer covering the first control gate layer, the gate dielectric layer and the first floating gate structure is formed.

[0012] Optionally, after forming the second control gate material layer, the method further includes:

[0013] forming a patterned mask layer on the second control gate material layer;

[0014] The second control gate material layer, the first control gate layer and the gate dielectric layer are sequentially etched using the patterned mask layer as a mask to form a first control gate structure located on the first floating gate structure, and a second gate dielectric layer located on the second floating gate structure, a first control gate located on the second gate dielectric layer and a second control gate located on the first control gate are formed, wherein the first control gate and the second control constitute a second control gate structure.

[0015] Optionally, the substrate has an isolation structure; after the gate dielectric material layer is formed, the gate dielectric material layer also covers the isolation structure exposed by the first floating gate structure and the second floating gate structure.

[0016] Optionally, the first floating gate structure includes a first gate insulating layer located on the substrate and a first floating gate layer located on the first gate insulating layer; the second floating gate structure includes a second gate insulating layer located on the substrate and a second floating gate layer located on the second gate insulating layer.

[0017] Optionally, the thickness of the first floating gate layer is 800-1000 angstroms, the thickness of the second floating gate layer is 1000-1600 angstroms, the thickness of the gate dielectric material layer is 100-200 angstroms, and the thickness of the first control gate layer is 200-400 angstroms.

[0018] Optionally, the material of the first floating gate layer is polysilicon.

[0019] Optionally, the material of the second floating gate layer is polysilicon.

[0020] Optionally, the material of the first gate insulating layer is silicon oxide.

[0021] Optionally, the second gate insulating layer is made of silicon oxide.

[0022] Optionally, the gate dielectric material layer is an ONO structure.

[0023] Optionally, the material of the first control gate material layer is ONO polysilicon.

[0024] Optionally, the second control gate material layer is made of polysilicon.

[0025] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0026] a substrate, the substrate comprising a storage area and a peripheral area;

[0027] a plurality of discrete first floating gate structures located on the storage area and a plurality of discrete second floating gate structures located on the peripheral area; the thickness of the second floating gate structure is greater than or equal to the sum of the thickness of the first floating gate structure, a gate dielectric layer subsequently formed on the first floating gate structure, and a first control gate layer located on the gate dielectric layer;

[0028] A gate dielectric layer located on the sidewalls of the first floating gate structure, the top and sidewalls of the second floating gate structure, and the substrate where the first floating gate structure and the second floating gate structure are exposed;

[0029] A first control gate layer located on the gate dielectric layer;

[0030] A second control gate material layer is located on the first control gate layer, the gate dielectric layer and the first floating gate structure.

[0031] Optionally, the first floating gate structure includes a first gate insulating layer located on the substrate and a first floating gate layer located on the first gate insulating layer; the second floating gate structure includes a second gate insulating layer located on the substrate and a second floating gate layer located on the second gate insulating layer.

[0032] Optionally, the substrate further includes an isolation structure; and the gate dielectric material layer is located on the isolation structure where the first floating gate structure and the second floating gate structure are exposed.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] A method for forming a semiconductor structure in an embodiment of the present invention comprises: providing a substrate, the substrate comprising a peripheral region and a storage region; the peripheral region having a plurality of discrete first floating gate structures, the storage region having a plurality of discrete second floating gate structures, the thickness of the first floating gate structure being greater than the sum of the thickness of the second floating gate structure, a gate dielectric layer subsequently formed on the second floating gate structure, and a first control gate layer located on the gate dielectric layer; forming the gate dielectric material layer conformally covering the first floating gate structure, the second floating gate structure, and the exposed portions of the first floating gate structure and the second floating gate structure; forming a first control gate material layer covering the gate dielectric material layer; taking the top surface of the first floating gate structure as a stop position, performing a chemical mechanical polishing process on the first control gate material layer and the gate dielectric material layer so that the first control gate material layer and the gate dielectric material layer form the first control gate layer and the gate dielectric layer respectively; after performing the chemical mechanical polishing process, forming a second control gate material layer covering the first control gate layer, the gate dielectric layer, and the first floating gate structure. Among them, the thickness of the first floating gate structure is greater than or equal to the sum of the thickness of the second floating gate structure and the gate dielectric layer subsequently formed on the second floating gate structure and the first control gate layer located on the gate dielectric layer. Therefore, a chemical mechanical polishing process can be performed on the first control gate material layer and the gate dielectric material layer with the top surface of the first floating gate structure as the stop position, so that the second control gate material layer formed subsequently can contact the first floating gate structure, and damage caused by the plasma ions used in the plasma etching process penetrating into the first floating gate structure during the process of using the plasma etching process to form an opening to expose the first floating gate structure can be avoided, thereby improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 5 A schematic diagram of an intermediate structure formed in each step of a method for forming a semiconductor structure;

[0036] Figures 6 to 10 It is a schematic diagram of an intermediate structure formed in each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As can be seen from the background technology, the performance of existing NAND flash memory devices needs to be improved.

[0038] The reasons why the performance of existing NAND flash memory devices needs to be improved will be analyzed below in conjunction with a method for forming a semiconductor structure.

[0039] See also Figure 1A substrate 10 is provided, wherein the substrate 10 includes a peripheral region I and a storage region II; the peripheral region I has a plurality of discrete first floating gate structures 11, and the storage region II has a plurality of discrete second floating gate structures 14. The first floating gate structure 11 includes a first gate insulating layer 12 located on the substrate 10 and a first floating gate layer 13 located on the first gate insulating layer 12, and the second floating gate structure 14 includes a second gate insulating layer 15 located on the substrate 10 and a second floating gate layer 16 located on the second gate insulating layer 15.

[0040] See also Figure 2 , forming a gate dielectric material layer 17 that conformally covers the first floating gate structure 11 , the second floating gate structure 14 , and the exposed portions of the substrate 10 of the first floating gate structure 11 and the second floating gate structure 14 .

[0041] See also Figure 3 , forming a first control gate material layer 18 covering the gate dielectric material layer 17 .

[0042] See also Figure 4 , the first control gate material layer 18 , the gate dielectric material layer and the second floating gate structure 14 are etched to form an opening 19 exposing the second floating gate structure 14 .

[0043] See also Figure 5 After forming the opening 19 , a second control gate material layer 20 is formed to cover the first control gate material layer 18 , and the second control gate material layer 20 also fills the opening 19 .

[0044] In the above-mentioned method for forming a semiconductor structure, the process of etching the first control gate material layer 18, the gate dielectric material layer and the second floating gate structure 14 is a plasma etching process. During the execution of the plasma etching process, the plasma ions used in the plasma etching process will penetrate into the first floating gate structure 14, causing damage to the first gate insulation layer 15 in the first floating gate structure 14, thereby affecting the performance of the formed NAND device.

[0045] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a peripheral area and a storage area; the peripheral area having a plurality of discrete first floating gate structures, the storage area having a plurality of discrete second floating gate structures, the thickness of the first floating gate structure being greater than or equal to the sum of the thickness of the second floating gate structure, a gate dielectric layer subsequently formed on the second floating gate structure, and a first control gate layer located on the gate dielectric layer; forming the gate dielectric material layer conformally covering the first floating gate structure, the second floating gate structure, and the exposed portions of the first floating gate structure and the second floating gate structure; forming a first control gate material layer covering the gate dielectric material layer; taking the top surface of the first floating gate structure as a stop position, performing a chemical mechanical polishing process on the first control gate material layer and the gate dielectric material layer so that the first control gate material layer and the gate dielectric material layer form the first control gate layer and the gate dielectric layer, respectively; after performing the chemical mechanical polishing process, forming a second control gate material layer covering the first control gate layer, the gate dielectric layer, and the first floating gate structure.

[0046] In the method for forming a semiconductor structure in an embodiment of the present invention, the thickness of the first floating gate structure is greater than or equal to the sum of the thickness of the second floating gate structure, the gate dielectric layer subsequently formed on the second floating gate structure, and the first control gate layer located on the gate dielectric layer. Therefore, a chemical mechanical polishing process can be performed on the first control gate material layer and the gate dielectric material layer with the top surface of the first floating gate structure as a stop position to expose the top surface of the first floating gate structure, so that the second control gate material layer subsequently formed can contact the first floating gate structure, and damage caused by the plasma ions used in the plasma etching process penetrating into the first floating gate structure during the process of using a plasma etching process to form an opening to expose the first floating gate structure can be avoided, thereby improving the performance of the formed semiconductor structure.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] The following will be combined Figures 6 to 10 The method for forming the NAND flash memory device in the embodiment of the present invention is further introduced in detail.

[0049] See also Figure 6, providing a substrate 100, the substrate 100 including a peripheral region I and a storage region II; the peripheral region I has a plurality of discrete first floating gate structures 141, the storage region II has a plurality of discrete second floating gate structures 142, the thickness of the first floating gate structure 141 is greater than the sum of the thickness of the second floating gate structure 141 and a gate dielectric material layer subsequently formed on the second floating gate structure 142 and a second control gate structure located on the gate dielectric material layer.

[0050] In a specific implementation, the substrate 100 provides a process platform for the subsequent formation of a flash memory. Specifically, the substrate 100 is used to form a NAND Flash device.

[0051] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or may be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates, or other materials suitable for process requirements or easy to integrate.

[0052] The substrate 100 can be divided into a peripheral region I and a storage region II, wherein a plurality of discrete first floating gate structures 141 are formed on the peripheral region I, and a plurality of discrete second floating gate structures 142 are formed on the storage region II. Compared with the peripheral region I, the storage region II has a higher degree of integration, and the second floating gate structures 142 are relatively dense. Among them, the first floating gate structure 141 located on the peripheral region I is used to subsequently form a logic gate structure, and the second floating gate structure 142 located on the storage region II is used to subsequently form a storage gate structure and a selection gate structure. The number of the first floating gate structure 141 on the peripheral region I and the second floating gate structure 142 on the storage region II is not limited to a certain numerical range, and those skilled in the art can set them according to actual needs.

[0053] In this embodiment, the first floating gate structure 141 located in the peripheral area I includes a first gate insulation layer 110 located on the substrate 100 and a first floating gate (Floating Gate, FG) layer 120 located on the first gate insulation layer 110, and the second floating gate structure 142 located in the storage area II includes a second gate insulation layer 110' located on the substrate 100 and a second floating gate layer 120' located on the second gate insulation layer 110'.

[0054] In the present embodiment, the first gate insulating layer 110 and the second gate insulating layer 110' are tunneling oxide layers (TOX) deposited on the substrate 100, and the tunneling oxide layers are used as isolation layers between the first floating gate layer 120 and the second floating gate layer 120' and the substrate 100, so as to prevent the electrons stored in the first floating gate layer 110 and the second floating gate layer 110' from entering the substrate 100 during the data storage process, so as to reduce the loss of electrons, that is, the first gate insulating layer 110 and the second gate insulating layer 110' are used to prevent the data stored in the flash memory from being lost.

[0055] In this embodiment, both the first gate insulating layer 110 and the second gate insulating layer 110 ′ are silicon oxide layers, and the thicknesses thereof can be adjusted by those skilled in the art as required to obtain better effects.

[0056] In this embodiment, an isolation structure 103 is further formed in the substrate 100. Specifically, in the semiconductor substrate 100, an isolation structure 103 is formed between adjacent first floating gate structures 141, adjacent second floating gate structures 142, and between adjacent first floating gate structures 141 and second floating gate structures 142.

[0057] The isolation structure 103 is used to define an active area (AA) and an isolation area of ​​the substrate 100. The substrate 100 isolated by the isolation structure 103 is used as the active area, and the remaining area is used as the isolation area.

[0058] In this embodiment, the isolation structure 103 is a shallow trench isolation (STI) structure, and the material of the isolation structure 103 is silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxide.

[0059] In this embodiment, the first floating gate structure 141 on the peripheral region I, the second floating gate structure 142 on the storage region II, and the isolation structure 103 are formed in the same process step.

[0060] Specifically, a gate insulating material layer is first formed on the substrate 100, and a first polysilicon film is formed on the gate insulating material layer; a patterned hard mask layer is formed on the first polysilicon film; the first polysilicon film and the gate insulating material layer are sequentially etched using the hard mask layer as a mask, so that a first floating gate structure 141 consisting of the first gate insulating layer 110 and the first floating gate layer 120 is formed on the peripheral area I, a second floating gate structure 142 consisting of the second gate insulating layer 110' and the second floating gate layer 120' is formed on the storage area II, and a first trench 101 is formed between adjacent first floating gate structures 141 and between adjacent first floating gate structures 141 and second floating gate structures 142, and a second trench 102 is formed between adjacent second floating gate structures; the patterned hard mask layer is removed; after removing the patterned hard mask layer, an isolation material layer is filled in the first trench 101 and the second trench 102 to form the shallow trench isolation structure 103.

[0061] In this embodiment, the thickness of the first floating gate structure 141 is greater than or equal to the sum of the thickness of the second floating gate structure 142, the gate dielectric material layer subsequently formed on the second floating gate structure 142, and the second control gate structure located on the gate dielectric material layer, so that in the subsequent process of removing a portion of the thickness of the first control gate material layer on the storage area by a chemical mechanical polishing process, the gate dielectric material layer and the first control gate material layer on the top of the second floating gate structure on the peripheral area can be removed at the same time, thereby exposing the top surface of the second floating gate structure, and further allowing the subsequently formed second control gate layer to contact the first floating gate structure 141.

[0062] In this embodiment, the thickness of the first floating gate layer is 800-1000 angstroms, the thickness of the second floating gate layer is 1000-1600 angstroms, the thickness of the gate dielectric layer is 100-200 angstroms, and the thickness of the first control gate layer is 200-400 angstroms.

[0063] In this embodiment, the upper surface of the isolation structure 103 is higher than the lower surfaces of the first floating gate structure 141 and the second floating gate structure 142, that is, the isolation structure 103 also covers part of the side walls of the first floating gate structure 141 and the second floating gate structure 142, thereby improving the electrical isolation effect between adjacent first floating gate structures 141, adjacent second floating gate structures 142, and adjacent first floating gate structures 141 and second floating gate structures 142.

[0064] In a specific implementation, while forming the first floating gate structure 141, the second floating gate structure 142 and the isolation structure 103, the first trenches 101 between adjacent first floating gate structures 141 and the first floating gate structure 141 and the second floating gate structure 142 form first trenches 101', and the second trenches 102 between adjacent second floating gate structures 142 form second trenches 102'. Accordingly, the width of the first trench 101' is greater than the width of the second trench 102'.

[0065] It should be noted that, in this embodiment, the peripheral area I and the storage area II are taken as adjacent areas for illustration. In other embodiments, the peripheral area I and the storage area II may also be isolated from each other.

[0066] See also Figure 7 , forming the gate dielectric material layer 130 conformally covering the first floating gate structure 141 , the second floating gate structure 142 , and the exposed portions of the substrate 100 of the first floating gate structure 141 and the second floating gate structure 142 .

[0067] The gate dielectric material layer 130 is used to form a gate dielectric material layer in the subsequent process. In this embodiment, the gate dielectric material layer 130 is used to form an inter-poly dielectric layer (IPD).

[0068] In this embodiment, the gate dielectric material layer 130 is a stacked structure. Specifically, the gate dielectric material layer 130 is an oxide-nitride-oxide (ONO) structure, and the gate dielectric material layer 130 includes a first sub-gate dielectric material layer (not shown) conformally covering the first floating gate structure 141, the second floating gate structure 142, and the substrate 100 exposed by the first floating gate structure 141 and the second floating gate structure 142, a second sub-gate dielectric material layer (not shown) conformally covering the first sub-gate dielectric material layer, and a third sub-gate dielectric material layer (not shown) conformally covering the second sub-gate dielectric material layer. Correspondingly, the material of the first sub-gate dielectric material layer is silicon oxide, the material of the second sub-gate dielectric material layer is silicon nitride, and the material of the third sub-gate dielectric material layer is silicon oxide. The ONO structure has good corrosion resistance and compactness, can play a good protective role for the second floating gate structure, and can play an isolation role between the second floating gate structure and the second control gate structure formed subsequently.

[0069] In other embodiments, the gate dielectric material layer may also be a single-layer structure. The gate dielectric material layer may also be other dielectric materials.

[0070] It should be noted that when an isolation structure 103 is also formed in the substrate 100 , the gate dielectric material layer 130 covers the first floating gate structure 141 , the second floating gate structure 142 , and the isolation structure 103 exposed between the first floating gate structure 141 and the second floating gate structure 142 .

[0071] See also Figure 8 , forming a first control gate material layer 140 covering the gate dielectric material layer 130 .

[0072] The first control gate material layer 140 is used to subsequently form a first control gate layer.

[0073] In this embodiment, the material of the first control gate material layer is ONO polysilicon. In other embodiments, the first control gate material layer may also be made of other materials.

[0074] The process for forming the first control gate material layer 140 may be a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a high temperature furnace process.

[0075] See also Fig. 9 , taking the top surface of the first floating gate structure 141 as the stop position, performing a chemical mechanical polishing process on the first control gate material layer 140 and the gate dielectric material layer 130, so that the remaining first control gate material layer 140 and the gate dielectric material layer 130 form a first control gate layer 140' and a gate dielectric layer 130' respectively.

[0076] As mentioned above, the height of the first floating gate structure 141 on the peripheral region I is greater than the sum of the thickness of the second floating gate structure 142 on the storage region II, the gate dielectric layer 130' located on the second floating gate structure 142, and the first control gate layer 140' located on the gate dielectric layer 130. Therefore, with the top surface of the first floating gate structure 141 as the stop position, the chemical mechanical polishing process is performed on the first control gate material layer 140 and the gate dielectric material layer 130 to expose the top surface of the first floating gate structure 141, so that the second control gate material layer formed subsequently can contact the first floating gate structure 141. Therefore, it is possible to avoid the plasma ions used in the plasma etching process from penetrating into the first floating gate structure 141 and causing damage to the first gate insulation layer 110 in the first floating gate structure 141. In addition, the chemical mechanical polishing process can be used to grind the first control gate material layer 140 and the gate dielectric material layer 130 with high precision and low damage, so that the grinding thickness can be accurately controlled.

[0077] See also Fig.10After performing a chemical mechanical polishing process, a second control gate material layer 150 is formed covering the first floating gate structure 141, the first control gate layer 140' and the gate dielectric layer 130'.

[0078] The second control gate material layer 150 on the peripheral area I is used for subsequent etching to form a first control gate structure located on the top of the first floating gate structure 141. The second control gate material layer 150 and the first control gate layer 140' on the storage area II are used for subsequent etching to form a second gate dielectric layer located on the second floating gate structure 142, a first control gate layer located on the second gate dielectric layer, and a second control gate layer located on the first control gate layer. The first control gate layer and the second control layer constitute a second control gate structure.

[0079] In this embodiment, after forming the second control gate material layer 150, it also includes: forming a patterned mask layer on the second control gate material layer 150; etching the second control gate material layer 150, the first control gate structure layer 140' and the gate dielectric layer 130' in sequence using the patterned mask layer as a mask to form a first control gate structure located on the first floating gate structure 141, and forming a second gate dielectric layer located on the second floating gate structure 142, a first control gate layer located on the second gate dielectric layer and a second control gate layer located on the first control gate layer, the first control gate layer and the second control layer constitute a second control gate structure.

[0080] Accordingly, an embodiment of the present invention further provides a semiconductor structure.

[0081] Please continue to see Fig.10 The semiconductor structure includes: a substrate 100, the substrate 100 includes a peripheral area I and a storage area II; a plurality of discrete first floating gate structures 141 located on the peripheral area I and a plurality of discrete second floating gate structures 142 located on the storage area II; a gate dielectric layer 130' of the substrate 100 located on the sidewalls of the first floating gate structure 141, the top and sidewalls of the second floating gate structure 142, and the first floating gate structure 141 and the second floating gate structure 142 exposed; a first control gate layer 140' located on the gate dielectric layer 130'; and a second control gate material layer 150 located on the first control gate layer 140', the gate dielectric layer 130', and the first floating gate structure 141.

[0082] In this embodiment, the first floating gate structure 141 includes a first gate insulating layer 110 located on the substrate 100 and a first floating gate layer 120 located on the first gate insulating layer 110; the second floating gate structure 142 includes a second gate insulating layer 110' located on the substrate 100 and a second floating gate layer 120' located on the second gate insulating layer 110'.

[0083] In this embodiment, the substrate 100 further includes an isolation structure 103 ; the gate dielectric layer 130 ′ is located on the isolation structure 103 where the first floating gate structure 141 and the second floating gate structure 142 are exposed.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a storage area and a peripheral area; a plurality of discrete second floating gate structures located on the storage region and a plurality of discrete first floating gate structures located on the peripheral region; The thickness of the first floating gate structure is greater than or equal to the sum of the thickness of the second floating gate structure, a gate dielectric layer subsequently formed on the second floating gate structure, and a first control gate layer located on the gate dielectric layer; A gate dielectric layer located on the sidewalls of the first floating gate structure, the top and sidewalls of the second floating gate structure, and the substrate where the first floating gate structure and the second floating gate structure are exposed; The substrate further includes an isolation structure; the gate dielectric layer is located on the isolation structure where the first floating gate structure and the second floating gate structure are exposed; the isolation structures of the peripheral area and the storage area are flush, and the gate dielectric layer is located on the isolation structure of the substrate; A first control gate layer located on the gate dielectric layer; A second control gate material layer is located on the first control gate layer, the gate dielectric layer and the first floating gate structure.

2. The semiconductor structure according to claim 1, characterized in that: The first floating gate structure includes a first gate insulating layer located on the substrate and a first floating gate layer located on the first gate insulating layer; the second floating gate structure includes a second gate insulating layer located on the substrate and a second floating gate layer located on the second gate insulating layer.

3. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, the substrate comprising a peripheral region and a storage region; the peripheral region has a plurality of discrete first floating gate structures, the storage region has a plurality of discrete second floating gate structures, the thickness of the first floating gate structure is greater than or equal to the sum of the thickness of the second floating gate structure, a gate dielectric layer subsequently formed on the second floating gate structure, and a first control gate layer located on the gate dielectric layer; forming a gate dielectric material layer conformally covering the first floating gate structure, the second floating gate structure, and the exposed portions of the first floating gate structure and the second floating gate structure; forming a first control gate material layer covering the gate dielectric material layer; Taking the top surface of the first floating gate structure as a stop position, performing a chemical mechanical polishing process on the first control gate material layer and the gate dielectric material layer, so that the first control gate material layer and the gate dielectric material layer form the first control gate layer and the gate dielectric layer respectively; After performing the chemical mechanical polishing process, a second control gate material layer covering the first control gate layer, the gate dielectric layer and the first floating gate structure is formed.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: After forming the second control gate material layer, the method further includes: forming a patterned mask layer on the second control gate material layer; The second control gate material layer, the first control gate layer and the gate dielectric layer are sequentially etched using the patterned mask layer as a mask to form a first control gate structure located on the first floating gate structure, and a second gate dielectric layer located on the second floating gate structure, a first control gate located on the second gate dielectric layer and a second control gate located on the first control gate are formed, wherein the first control gate and the second control gate constitute a second control gate structure.

5. The method for forming a semiconductor structure according to claim 3, wherein: The substrate has an isolation structure; after the gate dielectric material layer is formed, the gate dielectric material layer also covers the isolation structure exposed by the first floating gate structure and the second floating gate structure.

6. The method for forming a semiconductor structure according to claim 3, characterized in that: The first floating gate structure includes a first gate insulating layer located on the substrate and a first floating gate layer located on the first gate insulating layer; the second floating gate structure includes a second gate insulating layer located on the substrate and a second floating gate layer located on the second gate insulating layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The thickness of the first floating gate layer is 800-1000 angstroms, the thickness of the second floating gate layer is 1000-1600 angstroms, the thickness of the gate dielectric layer is 100-200 angstroms, and the thickness of the first control gate layer is 200-400 angstroms.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first floating gate layer is polysilicon.

9. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second floating gate layer is polysilicon.

10. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first gate insulating layer is silicon oxide.

11. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second gate insulating layer is silicon oxide.

12. The method for forming a semiconductor structure according to claim 3, characterized in that: The gate dielectric material layer is of ONO structure.

13. The method for forming a semiconductor structure according to claim 3, characterized in that: The material of the first control gate material layer is ONO polysilicon.

14. The method for forming a semiconductor structure according to claim 3, wherein: The material of the second control gate material layer is polysilicon.

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