Semiconductor device and data storage system including semiconductor device

Abstract

A semiconductor device includes a stack structure, and an insulating structure covering the stack structure, a vertical storage structure penetrating the stack structure, and a separation structure penetrating the stack structure and having an upper surface located at a height higher than an upper surface of the vertical storage structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked in the vertical direction and spaced apart from each other. At a height between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical storage structure includes storage side surface slope change portions, and a side surface of the separation structure includes separation side surface slope change portions provided at substantially the same height as some of the storage side surface slope change portions.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0038069, filed on March 24, 2021, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and data systems including such semiconductor devices. Background Technology

[0004] There is a need for semiconductor devices capable of storing high-capacity data in electronic systems requiring data storage. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, to improve the data storage capacity of semiconductor devices, semiconductor devices incorporating three-dimensional storage cells instead of two-dimensional storage cells have been proposed.

[0005] In VNAND flash memory devices, a vertical storage structure and a vertical support structure are formed simultaneously, and gate contact plugs, peripheral contact plugs, and separation structures that separate the gate stack structure are formed through different processes. Summary of the Invention

[0006] Embodiments of the present invention provide semiconductor devices with increased integration and improved reliability.

[0007] Another embodiment of the present invention provides a data storage system including semiconductor devices.

[0008] According to an embodiment of the present invention, a semiconductor device includes: a first structure; a second structure, the second structure including: a stacked structure comprising at least three gate stacks stacked vertically on the first structure; an insulating structure covering at least a portion of the stacked structure; a vertical memory structure penetrating at least the stacked structure; and a separation structure penetrating at least the stacked structure, the separation structure having an upper surface at a height higher than the upper surface of the vertical memory structure. Each of the at least three gate stacks includes gate layers stacked vertically and spaced apart from each other. At a height between the lowermost and uppermost gate layers in the stacked structure, the side surface of the vertical memory structure includes a plurality of N memory side surface slope changes, and the side surface of the separation structure includes M separation side surface slope changes located at substantially the same height as the M memory side surface slope changes of the plurality of N memory side surface slope changes, wherein M < N, N is a natural number of 2 or greater, and M is a natural number of 1 or greater.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a lower structure; an upper structure comprising: a stacked structure including at least three gate stacks stacked vertically on the lower structure; an insulating structure covering at least a portion of the stacked structure; a vertical memory structure that penetrates at least the stacked structure; peripheral contact plugs; a plurality of gate contact plugs; and a separation structure that penetrates at least the stacked structure and is linear in a plan view. Each of the at least three gate stacks includes gate layers stacked vertically and spaced apart from each other. At a height between the lowermost and uppermost gate layers in the stacked structure, each of the side surfaces of the vertical memory structure and the peripheral contact plugs includes a plurality of first slope changes in number N, and the side surface of the separation structure includes M second slope changes located at substantially the same height as the M first slope changes in number N, wherein M < N and N and M are different natural numbers. At a height higher than the uppermost gate layer, the side surface of the vertical storage structure, the side surface of the peripheral contact plug, the side surface of the separation structure, and the side surface of each gate contact plug in the gate contact plug include a first slope changing section located at substantially the same height, and the side surface of the separation structure is substantially vertical at the same height as the lowest first slope changing section among the plurality of first slope changing sections of number N.

[0010] According to an embodiment of the present invention, a data storage system includes: a main substrate; a semiconductor device disposed on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate. The semiconductor device includes: a lower structure; an upper structure, the upper structure including: a stacked structure comprising at least three gate stacks stacked vertically on the lower structure; an insulating structure covering at least a portion of the stacked structure; a vertical storage structure that at least penetrates the stacked structure; peripheral contact plugs; a plurality of gate contact plugs; and a separation structure that at least penetrates the stacked structure and has a linear shape in a plan view. Each of the at least three gate stacks includes gate layers stacked vertically and spaced apart from each other. At the height between the bottom and top gate layers in the stacked structure, each of the side surfaces of the vertical storage structure and the peripheral contact plug includes a plurality of first slope changing sections of number N. The side surface of the separation structure includes M second slope changing sections located at substantially the same height as the M first slope changing sections of the plurality of N first slope changing sections, where M < N and N and M are distinct natural numbers. At a height higher than the top gate layer, the side surfaces of the vertical storage structure, the peripheral contact plug, the separation structure, and each gate contact plug include first upward slope changing sections located at substantially the same height. The side surface of the separation structure is substantially vertical at the same height as the lowest of the plurality of N first slope changing sections. Attached Figure Description

[0011] Figure 1 This is a schematic perspective view of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 2A and Figure 2B This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 3A and Figure 3C This is a schematic partial enlarged view of a portion of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 4A and Figure 4B This is a schematic cross-sectional view of a semiconductor device according to a modified embodiment of the present invention.

[0015] Figure 5A and Figure 5B This is a schematic partial enlarged view of a portion of a semiconductor device according to a modified embodiment of the present invention.

[0016] Figure 6 and Figure 7 This is a schematic diagram of a semiconductor device according to a modified embodiment of the present invention.

[0017] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to a modified embodiment of the present invention.

[0018] Figure 9A and Figure 9B This is a flowchart of a process for forming a semiconductor device according to an embodiment of the present invention.

[0019] Figure 10A , Figure 10B , Figure 11A and Figure 11B This is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention.

[0020] Figure 12 A data storage system including semiconductor devices is illustrated schematically according to an embodiment of the present invention.

[0021] Figure 13 This is a schematic perspective view of a data storage system including semiconductor devices according to embodiments of the present invention.

[0022] Figure 14 This is a cross-sectional view of a data storage system including semiconductor devices according to embodiments of the present invention. Detailed Implementation

[0023] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0024] Reference Figure 1 A semiconductor device according to an embodiment of the concept of the present invention is described. Figure 1 This is a schematic perspective view of a semiconductor device according to an embodiment of the present invention.

[0025] refer to Figure 1 In an embodiment, the semiconductor device 1 includes a first structure LS and a second structure US disposed on the first structure LS. The second structure US includes a plurality of memory structures M1 and M2. Although Figure 1 Two storage structures M1 and M2 are shown, but the embodiments are not limited thereto, and in other embodiments, more than two storage structures may be provided. Each of the plurality of storage structures M1 and M2 includes a separation structure 87, a first region MCA disposed between the separation structures 87, and a second region SA disposed on at least one side of the first region MCA.

[0026] In the embodiment, the first region MCA is a storage cell array region or a storage cell region, and the second region SA is a step region.

[0027] In an embodiment, the first region (i.e., the memory cell array region) disposed between a pair of spaced-apart and parallel separate structures 87 in the first region MCA is a memory block. Each of the plurality of memory structures M1 and M2 also includes a through region TA disposed between a pair of first regions in the first region MCA. The semiconductor device 1 also includes peripheral contact plugs 111. At least some of the peripheral contact plugs 111 penetrate the through region TA.

[0028] In the following text, reference will be made to Figure 2A and Figure 2B An example describing semiconductor device 1. Figure 2A It is along Figure 1 A schematic cross-sectional view taken from line I-I', and Figure 2B It is along Figure 1 A schematic cross-sectional view taken from line II-II'.

[0029] Combination Figure 1 refer to Figure 2A and Figure 2B In an embodiment, the first structure LS of the semiconductor device 1 includes a patterned structure 23. The patterned structure 23 includes at least one silicon layer.

[0030] In an embodiment, the patterned structure 23 includes a lower patterned layer 23a, a first intermediate patterned layer 23b1, a second intermediate patterned layer 23b2, and an upper patterned layer 23c. The first intermediate patterned layer 23b1 and the second intermediate patterned layer 23b2 are spaced apart from each other on the lower patterned layer 23a. The upper patterned layer 23c covers the first intermediate patterned layer 23b1 and the second intermediate patterned layer 23b2 on the lower patterned layer 23a. The lower patterned layer 23a has a thickness greater than each of the first intermediate patterned layer 23b1, the second intermediate patterned layer 23b2, and the upper patterned layer 23c. At least one of the lower patterned layer 23a, the first intermediate patterned layer 23b1, the second intermediate patterned layer 23b2, and the upper patterned layer 23c includes a silicon layer. For example, the lower patterned layer 23a, the first intermediate patterned layer 23b1, and the upper patterned layer 23c may include silicon layers (e.g., silicon layers with N-type conductivity), and the second intermediate patterned layer 23b2 may include a material different from that of the silicon layers. For example, the second intermediate patterned layer 23b2 may include multiple layers stacked in sequence, such as a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence.

[0031] In an embodiment, the first structure LS includes: a semiconductor substrate 5; peripheral circuits 9 and 13 on the semiconductor substrate 5; peripheral pads 15 electrically connected to the peripheral circuits 9 and 13; and a lower insulating structure 21 on the semiconductor substrate 5 and covering the peripheral circuits 9 and 13 and the peripheral pads 15. The semiconductor substrate 5 includes a device isolation layer 7s defining an active region 7a. The peripheral circuits 9 and 13 include: circuit elements 9, such as transistors including a peripheral gate 9a disposed on the active region 7a, and peripheral source / drain electrodes 9b disposed on both sides of the peripheral gate 9a in the active region 7a; and circuit interconnects 13 electrically connected to the circuit elements 9.

[0032] In an embodiment, the first structure LS further includes: a capping layer 17 formed on each peripheral pad 15; and an etch stop layer 19 formed on the capping layer 17. In an embodiment, the capping layer 17 is formed of a silicon layer, and the etch stop layer 19 is formed of an insulating material such as silicon oxide or silicon nitride.

[0033] In this embodiment, the patterned structure 23 is disposed on the lower insulating structure 21. The peripheral pads 15 include a ground pad 15g, a first peripheral pad 15a, a second peripheral pad 15b, and a third peripheral pad 15c.

[0034] In one embodiment, a portion of the lower patterned layer 23a of the patterned structure 23 extends downward to be electrically connected to the ground pad 15g. The ground pad 15g is grounded to the ground region 11 of the semiconductor substrate 5 via the circuit interconnect 13.

[0035] In an embodiment, the first structure LS further includes: an outer insulating layer 26o disposed outside the patterned structure 23; a first inner insulating layer 26i_1 penetrating the patterned structure 23; and a second inner insulating layer 26i_2 penetrating the patterned structure 23.

[0036] In an embodiment, the first inner insulating layer 26i_1 has a linear shape in a plan view. Each second inner insulating layer 26i_2 may have a circular, elliptical, or polygonal shape.

[0037] In an embodiment, the second structure US of the semiconductor device 1 includes a stacked structure GS disposed in the first region MCA and extending from the first region MCA into the second region SA. The stacked structure GS includes at least three stacked groups GR1, GR2, and GR3 stacked along the vertical direction Z. For example, the stacked structure GS includes a lower stacked group GR1, an intermediate stacked group GR2 on the lower stacked group GR1, and an upper stacked group GR3 on the intermediate stacked group GR2. The lower stacked group GR1 includes alternately stacked lower interlayer insulating layers 32a and lower gate layers 32g, the intermediate stacked group GR2 includes alternately stacked intermediate interlayer insulating layers 44a and intermediate gate layers 44g, and the upper stacked group GR3 includes alternately stacked upper interlayer insulating layers 58a and upper gate layers 58g.

[0038] In this embodiment, the lower gate layers 32g are stacked vertically in a Z-direction and spaced apart to form a lower gate stack group; the middle gate layers 44g are stacked vertically in a Z-direction and spaced apart to form a middle gate stack group; and the upper gate layers 55g are stacked vertically in a Z-direction and spaced apart to form an upper gate stack group. In this regard, reference numerals 32g, 44g, and 55g can also be used to refer to the lower gate stack group, the middle gate stack group, and the upper gate stack group, respectively.

[0039] In an embodiment, the lower gate layer 32g, the middle gate layer 44g, and the upper gate layer 58g include gate pads GP, which are located at the ends of the lower gate layer 32g, the middle gate layer 44g, and the upper gate layer 58g and are arranged in a stepped shape in the second region SA. However, the gate pads GP are not limited to... Figure 2A The stepped shape shown is possible, and in other embodiments it can be arranged in various other shapes.

[0040] In this embodiment, the thickness of each gate pad GP is greater than the thickness of each of the lower gate layer 32g, the middle gate layer 44g, and the upper gate layer 58g.

[0041] In an embodiment, the second structure US further includes intermediate insulating structures 36, 48, and 62 covering at least a portion of the stacked structure GS. The intermediate insulating structures 36, 48, and 62 include: a first intermediate insulating layer 36 disposed on the lower structure LS and covering the gate pad GP of the lower gate layer 32g; a second intermediate insulating layer 48 disposed on the first intermediate insulating layer 36 and covering the gate pad GP of the intermediate gate layer 44g; and a third intermediate insulating layer 62 disposed on the second intermediate insulating layer 48 and covering the gate pad GP of the upper gate layer 58g.

[0042] In an embodiment, the second structure US further includes upper insulating structures 68, 84, 90, and 116 disposed on the stacked structure GS and the intermediate insulating structures 36, 48, and 62. The intermediate insulating structures 36, 48, and 62 and the upper insulating structures 68, 84, 90, and 116 form an insulating structure.

[0043] In an embodiment, the upper insulating structures 68, 84, 90 and 116 include: a first upper insulating layer 68, a second upper insulating layer 84, a third upper insulating layer 90 and a fourth upper insulating layer stacked in sequence.

[0044] In an embodiment, the semiconductor device 1 further includes a vertical memory structure 71 that penetrates at least the stacked structure GS in the first region MCA. A plurality of vertical memory structures 71 are provided. The vertical memory structures 71 extend downward and penetrate the stacked structure GS, extending into the patterned structure 23. For example, the vertical memory structure 71 extends through the upper patterned layer 23c and the first intermediate patterned layer 23b1 and extends into the lower patterned layer 23a to contact the lower patterned layer 23a. The vertical memory structure 71 extends upward from the stacked structure GS and penetrates the first upper insulating layer 68. The upper surface of the vertical memory structure 71 is coplanar with the upper surface of the first upper insulating layer 68.

[0045] In an embodiment, the semiconductor device 1 further includes a supporting vertical structure 81 that penetrates at least the stacked structure GS in the second region SA. A plurality of supporting vertical structures 81 are provided. The supporting vertical structures 81 extend into the patterned structure 23. For example, the supporting vertical structures 81 sequentially extend through the upper patterned layer 23c and the second intermediate patterned layer 23b2 into the lower patterned layer 23a to contact the lower patterned layer 23a. The supporting vertical structures 81 extend upward from the stacked structure GS to penetrate the first upper insulating layer 68. The upper surface of the supporting vertical structure 81 is coplanar with the upper surface of the first upper insulating layer 68.

[0046] In the embodiments, the above references Figure 1 The described separation structure 87 penetrates at least the stacked structure GS. The separation structure 87 extends downward from the stacked structure GS to contact the lower patterned layer 23a of the patterned structure 23. The separation structure 87 extends upward from the stacked structure GS to penetrate the first upper insulating layer 68 and the second upper insulating layer 84. The upper surface of the separation structure 87 is coplanar with the upper surface of the second upper insulating layer 84.

[0047] In the embodiments, the above references Figure 1The described through-region TA is located on the first inner insulating layer 26i_1. The through-region TA includes a lower horizontal insulating layer 32d, an intermediate horizontal insulating layer 44d, and an upper horizontal insulating layer 58d disposed at substantially the same height as the lower gate layer 32g, the intermediate gate layer 44g, and the upper gate layer 58g. In the through-region TA, the lower interlayer insulating layer 32a, the intermediate interlayer insulating layer 44a, and the upper interlayer insulating layer 58a, as well as the lower horizontal insulating layer 32d, the intermediate horizontal insulating layer 44d, and the upper horizontal insulating layer 58d, are stacked alternately and repeatedly. The lower horizontal insulating layer 32d, the intermediate horizontal insulating layer 44d, and the upper horizontal insulating layer 58d are formed of silicon nitride, and the lower interlayer insulating layer 32a, the intermediate interlayer insulating layer 44a, and the upper interlayer insulating layer 58a are formed of silicon oxide.

[0048] In one embodiment, the peripheral contact plug 111 penetrates at least a portion of the second structure US. The peripheral contact plug 111 includes a first peripheral contact plug 111a, a second peripheral contact plug 111b, and a third peripheral contact plug 111c.

[0049] In this embodiment, the first peripheral contact plug 111a is spaced apart from the stacked structure GS, penetrates the intermediate insulating structures 36, 48 and 62, the outer insulating layer 26o, and the first upper insulating layer 68, the second upper insulating layer 84 and the third upper insulating layer 90, and contacts the first peripheral pad 15a. The upper surface of the first peripheral contact plug 111a is coplanar with the upper surface of the third upper insulating layer 90.

[0050] In this embodiment, the second peripheral contact plug 111b penetrates the lower interlayer insulation layer 32a, the middle interlayer insulation layer 44a, and the upper interlayer insulation layer 58a, as well as the lower horizontal insulation layer 32d, the middle horizontal insulation layer 44d, and the upper horizontal insulation layer 58d in the through region TA. It also penetrates the first inner insulation layer 26i_1, the first upper insulation layer 68, the second upper insulation layer 84, and the third upper insulation layer 90, and contacts the second peripheral pad 15b. The upper surface of the second peripheral contact plug 111b is coplanar with the upper surface of the third upper insulation layer 90.

[0051] In this embodiment, the third peripheral contact plug 111c is spaced apart from the stacked structure GS, penetrates the intermediate insulating structures 36, 48 and 62, as well as the first upper insulating layer 68, the second upper insulating layer 84 and the third upper insulating layer 90, and contacts the lower patterned layer 23a. The upper surface of the third peripheral contact plug 111c is coplanar with the upper surface of the third upper insulating layer 90.

[0052] In this embodiment, the lower surface of the peripheral contact plug 111 is located at a lower height than the lower surface of the vertical storage structure 71, and the upper surface of the peripheral contact plug 111 is located at a higher height than the upper surface of the vertical storage structure 71.

[0053] In an embodiment, the semiconductor device 1 further includes a gate contact plug 106 that penetrates at least a portion of the second structure US and is electrically connected to gate layers 32g, 44g, and 58g. Each gate contact plug 106 has: a lower surface at a height lower than the lowest gate layer 32g_L among the gate layers 32g, 44g, and 58g; and an upper surface at a height higher than the uppermost gate layer 58g_U among the gate layers 32g, 44g, and 58g.

[0054] In this embodiment, gate contact plugs 106 contact gate pads GP. Gate contact plugs 106 extend through gate pads GP. For example, one gate contact plug 106 is electrically connected to and extends through one gate pad GP. A buffer insulating layer 103 is disposed between the gate layers located at a height lower than the gate pads GP and the gate contact plugs 106. For example, based on a gate pad GP and a gate contact plug 106 in contact with each other, the buffer insulating layer 103 is disposed between the gate layers located lower than the gate pads GP and the gate contact plugs 106. The buffer insulating layer 103 is formed of silicon oxide.

[0055] In one embodiment, the gate contact plug 106 has a lower surface at a height lower than the lowest gate layer 38g_L and an upper surface at a height higher than the highest gate layer 58g_U. The lower surface of the gate contact plug 106 is located at a height lower than the lower surface of the vertical memory structure 71, and the upper surface of the gate contact plug 106 is located at a height higher than the upper surface of the vertical memory structure 71.

[0056] In an embodiment, the semiconductor device 1 includes: a bit line contact plug 119 that penetrates the upper insulating structures 68, 84, 90 and 116 and is electrically connected to the vertical storage structure 71; and an upper contact plug 120 that penetrates the fourth upper insulating layer 116 and is electrically connected to the peripheral contact plug 111.

[0057] In this embodiment, the semiconductor device 1 further includes: a bit line 123, which is electrically connected to the vertical memory structure 71 on the fourth upper insulating layer 116 and via a bit line contact plug 119; and a peripheral interconnect 124, which is electrically connected to a first peripheral contact plug 111a and a third peripheral contact plug 111c on the fourth upper insulating layer 116 and via an upper contact plug 120, respectively. A second peripheral contact plug 111b is electrically connected to the bit line 123 via an upper contact plug 120.

[0058] In the following text, reference will be made to Figure 3A The vertical storage structure 71 and the separate structure 87 disclosed above are described. Figure 3A yes Figure 2B A magnified view of region "A" in the image.

[0059] Combination Figures 1 to 2B refer to Figure 3AIn one embodiment, the side surface of the vertical storage structure 71 at the height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U includes a plurality of N storage side surface slope changing sections 71s_1a and 71s_1b. The side surface of the separation structure 87 includes a plurality of M separation side surface slope changing sections 87s_1 disposed at a height substantially the same as the M slope changing sections 71s_1b, where M < N.

[0060] Here, N is a natural number of 2 or greater, and M is a natural number less than N, such as a natural number of 1 or greater. For example, M could be N-1. Or, N could be 2 and M could be 1.

[0061] In the embodiment, the M separate side surface slope changing sections 87s_1 are located at substantially the same height as the storage side surface slope changing section 71s_1b, which is higher than the lowest storage side surface slope changing section 71s_1a and 71s_1b among the N storage side surface slope changing sections 71s_1a and 71s_1b.

[0062] In an embodiment, at a height higher than the uppermost gate layer 58g_U, the vertical storage structure 71 includes at least one upper surface slope changing portion 71s_2.

[0063] In one embodiment, at a height higher than the uppermost gate layer 58g_U, the separation structure 87 includes at least one upper surface slope changing portion 87s_2. The upper surface slope changing portion 71s_2 of the vertical storage structure 71 and the upper surface slope changing portion 87s_2 of the separation structure 87 are located at substantially the same height.

[0064] In an embodiment, the "slope changing section" refers to a side surface section having a third slope between the upper side surface section of the first slope and the lower side surface section of the second slope, as defined below. Each of the first and second slopes is a vertical or near-vertical slope, and the third slope is gentler or less steep than each of the first and second slopes. Each of the first and second slopes is a steep slope, and the third slope is a gentle or less steep slope. For example, the side surface of the vertical storage structure 71 includes: a lower side surface portion 71sa with a steep slope; a first intermediate side surface portion 71sb above the lower side surface portion 71sa and with a steep slope; a first storage side surface slope changing portion 71s_1a between the lower side surface portion 71sa and the first intermediate side surface portion 71sb and with a gentle slope; a second intermediate side surface portion 71sc above the first intermediate side surface portion 71sb and with a steep slope; a second storage side surface slope changing portion 71s_1b between the first intermediate side surface portion 71sb and the second intermediate side surface portion 71sc and with a gentle slope; an upper side surface portion 71sd above the second intermediate side surface portion 71sc and with a steep slope; and an upper side surface slope changing portion 71s_2 between the second intermediate side surface portion 71sc and the upper side surface portion 71sd and with a gentle slope. Here, "steep slope" and "gentle slope" are terms indicating relative slope, wherein a gentle slope is less steep than a steep slope, a steep slope has different slopes on different sides, and a gentle slope has different slopes on different slope transition sections.

[0065] In an embodiment, the side surface of the separation structure 87 includes: a lower side surface portion 87sa with a steep slope; an intermediate side surface portion 87sb above the lower side surface portion 87sa and with a steep slope; a separation side surface slope changing portion 87s_1 between the lower side surface portion 87sa and the intermediate side surface portion 87sb and with a gentler or less steep slope; an upper side surface portion 87sc above the intermediate side surface portion 87sb and with a steep slope; and an upper slope changing portion 87s_2 between the intermediate side surface portion 87sb and the upper side surface portion 87sc and with a gentler or less steep slope.

[0066] Therefore, in the embodiments, even if not described separately below, the "side surface slope changing part" or "slope changing part" is a part that is provided between the steep slope of the upper side surface part provided at the upper part of the side surface slope changing part and the steep slope of the lower side surface part provided at the lower part of the side surface slope changing part and has a gentle slope.

[0067] In the embodiments, the terms "storage side surface slope changing section" and "separation side surface slope changing section" are used to distinguishably describe the changing sections of different components and can be replaced by other terms such as slope. For example, "storage side surface slope changing section" and "separation side surface slope changing section" can be replaced and described as "first slope changing section" and "second slope changing section," respectively, or can be replaced and described as "first side surface slope changing section" and "second side surface slope changing section," respectively.

[0068] In this embodiment, at a height between the lowest gate layer 32g_L and the highest gate layer 58g_U, the N memory side surface slope changing portions 71s_1a and 71s_1b of the vertical memory structure 71 are located vertically between at least three adjacent gate stack groups. For example, the first memory side surface slope changing portion 71s_1a of the N memory side surface slope changing portions 71s_1a and 71s_1b is located at a height between the lower gate stack group 32g and the middle gate stack group 44g, and the second memory side surface slope changing portion 71s_1b is located at a height between the middle gate stack group 44g and the upper gate stack group 58g.

[0069] In one embodiment, the side surface of the separation structure 87 is at approximately the same vertical height as the slope change portion 71s_1a of the lowest storage side surface.

[0070] In this embodiment, each lower gate layer 32g includes a first layer 31a and a second layer 31b. The first layer 31a covers the upper and lower surfaces of the second layer 31b and extends between the vertical storage structure 71 and the second layer 31b. Furthermore, each of the intermediate gate layer 44g and the upper gate layer 55g also includes a first layer and a second layer having substantially similar structures.

[0071] In an embodiment, the first layer 31a comprises a dielectric material, and the second layer 31b comprises a conductive material. For example, the first layer 31a comprises a high-k dielectric (e.g., AlO), and the second layer 31b comprises a conductive material (e.g., TiN, WN, Ti, or W).

[0072] In an embodiment, the first layer 31a includes a first conductive material (e.g., TiN or W, etc.), and the second layer 31b includes a second conductive material (e.g., Ti or W, etc.) that is different from the first conductive material.

[0073] In the embodiments, each of the lower gate layer 32g, the middle gate layer 44g, and the upper gate layer 58g is formed of at least one of doped polysilicon, a metal semiconductor compound (e.g., TiSi, TaSi, CoSi, NiSi, or WSi), a metal nitride (e.g., TiN, TaN, or WN), or a metal (e.g., Ti or W).

[0074] In an embodiment, the vertical storage structure 71 includes: a gap-filling insulating layer 73; a channel material layer 75 covering the outer and bottom surfaces of the gap-filling insulating layer 73; a data storage structure 72 covering the outer and bottom surfaces of the channel material layer 73; and a pad pattern 79 on the gap-filling insulating layer 73.

[0075] In one embodiment, the data storage structure 72 includes: a first dielectric layer 72b covering the outer and bottom surfaces of the channel material layer 75; a data storage layer 72d covering the outer and bottom surfaces of the first dielectric layer 72b; and a second dielectric layer 72a covering the outer and bottom surfaces of the data storage layer 72d. The first dielectric layer 72b is in contact with the channel material layer 73, and the data storage layer 72d is spaced apart from the channel material layer 73.

[0076] In an embodiment, the gap-filling insulating layer 73 comprises silicon oxide, such as ALD silicon oxide formed by an atomic layer deposition (ALD) process, or silicon oxide in which voids are formed.

[0077] In one embodiment, the first dielectric layer 72b comprises silicon oxide or silicon oxide doped with impurities. The second dielectric layer 72a comprises at least one of silicon oxide and a high-k dielectric. The data storage layer 72d comprises a charge-trapping material, such as silicon nitride.

[0078] In one embodiment, the data storage layer 72d includes a region for storing data in a semiconductor device such as a flash memory device. The channel material layer 73 includes polysilicon. The pad pattern 79 includes at least one of doped polysilicon, metal nitride (e.g., TiN), metal (e.g., W), or metal semiconductor compound (e.g., TiSi).

[0079] In one embodiment, the first intermediate patterned layer 23b1 of the patterned structure 23 penetrates the data storage structure 72 of the vertical storage structure 71 to contact the channel material layer 73.

[0080] In an embodiment, the bit line contact plug 119 includes: a plug pattern 118b; and a conductive liner 118a covering the side and bottom surfaces of the plug pattern 118b.

[0081] Next, we will refer to Figure 3B The above describes the peripheral contact plug 111. Figure 3B yes Figure 2B Area B1 and Figure 2A A partial enlarged view of region B2. In the following text, the peripheral contact plug 111 of one of the first peripheral contact plug 111a and the second peripheral contact plug 111b will be described.

[0082] Combination Figures 1 to 3Arefer to Figure 3B In this embodiment, at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U, similar to the side surface of the vertical storage structure 71, the side surface of the peripheral contact plug 111 includes a plurality of N peripheral contact side surface slope changing portions 111s_1a and 111s_1b, which are disposed at substantially the same height as the plurality of N storage side surface slope changing portions 71s_1a and 71s_1b. At a height higher than the uppermost gate layer 58g_U, the peripheral contact plug 111 includes at least one upper side surface slope changing portion 111s_2. The upper side surface slope changing portion 71s_2 of the vertical storage structure 71 and the upper side surface slope changing portion 111s_2 of the peripheral contact plug 111 are disposed at substantially the same height.

[0083] In an embodiment, the side surface of the peripheral contact plug 111 includes: a lower side surface portion 111sa; a first intermediate side surface portion 111sb above the lower side surface portion 111sa; a first peripheral contact side surface slope changing portion 111s_1a between the lower side surface portion 111sa and the first intermediate side surface portion 111sb and having a slope that is gentler or less steeper than that of each of the lower side surface portion 111sa and the first intermediate side surface portion 111sb; a second intermediate side surface portion 111sc above the first intermediate side surface portion 111sb; and a second intermediate side surface portion 111sc above the first intermediate side surface portion 111sb. The second peripheral contact side surface slope changing portion 111s_1b is located between the intermediate side surface portions 111sc and has a slope that is gentler or less steeper than that of each of the first intermediate side surface portion 111sb and the second intermediate side surface portion 111sc; the upper side surface portion 111sd is located above the second intermediate side surface portion 111sc; and the upper side surface slope changing portion 111s_2 is located between the second intermediate side surface portion 111sc and the upper side surface portion 111sd and has a slope that is gentler or less steeper than that of each of the second intermediate side surface portion 111sc and the upper side surface portion 111sd.

[0084] In one embodiment, the peripheral contact plug 111 includes a plug pattern 113b and a conductive liner 113a covering the side and bottom surfaces of the plug pattern 113b. The plug pattern 113b includes a conductive material (e.g., tungsten), and the conductive liner 113a includes a conductive material (e.g., Ti or TiN). However, the embodiments are not limited thereto, and in other embodiments, the conductive material may be replaced with various materials other than those disclosed.

[0085] In one embodiment, the upper contact plug 120 includes: a plug pattern 120b; and a conductive liner 120a covering the side and bottom surfaces of the plug pattern 120b.

[0086] Next, we will refer to Figure 3C The above-disclosed gate contact plug 106 and supporting vertical structure 81 are described. Figure 3C yes Figure 2A A magnified view of region C in the diagram. One of the gate contact plugs 106 will be described below.

[0087] Combination Figures 1 to 3B refer to Figure 3C At the height between the lowest gate layer 32g_L and the highest gate layer 58g_U, similar to the side surface of the vertical storage structure 71, the side surface of the gate contact plug 106 includes N gate contact side surface slope changing portions 106s_1a and 106s_1b, which are disposed at substantially the same height as the N storage side surface slope changing portions 71s_1a and 71s_1b. At a height higher than the highest gate layer 58g_U, the gate contact plug 106 includes at least two upper side surface slope changing portions 106s_2a and 106s_2b.

[0088] In an embodiment, the first upper surface slope changing portion 106s_2a, which is located in the lower part of the at least two upper surface slope changing portions 106s_2a and 106s_2b of the gate contact plug 106, is located at substantially the same height as the upper surface slope changing portion 71s_2 of the vertical storage structure 71.

[0089] In an embodiment, the second upper surface slope changing portion 106s_2b, which is located on the upper part of at least two upper surface slope changing portions 106s_2a and 106s_2b of the gate contact plug 106, is located at a height higher than the upper surface of the vertical storage structure 71.

[0090] In one embodiment, the gate contact plug 106 includes: a plug pattern 108b; and a conductive liner 108a covering the side and bottom surfaces of the plug pattern 108b. The plug pattern 108b includes a conductive material (e.g., tungsten), and the conductive liner 108a includes a conductive material (e.g., Ti or TiN).

[0091] In one embodiment, the gate contact plug 106 includes a horizontal extension 106p that extends horizontally from the vertical portion to contact the gate pad GP. When the gate layer is disposed at a height lower than the gate pad GP that contacts the gate contact plug 106, as described above, a buffer insulating layer 103 is disposed between the gate layer and the gate contact plug 106 at a height lower than the gate pad GP, and overlaps with the horizontal extension 106p.

[0092] In this embodiment, similar to the side surface of the vertical storage structure 71, at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U, the side surface supporting the vertical structure 81 includes a plurality of N supporting side surface slope changing portions 87s_1a and 87s_1b, which are disposed at substantially the same height as the plurality of N storage side surface slope changing portions 71s_1a and 71s_1b. At a height higher than the uppermost gate layer 58g_U, the supporting vertical structure 81 includes an upper side surface slope changing portion 81s_2 disposed at substantially the same height as the upper side surface slope changing portion 71s_2 of the vertical storage structure 71.

[0093] In an embodiment, the supporting vertical structure 81 is formed of a material layer substantially the same as that of the vertical storage structure 71. For example, the supporting vertical structure 81 includes: a gap-filling insulating layer 73'; a channel material layer 75' covering the outer and bottom surfaces of the gap-filling insulating layer 73'; and a data storage structure 72' covering the outer and bottom surfaces of the channel material layer 75'. The data storage structure 72' includes: a first dielectric layer 72b' covering the outer and bottom surfaces of the channel material layer 75'; a data storage layer 72d' covering the outer and bottom surfaces of the first dielectric layer 72b'; and a second dielectric layer 72a' covering the outer and bottom surfaces of the data storage layer 72d'.

[0094] As described above, in the embodiment, at a height higher than the uppermost gate layer 58g_U, the side surface of the vertical storage structure 71, the side surface of each peripheral contact plug 111, the side surface supporting the vertical structure 81, and the side surface of each gate contact plug 106 include first slope changing portions 71s_2, 81s_2, 111s_2, and 106s_2a disposed at substantially the same height, and the side surface of each gate contact plug 106 includes a second slope changing portion 106s_2b disposed at a height higher than the first slope changing portions 71s_2, 81s_2, 111s_2, and 106s_2a.

[0095] Next, we will refer to Figure 4A and Figure 4B A semiconductor device according to a modified embodiment of the present invention is described. Figure 4A It is along Figure 1 A schematic cross-sectional view taken from line I-I', and Figure 4B It is along Figure 1 A schematic cross-sectional view taken from line II-II'. (Referring to...) Figure 4A and Figure 4BIn the description of the semiconductor device according to the modified embodiment of the present invention, the modified or replaced components of the above-described semiconductor device 1 will be described, and the description of components that are substantially the same as the above-described components, components that can be easily understood from the above-described components, or components that can be easily understood from the above-described drawings will be omitted.

[0096] refer to Figure 4A and Figure 4B In an embodiment, semiconductor device 1' includes a first structure LS and a second structure US disposed on the first structure LS. (Refer to above) Figure 2A and Figure 2B The described stacking structure GS, which includes at least three stacking groups GR1, GR2 and GR3, is replaced with a stacking structure GS', which includes at least four stacking groups GR1, GR2a, GR2b and GR3.

[0097] In an embodiment, the four stack groups GR1, GR2a, GR2b, and GR3 include: a lower stack group GR1; a first intermediate stack group GR2a disposed on the lower stack group GR1; a second intermediate stack group GR2b disposed on the first intermediate stack group GR2a; and an upper stack group GR3 disposed on the second intermediate stack group GR2b. The lower stack group GR1 includes alternately stacked lower interlayer insulating layers 32a and lower gate layers 32g, the first intermediate stack group GR2a includes alternately stacked first intermediate interlayer insulating layers 44a1 and first intermediate gate layers 44g1, the second intermediate stack group GR2b includes alternately stacked second intermediate interlayer insulating layers 44a2 and second intermediate gate layers 44g2, and the upper stack group GR3 includes alternately stacked upper interlayer insulating layers 58a and upper gate layers 58g.

[0098] In this embodiment, lower gate layers 32g are stacked and spaced apart to form a lower gate stack group, first intermediate gate layers 44g1 are stacked and spaced apart to form a first intermediate gate stack group, second intermediate gate layers 44g2 are stacked and spaced apart to form a second intermediate gate stack group, and upper gate layers 55g are stacked and spaced apart to form an upper gate stack group. In this regard, reference numerals 32g, 44g1, 44g2, and 55g can also be used to refer to the lower gate stack group, the first intermediate gate stack group, the second intermediate gate stack group, and the upper gate stack group, respectively.

[0099] In the embodiments, the terms "lower," "first intermediate," "second intermediate," and "upper" are used to distinguish the gate stack groups from each other and may be replaced by other terms. For example, the terms "lower," "first intermediate," "second intermediate," and "upper" may be replaced by the terms "first," "second," "third," and "fourth," respectively.

[0100] Similar to the reference above Figures 1 to 2BIn the described embodiment, the lower gate layer 32g, the first intermediate gate layer 44g1, the second intermediate gate layer 44g2, and the upper gate layer 58g include gate pads GP, which are located at the ends of the lower gate layer 32g, the first intermediate gate layer 44g1, the second intermediate gate layer 44g2, and the upper gate layer 58g and are arranged in a stepped shape in the second region SA.

[0101] In an embodiment, the second structure US further includes intermediate insulating structures 36, 48a, 48b, and 62 covering at least a portion of the stacked structure GS′. The intermediate insulating structures 36, 48a, 48b, and 62 include: a first intermediate insulating layer 36 covering the gate pad GP of the lower gate layer 32g on the lower structure LS; a second intermediate insulating layer 48a covering the gate pad GP of the first intermediate gate layer 44g1 on the first intermediate insulating layer 36; a third intermediate insulating layer 48b covering the gate pad GP of the second intermediate gate layer 44g2 on the second intermediate insulating layer 48a; and a fourth intermediate insulating layer 62 covering the gate pad GP of the upper gate layer 58g on the third intermediate insulating layer 48b.

[0102] In an embodiment, the second structure US further includes upper insulating structures 68, 84, 90, and 116, which include those referenced above. Figure 2A and Figure 2B The first to fourth upper insulating layers 68, 84, 90 and 116 are described as being substantially the same.

[0103] In the embodiments, the above references Figure 1 The described through region TA includes a lower horizontal insulating layer 32d, a first intermediate horizontal insulating layer 44d1, a second intermediate horizontal insulating layer 44d2, and an upper horizontal insulating layer 58d, which are respectively disposed at the same height as the lower gate layer 32g, the first intermediate gate layer 44g1, the second intermediate gate layer 44g2, and the upper gate layer 58g.

[0104] In an embodiment, the semiconductor device 1' further includes: a vertical storage structure 171 that penetrates at least the stacked structure GS' in the first region MCA; a supporting vertical structure 181 that penetrates the stacked structure GS' in the second region SA; and a separation structure 287 that penetrates at least the stacked structure GS'. The semiconductor device 1' also includes peripheral contact plugs 211, which include a first peripheral contact plug 211a, a second peripheral contact plug 211b, and a third peripheral contact plug 211c.

[0105] In the following text, reference will be made to Figure 5A The vertical storage structure 171 and the separate structure 287 disclosed above are described. Figure 5A yes Figure 4B A magnified view of a portion of region "A1".

[0106] Combination Figure 4A and Figure 4B refer to Figure 5A The side surface of the vertical storage structure 171 includes: side surface portions 171sa, 171sb1, 171sb2, 171sc, and 171sd, all having steep slopes; and side surface slope changing portions located between adjacent side surface portions 171sa, 171sb1, 171sb2, 171sc, and 171sd, having relatively gentle slopes. On the side surface of the vertical storage structure 171, the side surface slope changing portions may include: a plurality of N storage side surface slope changing portions 171s_1a, 171s_1ab, and 171s_1b disposed at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_L; and at least one upper side surface slope changing portion 171s_2 disposed at a height higher than the uppermost gate layer 58g_L.

[0107] In an embodiment, the side surface of the separation structure 287 includes: side surface portions 287sa, 287sb, 287sc, and 287sd, all having steep slopes; and side surface slope changing portions located between adjacent side surface portions 287sa, 287sb, 287sc, and 287sd, having relatively gentle slopes. On the side surface of the separation structure 287, the side surface slope changing portions include: a plurality of separation side surface slope changing portions 287s_1a and 287s_1b, numbered M, located at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U; and at least one upper side surface slope changing portion 287s_2 located at a height higher than the uppermost gate layer 58g_U. The slope changing part 171s_2 of the upper side surface of the vertical storage structure 171 and the slope changing part 287s_2 of the upper side surface of the separation structure 287 are set at substantially the same height.

[0108] In this embodiment, a plurality of M separate side surface slope changing portions 287s_1a and 287s_1b, located at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U, on the side surface of the separation structure 287, are located at substantially the same height as a plurality of M (M < N) memory side surface slope changing portions 171s_1ab and 171s_1b among the N memory side surface slope changing portions 171s_1a, 171s_1ab and 171s_1b. For example, M of the N memory side surface slope changing portions 171s_1a, 171s_1ab and 171s_1b (where M < N) are located at substantially the same height. For example, the M separate side surface slope changing sections 287s_1a and 287s_1b are located at approximately the same height as the M storage side surface slope changing sections 171s_1a, 171s_1ab and 171s_1b, which are located higher than the side surface slope changing section 171s_1a located at the bottommost position.

[0109] Both N and M are natural numbers, and N is greater than M. For example, N is a natural number of 3 or greater, and M is N-1. For example, N can be 3, and M can be 2.

[0110] Next, we will refer to Figure 5B Describe one of the peripheral contact plugs 211 disclosed above. Figure 5B yes Figure 4A A magnified view of a portion of region "B2a".

[0111] Combination Figure 4A , Figure 4B and Figure 5A refer to Figure 5B In an embodiment, the side surface of the peripheral contact plug 211 includes: side surface portions 211sa, 211sb1, 211sb2, 211sc, and 211sd, all having steep slopes; and side surface slope changing portions disposed between adjacent side surface portions 211sa, 211sb1, 211sb2, 211sc, and 211sd, having relatively gentle slopes. On the side surface of the peripheral contact plug 211, the side surface slope changing portions include: a plurality of peripheral contact side surface slope changing portions 211s_1a, 211s_1ab, and 211s_b, numbered N, located at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U; and at least one upper side surface slope changing portion 211s_2 located at a height higher than the height of the uppermost gate layer 58g_U.

[0112] In the embodiment, the N peripheral contact side surface slope changing parts 211s_1a, 211s_1ab, and 211s_b are located at the reference above. Figure 5A The N storage side surface slope change sections 171s_1a, 171s_1ab, and 171s_1b are described at essentially the same height.

[0113] In an embodiment, the slope change portion 211s_2 of the upper surface of the side surface of the peripheral contact plug 211 is located at substantially the same height as the slope change portion 171s_2 of the upper surface of the side surface of the vertical storage structure 171.

[0114] Next, we will refer to Figure 6 and Figure 7 A semiconductor device according to a modified embodiment of the present invention is described. Figure 6 It is along Figure 1 A schematic cross-sectional view taken from line II-II', and Figure 7 yes Figure 6 A magnified view of area "A2". (Refer to...) Figure 6 and Figure 7 When describing a semiconductor device according to a modified embodiment of the present invention, the above references will be described. Figure 4B and Figure 5A An example of a modification to the described separation structure 287.

[0115] refer to Figure 6 and Figure 7 In the embodiments, the above references Figure 4B and Figure 5A The described separation structure 287 was replaced with Figure 6 and Figure 7 The separation structure 387. For example, the side surface of the separation structure 387 includes: side surface portions 387sa, 387sb, and 387sc, all having steep slopes; and side surface slope changing portions located between adjacent side surface portions 387sa, 387sb, and 387sc, having relatively gentle slopes. On the side surface of the separation structure 387, the side surface slope changing portions include: N-2 separation side surface slope changing portions 387s_1 located at a height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U; and at least one upper side surface slope changing portion 387s_2 located at a height higher than the uppermost gate layer 58g_U. The upper side surface slope changing portions 171s_2 of the side surface of the vertical storage structure 171 and the upper side surface slope changing portions 387s_2 of the side surface of the separation structure 387 are located at substantially the same height.

[0116] As referenced above Figure 5AIn the embodiment, when the side surface of the vertical storage structure 171 located at the height between the lowermost gate layer 32g_L and the uppermost gate layer 58g_U includes N storage side surface slope changing parts 171s_1a, 171s_1ab and 171s_1b, N-2 is a natural number of 1 or greater, and N is a natural number of 3 or greater.

[0117] In the embodiment, the N-2 separate side surface slope changing sections 387s_1 are located at substantially the same height as the intermediate storage side surface slope changing section 171s_ab, which is disposed between the lower storage side surface slope changing section 171s_1a, 171s_1ab, and 171s_1b, and is disposed between the lower storage side surface slope changing section 171s_1a disposed at the bottom and the upper storage side surface slope changing section 171s_1b disposed at the top.

[0118] Refer to the above Figure 2A and Figure 2B In the described semiconductor device 1, in one embodiment, peripheral circuits 9 and 13 are disposed below the stacked structure GS. However, embodiments of the present invention are not limited thereto. For example, in other embodiments, peripheral circuits 9 and 13 are disposed on the stacked structure GS. (See reference...) Figure 8 An embodiment is described in which peripheral circuits 9 and 13 are arranged on a stacked structure GS. Figure 8 This is a schematic cross-sectional view of an example of a modification of a semiconductor device according to an embodiment of the present invention.

[0119] refer to Figure 8 In an embodiment, semiconductor device 1” includes a first chip structure CH1 and a second chip structure CH2 bonded to the first chip structure CH1. The second chip structure CH2 includes the patterned structure 23, insulating layer 26o and insulating layer 26i-2, stacked structure GS, intermediate insulating structures 36, 48 and 62, and upper insulating structures 68, 84, 90 and 116 as described above. The second chip structure CH2 also includes... Figure 2A The lower insulating structure 221 corresponds to the lower insulating structure 21. The second chip structure CH2 also includes a gate contact plug 106, which penetrates the gate pads GP of gate layers 32g, 44g, and 58g in the stepped region SA and is electrically connected to the gate pads GP. The second chip structure CH2 also includes the features described above. Figure 2A Vertical storage structure 71 Figure 2A The supporting vertical structure 81, the peripheral contact plug 111, and the separation structure ( Figure 2B 87) Figure 2A Upper contact plug 120 Figure 2A The bit line contact plug 119, Figure 2A bit lines 123, and Figure 2A124 peripheral interconnects.

[0120] In an embodiment, the second chip structure CH2 further includes a gate connection plug 121 disposed on the gate contact plug 106 and a gate interconnect 126 disposed on the gate connection plug 121.

[0121] In one embodiment, the second chip structure CH2 further includes: a first bonding pattern 155; and a first bonding insulating layer 150 surrounding the side surface of the first bonding pattern 155. The first bonding pattern 155 is electrically connected to bit lines 123, gate interconnects 126, and peripheral interconnects 124. The first bonding pattern 155 comprises metal (e.g., copper).

[0122] In an embodiment, the first chip structure CH1 includes components similar to those of the lower structure LS as described above. For example, the first chip structure CH1 includes: a semiconductor substrate 305; peripheral circuits 311 and 313 below the semiconductor substrate 305; a second bonding pattern 315 electrically connected to the peripheral circuits 311 and 313 and bonded to the first bonding pattern 155; and a second bonding insulating layer 321 bonded to the first bonding insulating layer 150.

[0123] In an embodiment, the first chip structure CH1 further includes: an insulating layer 360 disposed on a semiconductor substrate 305; input / output pads 380 disposed on the insulating layer 360; and an input / output connection pattern 370 that penetrates the semiconductor substrate 305 and the insulating layer 360 and electrically connects the input / output pads 380 to peripheral circuits 311 and 313.

[0124] Next, we will refer to Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B Examples of methods for forming semiconductor devices according to embodiments of the present invention are described. Figure 9A and Figure 9B This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention; and Figure 10A , Figure 10B , Figure 11A and Figure 11B This is a cross-sectional view of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 10A and Figure 11A It is along Figure 1 A schematic cross-sectional view taken from line I-I', and Figure 10B and Figure 11B It is along Figure 1 A schematic cross-sectional view taken from line II-II'.

[0125] refer to Figure 1 , Figure 9A , Figure 10A and Figure 10B In this embodiment, a lower structure LS is formed in operation S10. The lower structure LS may be referred to as the first structure. The formed lower structure LS includes: a semiconductor substrate 5; a device isolation layer 7s defining a peripheral active region 7a on the semiconductor substrate 5; peripheral circuits 9 and 13 formed on the semiconductor substrate 5; a peripheral pad 15 electrically connected to the peripheral circuits 9 and 13; and a lower insulating structure 21 covering the peripheral circuits 9 and 13 and the peripheral pad 15 on the semiconductor substrate 5. The peripheral circuits 9 and 13 include: circuit elements 9, such as transistors including a peripheral gate 9b and a peripheral source / drain 9a; and circuit interconnects 13 electrically connected to the circuit elements 9. The peripheral pad 15 is electrically connected to the circuit interconnects 13.

[0126] In one embodiment, the peripheral pads 15 include first peripheral pads to third peripheral pads 15a, 15b, and 15c. In another embodiment, each peripheral pad 15 includes a conductive material (e.g., a metal such as tungsten).

[0127] In an embodiment, the lower structure LS further includes: a capping layer 17 formed on each peripheral pad 15; and an etch stop layer 19 formed on the capping layer 17. In an embodiment, the capping layer 17 is formed of a silicon layer, and the etch stop layer 19 is formed of an insulating material (e.g., silicon oxide or silicon nitride).

[0128] In an embodiment, forming the lower structure LS further includes forming a patterned structure 23 and insulating layers 26i_1, 26i_2, and 26o on the lower insulating structure 21. Insulating layers 26i_1, 26i_2, and 26o include: an outer insulating layer 26o disposed outside the patterned structure 23; a first inner insulating layer 26i_1 penetrating the patterned structure 23; and a second inner insulating layer 26i_2 penetrating the patterned structure 23.

[0129] In an embodiment, the patterned structure 23 includes a plurality of patterned layers stacked sequentially. For example, the patterned structure 23 includes: a lower patterned layer 23a; an intermediate patterned layer 23b spaced apart from each other and disposed on the lower patterned layer 23a; and an upper patterned layer 23c disposed on the intermediate patterned layer 23b. At least one of the lower patterned layer 23a, the intermediate patterned layer 23b, and the upper patterned layer 23c is a silicon layer. For example, both the lower patterned layer 23a and the upper patterned layer 23c are silicon layers (e.g., silicon layers with N-type conductivity), and the intermediate patterned layer 23b is a material layer different from the silicon layer (e.g., a silicon oxide layer and / or a silicon nitride layer).

[0130] In an embodiment, a first molding group 30m is formed in operation S15. Forming the first molding group 30m includes: forming alternating and repeatedly stacked first interlayer insulating layers 32a and first sacrificial gate layers 32b; patterning the first interlayer insulating layers 32a and first sacrificial gate layers 32b to form a stepped shape; and forming a pad layer 34 on a portion of the stepped-shaped first sacrificial gate layer 32b. The pad layer 34 may be formed on the ends of the stepped-shaped first sacrificial gate layer 32b. The lowermost and uppermost layers of the first interlayer insulating layers 32a and first sacrificial gate layers 32b are the first interlayer insulating layers. The first interlayer insulating layer 32a is formed of silicon oxide. The first sacrificial gate layer 32b and pad layer 34 are formed of silicon nitride or polysilicon.

[0131] In one embodiment, a first intermediate insulating layer 36 is formed on the lower structure LS and covers the stepped portion of the stepped first sacrificial gate layer 32b and the pad layer 34.

[0132] In this embodiment, lower vertical sacrificial structures 39a, 39b, 39c, and 39d are formed in operation S20. The lower vertical sacrificial structures 39a, 39b, 39c, and 39d are respectively formed on the reference surface to be formed. Figure 2A and Figure 2B The area described includes the vertical storage structure 71, the supporting vertical structure 81, the gate contact plug 106, and the peripheral contact plug 111.

[0133] refer to Figure 1 , Figure 9A , Figure 9B , Figure 11A and Figure 11B In an embodiment, a second molding group 42m is formed in operation S25. Forming the second molding group 42m includes: forming alternating and repeatedly stacked second interlayer insulating layers 44a and second sacrificial gate layers 44b; patterning the second interlayer insulating layers 44a and second sacrificial gate layers 44b to form a stepped shape; and forming a pad layer 46 on a portion of the stepped-shaped second sacrificial gate layer 44b. The pad layer 46 may be formed on the ends of the stepped-shaped second sacrificial gate layer 44b. The lowest and highest layers of the second interlayer insulating layers 44a and second sacrificial gate layers 44b are second interlayer insulating layers. The second interlayer insulating layer 44a is formed of silicon oxide. The second sacrificial gate layer 44b and the pad layer 46 are formed of silicon nitride or polysilicon.

[0134] In one embodiment, a second intermediate insulating layer 48 is formed on the first intermediate insulating layer 36 and covers the stepped portion of the stepped second sacrificial gate layer 44b and the pad layer 46.

[0135] In this embodiment, during operation S30, intermediate vertical sacrificial structures 51a, 51b, 51c, and 51d are formed, respectively contacting the lower vertical sacrificial structures 39a, 39b, 39c, and 39d, and a lower sacrificial separation structure 52 is formed, penetrating the first molding group 30m and the second molding group 42m. The lower sacrificial separation structure 52 is spaced apart from the lower patterned layer 23a and contacts the upper patterned layer 23c. The lower sacrificial separation structure 52 is spaced apart from the intermediate patterned layer 23b.

[0136] In an embodiment, a third molding group 56m is formed in operation S35. Forming the third molding group 56m includes: forming alternating and repeatedly stacked third interlayer insulating layers 58a and third sacrificial gate layers 58b; patterning the third interlayer insulating layers 58a and third sacrificial gate layers 58b to form a stepped shape; and forming a pad layer 60 on a portion of the stepped-shaped third sacrificial gate layer 58b. The pad layer 60 may be formed on the ends of the stepped-shaped third sacrificial gate layer 58b. The bottom and top layers of the third interlayer insulating layers 58a and third sacrificial gate layers 58b are third interlayer insulating layers. The third interlayer insulating layer 58a is formed of silicon oxide. The third sacrificial gate layer 58b and the pad layer 60 are formed of silicon nitride or polysilicon.

[0137] In one embodiment, a third intermediate insulating layer 62 is formed on the second intermediate insulating layer 48 and covers the stepped portion of the stepped third sacrificial gate layer 58b and the pad layer 60.

[0138] In an embodiment, during operation S40, upper vertical sacrificial structures 64a, 64b, 64c and 64d are formed to contact the intermediate vertical sacrificial structures 51a, 51b, 51c and 51d respectively, and an upper sacrificial separation structure 65 is formed to penetrate the third molding group 56m to contact the lower sacrificial separation structure 52.

[0139] In the embodiment, the lower vertical sacrificial structures 39a, 39b, 39c and 39d, the middle vertical sacrificial structures 51a, 51b, 51c and 51d, and the upper vertical sacrificial structures 64a, 64b, 64c and 64d constitute vertical sacrificial structures 66a, 66b, 66c and 66d, and the lower sacrificial separation structure 52 and the upper sacrificial separation structure 65 constitute sacrificial separation structure 67.

[0140] In the embodiments, reference is now made to Figure 9BIn operation S45, vertical sacrificial structures 66a, 66b, 66c, and 66d are formed in the regions where the vertical storage structure 71, the supporting vertical structure 81, the gate contact plug 106, and the peripheral contact plug 111 will be formed, respectively. For example, the vertical sacrificial structures 66a, 66b, 66c, and 66d include: a storage sacrificial vertical structure 66a for forming the vertical storage structure 71; a supporting sacrificial vertical structure 66b for forming the supporting vertical structure 81; a peripheral contact vertical sacrificial structure 66c for forming the peripheral contact plug 111; and a gate contact sacrificial vertical structure 66d for forming the gate contact plug 106.

[0141] refer to Figure 1 , Figure 9B , Figure 11A , Figure 11B , Figure 2A and Figure 2B In one embodiment, a first upper insulating layer 68 is formed on the vertical sacrificial structures 66a, 66b, 66c and 66d, the third molding group 56m, and the third intermediate insulating layer 62.

[0142] In one embodiment, a hole is formed penetrating the first upper insulating layer 68, which exposes the storage sacrificial vertical structure 66a and the support sacrificial vertical structure 66b, respectively. The exposed storage sacrificial vertical structure 66a and the exposed support sacrificial vertical structure 66b are removed to form a storage vertical hole and a support vertical hole. A vertical storage structure 71 and a support vertical structure 81 are formed in the storage vertical hole and the support vertical hole, respectively.

[0143] In an embodiment, a second upper insulating layer 84 is formed on the first upper insulating layer 68. A preliminary gate contact plug is formed in operation S50. Forming the preliminary gate contact plug includes: forming a hole exposing the gate contact sacrificial vertical structure 66d, which sequentially passes through the second upper insulating layer 84 and the first upper insulating layer 68; removing the gate contact sacrificial vertical structure 66d exposed by the hole to form a preliminary gate contact hole; partially etching the sacrificial gate layer 32b, sacrificial gate layer 44b, and sacrificial gate layer 58b, as well as the pad layer 34, pad layer 56, and pad layer 60 exposed by the preliminary gate contact hole to form a space; and forming a filling layer through the partially... A buffer insulating layer 103 is formed by etching the spaces formed by the sacrificial gate layers 32b, 44b, and 58b that do not contact the pad layers 34, 56, and 60; and a material layer is formed that partially fills the spaces formed by partially etching the pad layers 34, 56, and 60 and the sacrificial gate layers 32b, 44b, and 58b that contact the pad layers 34, 56, and 60.

[0144] In an embodiment, an isolation trench is formed in operation S55. Forming the isolation trench includes: forming openings that sequentially penetrate the first upper insulating layer 68 and the second upper insulating layer 84, exposing the sacrificial separation structure 67; and removing the exposed sacrificial separation structure 67.

[0145] In one embodiment, a sacrificial spacer is formed on the sidewall of the isolation trench to expose the intermediate patterned layer at the lower portion of the intermediate patterned layer 23b in the first region MCA. The exposed intermediate patterned layer at the lower portion of the first region MCA is removed, and a first intermediate patterned layer 23b1 is formed in the space created by removing the exposed intermediate patterned layer. The sacrificial spacer is also removed. The intermediate patterned layer 23b at the lower portion of the second region SA is retained, and a second intermediate patterned layer 23b2 is formed.

[0146] In an embodiment, during operation S60, the sacrificial gate layers 32b, 44b, and 58b in the first to third molding groups 30m, 42m, and 56m are replaced by gate layers 32g, 44g, and 58g. For example, the sacrificial gate layers 32b, 44b, and 58b exposed by the isolation trench are etched to form a void, and gate layers 32g, 44g, and 58g are formed in the void.

[0147] In an embodiment, during the process of etching the sacrificial gate layer 32b, sacrificial gate layer 44b, and sacrificial gate layer 58b to form a void, the vertical storage structure 71 and the supporting vertical structure 81 serve as supports to prevent the interlayer insulating layers 32a, 44a, and 58a from bending or deforming.

[0148] In an embodiment, a portion of the sacrificial gate layer 32b, sacrificial gate layer 44b, and sacrificial gate layer 58b is retained in the through region TA to form horizontal insulating layers 32d, 44d, and 58d.

[0149] In one embodiment, a third upper insulating layer 90 is formed on the second upper insulating layer 84. In operation S70, a gate contact plug 106 and a peripheral contact plug 111 are formed. Forming the gate contact plug 106 and the peripheral contact plug 111 includes: forming a hole penetrating the third upper insulating layer 90 and exposing a preliminary gate contact plug; forming a hole penetrating the first upper insulating layer to the third upper insulating layers 68, 84, and 90 and exposing a peripheral contact vertical sacrificial structure 66c; removing the exposed preliminary gate contact plug and the exposed peripheral contact vertical sacrificial structure 66c to form a gate contact hole and a peripheral contact hole, respectively; and filling the gate contact hole and the peripheral contact hole with a conductive material, respectively. The buffer insulating layer 103 is retained while the exposed preliminary gate contact plug is removed.

[0150] In this embodiment, a fourth upper insulating layer 116 is formed on the third upper insulating layer 90. An interconnect process is performed in operation S75. Performing the interconnect process includes: forming a bit line contact plug 119 that penetrates the first upper insulating layer to the fourth upper insulating layers 68, 84, 90, and 116 and is electrically connected to the vertical memory structure 71; forming an upper contact plug 120 that penetrates the fourth upper insulating layer 116 and is electrically connected to a peripheral contact plug 111; and forming a bit line 123 and a peripheral interconnect 124.

[0151] Figure 12 A data storage system comprising a semiconductor device according to an embodiment of the present invention is illustrated schematically.

[0152] refer to Figure 12 According to an embodiment of the present invention, a data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including the semiconductor device 1100 or an electronic device including the storage device. For example, the data storage system 1000 may be a solid-state drive (SSD) device including the semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0153] In this embodiment, the data storage system 1000 is an electronic system for storing data.

[0154] In an embodiment, the semiconductor device 1100 may be based on the above reference. Figures 1 to 8 The semiconductor device described in any of the embodiments, or which may be referenced above, is... Figures 9A to 11B The method described is used to manufacture a semiconductor device. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0155] In an embodiment, the first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F includes the structure described above. Figure 2A 9. Peripheral circuit.

[0156] In an embodiment, the second structure 1100S is a memory cell structure, which includes a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0157] In an embodiment, the patterned structure 23 includes a silicon layer with N-type conductivity, and the N-type conductive silicon layer is a common source line (CSL).

[0158] In an embodiment, in the second structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 can be modified differently according to the embodiment.

[0159] In this embodiment, both upper transistors UT1 and UT2 include a string select transistor, and both lower transistors LT1 and LT2 include a ground select transistor. Lower gate line LL1 and lower gate line LL2 are the gate electrodes of lower transistor LT1 and lower transistor LT2, respectively. Word line WL is the gate electrode of the memory cell transistor MCT, and upper gate line UL1 and upper gate line UL2 are the gate electrodes of upper transistor UT1 and upper transistor UT2, respectively.

[0160] In the embodiment, the gate layers 32g, 44g and 58g constitute the lower gate line LL1 and LL2, the word line WL, and the upper gate line UL1 and UL2.

[0161] In this embodiment, both lower transistors LT1 and LT2 include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. Both upper transistors UT1 and UT2 include a series select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 is used for an erase operation to delete data stored in the memory cell transistor MCT using the gate-induced drain leakage (GIDL) phenomenon.

[0162] In the embodiment, the common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 are electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S.

[0163] In an embodiment, bit line BL is electrically connected to page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S. Bit line BL is bit line 123 as described above.

[0164] In an embodiment, in the first structure 1100F, decoder circuit 1110 and page buffer 1120 perform control operations on at least one selected memory cell transistor (MCT) from a plurality of memory cell transistors (MCTs). Decoder circuit 1110 and page buffer 1120 are controlled by logic circuit 1130. Semiconductor device 1000 communicates with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 are electrically connected to logic circuit 1130 via input / output interconnects 1135 extending from the first structure 1100F to the second structure 1100S.

[0165] In one embodiment, controller 1200 includes processor 1210, NAND controller 1220, and host interface 1230. In another embodiment, data storage system 1000 includes a plurality of semiconductor devices 1100. In this case, controller 1200 controls the plurality of semiconductor devices 1000.

[0166] In this embodiment, processor 1210 controls the overall operation of data storage system 1000 and controller 1200. Processor 1210 operates according to pre-loaded firmware and accesses semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 includes NAND interface 1221, which handles communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) can be sent. Host interface 1230 provides communication functionality between data storage system 1000 and an external host. When a control command is received from an external host through host interface 1230, processor 1210 controls semiconductor device 1100 in response to the control command.

[0167] Figure 13 It is a perspective view of a data storage system including semiconductor devices according to embodiments of the present invention.

[0168] refer to Figure 13 According to an embodiment of the present invention, a data storage system 2000 includes a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 via interconnect patterns 2005 formed on the main substrate 2001.

[0169] In one embodiment, the main substrate 2001 includes a connector 2006 comprising a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In one embodiment, the data storage system 2000 may communicate with the external host via any of a variety of interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In one embodiment, the data storage system 2000 operates via power supplied by the external host through the connector 2006. The data storage system 2000 also includes a power management integrated circuit (PMIC) that distributes the power received from the external host to the controller 2002 and the semiconductor package 2003.

[0170] In this embodiment, the controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0171] In this embodiment, DRAM 2004 is a buffer memory that mitigates the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 in the data storage system 2000 also operates as a high-speed cache memory and provides space for temporarily storing data during the control operations of the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to the NAND controller that controls the semiconductor package 2003, controller 2002 also includes a DRAM controller that controls DRAM 2004.

[0172] In an embodiment, the semiconductor package 2003 includes a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b is a semiconductor package including a plurality of semiconductor chips 2200. Each semiconductor chip 2200 includes, according to the above reference... Figure 1 The semiconductor device described in any of the embodiments of FIG3 or referenced above Figures 9A to 11B The semiconductor device is manufactured using the method described in the section on forming a semiconductor device.

[0173] In an embodiment, each of the first semiconductor package 2003a and the second semiconductor package 2003b includes: a package substrate 2100; a semiconductor chip 2200 on the package substrate 2100; an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200; a connection structure 2400 that electrically connects the semiconductor chip 2200 to the package substrate 2100; and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0174] In this embodiment, the package substrate 2100 is a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 includes input / output pads 2210.

[0175] In an embodiment, the connection structure 2400 is a bonding wire that electrically connects the input / output pads 2210 to the package-on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 are electrically connected to each other via bonding wires and can be electrically connected to the package-on-package pads 2130 of the package substrate 2100. Alternatively, according to an embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 are electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a bonding wire-type connection structure 2400.

[0176] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in a single package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on a separate insertion substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other via wiring formed on the insertion substrate.

[0177] Figure 14 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. Figure 14 It shows Figure 13 Semiconductor packaging 2003, and conceptually demonstrated Figure 13 The semiconductor package 2003 is cut off along line III-III'.

[0178] refer to Figure 14In this embodiment, the packaging substrate 2100 of the semiconductor package 2003 is a printed circuit board. The packaging substrate 2100 includes: a packaging substrate body portion 2120; an upper packaging pad 2130 disposed on the upper surface of the packaging substrate body portion 2120; a lower pad 2125 disposed on or exposed through the lower surface of the packaging substrate body portion 2120; and an internal interconnect 2135 that electrically connects the upper pad 2130 and the lower pad 2125 to each other within the packaging substrate body portion 2120. The upper pad 2130 is electrically connected to the connection structure 2400. The lower pad 2125 is connected to the interconnect pattern 2005 of the main substrate 2010 of the data storage system 2000 via a conductive connection portion 2800.

[0179] In an embodiment, each semiconductor chip 2200 includes: a semiconductor substrate 3010; and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes: a peripheral circuit region including a peripheral interconnect 3110. The second structure 3200 includes: a common source line 3205; a gate stack structure 3210 disposed on the common source line 3205; a memory channel structure 3220 and an isolation structure 3230 penetrating the gate stack structure 3210; a bit line 3240 electrically connected to the memory channel structure 3220; and a word line WL electrically connected to the gate stack structure 3210. Figure 2A The gate contact plug 106 is in the middle. The first structure 3100 includes Figure 12 The first structure 1000F, and the second structure 3200 include Figure 12 The second structure 1000S.

[0180] In an embodiment, each semiconductor chip 2200 includes a through interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through interconnect 3245 penetrates the gate stack structure 3210 and is also disposed outside the gate stack structure 3210.

[0181] In an embodiment, each semiconductor chip 2200 further includes: an input / output interconnect 3265 electrically connected to a peripheral interconnect 3110 of the first structure 3100 and extending into the second structure; and an input / input pad 2210 electrically connected to the input / output interconnect 3265.

[0182] exist Figure 14 In the embodiment, the enlarged portion of the semiconductor device 1, indicated by reference numeral 1, is shown. Figure 14 The semiconductor chip 2200 can be modified to include Figure 2A The cross-sectional structure is shown. Therefore, each semiconductor chip 2200 includes the cross-sectional structure as described above. Figures 1 to 8The semiconductor device 1 in any of the described embodiments or referenced above Figures 9A to 9B Semiconductor device 1 manufactured by the method described for forming a semiconductor device.

[0183] As described above, according to embodiments of the present invention, the integration density of the semiconductor device can be increased because the gate layers can be stacked in a vertical direction. Therefore, a semiconductor device with increased integration density and a data storage system including the semiconductor device can be provided.

[0184] According to embodiments of the present invention, a method is provided that simultaneously performs some semiconductor processes, including forming a vertical memory structure, supporting a vertical structure, gate contact plugs, peripheral contact plugs, and a discrete structure, while increasing the number of gate layers stacked in the vertical direction. Therefore, productivity can be increased, and the integration density of the semiconductor device can be increased.

[0185] While embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: First structure; The second structure includes a stacked structure and an insulating structure covering at least a portion of the stacked structure; A vertical storage structure, wherein the vertical storage structure penetrates at least the stacking structure; as well as A separation structure that penetrates at least the stacked structure, and the separation structure having an upper surface located at a height higher than the upper surface of the vertical storage structure. in, The stacked structure includes at least three gate stacks stacked vertically on the first structure. Each of the at least three gate stack groups comprises a plurality of gate layers stacked along the vertical direction and spaced apart from each other, and At the height between the lowest and highest gate layers in the stacked structure, the side surface of the vertical memory structure includes N memory side surface slope changing sections. The side surface of the separation structure includes M separation side surface slope changing sections, which are positioned at substantially the same height as M storage side surface slope changing sections out of a plurality of N storage side surface slope changing sections, where M < N. Where N is a natural number of 2 or greater, and Where M is a natural number of 1 or greater.

2. The semiconductor device according to claim 1, wherein, Each of the N storage-side surface slope changing sections and the M separation-side surface slope changing sections has a first slope between the upper and lower surface sections. The first slope is less steep than the slope of each of the upper and lower surface portions.

3. The semiconductor device according to claim 1, wherein, The at least three gate stack groups include a first gate stack group, a second gate stack group, and a third gate stack group stacked sequentially along the vertical direction. N is 2, and M is 1, and The separation side surface slope change section is located at the same height as the higher of the two storage side surface slope change sections.

4. The semiconductor device according to claim 1, wherein, The at least three gate stack groups include a first gate stack group, a second gate stack group, a third gate stack group, and a fourth gate stack group stacked sequentially along the vertical direction. N is 3, and M is 2, and The two separation side surface slope changing sections are located at substantially the same height as the two storage side surface slope changing sections that are positioned at a height higher than the lowest storage side surface slope changing section among the three storage side surface slope changing sections.

5. The semiconductor device according to claim 1, wherein, The at least three gate stack groups include a first gate stack group, a second gate stack group, a third gate stack group, and a fourth gate stack group stacked sequentially along the vertical direction. N is 3, and M is 1, and The separation side surface slope changing section is located at substantially the same height as the intermediate storage side surface slope changing section, which is situated between the lowest and highest storage side surface slope changing sections of the three storage side surface slope changing sections.

6. The semiconductor device according to claim 1, wherein, On the side surface of the vertical storage structure, a plurality of N storage side surface slope changing sections are disposed between the at least three gate stack groups that are adjacent to each other along the vertical direction.

7. The semiconductor device according to claim 1, wherein, At a height higher than the uppermost gate layer, the side surface of the vertical storage structure includes a first slope-changing section.

8. The semiconductor device according to claim 7, wherein, At a height higher than the uppermost grid layer, the side surface of the separation structure includes a second upward slope changing section.

9. The semiconductor device according to claim 8, wherein, The first slope changing section and the second slope changing section are located at substantially the same height.

10. The semiconductor device according to claim 1, further comprising: Supporting the vertical structure, in, The gate layers are stacked and spaced apart from each other in the first region of the second structure along the vertical direction, and the gate layers extend from the first region of the second structure to the second region of the second structure. The gate layer includes gate pads arranged in a stepped shape in the second region of the second structure. The vertical storage structure penetrates the gate layer in the first region of the second structure. The supporting vertical structure penetrates the gate layer in the second region of the second structure, and, At the height between the lowest gate layer and the highest gate layer, the side surface supporting the vertical structure includes: a plurality of N supporting side surface slope changing sections, each located at a height substantially the same as the plurality of N storage side surface slope changing sections.

11. The semiconductor device according to claim 1, further comprising: A peripheral contact plug that penetrates at least a portion of the second structure. Wherein, the peripheral contact plug is spaced apart from the gate layer of the stacked structure, and, At the height between the lowest gate layer and the highest gate layer, the side surface of the peripheral contact plug includes: a plurality of peripheral contact side surface slope changing portions, numbered N, located at substantially the same height as the plurality of storage side surface slope changing portions.

12. The semiconductor device according to claim 11, wherein, At a height higher than the uppermost gate layer, the side surface of the peripheral contact plug includes an upper slope changing portion. The upper surface of the peripheral contact plug is located at a height higher than the upper surface of the vertical storage structure, and The lower surface of the peripheral contact plug is located at a lower height than the lower surface of the vertical storage structure.

13. The semiconductor device according to claim 1, further comprising: Grid contact plug, in, The gate layers are stacked in the first region of the second structure along the vertical direction, and extend from the first region of the second structure into the second region of the second structure. The gate layer includes gate pads arranged in a stepped shape in the second region of the second structure. The gate contact plug penetrates the gate pad and is electrically connected to the gate pad. Each of the gate contact plugs includes a lower surface at a height lower than the lowest gate layer and an upper surface at a height higher than the highest gate layer, and, At the height between the lowest gate layer and the highest gate layer, the side surface of one of the gate contact plugs includes: a plurality of gate contact side surface slope changing portions of a number N located at substantially the same height as the plurality of storage side surface slope changing portions of a number N.

14. The semiconductor device according to claim 13, wherein, At a height higher than the uppermost gate layer, the side surface of one of the gate contact plugs includes at least two slope-changing portions.

15. The semiconductor device according to claim 1, wherein, The first structure includes: a semiconductor substrate; peripheral circuitry on the semiconductor substrate; peripheral pads electrically connected to the peripheral circuitry; and a patterned structure on the semiconductor substrate at a height higher than the peripheral pads. The separation structure has a lower surface that contacts the patterned structure. The vertical storage structure has a lower surface that contacts the patterned structure, and The lower surface of the vertical storage structure is located at a lower height than the lower surface of the separation structure.

16. The semiconductor device according to claim 15, wherein, The patterned structure includes a first patterned layer, a second patterned layer disposed on the first patterned layer, and a third patterned layer disposed on the second patterned layer. The vertical storage structure penetrates the second patterning layer and the third patterning layer and extends into the first patterning layer. The vertical storage structure includes: a gap-filling insulating layer; a channel material layer covering the side and bottom surfaces of the gap-filling insulating layer; a pad pattern on the gap-filling insulating layer in contact with the channel material layer; and a data storage structure covering at least the outer surface of the channel material layer. The data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer. The second patterned layer penetrates the data storage structure and contacts the channel material layer.

17. A semiconductor device, comprising: Lower structure; The upper structure includes a stacked structure and an insulating structure covering at least a portion of the stacked structure; A vertical storage structure, wherein the vertical storage structure penetrates at least the stacking structure; Peripheral contact plug; Multiple gate contact plugs; as well as A separation structure that at least penetrates the stacked structure and has a linear shape in a plan view. in, The stacked structure includes at least three gate stacks stacked vertically on the lower structure. Each of the at least three gate stack groups comprises gate layers stacked along the vertical direction and spaced apart from each other, and At the height between the lowest and highest gate layers in the stacked structure, the side surface of each vertical storage structure in the vertical storage structure and the side surface of each peripheral contact plug in the peripheral contact plug include a plurality of first slope changing portions in number N. The side surface of the separation structure includes M second slope-changing sections, which are located at substantially the same height as M of the N first slope-changing sections, where M < N. Where N and M are distinct natural numbers, and, At a height higher than the uppermost gate layer, the side surfaces of the vertical storage structure, the peripheral contact plugs, the separation structure, and each of the plurality of gate contact plugs include a first upward slope variation portion located at substantially the same height, and, The side surface of the separation structure is substantially vertical at the same height as the lowest of the multiple first slope changing sections, which are numbered N.

18. The semiconductor device according to claim 17, wherein, The gate layers are stacked in the first region of the upper structure along the vertical direction and extend from the first region of the upper structure to the second region of the upper structure. The gate layer includes gate pads arranged in a stepped shape in the second region of the upper structure. The gate contact plug is electrically connected to the gate pad, and At a height higher than the uppermost gate layer, the side surface of each gate contact plug also includes a second slope changing portion located at a height higher than the first slope changing portion. The first slope changing section, the second slope changing section, the first upper slope changing section, and the second upper slope changing section all have a first slope located between the upper surface section and the lower surface section, and The first slope is less steep than the slope of each of the upper and lower surface portions.

19. A data storage system, comprising: main substrate; Semiconductor devices are disposed on the main substrate; as well as A controller, electrically connected to the semiconductor device on the main substrate, The semiconductor device includes: Lower structure; The upper structure includes a stacked structure and an insulating structure covering at least a portion of the stacked structure; A vertical storage structure, wherein the vertical storage structure penetrates at least the stacking structure; Peripheral contact plug; Multiple gate contact plugs; and A separation structure that at least penetrates the stacked structure and has a linear shape in a plan view. in, The stacked structure includes at least three gate stacks stacked vertically on the lower structure. Each of the at least three gate stack groups comprises gate layers stacked along the vertical direction and spaced apart from each other, and At the height between the lowest and highest gate layers in the stacked structure, each of the side surfaces of the vertical storage structure and the peripheral contact plug includes a plurality of first slope changing portions, numbered N. The side surface of the separation structure includes M second slope-changing sections, which are located at substantially the same height as M of the N first slope-changing sections, where N and M are distinct natural numbers and M < N. At a height higher than the uppermost gate layer, the side surfaces of the vertical storage structure, the peripheral contact plugs, the separation structure, and each gate contact plug include a first upward slope variation at substantially the same height. At the same height as the lowest first slope changing section in the first slope changing section of the number N, the side surface of the separation structure is substantially vertical.

20. The data storage system according to claim 19, wherein, The gate layers are stacked in the first region of the upper structure along the vertical direction and extend from the first region of the upper structure into the second region of the upper structure. The gate layer includes gate pads arranged in a stepped shape in the second region of the upper structure. The gate contact plug is electrically connected to the gate pad, and At a height higher than the uppermost gate layer, the side surface of each gate contact plug also includes a second slope changing portion located at a height higher than the first slope changing portion. The first slope changing section, the second slope changing section, the first upper slope changing section, and the second upper slope changing section all have a first slope located between the upper surface section and the lower surface section, and The first slope is less steep than the slope of each of the upper and lower surface portions.

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