Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method of the semiconductor structure, the semiconductor structure comprising: a substrate; a semiconductor column on the substrate, the semiconductor column having a channel region and first and second source-drain regions on opposite sides of the channel region; the semiconductor column further comprising: a first doped region, the semiconductor column of the first doped region surrounding part of a side surface of the semiconductor column of the first source-drain region, and the semiconductor column of the first doped region being connected to the semiconductor column of the channel region, the doping ion type of the first doped region being different from the doping ion type of the first source-drain region, and the semiconductor column of the first doped region being grounded. The embodiment of the present disclosure is beneficial to inhibiting the floating body effect of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] In field-effect transistors (FETs), the floating body effect is common. This effect occurs when holes accumulate in the channel, creating a voltage that increases the drain current. The floating body effect causes a warping of the device's output characteristic curve, known as the Kink effect. The Kink effect has numerous adverse effects on device and circuit performance and reliability.

[0003] As the integration density of semiconductor devices increases, the size of memory devices such as dynamic random access memory (DRAM) is becoming smaller and smaller. Therefore, the structure of 3D DRAM is receiving increasing attention. In the 3D DRAM structure, semiconductor pillars are usually formed in a horizontal stack, and word lines or bit lines are usually arranged in a stepped manner to save space and improve integration density.

[0004] However, the current semiconductor structure is more prone to the buoyancy effect. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for preparing the semiconductor structure, which at least helps to suppress the buoyancy effect of the semiconductor structure.

[0006] This disclosure provides a semiconductor structure, including: a substrate; a semiconductor pillar located on the substrate, the semiconductor pillar having a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region; the semiconductor pillar further includes: a first doped region, the semiconductor pillar of the first doped region surrounding a portion of the side surface of the semiconductor pillar of the first source / drain region, and the semiconductor pillar of the first doped region being connected to the semiconductor pillar of the channel region, the dopant ion type of the first doped region being different from the dopant ion type of the first source / drain region, and the semiconductor pillar of the first doped region being used for electrical connection to ground.

[0007] In some embodiments, the dopant ion type in the channel region is the same as the dopant ion type in the first dopant region.

[0008] In some embodiments, the dopant ions in the channel region and the first doped region are P-type, the dopant ions in the first source / drain region and the second source / drain region are N-type, and the first source / drain region serves as the source of the transistor.

[0009] In some embodiments, the semiconductor pillar exposes a portion of the side surface of the semiconductor pillar in the first source / drain region, and the semiconductor pillar exposes the end face of the semiconductor pillar in the first doped region.

[0010] In some embodiments, the system further includes a grounding post electrically connected to the exposed semiconductor post end face of the first doped region.

[0011] In some embodiments, the system further includes: a first dielectric layer surrounding the side surface of the semiconductor pillar, and at least a portion of the first dielectric layer surrounding the side surface of the semiconductor pillar between the first source / drain region and the channel region; and a second dielectric layer surrounding the side surface of the semiconductor pillar, the second dielectric layer and the first dielectric layer being located on opposite sides of the first source / drain region, and the second dielectric layer surrounding at least a portion of the side surface of the semiconductor pillar of the first doped region.

[0012] In some embodiments, the side of the semiconductor pillar facing the first source / drain region toward the first dielectric layer is flush with the side of the first dielectric layer facing the first source / drain region, and the side of the semiconductor pillar facing the first source / drain region toward the second dielectric layer is flush with the side of the second dielectric layer facing the first source / drain region.

[0013] In some embodiments, a portion of the first dielectric layer is located on the surface of the semiconductor pillar of a portion of the first source / drain region, and a portion of the second dielectric layer is located on the surface of the semiconductor pillar of a portion of the first source / drain region.

[0014] In some embodiments, in the second direction, the thickness of the first dielectric layer is less than the thickness of the second dielectric layer, and the second direction is the direction from the channel region to the first source / drain region.

[0015] In some embodiments, the thickness of the first dielectric layer is 1 nm to 200 nm, and the thickness of the second dielectric layer is 30 nm to 500 nm.

[0016] In some embodiments, the ratio of the thickness of the first source / drain region in the first direction to the thickness of the semiconductor pillar in the first direction is less than 2 / 3, the first direction is the direction from the first source / drain region to the first doped region, and the first direction is perpendicular to the extension direction of the semiconductor pillar.

[0017] In some embodiments, it further includes: a bit line electrically connected to the semiconductor pillar side of the exposed first source / drain region.

[0018] In some embodiments, the size of the first source / drain semiconductor pillar is larger than the size of the second source / drain semiconductor pillar along the extension direction of the semiconductor pillar.

[0019] Accordingly, this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a semiconductor pillar on the substrate, the semiconductor pillar having a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region; further comprising: forming a first doped region in the semiconductor pillar, the semiconductor pillar of the first doped region surrounding a portion of the side surface of the semiconductor pillar of the first source / drain region, and the semiconductor pillar of the first doped region being connected to the semiconductor pillar of the channel region, the dopant ion type of the first doped region being different from the dopant ion type of the first source / drain region, and the semiconductor pillar of the first doped region being used for electrical connection to ground.

[0020] In some embodiments, the number of semiconductor pillars is multiple, and the multiple semiconductor pillars are stacked. The method for forming a first source / drain region includes: forming stacked semiconductor pillars on a substrate; forming a first isolation structure, the first isolation structure covering the side surfaces of the semiconductor pillars; etching a portion of the first isolation structure to expose the side surfaces of the semiconductor pillars to be formed as the first source / drain region; performing a doping process on the side surfaces of the semiconductor pillars to be formed as the first source / drain region to form an initial first source / drain region, the initial first source / drain region having first doped ions; and annealing the semiconductor pillars of the initial first source / drain region to transform the initial first source / drain region into the first source / drain region.

[0021] In some embodiments, the doping process is a plasma doping process.

[0022] In some embodiments, the method of forming a first doped region includes: forming a second isolation structure that covers the semiconductor pillar sidewalls of the first source / drain region; etching a portion of the first isolation structure to expose the semiconductor pillar sidewalls to which the first doped region is to be formed; performing a doping process on the semiconductor pillar sidewalls to which the first doped region is to be formed to form an initial first doped region, the initial first doped region having second doped ions; and performing an annealing process on the semiconductor pillars of the initial first doped region to transform the initial first doped region into a first doped region, wherein the type of the first doped ion is different from the type of the second doped ion.

[0023] In some embodiments, the method further includes: forming a first dielectric layer, the first dielectric layer surrounding the side surface of the semiconductor pillar, and at least a portion of the first dielectric layer surrounding the side surface of the semiconductor pillar between the first source / drain region and the channel region; forming a second dielectric layer, the second dielectric layer surrounding the side surface of the semiconductor pillar, the second dielectric layer and the first dielectric layer being located on opposite sides of the first source / drain region, and the second dielectric layer surrounding at least a portion of the side surface of the semiconductor pillar of the first doped region.

[0024] In some embodiments, a first dielectric layer and a second dielectric layer are formed before the step of forming the first source / drain region. The method of forming the first dielectric layer and the second dielectric layer includes: etching an initial isolation layer in a preset region to form a spaced first isolation trench and a second isolation trench, wherein the first isolation trench exposes a portion of the top surface of the substrate, and the second isolation trench exposes a portion of the top surface of the substrate, and in the direction from the first isolation trench to the second isolation trench, the width of the first isolation trench is smaller than the width of the second isolation trench; forming a first dielectric layer in the first isolation trench; and forming a second dielectric layer in the second isolation trench.

[0025] In some embodiments, the etched portion of the first isolation structure is: etching the first isolation structure between the first dielectric layer and the second dielectric layer, and exposing a portion of the top surface of the substrate.

[0026] The technical solutions provided in this disclosure have at least the following advantages:

[0027] In the semiconductor structure provided in this disclosure, the semiconductor pillar has a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region. The first source / drain region and the second source / drain region can serve as the source or drain of a transistor. The semiconductor pillar also includes a first doped region, with the semiconductor pillar of the first doped region surrounding a portion of the side surface of the semiconductor pillar of the first source / drain region. Thus, the remaining un-surrounded side surface can be used to connect bit lines. The semiconductor pillar of the first doped region is connected to the semiconductor pillar of the channel region, allowing the charge accumulated in the channel region to be transferred to the first doped region. Furthermore, the dopant ion type of the first doped region is different from that of the first source / drain region, ensuring that the first doped region does not interfere with the first source / drain region when it operates as the source of a transistor, thereby guaranteeing the normal operation of the semiconductor structure. Additionally, the semiconductor pillar with the first doped region is electrically connected to ground, allowing the charge accumulated in the channel to be discharged to ground through the first doped region, thereby suppressing the floating body effect. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0030] Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Figures 3 to 19 A schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure provided in another embodiment of this disclosure. Detailed Implementation

[0032] As can be seen from the background technology, there is a potential problem of buoyancy effect in current semiconductor structures.

[0033] Analysis revealed that one reason for the floating body effect in semiconductor structures is that, for field-effect transistors (FETs), under a sufficiently high drain voltage, electrons in the channel gain enough energy in the high-field region of the drain to generate electron-hole pairs through collisional ionization. Holes then move towards the channel region where the potential is lowered. Due to the high potential barrier at the gate-source junction, holes accumulate in the channel region, thus raising the potential of the channel region and forward biasing the gate-source junction. The positive potential on the floating body lowers the threshold voltage and increases the drain current, thereby producing the floating body effect.

[0034] This disclosure provides a semiconductor structure in which a first doped region is disposed within a semiconductor pillar. The first doped region surrounds a portion of the side surface of the semiconductor pillar containing a first source / drain region, and the semiconductor pillar containing the first doped region is connected to the semiconductor pillar containing the channel region. This allows accumulated charge in the channel region to be transferred to the first doped region. Furthermore, the dopant ion type in the first doped region differs from that in the first source / drain region, thus separating the first source / drain region from the first doped region and preventing electrical interference between them, ensuring the normal performance of the semiconductor structure. Additionally, the first doped region is used for grounding, allowing accumulated charge in the channel to be discharged to ground, thereby suppressing the floating body effect in the semiconductor structure.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0037] refer to Figure 1 as well as Figure 2The substrate; a semiconductor pillar 10 located on the substrate, the semiconductor pillar 10 having a channel region 101 and a first source / drain region 102 and a second source / drain region 103 located on opposite sides of the channel region 101; the semiconductor pillar 10 further includes: a first doped region 104, the semiconductor pillar 10 of the first doped region 104 surrounding a portion of the side surface of the semiconductor pillar 10 of the first source / drain region 102, and the semiconductor pillar 10 of the first doped region 104 being connected to the semiconductor pillar 10 of the channel region 101, the doping ion type of the first doped region 104 being different from the doping ion type of the first source / drain region 102, and the semiconductor pillar 10 of the first doped region 104 being used for electrical connection to ground.

[0038] The first doped region 104 is connected to the channel region 101, allowing charge in the channel region 101 to be transferred to the first doped region 104. The first doped region 104 is grounded, allowing charge in the channel region 101 to be discharged through it, thereby suppressing the floating body effect. Furthermore, the dopant ion type of the first doped region 104 is different from that of the first source / drain region 102, so that when the first source / drain region 102 is operating, it will not be interfered with by the dopant ions in the first doped region 104, thus maintaining optimal semiconductor structure performance.

[0039] The substrate is made of a semiconductor material. In some embodiments, the substrate is made of silicon. In other embodiments, the substrate may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0040] The semiconductor pillar 10 may be made of the same material as the substrate. In some embodiments, the semiconductor pillar 10 may be made of silicon.

[0041] In some embodiments, the dopant ion type of the channel region 101 is the same as that of the first doped region 104. Since the channel region 101 and the first doped region 104 are disposed in the same semiconductor pillar 10, i.e., the substrate material of the channel region 101 and the first doped region 104 is the same, setting the dopant ion type of the channel region 101 to be the same as that of the first doped region 104 allows the first doped region 104 to be considered an extension of the channel region 101. Thus, the charge moving towards the channel region 101 also moves towards the first doped region 104, allowing the first doped region 104 to bear a portion of the moving charge and improving the accumulation of charge in the channel region 101. Therefore, setting the dopant ion type of the first doped region 104 to be the same as that of the channel region 101 makes it easier for charge to be transferred to the first doped region 104 and discharged to ground, which is beneficial for further suppressing the floating body effect.

[0042] In some embodiments, the doped ions in the channel region 101 and the first doped region 104 are P-type, and the doped ions in the first source / drain region 102 and the second source / drain region 103 are N-type, with the first source / drain region 102 serving as the source of the transistor. The semiconductor structure can function as an NMOS transistor, where electrons move in the channel. Electrons in the channel gain sufficient energy in the high-field region at the drain end to generate electron-hole pairs, causing holes to move towards the lower-potential channel region 101. That is, holes move from the drain to the source, and due to the high potential barrier of the gate-source junction, holes accumulate in the channel region 101. Therefore, the first source / drain region 102 is set as the source of the transistor, that is, the holes move from the second source / drain region 103 to the first source / drain region 102, and the semiconductor pillars 10 of the first doped region 104 are arranged around the semiconductor pillars 10 of the first source / drain region 102. Therefore, when the holes move from the second source / drain region 103 to the channel region 101, they will flow into the first doped region 104, thereby enabling the first doped region 104 to play a better dissipation role.

[0043] In some embodiments, the semiconductor pillar 10 exposes a portion of the side surface of the semiconductor pillar 10 of the first source / drain region 102, and the semiconductor pillar 10 also exposes the end face of the semiconductor pillar 10 of the first doped region 104. The exposed portion of the side surface of the semiconductor pillar 10 of the first source / drain region 102 can be used to extract the electrical signal of the first source / drain region 102. By exposing the end face of the semiconductor pillar 10 of the first doped region 104, it is beneficial to extract the signal of the semiconductor pillar 10 of the first doped region 104 to the ground. In some embodiments, the entire end face of the semiconductor pillar 10 can be used as the end face of the semiconductor pillar 10 of the first doped region 104. Specifically, when the semiconductor pillar 10 is cuboid in shape, the semiconductor pillar 10 of the first doped region 104 can surround three sides of the semiconductor pillar 10 of the first source / drain region 102, exposing only the remaining side surface of the first source / drain region 102. This results in the first doped region 104 having a larger volume proportion in the entire semiconductor pillar 10, ensuring that the first doped region 104 can provide sufficient leakage capacity between the channel region 101 and the ground.

[0044] In some embodiments, the system further includes a grounding post 105, which is electrically connected to the exposed end face of the semiconductor pillar 10 of the first doped region 104. The grounding post 105 is used for coupling to a ground terminal and is also electrically connected to the semiconductor pillar 10 of the first doped region 104, allowing the charge transported in the semiconductor pillar 10 to be transferred to the ground terminal via the grounding post 105. This prevents the semiconductor pillar 10 of the first doped region 104 from failing to ground smoothly due to excessively small semiconductor structure size or excessively high integration. Furthermore, since the semiconductor end face of the first doped region 104 is also the end face of the semiconductor pillar 10, the relatively large operational space at the end face of the semiconductor pillar 10 makes the fabrication of the grounding post 105 at the end face of the semiconductor pillar 10 less difficult, which is beneficial for improving the yield of the semiconductor structure. Specifically, in some embodiments, the material of the grounding post 105 may be any one or a combination of doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), and titanium silicide (TiSi).

[0045] In some embodiments, the system further includes: a first dielectric layer 106, which surrounds the side of the semiconductor pillar 10, and at least a portion of the first dielectric layer 106 surrounds the side of the semiconductor pillar 10 between the first source / drain region 102 and the channel region 101; and a second dielectric layer 107, which surrounds the side of the semiconductor pillar 10, with the second dielectric layer 107 and the first dielectric layer 106 located on opposite sides of the first source / drain region 102, and the second dielectric layer 107 surrounding at least a portion of the side of the semiconductor pillar 10 of the first doped region 104. The first dielectric layer 106 serves to isolate the first source / drain region 102 from the channel region 101 and also provides support. Since the conductive pillar is placed horizontally relative to the substrate, the first dielectric layer 106 and the second dielectric layer 107 are arranged to surround the side of the semiconductor pillar 10. The first dielectric layer 106 and the second dielectric layer 107 have high rigidity, enabling them to support the semiconductor pillar 10 and prevent the semiconductor pillar 10 from breaking or collapsing on the substrate. The first dielectric layer 106 is provided to isolate the first source / drain region 102 from the channel region 101. Thus, when the word line is electrically connected to the semiconductor pillar 10 of the channel region 101 and the bit line is electrically connected to the semiconductor pillar 10 of the first source / drain region 102, the presence of the first dielectric layer 106 can isolate the word line and the bit line, preventing the word line and bit line from coming into contact with each other and causing electrical interference.

[0046] A second dielectric layer 107 is disposed around the semiconductor pillar 10, so that the second dielectric layer 107 can also serve to support the semiconductor pillar 10. Furthermore, the second dielectric layer 107 is disposed opposite to the first dielectric layer 106, and is located on opposite sides of the first source / drain region 102, and the second dielectric layer 107 also covers the side surface of the semiconductor pillar 10 of the first doped region 104. That is, the second dielectric layer 107 at least covers the side surface of the semiconductor pillar 10 between the first source / drain region 102 and the first doped region 104. Specifically, in some embodiments, the second dielectric layer 107 may be located between the end face of the first source / drain region 102 and the semiconductor pillar 10, that is, the second dielectric layer 107 covers the surface of the first source / drain region 102 facing the exposed semiconductor end of the first doped region 104. This prevents the semiconductor pillar 10 of the first source / drain region 102 from potentially contacting the grounding pillar 105 and causing the first source / drain region 102 to be grounded. This is because, since the grounding post 105 contacts the exposed semiconductor end face of the first doped region 104, and the first doped region 104 surrounds the first source / drain region 102, the distance between the first doped region 104 and the first source / drain region 102 is very close. When the grounding post 105 contacts the semiconductor post 10 of the first doped region 104, due to the small size of the semiconductor structure itself, and the excessive length of the push-well during the actual fabrication of the first source / drain region 102, the formed first source / drain region 102 extends towards the end face of the semiconductor post 10, making it easy for the grounding post 105 to contact the first source / drain region 102, thus causing the first source / drain region 102 to be grounded. Therefore, the second dielectric layer 107 can isolate the first source / drain region 102 from the exposed semiconductor post 10 end face of the first doped region 104, preventing the first source / drain region 102 from being electrically connected to the grounding post 105.

[0047] In some embodiments, the side of the first source / drain region 102 facing the semiconductor pillar 10 of the first dielectric layer 106 is flush with the side of the first dielectric layer 106 facing the first source / drain region 102, and the side of the first source / drain region 102 facing the semiconductor pillar 10 of the second dielectric layer 107 is flush with the side of the second dielectric layer 107 facing the first source / drain region 102. That is, the first source / drain region 102 is located between the first dielectric layer 106 and the second dielectric layer 107, meaning the distance between the first source / drain region 102 and the channel region 101 is at least the thickness of the first dielectric layer 106, thereby allowing the first dielectric layer 106 to effectively isolate the first source / drain region 102 from the channel region 101. The distance between the first source / drain region 102 and the end face of the semiconductor pillar 10 is at least the thickness of the second dielectric layer 107, so that the distance between the second dielectric layer 107 and the semiconductor end face of the exposed first doped region 104 is large. This can further prevent the semiconductor pillar 10 of the first source / drain region 102 from contacting the grounding pillar 105 located at the end face of the semiconductor pillar 10 of the exposed first doped region 104, thus preventing the first source / drain region 102 from being grounded.

[0048] In other embodiments, a portion of the first dielectric layer 106 is located on the surface of the semiconductor pillar 10 of a portion of the first source / drain region 102, and a portion of the second dielectric layer 107 is located on the surface of the semiconductor pillar 10 of a portion of the first source / drain region 102. This is because, due to the actual fabrication process of the first source / drain region 102, when performing push-well processing on the semiconductor pillar 10 to form the first source / drain region 102, the push-well depth of the first source / drain region 102 may be relatively deep, resulting in a closer distance between the first source / drain region 102 and the end face of the semiconductor pillar 10. Therefore, a portion of the first source / drain region 102 will be located at the semiconductor pillar 10 corresponding to the first dielectric layer 106, and a portion of the first source / drain region 102 will also be located at the semiconductor pillar 10 corresponding to the second dielectric layer 107.

[0049] For the reasons mentioned above, in some embodiments, it is necessary to set the thickness of the first dielectric layer 106 and the thickness of the second dielectric layer 107 to be relatively large, so as to prevent the first source / drain region 102 from passing through the first dielectric layer 106 and the second dielectric layer 107 due to the excessive depth of the push-in pit during the actual fabrication of the first source / drain region 102, so that the first dielectric layer 106 and the second dielectric layer 107 can play a better isolation role.

[0050] Since the second dielectric layer 107 also prevents the semiconductor pillars 10 of the first source / drain region 102 from being exposed to the outside, thus avoiding the problem of electrical connection between the semiconductor pillars 10 of the first source / drain region 102 and the ground pillar 105, in order to ensure that the second dielectric layer 107 can play a better isolation role, in some embodiments, the thickness of the first dielectric layer 106 can be set to be less than the thickness of the second dielectric layer 107 in the second direction, where the second direction is the direction from the channel region to the first source / drain region. That is, the thickness of the second dielectric layer 107 is larger. Given that the thickness of the first dielectric layer 106 is already large enough to prevent the first source / drain region 102 from passing through the first dielectric layer 106, setting the thickness of the second dielectric layer 107 to be larger than the thickness of the first dielectric layer 106 can further ensure that the first source / drain region 102 will not pass through the second dielectric layer 107. This allows the second dielectric layer 107 to better isolate the first source / drain region 102 from the exposed semiconductor end face of the first doped region 104, further avoiding the problem of the first source / drain region 102 being grounded.

[0051] In some embodiments, the thickness d1 of the first dielectric layer 106 can be 1 nm to 200 nm, and the thickness d2 of the second dielectric layer 107 can be 30 nm to 500 nm. Within this thickness range, on the one hand, the thickness of the first dielectric layer 106 and the second dielectric layer 107 is relatively large, thereby providing better isolation. On the other hand, the thickness of the first dielectric layer 106 and the second dielectric layer 107 is not excessively large, thereby reducing the overall size of the semiconductor structure and improving the integration density of the semiconductor device.

[0052] In some embodiments, the second dielectric layer 107 only covers a portion of the side surface of the semiconductor pillar 10 of the first doped region 104, meaning that the second dielectric layer 107 also exposes a portion of the side surface of the semiconductor pillar 10 of the first doped region 104. Specifically, the exposed side surface of the semiconductor pillar 10 of the first doped region 104 is located between the second dielectric layer 107 and the end face of the semiconductor pillar 10 of the first doped region 104, meaning that the distance between the end face of the second dielectric layer 107 away from the first source / drain region 102 and the end face of the semiconductor pillar 10 of the first doped region 104 is greater than 0. This ensures that the distance between the first source / drain region 102 and the exposed end face of the first doped region 104 at least includes the exposed side surface of the semiconductor pillar 10 of the first doped region 104 by the second dielectric layer 107, thereby further increasing the distance between the first source / drain region 102 and the exposed end face of the semiconductor pillar 10 of the first doped region 104, further preventing the first source / drain region 102 from grounding. Specifically, in some embodiments, the distance d3 between the side of the second dielectric layer 107 away from the first source / drain region 102 and the end face of the semiconductor pillar 10 of the first doped region 104 can be 10nm to 50nm.

[0053] It is understood that in other embodiments, the side of the second dielectric layer 107 away from the first source / drain region 102 may be flush with the end face of the semiconductor pillar 10, that is, the second dielectric layer 107 covers the side of the semiconductor pillar 10 of the first doped region 104 between the first source / drain region 102 and the semiconductor end face.

[0054] Specifically, in some embodiments, the first dielectric layer 106 and the second dielectric layer 107 may be made of the same material, specifically a type of nitride, such as silicon nitride.

[0055] In some embodiments, a third dielectric layer 108 may be provided between the second source / drain region 103 and the channel region 101, so that the third dielectric layer 108 serves both to isolate the channel region 101 and the second source / drain region 103 and to support the semiconductor pillar 10.

[0056] In some embodiments, the ratio of the thickness d4 of the first source / drain region 102 in the first direction X to the thickness d5 of the semiconductor pillar 10 in the first direction X is less than 2 / 3. The first direction X is the direction from the first source / drain region 102 to the first doped region 104, and the first direction X is perpendicular to the extension direction of the semiconductor pillar 10. It is understood that since the first doped region 104 surrounds the first source / drain region 102, the sum of the thickness of the first source / drain region 102 in the first direction X and the thickness of the first doped region 104 in the first direction X is equal to the thickness of the semiconductor pillar 10 in the first direction X. Since the thickness of the semiconductor pillar 10 is fixed, the greater the thickness of the first source / drain region 102 in the first direction X, the smaller the thickness of the first doped region 104 in the first direction X. Based on this, the thickness of the first source / drain region 102 in the first direction X is set to be less than 2 / 3 of the thickness of the semiconductor pillar 10 in the first direction X. That is, the thickness of the first source / drain region 102 in the first direction X is controlled to be not too large, thereby providing more space for the first doped region 104, so that the thickness of the semiconductor pillar 10 in the first doped region 104 is not too small, and thus the charge accumulated in the channel region 101 can pass smoothly through the first doped region 104, ensuring that there is sufficient leakage capacity between the channel and ground.

[0057] In some embodiments, along the extension direction of the semiconductor pillar 10, the size of the semiconductor pillar 10 of the first source / drain region 102 is larger than the size of the semiconductor pillar 10 of the second source / drain region 103, and the extension direction of the semiconductor pillar 10 is different from the first direction X. Since the sides of the semiconductor pillar 10 of the first source / drain region 102 are surrounded by the semiconductor pillar 10 of the first doped region 104, the thickness of the semiconductor pillar 10 of the first source / drain region 102 in the first direction X is less than the thickness of the semiconductor pillar 10 in the first direction X, while the thickness of the semiconductor pillar 10 of the second source / drain region 103 in the first direction X is equal to the thickness of the semiconductor pillar 10 in the first direction X. Therefore, it can be seen that the thickness of the first source / drain region 102 in the first direction X is less than the thickness of the second source / drain region 103 in the first direction X. In order to make the charge transfer performance of the first source / drain region 102 and the second source / drain region 103 similar when they are used as source and drain, thereby maintaining good performance of the semiconductor structure, the size of the semiconductor pillar 10 of the first source / drain region 102 is larger than the size of the semiconductor pillar 10 of the second source / drain region 103 along the extension direction of the semiconductor pillar 10. This makes the overall volume of the semiconductor pillar 10 of the first source / drain region 102 similar to the overall volume of the semiconductor pillar 10 of the second source / drain region 103, thus achieving similar charge transfer performance.

[0058] In some embodiments, the system further includes a bit line 109 electrically connected to the side of the exposed semiconductor pillar 10 of the first source / drain region 102. This allows the bit line 109 to draw out electrical signals from the first source / drain region 102. In some embodiments, when a plurality of stacked semiconductor pillars 10 are disposed on a substrate and the plurality of semiconductor pillars 10 are disposed parallel to the substrate surface, a bit line 109 can be electrically connected to the side of the semiconductor pillar 10 of the first source / drain region 102 in each of the stacked semiconductor pillars 10, allowing one bit line 109 to draw out electrical signals from the first source / drain regions 102 of the plurality of semiconductor pillars 10.

[0059] In some embodiments, the substrate further includes a plurality of arrayed semiconductor pillars 10 and a plurality of bit lines 109, and the plurality of arrayed semiconductor pillars 10 are disposed on the same layer. In each arrayed semiconductor pillar 10, the side of each first source / drain region 102 of the semiconductor pillar 10 forms an electrical connection with each bit line 109.

[0060] In some embodiments, bit line 109 may include a barrier layer, a conductive layer, and an insulating layer sequentially stacked along a direction away from the first source / drain region 102. In some embodiments, the conductive layer may be a metallic material, such as any one of tungsten, copper, or aluminum; in other embodiments, the conductive layer may be a semiconductor material, such as polysilicon. The barrier layer prevents interdiffusion between the conductive layer and the first source / drain region 102, and the barrier layer may be made of titanium nitride. The insulating layer isolates the conductive layer from other conductive devices in the semiconductor structure, and the insulating layer may be made of silicon oxide or silicon nitride.

[0061] In some embodiments, a word line 110 is further included, which is electrically connected to the side of the semiconductor pillar 10 of the channel region 101. The word line 110 can serve as the gate of the semiconductor structure, used to conduct the channel region 101 based on a control signal to realize carrier transport between the source and drain. In some embodiments, the word line 110 is arranged perpendicularly to the bit line 109 to select a semiconductor pillar 10. In some embodiments, when multiple stacked semiconductor pillars 10 are provided on the substrate, multiple word lines 110 are also provided. Each word line 110 is electrically connected to the side of the semiconductor pillar 10 of each channel region 101, and each word line 110 is perpendicular to the bit line 109, that is, the word line 110 is arranged parallel to the substrate surface. Since multiple word lines are arranged parallel to the substrate surface, in order to extract the electrical signal of each word line 110 and to prevent electrical interference between each word line 110, multiple word lines 110 are arranged in a stepped manner, so that each word line 110 can extract an electrical signal independently.

[0062] In some embodiments, when the substrate also has a plurality of arrayed semiconductor pillars 10, and the plurality of arrayed semiconductor pillars 10 are disposed in the same layer, a word line 110 may be provided to electrically connect all the channel regions 101 of a column of semiconductor pillars 10 arranged along the first direction X. In some embodiments, the material of the word line 110 may be at least one of tungsten, molybdenum, titanium, cobalt or ruthenium.

[0063] In some embodiments, the device may further include a gate dielectric layer (not shown) located between the word line 110 and the semiconductor pillars 10 of the channel region 101. The gate dielectric layer isolates the word line 110 from the semiconductor pillars 10 of the channel region 101. The gate dielectric layer is located on the surface of the semiconductor pillars 10 of the channel region 101, making the transistor composed of the group of semiconductor pillars 10 a low-voltage device. In other words, due to the presence of the gate dielectric layer, a smaller voltage is applied to the transistor to turn it on and complete data writing, thereby improving the performance of the semiconductor structure. In some embodiments, the material of the gate dielectric layer may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0064] In some embodiments, the system further includes a capacitor structure 112 electrically connected to the semiconductor pillar 10 of the second source / drain region 103. Specifically, the capacitor structure 112 may include a lower electrode layer (not shown), a capacitor dielectric layer (not shown), and an upper electrode layer (not shown) stacked sequentially along a direction away from the semiconductor pillar 10. The materials of the lower electrode layer and the upper electrode layer may be the same, and both materials may be at least one of platinum nickelide, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the materials of the lower electrode layer and the upper electrode layer may be different. The capacitor dielectric layer may be made of high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, and titanium oxide. In some embodiments, a fourth dielectric layer 111 may be provided between the semiconductor pillar 10 of the second source / drain region 103 and the capacitor structure 112, and the fourth dielectric layer 111 is disposed around the side of the semiconductor pillar 10. The fourth dielectric layer 111 serves to isolate the second source / drain region 103 from the capacitor structure 112, and also serves to support the semiconductor pillar 10.

[0065] In the semiconductor structure technical solution provided in the above-disclosed embodiments, by setting the first doped region 104 to be connected to the channel region 101, the charge in the channel region 101 can be transferred to the first doped region 104. Furthermore, the first doped region 104 is grounded, allowing the charge in the channel region 101 to be discharged through the first doped region 104, thereby suppressing the floating body effect. Additionally, the dopant ion type of the first doped region 104 is different from the dopant ion type of the first source / drain region 102. Therefore, when the first source / drain region 102 is operating, it will not be interfered with by the dopant ions in the first doped region 104, thus maintaining optimal semiconductor structure performance.

[0066] Accordingly, this disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0067] Figure 3 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 4 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction.

[0068] refer to Figure 3 as well as Figure 4 A substrate 100 is provided, and in some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate 100, a germanium-silicon substrate 100, a silicon carbide substrate 100, or a silicon-on-insulator substrate 100.

[0069] refer to Figures 3 to 19 Semiconductor pillars 10 are formed on substrate 100 (reference) Figure 2 The semiconductor pillar 10 has a channel region 101 (reference). Figure 2 ) and the first source / drain regions 102 located on opposite sides of the channel region 101 (reference) Figure 2 ) and the second source / drain region 103 (reference) Figure 2 It also includes: forming a first doped region 104 in the semiconductor pillar 10 (see reference). Figure 2 The semiconductor pillar 10 of the first doped region 104 surrounds a portion of the side surface of the semiconductor pillar 10 of the first source / drain region 102, and the semiconductor pillar 10 of the first doped region 104 is connected to the semiconductor pillar 10 of the channel region 101. The doped ion type of the first doped region 104 is different from that of the first source / drain region 102, and the semiconductor pillar 10 of the first doped region 104 is used for electrical connection to ground.

[0070] The first doped region is connected to the channel region so that the charge in the channel region can be transferred to the first doped region. The first doped region is grounded so that the current in the channel region can be discharged through the first doped region, thereby suppressing the floating body effect.

[0071] The first and second source / drain regions can serve as the source and drain of a semiconductor structure, respectively. In some embodiments, the dopant ion types in the first and second source / drain regions are the same. In some embodiments, when the semiconductor structure is used to form a junction transistor, the dopant ion types in the first and second source / drain regions are different from those in the channel region. For example, the dopant ion type in the channel region is P-type, and the dopant ion type in the first and second source / drain regions is N-type. In other embodiments, when the semiconductor structure is used to form a junctionless transistor, the dopant ion types in the first and second source / drain regions are the same as those in the channel region.

[0072] In some embodiments, the number of semiconductor pillars 10 is multiple, and the multiple semiconductor pillars 10 are stacked, wherein the multiple semiconductor pillars 10 are arranged parallel to the surface of the substrate 100, thereby improving the integration of the semiconductor device.

[0073] Formation of the first source / drain region 102 (reference) Figure 2 The methods include: (refer to) Figure 3 as well as Figure 16 Stacked semiconductor pillars 10 are formed on the substrate 100;

[0074] Figure 5 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 6 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction.

[0075] The method of forming the semiconductor pillar 10 may include: referencing Figures 3 to 6 Stacked initial semiconductor pillars 11 are formed on the substrate 100, with the initial semiconductor pillars 11 parallel to the surface of the substrate 100. Each of the stacked initial semiconductor pillars 11 is used to form subsequent semiconductor pillars 10. To prevent electrical interference between the subsequently formed semiconductor pillars 10 due to mutual contact, an initial isolation layer 12 is also formed during the formation of the initial semiconductor pillars 11. The initial isolation layer 12 is located between adjacent initial semiconductor pillars 11, serving both a supporting function for the multiple initial semiconductor pillars 11 and an isolation function. In some embodiments, the material of the initial semiconductor pillars 11 can be the same as the material of the substrate 100.

[0076] Specifically, in some embodiments, an initial isolation layer 12 and an initial semiconductor pillar 11 stacked on top of each other can be sequentially formed on a substrate 100 using an epitaxial process. The substrate 100 can be a silicon substrate, the initial semiconductor pillar 11 is made of the same material as the substrate 100, and the initial isolation layer 12 can be made of silicon germanide. When forming silicon germanide on the substrate 100 using an epitaxial process, since both the silicon substrate and silicon germanide contain silicon, and the lattice constants of the silicon substrate and silicon germanide are compatible, silicon germanide can be grown more easily using the silicon in the silicon substrate. This simplifies the fabrication process, and the resulting initial isolation layer 12 and initial semiconductor pillar 11 have high film quality and clear boundaries.

[0077] In some embodiments, the system further includes a capping layer 13, which is located on the surface of the topmost initial semiconductor pillar 11 and serves to protect the initial semiconductor pillar 11. In some embodiments, the capping layer 13 may be made of silicon oxide.

[0078] refer to Figure 5 as well as Figure 6 Multiple initial semiconductor pillars 11 are etched to form multiple semiconductor pillars 10. Simultaneously, multiple initial isolation layers 12 are etched so that the sidewalls of the initial isolation layers 12 are flush with the sidewalls of the semiconductor pillars 10. Specifically, in some embodiments, the step of forming multiple semiconductor pillars 10 may include: patterning the surface of the initial semiconductor pillars 11 to define the positions of the semiconductor pillars 10; and performing an etching process on the patterned initial semiconductor pillars 11 to form multiple stacked semiconductor pillars 10. In some embodiments, self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP) may be used to pattern the substrate 100.

[0079] In some embodiments, after forming the stacked semiconductor pillars 10, an initial isolation structure 14 is formed, which encloses the stacked semiconductor pillars 10 and the initial isolation layer 12 to isolate the semiconductor pillars 10 from other conductive elements in the semiconductor structure.

[0080] Figure 7 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 8 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction; Figure 9 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 10 Corresponding to Figure 2A schematic diagram of the cross-sectional structure along the bb' direction; Figure 11 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 12 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction.

[0081] refer to Figures 7 to 12 In some embodiments, the method further includes: forming a first dielectric layer 106, the first dielectric layer 106 surrounding the side of the semiconductor pillar 10, and at least a portion of the first dielectric layer 106 surrounding the side of the semiconductor pillar 10 between the first source / drain region 102 and the channel region 101; forming a second dielectric layer 107, the second dielectric layer 107 surrounding the side of the semiconductor pillar 10, the second dielectric layer 107 and the first dielectric layer 106 being located on opposite sides of the first source / drain region 102, and the second dielectric layer 107 surrounding at least a portion of the side of the semiconductor pillar 10 of the first doped region 104.

[0082] The first dielectric layer 106 serves two purposes: firstly, it isolates the first source / drain region 102 from the channel region 101, and secondly, it provides support. Since the conductive pillar is placed horizontally relative to the substrate 100, the first dielectric layer 106 and the second dielectric layer 107 are arranged around the side of the semiconductor pillar 10, thus supporting the semiconductor pillar 10 and preventing it from breaking or collapsing on the substrate 100.

[0083] A second dielectric layer 107 is disposed around the semiconductor pillar 10, so that the second dielectric layer 107 can also serve to support the semiconductor pillar 10. Furthermore, the second dielectric layer 107 is disposed opposite to the first dielectric layer 106, and is located on opposite sides of the first source / drain region 102. That is, the second dielectric layer 107 at least covers the side surface of the semiconductor pillar 10 between the first source / drain region 102 and the first doped region 104. Specifically, in some embodiments, the second dielectric layer 107 may be located between the end face of the first source / drain region 102 and the semiconductor pillar 10, thus preventing the semiconductor pillar 10 of the first source / drain region 102 from potentially contacting the grounding pillar 105 and causing the first source / drain region 102 to be grounded.

[0084] In some embodiments, a first dielectric layer 106 and a second dielectric layer 107 may be formed before the step of forming the first source / drain region 102. The method for forming the first dielectric layer 106 and the second dielectric layer 107 includes:

[0085] refer to Figures 3 to 6 Initial semiconductor pillars 11 are stacked on a substrate 100; an initial isolation layer 12 is formed between adjacent initial semiconductor pillars 11, and a portion of the initial isolation layer 12 and a portion of the initial semiconductor pillars 11 are etched to form semiconductor pillars 10.

[0086] refer to Figure 7 as well as Figure 8 The initial isolation layer 12 in the preset region is etched to form a first isolation trench 15 and a second isolation trench 16 spaced apart. The first isolation trench 15 exposes a portion of the top surface of the substrate 100, and the second isolation trench 16 exposes a portion of the top surface of the substrate 100. In the direction from the first isolation trench 15 to the second isolation trench 16, the width of the first isolation trench 15 is smaller than the width of the second isolation trench 16. It is worth noting that since the first dielectric layer 106 and the second dielectric layer 107 need to surround the side of the semiconductor pillar 10 in the preset region, only the initial isolation layer 12 in the preset region is etched, and the semiconductor pillar 10 in the preset region is not etched. Specifically, in some embodiments, since the material of the initial isolation layer 12 is silicon germanide and the material of the semiconductor pillar 10 is silicon, selective etching can be achieved by using different etching ratios for the initial isolation layer 12 and the semiconductor pillar 10. The etching process can be either dry etching or wet etching. The first isolation trench 15 and the second isolation trench 16 are exposed on the surface of the substrate 100. That is, the etching process simultaneously etches the stacked multilayer initial isolation layers 12. When the first dielectric layer 106 and the second dielectric layer 107 are formed in the first isolation trench 15 and the second isolation trench 16, the formed first dielectric layer 106 can surround the side of the stacked multilayer semiconductor pillar 10, and the second dielectric layer 107 can surround the side of the stacked multilayer semiconductor pillar 10, so that the first dielectric layer 106 and the second dielectric layer 107 can support the multilayer semiconductor pillar 10.

[0087] The width of the first isolation trench 15 is smaller than the width of the second isolation trench 16. Thus, when the first dielectric layer 106 is formed in the first isolation trench 15 and the second dielectric layer 107 is formed in the second isolation trench 16, the thickness of the first dielectric layer 106 is less than the thickness of the second dielectric layer 107. Setting the thickness of the second dielectric layer 107 to be greater than the thickness of the first dielectric layer 106 ensures that the subsequently formed first source / drain region 102 will not penetrate the second dielectric layer 107. This allows the second dielectric layer 107 to effectively isolate the first source / drain region 102 from the exposed semiconductor end face of the first doped region 104, avoiding the grounding problem of the first source / drain region 102.

[0088] refer to Figure 9 as well as Figure 10A first dielectric layer 106 is formed in a first isolation tank 15; and a second dielectric layer 107 is formed in a second isolation tank 16. In some embodiments, a deposition process can be used to deposit the materials of the first dielectric layer 106 and the second dielectric layer 107 in the first isolation tank 15 and the second isolation tank 16, respectively. The deposition process can be either a thermal oxidation process or an atomic layer deposition process. The deposited materials of the first dielectric layer 106 and the second dielectric layer 107 are mechanically polished using a CMP (Chemical Mechanical Polishing) process to make the top surfaces of the formed first dielectric layer 106 and the second dielectric layer 107 flat.

[0089] refer to Figure 11 as well as Figure 12 A first isolation structure 17 is formed, which covers each initial semiconductor pillar 11. A first dielectric layer and a second dielectric layer located on the top surface of the initial isolation structure 14 are processed using a CMP process to make the first dielectric layer and the second dielectric layer flush with the top surface of the initial isolation structure 14. In some embodiments, the method of forming the first isolation structure 17 may include: etching the initial isolation layer 12 to remove it, exposing the top surface and side surface of the semiconductor pillar 10; after removing the initial isolation layer 12, forming the first isolation structure 17 in the original position of the initial isolation layer 12, with the first isolation structure 17 covering the side surface of the semiconductor pillar 10. In some embodiments, the material of the first isolation structure 17 may be the same as that of the initial isolation structure 14, i.e., both are silicon oxide. Silicon oxide has good insulating properties, enabling the first isolation structure 17 to provide good isolation.

[0090] Figure 13 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 14 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction.

[0091] refer to Figure 13 as well as Figure 14 The first isolation structure 17 is etched to expose the side surface of the semiconductor pillar 10 to be formed as the first source / drain region 102. Specifically, the etching can be performed in the first direction X (refer to...). Figure 2The first isolation structure 17 on a portion of the semiconductor pillar 10 is etched to expose the side surface of the semiconductor pillar 10 in the first direction X, while the remaining semiconductor pillar 10 remains enclosed by the remaining portion of the first isolation structure 17. Thus, when a subsequent doping process is performed on the side surface of the semiconductor pillar 10, only the exposed side surface of the semiconductor pillar 10 will be doped, while the semiconductor pillar 10 enclosed by the remaining portion of the first isolation structure 17 will not be doped, thereby converting the portion of the semiconductor pillar 10 in the first direction X into the first source / drain region 102. Specifically, in some embodiments, the etching process of the portion of the first isolation structure 17 includes: patterning the surface of the first isolation structure 17 to define the location of the first source / drain region 102 to be formed; and etching the patterned first isolation structure 17 to expose the side surface of the semiconductor pillar 10 to be formed into the first source / drain region 102. Specifically, in some embodiments, SAQP or SADP processes can be used to pattern the substrate 100.

[0092] In some embodiments, when the first dielectric layer 106 and the second dielectric layer 107 are formed, the first isolation structure 17 between the first dielectric layer 106 and the second dielectric layer 107 can be etched, exposing a portion of the top surface of the substrate 100. Thus, during the subsequent doping process of the semiconductor pillars 10, only the sides of the semiconductor pillars 10 located between the first dielectric layer 106 and the second dielectric layer 107 are doped, allowing the formed first source / drain regions 102 to be located between the first dielectric layer 106 and the second dielectric layer 107, enabling the first dielectric layer 106 and the second dielectric layer 107 to isolate the first source / drain regions 102. Furthermore, by exposing a portion of the top surface of the substrate 100, the etching process exposes the sides of multiple stacked semiconductor pillars 10, allowing simultaneous doping of the sides of multiple stacked semiconductor pillars 10 during the doping process, which helps to save process steps.

[0093] Figure 15 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 16 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction.

[0094] refer to Figure 15 as well as Figure 16 The semiconductor pillar 10 to which the first source / drain region 102 is to be formed is subjected to a doping process to form an initial first source / drain region, which has first doped ions. It is understood that, due to the doping process, the push depth of the first source / drain region 102 is relatively large when the doping process is actually performed. Therefore, some of the first doped ions will diffuse into the semiconductor pillar 10 covered by the remaining part of the first isolation structure 17.

[0095] In some embodiments, when an etching process is performed on the side of the semiconductor pillar 10 between the first dielectric layer 106 and the second dielectric layer 107, the first doped ions also diffuse into the semiconductor pillar 10 corresponding to a portion of the first dielectric layer 106 and a portion of the second dielectric layer 107, such that the formed first source / drain region 102 is also located in the semiconductor pillar 10 corresponding to a portion of the first dielectric layer 106 and a portion of the second dielectric layer 107. Based on this, the thickness of the formed first dielectric layer 106 and the second dielectric layer 107 can be set to be relatively large, thereby preventing the formed first source / drain region 102 from penetrating through the first dielectric layer 106 and the second dielectric layer 107.

[0096] In some embodiments, the doping process is a plasma diffusion process. Compared to the example implantation process, the plasma diffusion process results in a shallower doping depth in the semiconductor pillar 10, thereby preventing the push-in depth of the first source / drain region 102 from being too large, thus reserving more space for the subsequent formation of the first doped region 104 surrounding the first source / drain region 102.

[0097] The semiconductor pillar 10 of the initial first source / drain region is annealed to transform the initial first source / drain region into the first source / drain region 102. After the diffusion process, the semiconductor pillar 10 of the initial first source / drain region is annealed to repair the lattice defects caused by the ion doping process during the doping process, so that the formed first source / drain region 102 has better performance.

[0098] Figure 17 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 18 as well as Figure 19 Corresponding to Figure 2 A schematic diagram of the cross-sectional structure along the bb' direction.

[0099] refer to Figures 17 to 19 In some embodiments, the method of forming the first doped region 104 includes forming a second isolation structure 18, the second isolation structure 18 covering the side of the semiconductor pillar 10 of the first source / drain region 102, so that when the semiconductor pillar 10 outside the first source / drain region 102 is subsequently doped, the second isolation structure 18 protects the first source / drain region 102 and prevents the semiconductor pillar 10 of the first source / drain region 102 from being doped with other dopant ions.

[0100] Specifically, refer to Figure 17 as well as Figure 18The method for forming the second isolation structure 18 may include: depositing material of the second isolation structure 18 on the side of the semiconductor pillar 10 corresponding to the first source / drain region 102 using a deposition process, wherein the material of the second isolation structure 18 covers the side of the semiconductor pillar 10 of each stacked first source / drain region 102; and mechanically polishing the deposited material of the second isolation structure 18 using a CMP process so that the top surface of the formed second isolation structure 18 is flush with the top surface of the isolation structure. In some embodiments, the material of the second isolation structure 18 may be the same as the material of the first isolation structure 17.

[0101] refer to Figure 19 The first isolation structure 17 is etched to expose the side surface of the semiconductor pillar 10 to which the first doped region 104 is to be formed; in some embodiments, the first isolation structure 17 is etched (refer to...) Figure 17 The process includes: patterning the surface of the first isolation structure 17 to define the location of the first doped region 104 to be formed; and etching the patterned first isolation structure 17 to expose the side surface of the semiconductor pillar 10 to be formed the first doped region 104. Specifically, in some embodiments, SAQP or SADP processes can be used to pattern the substrate 100.

[0102] The semiconductor pillar 10 to which the first doped region 104 is to be formed is subjected to a doping process to form an initial first doped region, which has second doped ions; in some embodiments, a plasma diffusion process can be used to dope the semiconductor pillar 10 to which the first doped region 104 is to be formed.

[0103] The semiconductor pillar 10 of the initial first doped region is annealed to transform the initial first doped region into a first doped region 104, where the type of the first doped ion is different from that of the second doped ion. Specifically, during the doping process, the type of the second doped ion is different from that of the first doped ion, so that when the first source / drain region 102 operates as the source of the transistor, the first doped region 104 will not interfere with the first source / drain region 102, thereby ensuring the normal operation of the semiconductor structure.

[0104] In some embodiments, the semiconductor pillar 10 exposes the end face of the semiconductor pillar 10 of the first doped region 104. It also includes a ground pillar 105, which is electrically connected to the exposed end face of the semiconductor pillar 10 of the first doped region 104 and is used for grounding. Forming the ground pillar 105 can prevent the semiconductor pillar 10 of the first doped region 104 from failing to ground smoothly due to the small size of the semiconductor structure or excessive integration. The method of forming the ground pillar 105 may include: etching a partial isolation structure to form a first via, the first via exposing the end face of the semiconductor pillar 10; and forming the ground pillar 105 in the ground pillar 105 using a deposition process. The material of the ground pillar 105 can be any or a combination of doped Si, doped Ge, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten silicide (WSi), cobalt silicide (CoSi), and titanium silicide (TiSi).

[0105] In some embodiments, the method of forming the channel region 101 may include: after forming the first doped region 104, forming a third isolation structure, the third isolation structure covering the side surface of the semiconductor pillar 10 of the first doped region 104; etching the isolation structure on the side surface of the semiconductor pillar 10 to be formed of the channel region 101 to expose the side surface of the semiconductor pillar 10 to be formed of the channel region 101 and the end face of the first doped region 104, so that the subsequently formed channel region 101 can contact the first doped region 104, and the charge accumulated in the channel region 101 can be discharged to the ground terminal through the first doped region 104; and performing a doping process on the semiconductor pillar 10 to be formed of the channel region 101. In some embodiments, the type of dopant ions in the channel region 101 may be the same as the type of dopant ions in the first doped region 104, thereby facilitating the transfer of charge accumulated in the channel region 101 to the first doped region 104 and being discharged to the ground terminal.

[0106] In the semiconductor structure fabrication method provided in the above embodiments, the first doped region 104 is connected to the channel region 101, allowing the charge in the channel region 101 to be transferred to the first doped region 104. Furthermore, the first doped region 104 is grounded, allowing the charge accumulated in the channel region 101 to be discharged through the first doped region 104, thereby suppressing the floating body effect. Moreover, the dopant ion type of the first doped region 104 is different from the dopant ion type of the first source / drain electrode, so that when the first source / drain region 102 is working, it will not be interfered with by the dopant ions in the first doped region 104, maintaining the normal performance of the semiconductor structure.

[0107] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A semiconductor pillar located on the substrate, the semiconductor pillar having a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region; The semiconductor pillar further includes: a first doped region, wherein the semiconductor pillar of the first doped region surrounds a portion of the side of the semiconductor pillar of the first source / drain region, and the semiconductor pillar of the first doped region is connected to the semiconductor pillar of the channel region, wherein the doping ion type of the first doped region is different from the doping ion type of the first source / drain region, and the semiconductor pillar of the first doped region is used for electrical connection to ground.

2. The semiconductor structure according to claim 1, characterized in that, The type of doped ions in the channel region is the same as the type of doped ions in the first doped region.

3. The semiconductor structure according to claim 2, characterized in that, The doped ions in the channel region and the first doped region are P-type, and the doped ions in the first source / drain region and the second source / drain region are N-type, with the first source / drain region serving as the source of the transistor.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor pillar exposes a portion of the side surface of the semiconductor pillar in the first source / drain region, and the semiconductor pillar exposes the end face of the semiconductor pillar in the first doped region.

5. The semiconductor structure according to claim 4, characterized in that, Also includes: A grounding post is electrically connected to the exposed semiconductor pillar end face of the first doped region.

6. The semiconductor structure according to claim 1 or 5, characterized in that, Also includes: A first dielectric layer surrounds the side of the semiconductor pillar, and at least a portion of the first dielectric layer surrounds the side of the semiconductor pillar between the first source / drain region and the channel region. A second dielectric layer surrounds the side surface of the semiconductor pillar, the second dielectric layer and the first dielectric layer are located on opposite sides of the first source / drain region, and the second dielectric layer surrounds at least a portion of the side surface of the semiconductor pillar of the first doped region.

7. The semiconductor structure according to claim 6, characterized in that, In the second direction, the side of the first source / drain region facing the semiconductor pillar of the first dielectric layer is flush with the side of the first dielectric layer facing the first source / drain region, and the side of the first source / drain region facing the semiconductor pillar of the second dielectric layer is flush with the side of the second dielectric layer facing the first source / drain region. The second direction is the direction in which the channel region points to the first source / drain region.

8. The semiconductor structure according to claim 6, characterized in that, A portion of the first dielectric layer is located on the surface of the semiconductor pillars of a portion of the first source / drain region, and a portion of the second dielectric layer is located on the surface of the semiconductor pillars of a portion of the first source / drain region.

9. The semiconductor structure according to claim 6, characterized in that, In the second direction, the thickness of the first dielectric layer is less than the thickness of the second dielectric layer, and the second direction is the direction from the channel region to the first source / drain region.

10. The semiconductor structure according to claim 6, characterized in that, The thickness of the first dielectric layer is 1 nm to 200 nm, and the thickness of the second dielectric layer is 30 nm to 500 nm.

11. The semiconductor structure according to claim 1 or 4, characterized in that, The ratio of the thickness of the first source / drain region in the first direction to the thickness of the semiconductor pillar in the first direction is less than 2 / 3. The first direction is the direction from the first source / drain region to the first doped region, and the first direction is perpendicular to the extension direction of the semiconductor pillar.

12. The semiconductor structure according to claim 1 or 4, characterized in that, Also includes: Bit lines are electrically connected to the exposed semiconductor pillar sides of the first source / drain regions.

13. The semiconductor structure according to claim 1, characterized in that, Along the extension direction of the semiconductor pillar, the size of the first source / drain region semiconductor pillar is larger than the size of the second source / drain region semiconductor pillar.

14. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A semiconductor pillar is formed on the substrate, the semiconductor pillar having a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region; It also includes: forming a first doped region in the semiconductor pillar, the semiconductor pillar of the first doped region surrounding a portion of the side of the semiconductor pillar of the first source / drain region, and the semiconductor pillar of the first doped region being connected to the semiconductor pillar of the channel region, the doping ion type of the first doped region being different from the doping ion type of the first source / drain region, and the semiconductor pillar of the first doped region being used for electrical connection to ground.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The method for forming the first source / drain region by having multiple semiconductor pillars stacked together includes: Stacked semiconductor pillars are formed on the substrate; A first isolation structure is formed, wherein the first isolation structure covers the side surface of the semiconductor pillar; The first isolation structure is etched to expose the sidewalls of the semiconductor pillars to be formed for the first source / drain region; The semiconductor pillar sidewall to be formed is doped to form an initial first source / drain region, wherein the initial first source / drain region has a first doped ion. The semiconductor pillars of the initial first source / drain region are annealed to transform the initial first source / drain region into the first source / drain region.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The doping process is a plasma doping process.

17. The method for preparing a semiconductor structure according to claim 15, characterized in that, The method for forming the first doped region includes: A second isolation structure is formed, which covers the sidewalls of the semiconductor pillars of the first source / drain region; The first isolation structure is etched to expose the side surface of the semiconductor pillar to which the first doped region is to be formed; A doping process is performed on the side surface of the semiconductor pillar to be formed into the first doped region to form an initial first doped region, wherein the initial first doped region has second doped ions; The semiconductor pillar of the initial first doped region is annealed to transform the initial first doped region into a first doped region, wherein the type of the first doped ion is different from that of the second doped ion.

18. The method for preparing a semiconductor structure according to claim 15, characterized in that, Also includes: A first dielectric layer is formed, the first dielectric layer surrounds the side surface of the semiconductor pillar, and at least a portion of the first dielectric layer surrounds the side surface of the semiconductor pillar between the first source / drain region and the channel region; A second dielectric layer is formed, which surrounds the side surface of the semiconductor pillar. The second dielectric layer and the first dielectric layer are located on opposite sides of the first source / drain region, and the second dielectric layer surrounds at least a portion of the side surface of the semiconductor pillar of the first doped region.

19. The method for preparing a semiconductor structure according to claim 18, characterized in that, The method for forming the first dielectric layer and the second dielectric layer before the step of forming the first source / drain region includes: Initial semiconductor pillars are stacked on the substrate; An initial isolation layer is formed, the initial isolation layer being located between adjacent initial semiconductor pillars; The initial isolation layer in the preset area is etched to form a first isolation trench and a second isolation trench spaced apart. The first isolation trench exposes a portion of the top surface of the substrate, and the second isolation trench exposes a portion of the top surface of the substrate. In the direction from the first isolation trench to the second isolation trench, the width of the first isolation trench is smaller than the width of the second isolation trench. The first dielectric layer is formed in the first isolation trench; and, The second dielectric layer is formed in the second isolation trench.

20. The method for preparing a semiconductor structure according to claim 18, characterized in that, The first isolation structure of the etched portion is: etching the first isolation structure between the first dielectric layer and the second dielectric layer, and exposing part of the top surface of the substrate.

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