Transistor and method of manufacturing the same, semiconductor structure and method of manufacturing the same
By designing a transistor with a surround structure and increasing the effective channel length, the problems of transistor breakdown under high voltage and insufficient drive current are solved, thereby improving the performance and data retention capacity of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-06-08
- Publication Date
- 2026-06-19
AI Technical Summary
Existing transistors are easily broken down under high voltage and have insufficient drive current, which leads to increased power consumption and shortened data retention life of memory devices.
Design a transistor structure in which a first channel region surrounds a first doped region, a second doped region surrounds the first channel region, and a third doped region surrounds the second doped region. The effective channel length is increased and the hot carrier effect is reduced by adjusting the doping concentration and shape.
It increases the transistor's punch-through voltage, increases the drive current, reduces the device's leakage current, and improves memory performance and data retention lifespan.
Smart Images
Figure CN115132829B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a transistor and a method for manufacturing the same, and a semiconductor structure and a method for manufacturing the same. Background Technology
[0002] Transistors, as switching and driving devices, are widely used in static random access memory, microcontrollers, microprocessors, and other digital logic circuit systems. Field-effect transistors (FETs) are voltage-controlled elements. In some semiconductor structures, such as the peripheral circuits of memory, a large number of FETs are arranged to perform logic operations. Therefore, transistors play a crucial role in semiconductor memory.
[0003] However, transistors in related technologies still have many problems that need to be improved. Summary of the Invention
[0004] In view of the above, embodiments of the present disclosure provide a transistor and a method for manufacturing the same, as well as a semiconductor structure and a method for manufacturing the same.
[0005] In a first aspect, embodiments of this disclosure provide a transistor, the transistor comprising:
[0006] First doped region;
[0007] The first channel region is disposed around the first doped region;
[0008] The second doped region is disposed around the first channel region;
[0009] The first gate is located on the first channel region;
[0010] A gate oxide layer is located between the first channel region and the first gate.
[0011] In the above scheme, the first doped region includes a source region and the second doped region includes a drain region; or, the first doped region includes a drain region and the second doped region includes a source region.
[0012] In the above scheme, the first gate at least covers the first channel region.
[0013] In the above scheme, the transistor further includes a third doped region; the third doped region includes a first sub-doped region and a second sub-doped region, the first sub-doped region surrounds the second doped region, the second sub-doped region is located between the first channel region and the second doped region and surrounds the first channel region.
[0014] In the above scheme, the doping concentration of the third doped region is less than the doping concentration of the first doped region and the second doped region.
[0015] In the above scheme, the first gate covers the first channel region, a portion of the first doped region, and a portion of the second sub-doped region.
[0016] In the above scheme, the shapes of the second doped region, the first channel region, and the first gate in the plane on the top surface of the first channel region all include annular shapes.
[0017] In the above scheme, the ring includes a circular ring and an elliptical ring.
[0018] In the above scheme, the transistor further includes:
[0019] The second channel region is disposed around the second doped region;
[0020] A fourth doped region is disposed around the second channel region;
[0021] The second gate is located on the second channel region, and the orthographic projection of the second gate onto the plane containing the top surface of the second channel region at least covers the second channel region;
[0022] When the first doped region includes a source region and the second doped region includes a drain region, the fourth doped region includes a source region;
[0023] When the first doped region includes a drain region and the second doped region includes a source region, the fourth doped region includes a drain region.
[0024] Secondly, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure including a plurality of transistors as described in any of the above embodiments, and the plurality of transistors are arranged in an array;
[0025] The semiconductor structure further includes an isolation structure; the isolation structure is located between the plurality of transistors and is used to isolate the plurality of transistors.
[0026] In the above scheme, the plurality of transistors includes a plurality of alternating first row transistors and second row transistors;
[0027] The centers of two adjacent transistors in each of the first row of transistors are C1 and C2, respectively. The center of the transistor in each of the second row of transistors is C3, which has the smallest sum of distances to the two adjacent transistors in the first row of transistors. The line connecting C1, C2, and C3 forms an equilateral triangle.
[0028] Thirdly, embodiments of this disclosure further provide a method for manufacturing a transistor, comprising:
[0029] Provide a first semiconductor layer;
[0030] The first semiconductor layer is etched to form a first semiconductor pillar; the first semiconductor pillar includes a first portion, a second portion surrounding the first portion, and a third portion surrounding the second portion;
[0031] A gate oxide layer is formed on the first semiconductor pillar;
[0032] A second semiconductor layer is formed on the gate oxide layer;
[0033] The second semiconductor layer is etched to form the first gate.
[0034] A first doped region is formed in the first portion, and a second doped region is formed in the third portion; after the first and second doped regions are formed, the second portion constitutes a first channel region.
[0035] In the above scheme, forming a first doped region in the first part and forming a second doped region in the third part includes:
[0036] A source region is formed in the first part, and a drain region is formed in the third part; or, a drain region is formed in the first part, and a source region is formed in the third part.
[0037] The method in the above scheme further includes:
[0038] Before forming the first doped region and the second doped region, a third doped region is formed in the third portion; the third doped region includes a first sub-doped region and a second sub-doped region, the first sub-doped region surrounding the second doped region, the second sub-doped region being located between the first channel region and the second doped region and surrounding the first channel region.
[0039] In the above scheme, the doping concentration of the third doped region is less than the doping concentration of the first doped region and the second doped region.
[0040] In the above scheme, the first semiconductor pillar further includes a fourth part and a fifth part, the fifth part surrounding the fourth part, and the fourth part surrounding the third part;
[0041] The etching process of the second semiconductor layer to form a first gate, wherein the first gate at least covers the second portion, includes:
[0042] The second semiconductor layer is etched to form a first gate and a second gate, wherein the first gate at least covers the second portion and the second gate at least covers the fourth portion;
[0043] The method further includes:
[0044] After the first gate is formed, a fourth doped region is formed in the fifth portion; after the fourth doped region is formed, the fourth portion constitutes a second channel region.
[0045] In the above scheme, when the first doped region includes a source region and the second doped region includes a drain region, the fourth doped region includes a source region;
[0046] When the first doped region includes a drain region and the second doped region includes a source region, the fourth doped region includes a drain region.
[0047] Fourthly, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, wherein a plurality of transistors are manufactured using the transistor manufacturing method described in any of the above embodiments, and the plurality of transistors are arranged in an array.
[0048] The method further includes:
[0049] An isolation structure is formed between the plurality of transistors; the isolation structure is used to isolate the plurality of transistors.
[0050] In the above scheme, the plurality of transistors includes a plurality of alternating first row transistors and second row transistors;
[0051] The centers of two adjacent transistors in each of the first row of transistors are C1 and C2, respectively. The center of the transistor in each of the second row of transistors is C3, which has the smallest sum of distances to the two adjacent transistors in the first row of transistors. The line connecting C1, C2, and C3 forms an equilateral triangle.
[0052] This disclosure provides a transistor and a method for manufacturing the same, as well as a semiconductor structure and a method for manufacturing the same. The transistor includes: a first doped region; a first channel region surrounding the first doped region; a second doped region surrounding the first channel region; a first gate located on the first channel region; and a gate oxide layer located between the first channel region and the first gate. In this disclosure, the first channel region surrounds the first doped region, and the second doped region surrounds the first channel region, increasing the effective channel length and thus increasing the drive current. This is more conducive to improving the transistor's punch-through voltage, making the transistor less prone to breakdown, thereby improving the performance of the semiconductor device. Attached Figure Description
[0053] Figure 1a A schematic diagram of a cross-sectional structure of a semiconductor structure provided in this embodiment of the present disclosure;
[0054] Figure 1bA second schematic diagram of a cross-sectional structure of a semiconductor structure provided in this embodiment of the present disclosure;
[0055] Figure 2a This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
[0056] Figure 2b A schematic diagram of a cross-sectional structure of a semiconductor structure provided in this disclosure is shown in Figure 3.
[0057] Figure 3a A top view of a transistor structure provided in an embodiment of this disclosure;
[0058] Figure 3b A three-dimensional structural schematic diagram of a transistor provided in an embodiment of this disclosure;
[0059] Figure 3c A top view of a transistor structure is provided as an embodiment of this disclosure;
[0060] Figure 3d A top view of a transistor structure is shown in Figure 3, which is an embodiment of this disclosure.
[0061] Figure 3e A top view of a transistor structure provided for an embodiment of this disclosure is shown in Figure 4.
[0062] Figure 3f A top view of a transistor structure provided in an embodiment of this disclosure. Figure 5 ;
[0063] Figure 3g A top view of a transistor structure provided in this disclosure is shown in Figure 6.
[0064] Figure 4a A schematic diagram of an array arrangement of multiple transistors provided in an embodiment of this disclosure;
[0065] Figure 4b Schematic diagram 2 showing an array arrangement of multiple transistors provided in an embodiment of this disclosure;
[0066] Figure 5 A schematic diagram illustrating the implementation flow of a transistor manufacturing method provided in this disclosure embodiment;
[0067] Figures 6a-6e This is a schematic diagram of a transistor manufacturing process provided in an embodiment of the present disclosure. Detailed Implementation
[0068] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.
[0069] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0070] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0071] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0072] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0073] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.
[0074] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0075] Typical semiconductor structures, such as the peripheral circuits of memory, are integrated circuits based on Complementary Metal-Oxide Semiconductor (CMOS), which is designed and manufactured around field-effect transistors (FETs). There are two basic types of FETs: junction field-effect transistors (JFETs) and metal-oxide-semiconductor (MOS) transistors. In a MOS FET, the gate, which serves as the input terminal, is insulated from the other two terminals by a thin dielectric layer (called the gate oxide layer), resulting in a high input resistance. A MOSFET has three electrodes: gate, source, and drain. The source and drain are either heavily doped with n-type or p-type doping. MOSFETs can be further classified into two categories based on their doping type: ... Figure 1a The n-type MOSFET shown and as Figure 1b The p-type MOSFET shown.
[0076] In existing memory circuits, as the integration requirements of memory continue to increase, the transistors and the distance between adjacent transistors (expressed as pitch) are becoming smaller and smaller. These increasingly smaller transistors often need to withstand high voltages. For example, during an erase operation on a memory cell, the bit line driver needs to withstand approximately 22V. Due to the pitch limitation, transistors can be designed with an asymmetric structure. However, as the transistor pitch decreases, the source-drain breakdown voltage (BVDSS) of the transistor decreases, meaning it is more easily broken down.
[0077] In MOSFET manufacturing, the active region is typically created by low-dose, high-energy ion doping to form a lightly doped diffusion region (LDD). This diffusion region overlaps significantly with the bottom of the gate. Under high electric fields, this can easily induce gate-induced drain leakage (GIDL) at the drain. GIDL leakage exists between the drain and the substrate and flows through the memory cells, particularly unselected cells connected to the same bit line. This leads to increased device power consumption, increased read / write interference, and reduced data retention time.
[0078] Figure 2a This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2b This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure. Figure 2a as well as Figure 2b As shown, the semiconductor structure includes multiple transistors. Each transistor includes a first doped region 201, a second doped region 203, a first channel region 202, a third doped region 205, a first gate 204, and an isolation structure 206 disposed within a rectangular region. The first doped region 201 and the second doped region 203 are located on opposite sides of the rectangular region, the first channel region 202 is located between the first doped region 201 and the second doped region 203, and the second doped region 203 is located within the third doped region 205.
[0079] Here, the first doped region 201 is the source region, the second doped region 203 is the drain region, and the third doped region 205 is the lightly doped drain region. The first doped region 201, the second doped region 203, the third doped region 205, and the first channel region 202 are located in the substrate 207.
[0080] The semiconductor structure here also includes an isolation structure 206, which is located between the plurality of transistors. The isolation structure 206 is a shallow trench isolation (STI), which isolates the active regions between the plurality of transistors disposed on the substrate into independent regions to achieve independent operation of each.
[0081] from Figure 2a as well as Figure 2b As can be seen, the top view of the first doped region 201, the second doped region 203, the first channel region 202, and the third doped region 205 is rectangular. The first doped region 201 and the second doped region 203 are asymmetrically distributed on both sides of the first gate 204, and multiple transistors form a transistor array arranged in an array. From Figure 2b As can be seen, the first gate 204 has a partially overlapping region with the source region and the lightly doped drain region. The source, drain, and lightly doped region can be disposed in the substrate.
[0082] In some specific examples, as the erase voltage increases, the GIDL effect can be reduced by decreasing the doping concentration of the lightly doped drain region, thereby improving BVDss. However, this approach reduces the drive current, so ensuring a large drive current while improving BVDss becomes a pressing issue.
[0083] In view of the above problems, this disclosure provides a transistor and a method for manufacturing the same.
[0084] Figure 3a A top view of a transistor structure provided in an embodiment of this disclosure; Figure 3b A three-dimensional structural schematic diagram of a transistor provided in an embodiment of this disclosure; Figure 3c as well as Figure 3d This is a top view schematic diagram of another transistor structure provided in an embodiment of this disclosure. It should be noted that... Figure 3d This is a top view observed through the first gate 304 at the top. Figure 3d The first gate 304 is not shown, which makes the location of the first channel region 302 more clearly visible.
[0085] like Figure 3a as well as Figure 3b As shown, the transistor includes:
[0086] First doped region 301;
[0087] The first channel region 302 is disposed around the first doped region 301;
[0088] The second doped region 303 is disposed around the first channel region 302;
[0089] The first gate 304 is located on the first channel region 302;
[0090] A gate oxide layer is located between the first channel region 302 and the first gate 304.
[0091] Here, the first doped region 301, the second doped region 303, and the first channel region 302 can be formed in the substrate or in a semiconductor layer formed by deposition or other processes. The substrate can include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.
[0092] Here, the concept of the first doped region 301 is not limited to a plane; it can be understood as a part of the transistor and can be a three-dimensional structure.
[0093] Here, the material of the first gate 304 includes, but is not limited to, polysilicon.
[0094] In some embodiments, the first doped region 301 includes a source region and the second doped region 303 includes a drain region; or, the first doped region 301 includes a drain region and the second doped region 303 includes a source region.
[0095] Here, the source region forms the source of the transistor, and the drain region forms the drain of the transistor.
[0096] Here, the source and drain regions have the same doping type, and the doping type of the source and drain regions is different from the doping type of the substrate. For example, when the substrate is an n-type substrate, the source and drain regions are p-type doped; when the substrate is a p-type substrate, the source and drain regions are n-type doped.
[0097] Here, the gate oxide layer is used to electrically isolate the first channel region 302 and the first gate 304. The material of the gate oxide layer may include, but is not limited to, silicon oxide, hafnium oxide, aluminum oxide, etc.
[0098] Specifically, the gate oxide layer can be used to sense different electric fields and apply them to the surface of the first channel region 302, so that minority carriers in the semiconductor layer are adsorbed onto the surface of the first channel region 302 and accumulated and inverted, making the gate oxide layer the same as the source and drain regions, thereby realizing the conduction between the source and drain regions.
[0099] It is understandable that after applying a gate voltage to the first gate 304, i.e. generating a strong electric field, electrons drift and accelerate continuously along the direction of the electric field, thus gaining a large amount of kinetic energy. When these electrons travel from the source to the drain, they collide with the gate oxide layer and are injected into the gate oxide layer, thereby generating a hot carrier effect. This hot carrier effect has a significant impact on the reliability of the transistor.
[0100] Based on this, the present disclosure proposes the following technical solutions to improve the hot carrier effect.
[0101] In some embodiments, such as Figure 3c as well as Figure 3d As shown, the transistor further includes a third doped region 305; the third doped region 305 includes a first sub-doped region 305' and a second sub-doped region 305', the first sub-doped region 305' surrounds the second doped region 303, the second sub-doped region 305' is located between the first channel region 302 and the second doped region 303, and the second sub-doped region 305' surrounds the first channel region 302.
[0102] In some embodiments, the doping concentration of the third doped region 305 is less than the doping concentration of the first doped region 301 and the second doped region 303.
[0103] In some specific examples, the third doped region 305 may include a lightly doped drain region.
[0104] In some specific examples, the doping concentration of the first doped region 301 is substantially the same as that of the second doped region 303.
[0105] Here, "basically the same doping concentration" can be understood as meaning that the doping concentration of the first doped region 301 and the doping concentration of the second doped region 303 can be equal, but a certain difference is allowed within a certain error range. Specifically, this doping concentration error range can include differences caused by manufacturing errors. Furthermore, this error range includes, but is not limited to, the situations described above.
[0106] In some embodiments, the first gate 304 at least covers the first channel region 302.
[0107] Here, the first gate 304 covering at least the first channel region 302 can be understood as the first gate 304 covering the first channel region 302 on the plane where the top surface of the first channel region 302 is located, but not only covering the first channel region 302, but may also cover other regions.
[0108] It is understandable that the third doped region 305 is a structure adopted by the device to reduce the drain electric field and improve the hot carrier effect. That is, a low-doped region is set in the first channel region 302 near the drain, so that the third doped region 305 also bears part of the voltage, thereby reducing the hot carrier effect.
[0109] Here, the doping type of the third doped region 305 is the same as that of the first doped region 301 and the second doped region 303. The specific doping types of the first doped region 301, the second doped region 303, and the third doped region 305 are illustrated below.
[0110] In some specific examples, the transistor can be an n-type transistor or a p-type transistor.
[0111] In an n-type transistor, when the first doped region 301 and the second doped region 303 are n-type doped, the third doped region 305 is also n-type doped.
[0112] In a p-type transistor, when the first doped region 301 and the second doped region 303 are p-type doped, the third doped region 305 is also p-type doped.
[0113] In some embodiments, the first gate 304 covers the first channel region 302, a portion of the first doped region 301, and a portion of the second sub-doped region 305.
[0114] In some specific examples, the first doped region 301, the second doped region 303, and the third doped region 305 can be formed by ion implantation or diffusion processes.
[0115] It is understandable that in actual ion implantation or diffusion processes, since the ion implantation or diffusion area cannot be completely precisely controlled, there is a small overlap between the first channel region 302 and the first doped region 301 and the third doped region 305 in the orthogonal projection direction of the plane on which the top surface of the first channel region 302 is located. The impact of this on the performance of the transistor itself is negligible.
[0116] In some embodiments, the orthographic projections of the second doped region 303, the first channel region 302, and the first gate 304 onto the plane containing the top surface of the first channel region all include annular shapes.
[0117] In some embodiments, the ring includes a circular ring and an elliptical ring.
[0118] Figures 3a-3d An exemplary case is shown where the second doped region 303, the first channel region 302, and the first gate 304 are all annular in shape; Figure 3e An exemplary illustration shows a case where the second doped region 303, the first channel region 302, and the first gate 304 are all elliptical rings. However, the ring shape is not limited to the circular and elliptical rings mentioned above; it may also include square rings, triangular rings, or any polygonal rings. The shapes of the second doped region 303, the first channel region 302, and the first gate 304 may be the same or different.
[0119] It should be noted that the shapes of the orthographic projections of the second doped region 303, the first channel region 302, and the first gate 304 onto the plane containing the top surface of the first channel region are not limited to this. In the embodiments of this disclosure, the shapes of the orthographic projections of the second doped region 303, the first channel region 302, and the first gate 304 onto the plane containing the top surface of the first channel region also include other shapes that are allowed under the influence of process differences.
[0120] In some specific examples, it is preferred that the second doped region 303, the first channel region 302, and the first gate 304 be in annular shape.
[0121] Understandably, firstly, compared to this disclosure... Figure 2a In the asymmetric transistor shown, the rectangular active region, when the first channel region 302 is set into a ring shape, has a larger effective channel length, thereby resulting in a larger total drive current; secondly, since the drive current is large enough, the doping concentration of the third doped region 305 can be reduced to improve BVDss; thirdly, the outer ring as the drain terminal can make the electric field more diffuse, which is beneficial to the improvement of BVDss.
[0122] Figure 3f as well as Figure 3g This is a top view schematic diagram of another transistor structure provided in an embodiment of this disclosure. It should be noted that... Figure 3g This is a top view observed through the first gate 304 and the second gate 310 at the top. Figure 3g The first gate 304 and the second gate 310 are not shown, so that the positions of the first channel region 302 and the second channel region 309 can be shown more clearly.
[0123] In some embodiments, the transistor further includes:
[0124] The second channel region 309 is disposed around the second doped region 303;
[0125] The fourth doped region 311 is disposed around the second channel region 309;
[0126] The second gate 310 is located on the second channel region 309, and the orthographic projection of the second gate 310 onto the plane containing the top surface of the second channel region 309 at least covers the second channel region 309.
[0127] When the first doped region 301 includes a source region and the second doped region 303 includes a drain region, the fourth doped region 311 includes a source region;
[0128] When the first doped region 301 includes a drain region and the second doped region 303 includes a source region, the fourth doped region 311 includes a drain region.
[0129] It is understood that when the first doped region 301 includes a source region, the second doped region 303 includes a drain region, and the fourth doped region 311 includes a source region, the two sources share a drain region; when the first doped region 301 includes a drain region, the second doped region 303 includes a source region, and the fourth doped region 311 includes a drain region, the two drains share a source region.
[0130] In some specific examples, the transistor includes a high-voltage metal-oxide-semiconductor (MOSFET) field-effect transistor (FET) with a maximum gate-source voltage greater than 15 volts. Here, the maximum gate-source voltage, also known as the gate-source rated voltage, is the maximum voltage that can be applied between the gate and source terminals, thereby preventing damage to the gate oxide layer due to excessive voltage. In some specific examples, the gate oxide layer can withstand voltages much higher than the gate-source rated voltage. However, the transistor is not limited to the aforementioned high-voltage MOSFET; other low-voltage MOSFETs with a maximum gate-source voltage less than 15 volts are also applicable. In some specific examples, the maximum gate-source voltage of the MOSFET may be less than 35 volts.
[0131] Based on the transistors provided in the above embodiments, this disclosure also provides a semiconductor structure, the semiconductor structure including a plurality of transistors as described in any of the above embodiments, and the plurality of transistors are arranged in an array;
[0132] The semiconductor structure further includes an isolation structure; the isolation structure is located between the plurality of transistors and is used to isolate the plurality of transistors.
[0133] It is understandable that the circular active region is not surrounded by the corners formed by STI, which can improve the boundary effect caused by STI, reduce leakage, and thus improve the performance of the device.
[0134] The arrangement of the multiple transistors in the array can include various methods. Two examples of transistor array arrangement are listed below.
[0135] The first type, such as Figure 4aAs shown, the plurality of transistors includes a plurality of alternating first row transistors and second row transistors;
[0136] The centers of two adjacent transistors in each of the first row of transistors are C1 and C2, respectively. The center of the transistor in each of the second row of transistors is C3, which has the smallest sum of distances to the two adjacent transistors in the first row of transistors. The line connecting C1, C2, and C3 forms an equilateral triangle.
[0137] It should be noted that the lines connecting C1, C2, and C3 here include, but are not limited to, equilateral triangles; they can also be other triangles, such as isosceles triangles. Understandably, when the lines connecting C1, C2, and C3 form an equilateral triangle, the area utilization rate is the highest.
[0138] The second type allows multiple transistors to be arranged as follows: Figure 4b The layout shown is arranged as described. Figure 4b The lines connecting the center of transistors T1, T2, T3, and T4 in the diagram form a square.
[0139] Figure 4a The arrangement shown is a preferred method. It is understood that when the same number of transistors exist in the same space, the first arrangement maximizes the distance between adjacent transistors, which can improve the problem of mutual interference between transistors.
[0140] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory.
[0141] In some specific examples, the memory includes, but is not limited to, three-dimensional NAND flash memory, dynamic random access memory, ferroelectric memory, phase change memory, magnetic change memory, or resistive change memory.
[0142] This disclosure provides a transistor comprising: a first doped region 301; a first channel region 302 disposed around the first doped region 301; a second doped region 303 disposed around the first channel region 302; a first gate 304 located on the first channel region 302; and a gate oxide layer located between the first channel region 302 and the first gate 304. The first channel region 302 surrounds the first doped region 301, and the second doped region 303 surrounds the first channel region 302, thereby increasing the effective channel length and thus increasing the drive current. This is more conducive to improving the punch-through voltage of the transistor, thereby improving the performance of the semiconductor device.
[0143] Based on the transistor described above, embodiments of this disclosure also provide a method for manufacturing a transistor. Figure 5This is a schematic diagram illustrating the implementation flow of a transistor manufacturing method provided in an embodiment of this disclosure. Figures 6a-6e A schematic diagram of the transistor manufacturing process provided in this disclosure embodiment, wherein Figure 6b for Figure 6a A top-view structural diagram. (See diagram below.) Figure 5 As shown, the method includes the following steps:
[0144] Step 501: Provide a first semiconductor layer;
[0145] Step 502: As Figures 6a-6b As shown, the first semiconductor layer is etched to form a first semiconductor pillar 307; the first semiconductor pillar 307 includes a first portion 307-1, a second portion 307-2 surrounding the first portion 307-1, and a third portion 307-3 surrounding the second portion 307-2;
[0146] Step 503: Form a gate oxide layer on the first semiconductor pillar;
[0147] Step 504: As Figure 6c As shown, a second semiconductor layer 308 is formed on the gate oxide layer;
[0148] Step 505: As Figure 6d As shown, the second semiconductor layer 308 is etched to form the first gate 304;
[0149] Step 506: As Figure 6e As shown, a first doped region 301 is formed in the first portion 307-1, and a second doped region 303 is formed in the third portion 307-3; after the formation of the first doped region 301 and the second doped region 303, the second portion 307-2 constitutes a first channel region 302.
[0150] In step 501, the first semiconductor layer may include a substrate, or it may be a semiconductor layer formed by a deposition process or other processes. The substrate material may include silicon (Si), germanium (Ge), silicon germanide (SiGe) substrates, etc.; in some specific embodiments, the substrate may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); in some specific examples, the deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.
[0151] In step 502, the first semiconductor layer can be etched using a dry etching process, such as plasma etching or reactive ion etching, to form the first semiconductor pillar 307.
[0152] Here, the shape of the first semiconductor pillar may include a cylinder, an elliptical cylinder, a triangular prism, and other polygonal prisms.
[0153] In step 503, the main task is to form a gate oxide layer.
[0154] In some specific examples, the material of the gate oxide layer may include, but is not limited to, silicon oxide.
[0155] In some specific examples, it can be formed using processes such as PVD, CVD, and ALD.
[0156] In step 504, the second semiconductor layer 308 includes, but is not limited to, polycrystalline silicon. It can be formed by processes such as PVD, CVD, and ALD.
[0157] In step 505, the second semiconductor layer 308 can be etched using a dry etching process, such as plasma etching or reactive ion etching, to form the first gate 304.
[0158] In step 506, a diffusion process or an ion implantation process can be used to form the first doped region 301 and the second doped region 303.
[0159] In some embodiments, forming a first doped region 301 in the first portion 307-1 and forming a second doped region 303 in the third portion 307-3 includes:
[0160] A source region is formed in the first portion 307-1, and a drain region is formed in the third portion 307-3; or, a drain region is formed in the first portion 307-1, and a source region is formed in the third portion 307-3.
[0161] In some embodiments, the method further includes: forming a third doped region 305 in the third portion 307-3 before forming the first doped region 301 and the second doped region 303; the third doped region 305 includes a first sub-doped region 305' and a second sub-doped region 305', the first sub-doped region 305' surrounding the second doped region 303, the second sub-doped region being located between the first channel region and the second doped region and surrounding the first channel region.
[0162] In some embodiments, the doping concentration of the third doped region 305 is less than the doping concentration of the first doped region 301 and the second doped region 303.
[0163] In some specific examples, diffusion or ion implantation processes can be used to form the third doped region 305.
[0164] In some specific examples, the doping types of the first doped region 301, the second doped region 303, and the third doped region 305 can be selected according to specific circumstances. When the transistor is an n-type transistor, the doping types of the first doped region 301, the second doped region 303, and the third doped region 305 are all n-type doped. When the transistor is a p-type transistor, the first doped region 301, the second doped region 303, and the third doped region 305 are all p-type doped.
[0165] For example, when the doping type is p-type doping, the p-type impurity source can be boron, boron difluoride, or indium, and the p-type impurity source is not limited to these. For example, when the doping type is n-type doping, the n-type impurity source can be phosphorus (P) or arsenic (As), and the n-type impurity source is not limited to these.
[0166] In some embodiments, the first semiconductor pillar 307 further includes a fourth portion and a fifth portion, the fifth portion surrounding the fourth portion, and the fourth portion surrounding the third portion 307-3;
[0167] The etching process of the second semiconductor layer 308 to form a first gate 304, wherein the first gate 304 at least covers the second portion 307-2, includes:
[0168] The second semiconductor layer 308 is etched to form a first gate 304 and a second gate 310. The first gate 304 at least covers the second portion 307-2, and the second gate 310 at least covers the fourth portion.
[0169] The method further includes:
[0170] After the first gate 304 is formed, a fourth doped region 311 is formed in the fifth portion; after the fourth doped region 311 is formed, the fourth portion constitutes a second channel region 309.
[0171] In some embodiments, when the first doped region 301 includes a source region and the second doped region 303 includes a drain region, the fourth doped region 311 includes a source region;
[0172] When the first doped region 301 includes a drain region and the second doped region 303 includes a source region, the fourth doped region 311 includes a drain region.
[0173] Based on the above-described transistor manufacturing method, this disclosure also provides a semiconductor structure manufacturing method, which manufactures a plurality of transistors using the transistor manufacturing method described in any of the above embodiments, wherein the plurality of transistors are arranged in an array.
[0174] The method further includes:
[0175] An isolation structure is formed between the plurality of transistors; the isolation structure is used to isolate the plurality of transistors.
[0176] The isolation structure is used to isolate the active regions of multiple transistors into independent regions.
[0177] In some embodiments, the plurality of transistors includes a plurality of alternating first rows of transistors and second rows of transistors;
[0178] The centers of two adjacent transistors in each of the first row of transistors are C1 and C2, respectively. The center of the transistor in each of the second row of transistors is C3, which has the smallest sum of distances to the two adjacent transistors in the first row of transistors. The line connecting C1, C2, and C3 forms an equilateral triangle.
[0179] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.
[0180] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0181] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A transistor, characterized in that, include: First doped region; The first channel region is disposed around the first doped region; A second doped region is disposed around the first channel region; The first gate is located on the first channel region; A gate oxide layer is located between the first channel region and the first gate; The second channel region is disposed around the second doped region; A fourth doped region is disposed around the second channel region; The second gate is located on the second channel region, and the orthographic projection of the second gate onto the plane containing the top surface of the second channel region at least covers the second channel region; When the first doped region includes a source region and the second doped region includes a drain region, the fourth doped region includes a source region; When the first doped region includes a drain region and the second doped region includes a source region, the fourth doped region includes a drain region; The shape of the orthographic projection of the transistor onto the plane containing the top surface of the first channel region includes a circle or an ellipse.
2. The transistor according to claim 1, characterized in that, The first doped region includes a source region, and the second doped region includes a drain region; or, the first doped region includes a drain region, and the second doped region includes a source region.
3. The transistor according to claim 1, characterized in that, The first gate at least covers the first channel region.
4. The transistor according to claim 1, characterized in that, The transistor further includes a third doped region; the third doped region includes a first sub-doped region and a second sub-doped region, the first sub-doped region surrounds the second doped region, the second sub-doped region is located between the first channel region and the second doped region and surrounds the first channel region.
5. The transistor according to claim 4, characterized in that, The doping concentration of the third doped region is less than that of the first doped region and the second doped region.
6. The transistor according to claim 4, characterized in that, The first gate covers the first channel region, a portion of the first doped region, and a portion of the second sub-doped region.
7. The transistor according to claim 1, characterized in that, The shapes of the second doped region, the first channel region, and the first gate as projected onto the plane containing the top surface of the first channel region all include annular shapes.
8. The transistor according to claim 7, characterized in that, The rings include circular rings and elliptical rings.
9. A semiconductor structure, characterized in that, The semiconductor structure includes a plurality of transistors as described in any one of claims 1 to 8, and the plurality of transistors are arranged in an array; The semiconductor structure further includes an isolation structure; the isolation structure is located between the plurality of transistors and is used to isolate the plurality of transistors.
10. The semiconductor structure according to claim 9, characterized in that, The plurality of transistors includes a plurality of alternating first row transistors and second row transistors; The centers of two adjacent transistors in each of the first row of transistors are C1 and C2, respectively. The center of the transistor in each of the second row of transistors is C3, which has the smallest sum of distances to the two adjacent transistors in the first row of transistors. The line connecting C1, C2, and C3 forms an equilateral triangle.
11. A method for manufacturing a transistor, characterized in that, include: Provide a first semiconductor layer; The first semiconductor layer is etched to form a first semiconductor pillar; The first semiconductor pillar includes a first portion, a second portion surrounding the first portion, a third portion surrounding the second portion, a fourth portion surrounding the third portion, and a fifth portion surrounding the fourth portion; A gate oxide layer is formed on the first semiconductor pillar; A second semiconductor layer is formed on the gate oxide layer; The second semiconductor layer is etched to form a first gate and a second gate, wherein the first gate at least covers the second portion and the second gate at least covers the fourth portion; A first doped region is formed in the first part, and a second doped region is formed in the third part; After the first doped region and the second doped region are formed, the second portion constitutes the first channel region; A fourth doped region is formed in the fifth portion; after the fourth doped region is formed, the fourth portion constitutes a second channel region; When the first doped region includes a source region and the second doped region includes a drain region, the fourth doped region includes a source region; When the first doped region includes a drain region and the second doped region includes a source region, the fourth doped region includes a drain region; The shape of the orthographic projection of the transistor onto the plane containing the top surface of the first channel region includes a circle or an ellipse.
12. The method for manufacturing a transistor according to claim 11, characterized in that, The process of forming a first doped region in the first portion and a second doped region in the third portion includes: A source region is formed in the first part, and a drain region is formed in the third part; or, a drain region is formed in the first part, and a source region is formed in the third part.
13. The method for manufacturing a transistor according to claim 11, characterized in that, The method further includes: Before forming the first doped region and the second doped region, a third doped region is formed in the third portion; the third doped region includes a first sub-doped region and a second sub-doped region, the first sub-doped region surrounding the second doped region, the second sub-doped region being located between the first channel region and the second doped region and surrounding the first channel region.
14. The method for manufacturing a transistor according to claim 13, characterized in that, The doping concentration of the third doped region is less than that of the first doped region and the second doped region.
15. A method for manufacturing a semiconductor structure, characterized in that, A plurality of transistors are manufactured using the transistor manufacturing method according to any one of claims 11 to 14, wherein the plurality of transistors are arranged in an array; The method further includes: An isolation structure is formed between the plurality of transistors; the isolation structure is used to isolate the plurality of transistors.
16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The plurality of transistors includes a plurality of alternating first row transistors and second row transistors; The centers of two adjacent transistors in each of the first row of transistors are C1 and C2, respectively. The center of the transistor in each of the second row of transistors is C3, which has the smallest sum of distances to the two adjacent transistors in the first row of transistors. The line connecting C1, C2, and C3 forms an equilateral triangle.