Signal generation circuit and memory

Abstract

Embodiments of the present application provide a signal generation circuit and a memory. The signal generation circuit comprises: a clock delay module configured to delay an initial pulse signal and output an intermediate signal, the intermediate signal being delayed from the initial pulse signal by a first delay duration, the first delay duration being equal to one or more clock periods; a physical delay module configured to delay the intermediate signal to output a target signal, the target signal being delayed from the initial pulse signal by a target duration if an actual delay duration of the physical delay module is equal to a second delay duration, a difference between the actual delay duration and the second delay duration fluctuating within a first preset range, the second delay duration being shorter, the first preset range being narrower; and a generation module configured to output a functional pulse signal, a pulse width of the functional pulse signal being equal to a time interval of rising edges of the initial pulse signal and the target signal. Embodiments of the present application are beneficial to accurately controlling the pulse width of the functional pulse signal.

Description

Technical Field

[0001] This invention relates to the semiconductor field, and in particular to a signal generation circuit and a memory. Background Technology

[0002] In the circuit design of the column select signal (CSL) decoder of DDR4 chips, the pulse width of the CSL signal is limited. Typically, a physical delay is used to form a pulse width independent of the clock frequency, which is then transmitted to the memory structure for operation.

[0003] In traditional CSL signal generation circuits, the pulse width of the CSL signal is not affected by the clock frequency, but only by the chip process corner type, operating voltage, and operating temperature. However, when the chip fabrication process is unstable, the chip process corner type is unstable, and during the actual use of the CSL signal generation circuit, the operating voltage and operating temperature are also unstable. Therefore, the pulse width of the CSL signal fluctuates significantly.

[0004] refer to Figure 1 When the chip process corner is at a fast process corner (FF corner), the actual delay time of the target signal obtained by physically delaying the initial pulse signal may be insufficient, resulting in the actual pulse width of the CSL signal being insufficient relative to the preset pulse width (indicated by the dashed line); Reference Figure 2 When the chip process corner is at a relatively slow process corner (SS corner), the actual delay time of the target signal obtained by physically delaying the initial pulse signal may be too long, resulting in the pulse width of the CSL signal being too long relative to the preset pulse width (indicated by the dashed line). Both of these situations can cause data read / write failures, meaning the CSL signal has low efficiency. Summary of the Invention

[0005] This invention provides a signal generation circuit and a memory, which facilitates accurate control of the pulse width of functional pulse signals and improves the efficiency of functional pulse signals.

[0006] To address the aforementioned problems, this invention provides a signal generation circuit, comprising: a clock delay module for receiving a clock signal and an initial pulse signal, and for delaying the initial pulse signal to output an intermediate signal, wherein the intermediate signal is delayed by a first delay duration relative to the initial pulse signal, the first delay duration being equal to one or more clock cycles of the clock signal; a physical delay module for receiving and delaying the intermediate signal to output a target signal, wherein the preset delay duration of the physical delay module is a second delay duration, and if the actual delay duration of the physical delay module is equal to the second delay duration, the target signal is delayed by a target duration relative to the initial pulse signal, the difference between the actual delay duration and the second delay duration fluctuates within a first preset range, the shorter the second delay duration, the narrower the first preset range; and a generation module for receiving the initial pulse signal and the target signal, and outputting a functional pulse signal, wherein the pulse width of the functional pulse signal is equal to the time interval between the rising edge of the initial pulse signal and the rising edge of the target signal.

[0007] In addition, the first delay duration is equal to n clock cycles, and the clock delay module is also used to output multiple intermediate signals, with different values ​​of n corresponding to different intermediate signals, where n is a positive integer; the physical delay module is also used to receive a first flag signal, which represents the value of the clock cycle, and to receive one of the multiple intermediate signals according to the first flag signal and adjust the second delay duration so that the sum of the first delay duration and the second delay duration corresponding to the received intermediate signal is equal to the target duration.

[0008] In addition, the clock period is one of a plurality of different values, and the first delay duration varies according to the value of the clock period; the physical delay module is also used to adjust the second delay duration according to the first delay duration, so that the sum of the first delay duration and the second delay duration is equal to the target duration.

[0009] Additionally, the clock cycle includes a first clock cycle or a second clock cycle; the clock delay module is at least used to output a first intermediate signal and a second intermediate signal, the first delay duration corresponding to the first intermediate signal is equal to x clock cycles, and the first delay duration corresponding to the second intermediate signal is equal to y clock cycles, where x and y are positive integers; the physical delay module includes: a first delay unit, used to receive the first intermediate signal, the sum of the preset delay duration of the first delay unit and x first clock cycles equals the target duration; a second delay unit, used to receive the second intermediate signal, the sum of the preset delay duration of the second delay unit and y second clock cycles equals the target duration; a first signal selector, the first input terminal of the first signal selector is connected to the output terminal of the first delay unit, the second input terminal of the first signal selector is connected to the output terminal of the second delay unit, and the output terminal of the first signal selector is connected to the input terminal of the generation module, used to receive a first flag signal, if the first flag signal indicates that the clock cycle is the first clock cycle, then control the output terminal of the first signal selector to connect with the first input terminal; if the first flag signal indicates that the clock cycle is the second clock cycle, then control the output terminal of the first signal selector to connect with the second input terminal.

[0010] In addition, the first flag signal characterizes the delay between adjacent column address strobe signals.

[0011] Additionally, y>x; the clock delay module includes: a first clock unit, the output of which is connected to the input of the first delay unit, for receiving the initial pulse signal and outputting the first intermediate signal; and a second clock unit, connected between the first clock unit and the second delay unit, for receiving and delaying the first intermediate signal and outputting the second intermediate signal.

[0012] In addition, the first clock unit consists of x delay units connected in series, the delay units are used to receive and delay signals, and the delay duration of the delay units is equal to one clock cycle; the second clock unit consists of yx delay units connected in series.

[0013] In addition, the pulse width of the initial pulse signal is equal to the clock period, the rising edge of the initial pulse signal is the same as the rising edge of the clock signal, the delay unit is a D flip-flop, the triggering mode of the D flip-flop is edge-triggered, and the trigger input terminal of the D flip-flop is used to receive the clock signal.

[0014] Additionally, the clock cycle further includes a third clock cycle, a fourth clock cycle, or a fifth clock cycle; the clock delay module is at least used to output a third intermediate signal, a fourth intermediate signal, and a fifth intermediate signal, wherein the first delay duration corresponding to the third intermediate signal is equal to *a* clock cycles, the first delay duration corresponding to the fourth intermediate signal is equal to *b* clock cycles, and the first delay duration corresponding to the fifth intermediate signal is equal to *c* clock cycles, where *a*, *b*, and *c* are positive integers; the physical delay module further includes: a third delay unit, used to receive the third intermediate signal, wherein the preset delay duration of the third delay unit and *a* third clock cycles equals the target duration; and a fourth delay unit, used to receive the fourth intermediate signal, wherein the preset delay duration of the fourth delay unit and *b* third clock cycles equals the target duration. The sum of four clock cycles equals the target duration; a fifth delay unit is used to receive the fifth intermediate signal, and the preset delay duration of the fifth delay unit and the sum of c fifth clock cycles equals the target duration; the third input terminal of the first signal selector is connected to the output terminal of the third delay unit, the fourth input terminal of the first signal selector is connected to the output terminal of the fourth delay unit, and the fifth input terminal of the first signal selector is connected to the output terminal of the fifth delay unit; the first flag signal is also used to characterize the three clock cycles, the fourth clock cycle, or the fifth clock cycle, and the first signal selector is also used to control the output terminal of the first signal selector to be connected to the output terminal of the third delay unit, the output terminal of the fourth delay unit, or the output terminal of the fifth delay unit according to the first flag signal.

[0015] In addition, the signal generation circuit further includes: a native delay module, used to receive and delay the initial pulse signal to output a native signal, wherein the preset delay duration of the native delay module is the target duration, and the difference between the actual delay duration of the native delay module and the target duration fluctuates within a second preset range, wherein the shorter the target duration, the narrower the second preset range; the generation module includes: a second signal selector, used to receive the native signal and the target signal, and to receive a second flag signal, and to output the native signal or the target signal according to the second flag signal; a latch, used to receive the initial pulse signal, and to receive the native signal or the target signal, wherein if the native signal is received, the pulse width of the functional pulse signal is equal to the time interval between the rising edge of the initial pulse signal and the rising edge of the native signal.

[0016] In addition, the latch has a first input terminal and a second input terminal. The first input terminal is used to receive the initial pulse signal, and the second input terminal is used to receive the target signal or the original signal. If the level of the first input terminal is detected to become high, the latch continuously outputs a high-level signal until the level of the second input terminal is detected to become high, at which point the output high level of the latch changes back to low level.

[0017] In addition, the physical delay module is composed of m inverters connected in series, where m is an even number. Each inverter has a preset output hysteresis, and the sum of the m preset output hysteresis is equal to the second delay duration. The smaller m is, the narrower the first preset range.

[0018] In addition, the functional pulse signal is a column address strobe signal.

[0019] Accordingly, embodiments of the present invention also provide a memory, including the signal generation circuit described in any of the above claims.

[0020] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:

[0021] In the above technical solution, the initial pulse signal is delayed by both the clock delay module and the physical delay module, which shortens the second delay duration that needs to be achieved by the physical delay module. This reduces the delay fluctuations caused by the physical delay module, making the delay of the target signal relative to the initial pulse signal closer to the target duration. This allows for accurate control of the pulse width of the functional pulse signal and improves the efficiency of the functional pulse signal.

[0022] In addition, the physical delay module can select the corresponding intermediate signal based on the value of the clock cycle represented by the first flag signal, so that the first delay duration of the clock delay module is less than the target duration, and the proportion of the first delay duration corresponding to the intermediate signal to the target duration is relatively large, thereby shortening the second delay duration that needs to be implemented by the physical delay module as much as possible, and further reducing the delay fluctuation caused by the physical delay. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not to be limited in scale unless otherwise stated.

[0024] Figure 1 and Figure 2 This is a schematic diagram of signal generation.

[0025] Figure 3 This is a functional structure diagram of the signal generation circuit provided in an embodiment of the present invention;

[0026] Figure 4This is a schematic diagram of the signal generation circuit provided in an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the signal generation circuit provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0029] refer to Figure 3 The signal generation circuit includes: a clock delay module 10, used to receive a clock signal 2 and an initial pulse signal 1, and to delay the initial pulse signal 1 to output an intermediate signal 10a, wherein the intermediate signal 10a is delayed by a first delay duration relative to the initial pulse signal 1, the first delay duration being equal to one or more clock cycles of the clock signal 2; a physical delay module 20, used to receive and delay the intermediate signal 10a to output a target signal 20a, wherein the preset delay duration of the physical delay module 20 is a second delay duration, and if the actual delay duration of the physical delay module 20 is equal to the second delay duration, then the target signal 20a is delayed by the target duration relative to the initial pulse signal 1, and the difference between the actual delay duration and the second delay duration fluctuates within a first preset range, wherein the shorter the second delay duration, the narrower the first preset range; and a generation module 30, used to receive the initial pulse signal 1 and the target signal 20a, and to output a functional pulse signal 30a, wherein the pulse width of the functional pulse signal 30a is equal to the time interval between the rising edge of the initial pulse signal 1 and the rising edge of the target signal 20a.

[0030] In this embodiment, the first delay duration is equal to n clock cycles. The clock delay module 10 is also used to output multiple intermediate signals 10a, with different values ​​of n corresponding to different intermediate signals 10a, where n is a positive integer. The physical delay module 20 is also used to receive a first flag signal 20b, which represents the value of the clock cycle. Based on the first flag signal 20b, the module receives one of the multiple intermediate signals 10a and adjusts the second delay duration so that the sum of the first delay duration and the second delay duration corresponding to the received intermediate signal 10a is equal to the target duration.

[0031] When the value of n is large or the value of the clock cycle is large, the total duration of n clock cycles may be greater than the target duration. That is, the first delay duration corresponding to the intermediate signal 10a is greater than the target duration. In this case, the physical delay module 20 can only receive part of the intermediate signal 10a. The first delay duration corresponding to this part of the intermediate signal 10a is less than the target duration, so that the sum of the first delay duration and the second delay duration is equal to the target duration.

[0032] Furthermore, when the first delay duration corresponding to multiple intermediate signals 10a is less than the target duration, the physical delay module 20 can receive the intermediate signal 10a whose first delay duration is closest to the target duration, thereby minimizing the second delay duration that needs to be achieved by the physical delay module 20, narrowing the first preset range, and making the delay of the target signal 20a relative to the initial pulse signal 1 as close as possible to the target duration, thereby accurately controlling the pulse width of the functional pulse signal 30a near the target duration.

[0033] In this embodiment, the clock period is one of several different values, and the first delay duration varies according to the value of the clock period. The physical delay module 20 is also used to adjust the second delay duration according to the first delay duration so that the sum of the first delay duration and the second delay duration equals the target duration. As the value of the clock period changes, the first delay duration corresponding to the intermediate signal 10a received by the physical delay module 20 will also change. At this time, it is necessary to adjust the second delay duration of the physical delay module 20 in a timely manner to ensure that the sum of the first delay duration and the second delay duration equals the target duration, thereby accurately controlling the pulse width of the functional pulse signal 30a to approach the target duration.

[0034] The following uses a clock cycle including a first clock cycle and a second clock cycle as an example to provide a detailed explanation of the signal generation circuit.

[0035] refer to Figure 4The clock delay module 10 is used to output at least a first intermediate signal 11a and a second intermediate signal 12a. The first delay duration corresponding to the first intermediate signal 11a is equal to x clock cycles, and the first delay duration corresponding to the second intermediate signal 12a is equal to y clock cycles, where x and y are positive integers. The physical delay module 20 includes: a first delay unit 21 for receiving the first intermediate signal 11a, wherein the sum of the preset delay duration of the first delay unit 21 and x first clock cycles equals the target duration; a second delay unit 22 for receiving the second intermediate signal 12a, wherein the sum of the preset delay duration of the second delay unit 22 and y second clock cycles equals the target duration; a first signal selector 26; and a first signal selector 27. The first input terminal of the first signal selector 26 is connected to the output terminal of the first delay unit 21, the second input terminal of the first signal selector 26 is connected to the output terminal of the second delay unit 22, and the output terminal of the first signal selector 26 is connected to the input terminal of the generation module 30. It is used to receive the first flag signal 20b. If the first flag signal 20b indicates that the clock period is the first clock period, the output terminal of the first signal selector 26 is connected to the first input terminal, and the signal output by the first delay unit 21 is used as the target signal 20a. If the first flag signal 20b indicates that the clock period is the second clock period, the output terminal of the first signal selector 26 is connected to the second input terminal, and the signal output by the second delay unit 22 is used as the target signal 20a.

[0036] In other words, when the clock period of clock signal 2 changes, the physical delay module 20 can receive another intermediate signal 10a and adjust its own preset delay duration so that the sum of the first delay duration corresponding to the received intermediate signal 10a and the adjusted preset delay duration equals the target duration. It should be noted that if x first clock cycles equal y second clock cycles, that is, if the first delay duration of the first intermediate signal 11a under the first clock cycle condition equals the second delay duration of the second intermediate signal 12a under the second clock cycle condition, then the physical delay module 20 can also simply receive the other intermediate signal 10a without adjusting its own preset delay duration.

[0037] In this embodiment, when the y value is greater than the x value, the second intermediate signal 12a can be obtained by delaying the first intermediate signal 11a by yx clock cycles. Specifically, the clock delay module 10 includes: a first clock unit 11, the output of which is connected to the input of the first delay unit 21, for receiving the initial pulse signal 1 and outputting the first intermediate signal 11a; and a second clock unit 12, connected between the first clock unit 11 and the second delay unit 22, for receiving and delaying the first intermediate signal 11a and outputting the second intermediate signal 12a. This helps to reduce the complexity of the second clock unit 12, reduce its size, and reduce the size of the overall signal generation circuit.

[0038] In other embodiments, two independent clock units are used to receive the initial pulse signal and to generate the first intermediate signal and the second intermediate signal, respectively. This helps to avoid the second clock unit from failing due to damage to the first clock unit, and ensures that the signal generation circuit can at least partially work.

[0039] In this embodiment, the first clock unit 11 consists of x delay units (not shown) connected in series. The delay units are used to receive and delay signals, and the delay duration of the delay units is equal to one clock cycle. The second clock unit 12 consists of yx delay units connected in series. It should be noted that the delay of the delay units is only related to the clock cycle of the clock signal 2, and is not related to the chip process corner, actual operating temperature, or actual operating voltage.

[0040] Specifically, the pulse width of the initial pulse signal 1 is equal to the clock period of the clock signal 2, the rising edge of the initial pulse signal 1 is the same as the rising edge of the clock signal 2, the delay unit is a D flip-flop, the triggering mode of the D flip-flop is edge-triggered, and the trigger input of the D flip-flop is used to receive the clock signal 2.

[0041] The following example, using a first clock unit 11 containing a first D flip-flop and a second clock unit 12 containing a second D flip-flop, illustrates the signal reception and output process of the first clock unit 11 and the second clock unit 12: The data input terminal of the first D flip-flop is used to receive the initial pulse signal 1, the trigger input terminal is used to receive the clock signal 2, and the data output terminal is used to output the first intermediate signal 11a. The data output terminal is connected to the input terminal of the first delay unit 21 and the data input terminal of the second D flip-flop, respectively. The data input terminal of the second D flip-flop is used to receive the first intermediate signal 11a, the trigger input terminal is used to receive the clock signal 2, and the data output terminal is used to output the second intermediate signal 12a. The data output terminal is connected to the input terminal of the second delay unit 22.

[0042] The delay principle of the first D flip-flop in this application is as follows: When clock signal 2 enters the first rising edge period, the level of initial pulse signal 1 is detected. At this time, initial pulse signal 1 is at a low level or has just entered the rising edge period and has not yet risen to a high level. The first D flip-flop receiving initial pulse signal 1 outputs a low level, which lasts for one clock cycle. After one clock cycle, when clock signal 2 enters the second rising edge period, the level of initial pulse signal 1 is detected again. At this time, initial pulse signal 1 is at a high level or has just entered the falling edge period and has not yet fallen back to a low level. The first D flip-flop receiving initial pulse signal 1 outputs a high level, which lasts for one clock cycle. After another clock cycle, when clock signal 2 enters the third rising edge period, the level of initial pulse signal 1 is detected again. At this time, initial pulse signal 1 is at a low level, and the first D flip-flop receiving initial pulse signal 1 outputs a low level, and so on... In this way, the first D flip-flop can achieve a delay of one clock cycle.

[0043] It is understandable that the above only uses the first D flip-flop as an example to introduce the delay principle of the D flip-flop. The delay principle of other D flip-flops used to receive intermediate signal 10a or other types of signals is similar to that of the first D flip-flop. They all use the rising edge of clock signal 2 as the start time (i.e. the time when the rising edge period begins) as the detection time to detect, output and maintain the blocking of the signal level received at the data input terminal. They will not be elaborated on here.

[0044] Furthermore, in some embodiments, the initial pulse signal 1 is generated based on the clock signal 2. However, due to the inherent delay in the generation process, although the pulse width of the initial pulse signal 1 is one clock cycle, the rising edge of the initial pulse signal 1 occurs later than the rising edge of the corresponding clock signal 2. Specifically, refer to... Figure 5 When clock signal 2 enters the first rising edge period, initial pulse signal 1 is still at a low level, and the first intermediate signal 11a is at a low level accordingly. When clock signal 2 enters the second rising edge period, initial pulse signal 1 is at a high level, and the first intermediate signal 11a is at a high level accordingly. However, since the D flip-flop itself has a certain output time delay, the rising edge start time of the first intermediate signal 11a is later than the second rising edge start time of clock signal 2.

[0045] It should be noted that since the output delay of D flip-flops or other physical devices is an unavoidable defect, and even wires have extremely short output hysteresis, which is generally negligible, in the semiconductor field, describing different signals as having the same rise time does not mean that the rise times of different signals are completely identical. Rather, it means that the time interval between the rise times of different signals is within a certain range. As long as they are within this range, they are considered to be "the same". This "certain range" is not a fixed threshold range, but a dynamic threshold range affected by factors such as process corner type, operating voltage, and operating temperature.

[0046] In this embodiment, the clock cycle further includes a third clock cycle, a fourth clock cycle, or a fifth clock cycle; the clock delay module 10 is at least used to output a third intermediate signal 13a, a fourth intermediate signal 14a, and a fifth intermediate signal 15a, wherein the first delay duration corresponding to the third intermediate signal 13a is equal to a clock cycles, the first delay duration corresponding to the fourth intermediate signal 14a is equal to b clock cycles, and the first delay duration corresponding to the fifth intermediate signal 15a is equal to c clock cycles, where a, b, and c are positive integers; the physical delay module 20 includes: a third delay unit 23, used to receive the third intermediate signal 13a, wherein the preset delay duration of the third delay unit 23 and the sum of a third clock cycles equals the target duration; and a fourth delay unit 24, used to receive the fourth intermediate signal 14a, wherein the preset delay duration of the fourth delay unit 24 and the sum of b third clock cycles equals the target duration. The sum of the fourth clock cycles equals the target duration; the fifth delay unit 25 is used to receive the fifth intermediate signal 15a, and the preset delay duration of the fifth delay unit 25 and the sum of the c fifth clock cycles equal the target duration; the third input terminal of the first signal selector 26 is connected to the output terminal of the third delay unit 23, the fourth input terminal of the first signal selector 26 is connected to the output terminal of the fourth delay unit 24, and the fifth input terminal of the first signal selector 26 is connected to the output terminal of the fifth delay unit 25; the first flag signal 20b is also used to characterize the third clock cycle, the fourth clock cycle, or the fifth clock cycle, and the first signal selector 26 is also used to control the output terminal of the first signal selector 26 to be connected to the output terminal of the third delay unit 23, the output terminal of the fourth delay unit 24, or the output terminal of the fifth delay unit 25 according to the first flag signal 20b.

[0047] In this embodiment, a corresponding number of clock units are set according to the numerical value of the clock cycle. Each clock unit generates an intermediate signal 10a, and the number of intermediate signals 10a is the same as the numerical value of the clock cycle. In addition, the number of delay units is less than or equal to the number of intermediate signals 10a. When there are k identical values ​​in the durations of x first clock cycles, y second clock cycles, a third clock cycles, b fourth clock cycles, and c fifth clock cycles, 5-k+1 delay units can be set, one of which receives a different intermediate signal 10a according to the first flag signal 20b; or, 5 delay units can be set, where the second delay durations of k delay units are equal.

[0048] It should be noted that the number of clock cycle intervals is related to the type of memory chip and the signal represented by the first flag signal 20b. In this paper, the first flag signal 20b represents the delay between adjacent column address strobe signals (CAS to CAS command delay), abbreviated as tccd. In common memory chips, the parameters of tccd are 4, 5, 6, 7, and 8, that is, there are 5 types of tccd parameters, and correspondingly, there are 5 intervals of clock cycle intervals. In other embodiments, the number of clock cycles of the memory chip can be adjusted according to actual needs.

[0049] In this embodiment, the clock delay module 10 further includes: a third clock unit 13, connected between the second clock unit 12 and the third delay unit 23, for receiving and delaying the second intermediate signal 12a and outputting the third intermediate signal 13a; a fourth clock unit 14, connected between the third clock unit 13 and the fourth delay unit 24, for receiving and delaying the third intermediate signal 13a and outputting the fourth intermediate signal 14a; and a fifth clock unit 15, connected between the fourth clock unit 14 and the fifth delay unit 25, for receiving and delaying the fourth intermediate signal 14a and outputting the fifth intermediate signal 15a.

[0050] In this embodiment, the signal generation circuit further includes: a native delay module 40, used to receive and delay the initial pulse signal 1 to output a native signal 40a. The preset delay duration of the native delay module 40 is the target duration. The difference between the actual delay duration of the native delay module 40 and the target duration fluctuates within a second preset range. The shorter the target duration, the narrower the second preset range. The generation module 30 includes: a second signal selector 31, used to receive the native signal 40a and the target signal 20a, and to receive a second flag signal 31b, and to output the native signal 40a or the target signal 20a according to the second flag signal 31b; and a latch 32, used to receive the initial pulse signal 1, and to receive the native signal 40a or the target signal 20a. If the native signal 40a is received, the pulse width of the functional pulse signal 30a is equal to the time interval between the rising edge of the initial pulse signal 1 and the rising edge of the native signal 40a.

[0051] The second flag signal 31b is a selection control signal used to characterize the user's requirements and selection of the operating mode of the signal generation circuit. When the user selects a mode with smaller pulse width fluctuations in the functional pulse signal 30a, or in other words, a mode less affected by process angle, operating voltage, and operating temperature, the second signal selector 31 outputs the target signal; when the user selects a mode with larger pulse width fluctuations in the functional pulse signal 30a, or in other words, a mode more affected by process angle, operating voltage, and operating temperature, i.e., the real environment mode, the second signal selector 31 outputs the native signal.

[0052] In this embodiment, latch 32 has a first input terminal and a second input terminal. The first input terminal is used to receive an initial pulse signal 1, and the second input terminal is used to receive a target signal 20a or a native signal 40a. If the level of the first input terminal is detected to become high, latch 32 continuously outputs a high-level signal until the level of the second input terminal is detected to become high, at which point the output of latch 32 changes from high to low. Latch 32 can be configured as an SR latch.

[0053] In this embodiment, each physical delay module 20 is composed of inverters connected in series. Specifically, each physical delay module 20 consists of m inverters connected in series, where m is an even number. Each inverter has a preset output hysteresis, and the sum of the m preset output hysteresis values ​​equals the second delay duration. The smaller m is, the smaller the preset delay duration and the smaller the first preset range. The preset output hysteresis of the inverters is affected by process angle, operating temperature, and operating voltage. The delay fluctuation of the physical delay module 20 is the sum of the preset output hysteresis fluctuations of the m inverters. The fewer the number of inverters, the smaller the delay fluctuation of the physical delay module 20.

[0054] It is understood that each delay unit in the physical delay module 20 is composed of an even number of inverters connected in series, and the number of inverters contained in different delay units may be the same or different; in addition, in this paper, the functional pulse signal 30a is a column address strobe signal.

[0055] The generation of the functional pulse signal 30a will be described in detail below, taking the first clock unit 11, the second clock unit 12, the third clock unit 13, the fourth clock unit 14 and the fifth clock unit 15 as examples, each including only one D flip-flop.

[0056] refer to Figure 4 and Figure 5 The initial pulse signal 1 is generated based on the clock signal 2. The pulse width of the initial pulse signal 1 is equal to one clock cycle of the clock signal 2. However, due to the output hysteresis of the generating device itself, the starting time of the rising edge of the initial pulse signal 1 is slightly delayed relative to the starting time of the first rising edge of the clock signal 2.

[0057] After receiving the initial pulse signal 1, the first clock unit 11 delays the initial pulse signal 1 by one clock cycle to obtain the first intermediate signal 11a. It should be noted that, since the D flip-flop itself also has output hysteresis, the rising edge of the first intermediate signal 11a is slightly delayed compared to the second rising edge of the clock signal 2.

[0058] Similarly, the second clock unit 12 delays the first intermediate signal 11a by one clock cycle based on the rising edge of the clock signal 2 to obtain the second intermediate signal 12a. The rising edge of the second intermediate signal 12a is slightly delayed compared to the third rising edge of the clock signal 2. The third clock unit 13 delays the second intermediate signal 12a by one clock cycle to obtain the third intermediate signal 13a. The fourth clock unit 14 delays the third intermediate signal 13a by one clock cycle to obtain the fourth intermediate signal 14a. The fifth clock unit 15 delays the fourth intermediate signal 14a by one clock cycle to obtain the fifth intermediate signal 15a.

[0059] After receiving the initial pulse signal 1, the native delay module 40 delays the initial pulse signal 1 by a preset delay duration to obtain the native signal 40a. The preset delay duration is the target duration. Because the preset delay duration of the native delay module 40 is relatively large, the delay of the native signal 40a relative to the initial pulse signal 1 fluctuates significantly relative to the target duration. In addition, the native delay module 40 is generally composed entirely of inverters connected in series, and the fluctuation range of the native signal 40a is determined by the number of inverters.

[0060] Figure 5In the signal diagram shown, the first signal selector 26 controls the output terminal of the first signal selector 26 to connect with the output terminal of the fifth delay unit 25 according to the first flag signal 20b. After receiving the fifth intermediate signal 15a output by the corresponding fifth clock unit 15, the physical delay module 20 further delays the fifth intermediate signal 15a to obtain the target signal 20a. The second signal selector 31 outputs the target signal 20a according to the second flag signal 31b. The latch 32 outputs the function pulse signal 30a according to the initial pulse signal 1 and the target signal 20a.

[0061] It should be noted that during the actual connection of the D flip-flop and inverter, if the target delay duration cannot be obtained precisely, the connection should be made according to the rule that the actual target duration should be larger rather than smaller. That is, the sum of the first delay duration and the second delay duration should not be less than the target duration, thereby ensuring that the pulse width of the CSL signal can meet the preset requirements, that is, data reading and writing are completed within the pulse width of the CSL signal. Based on the above rule, when the clock cycle interval contains multiple typical values, the smallest typical value is selected to represent the clock cycle interval, thereby controlling the pulse width of the CSL signal to meet the read and write time requirements when the actual clock cycle is short. Specifically, if the pulse width of the CSL signal can meet the preset requirements when the actual clock cycle is short, then the pulse width of the CSL signal will necessarily meet the preset requirements when the actual clock cycle is long.

[0062] In one embodiment, the first clock unit 11 includes multiple D flip-flops connected in series. The first clock period is 1.5 ns, the second clock period is 1.07 / 1.25 ns, the third clock period is 0.83 ns / 0.93 ns, the fourth clock period is 0.75 ns, the fifth clock period is 0.625 / 0.68 ns, the target duration is 3.5 ns, and the preset output hysteresis of a single inverter is 0.05 ns. Accordingly, based on the above rules, 1.07 ns is selected to represent the second clock period, 0.83 ns is selected to represent the third clock period, and 0.625 ns is selected to represent the fifth clock period.

[0063] The specific value of the target duration is determined based on the pulse width requirement of the CSL signal, and the numerical range of multiple clock cycles is determined based on the parameters of tccd. Taking a Dynamic Random Access Memory (DRAM) DDR4 chip as an example, the correspondence between tccd parameters and data transfer rate, clock frequency, and clock cycle is as follows:

[0064]

[0065] Based on the above examples and rules, the first clock unit 11 can be configured to contain 2 D flip-flops, and the first delay unit 21 can be configured to contain 10 inverters. Under the condition that the clock period is the first clock period, the sum of the first delay duration and the second delay duration is 1.5×2+0.05×10=3.5ns; the second clock unit 12 can be configured to contain one D flip-flop, and the second delay unit 22 can be configured to contain 6 inverters. Under the condition that the clock period is the second clock period, the sum of the first delay duration and the second delay duration is 1.07×3+0.05×6=3.51ns; the third clock unit 13 can be configured to contain one D flip-flop, and the third delay unit 23 can be configured to contain 4 inverters. Under the condition that the clock period is the third clock period, the sum of the first delay duration and the second delay duration is 0.83×4+0.05×4=3.52ns.

[0066] Since the first delay duration will time out even if the fourth clock unit 14 contains only one D flip-flop when the clock cycle is the fourth clock cycle, i.e., 0.75×5=3.75>3.5ns, the fourth clock unit 14 can be removed or set to have no delay wire, so that the output of the third clock unit 13 is actually connected to the input of the third delay unit 23 and the input of the fourth delay unit 24 respectively. At the same time, the fourth delay unit 24 is set to contain 10 inverters, so that when the clock cycle is the fourth clock cycle, the sum of the first delay duration and the second delay duration is 0.75×4+0.05×10=3.5ns.

[0067] In other embodiments, each clock unit may be configured to contain only one D flip-flop; or, the first clock unit may contain a first D flip-flop and a second D flip-flop, with the data output terminal of the first D flip-flop connected to the data input terminal of the second D flip-flop. The first D flip-flop is used to receive an initial pulse signal and a clock signal, and the second D flip-flop is used to receive a clock signal and output a first intermediate signal. The second clock unit is connected in series between the first D flip-flop and the second delay unit. In this case, both the second clock unit and the third clock unit contain only one D flip-flop.

[0068] Furthermore, since the first delay duration corresponding to the fourth intermediate signal 14a is equal to 4 clock cycles, and when the clock cycle is the fourth clock cycle, the number of inverters contained in the fourth delay unit 24 is the same as the number of inverters contained in the first delay unit 21. Therefore, the fourth delay unit 24 can be discarded, and the first delay unit 21 can also be configured to receive the fourth intermediate signal 14 and the first flag signal 20b, so as to receive the first intermediate signal 11a or the fourth intermediate signal 14a according to the first flag signal 20b.

[0069] In addition, if the fourth clock unit 14 has no actual delay and the first delay duration corresponding to the fourth intermediate signal 14a is equal to 4 clock cycles, the fifth clock unit 15 can be configured to contain a D flip-flop and the fifth delay unit 25 can contain 8 inverters. Under the condition that the clock cycle is the fifth clock cycle, the sum of the first delay duration and the second delay duration is 0.625×5+0.05×8=3.525ns.

[0070] If the preset output hysteresis of a single inverter under normal conditions is 0.05ns, then to achieve a delay duration of 3.5ns, 70 inverters connected in series are required to form the native delay module 40. The following assumes that the preset output hysteresis of the inverters in each delay unit of the native delay module 40 and the physical delay module 20 fluctuates between 0.04ns and 0.06ns. 0.06ns represents the preset output hysteresis of the inverter under SS process corner, high temperature, and low pressure conditions, while 0.04ns represents the preset output hysteresis of the inverter under FF process corner, low temperature, and high pressure conditions. The differences between generating the functional pulse signal 30a using the target signal 20a and generating the functional pulse signal 30a using the native signal 40a will be explained in detail.

[0071] In the first clock cycle, the delay of the target signal 20a relative to the initial pulse signal 1 is between 3.4ns and 3.6ns. In the second clock cycle, the delay is between 3.45ns and 3.57ns. In the third clock cycle, the delay is between 3.48ns and 3.56ns. In the fourth clock cycle, the delay is between 3.4ns and 3.6ns. In the fifth clock cycle, the delay is between 3.445ns and 3.605ns. In other words, in different clock cycles, the pulse width of the functional pulse signal 30a generated based on the target signal 20a and the initial pulse signal 1 is between 3.4ns and 3.605ns.

[0072] Correspondingly, the delay of the native signal 40a compared to the initial pulse signal 1 is between 2.8ns and 4.2ns. Clearly, the pulse width of the functional pulse signal 30a obtained from the target signal 20a and the initial pulse signal 1 has higher stability and can be effectively applied to different process angle conditions, ensuring effective data reading and writing.

[0073] In this embodiment, the clock delay module and the physical delay module are used to delay the initial pulse signal together, shortening the second delay duration that needs to be achieved by the physical delay module. This reduces the delay fluctuations caused by the physical delay module, making the delay of the target signal relative to the initial pulse signal closer to the target duration. This allows for accurate control of the pulse width of the functional pulse signal and improves the efficiency of the functional pulse signal.

[0074] Accordingly, embodiments of the present invention also provide a memory that includes the signal generation circuit of any of the above-mentioned methods, thereby providing the memory with a high read / write success rate and high reliability.

[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A signal generation circuit, characterized in that, include: A clock delay module is used to receive a clock signal and an initial pulse signal, and to delay the initial pulse signal to output an intermediate signal, wherein the intermediate signal is delayed by a first delay duration relative to the initial pulse signal, and the first delay duration is equal to one or more clock cycles of the clock signal; A physical delay module is used to receive and delay the intermediate signal to output a target signal. The preset delay time of the physical delay module is a second delay time. If the actual delay time of the physical delay module is equal to the second delay time, the target signal is delayed by the target time compared to the initial pulse signal. The difference between the actual delay time and the second delay time fluctuates within a first preset range. The shorter the second delay time, the narrower the first preset range. The generation module is used to receive the initial pulse signal and the target signal, and output a functional pulse signal, wherein the pulse width of the functional pulse signal is equal to the time interval between the rising edge of the initial pulse signal and the rising edge of the target signal; A native delay module is used to receive and delay the initial pulse signal to output a native signal. The preset delay duration of the native delay module is the target duration. The difference between the actual delay duration of the native delay module and the target duration fluctuates within a second preset range. The shorter the target duration, the narrower the second preset range. The generation module includes: A second signal selector is configured to receive the native signal and the target signal, and to receive a second flag signal, and to output the native signal or the target signal according to the second flag signal; A latch is used to receive the initial pulse signal and the native signal or the target signal. If the native signal is received, the pulse width of the functional pulse signal is equal to the time interval between the rising edge of the initial pulse signal and the rising edge of the native signal.

2. The signal generation circuit according to claim 1, characterized in that, The first delay duration is equal to n clock cycles, and the clock delay module is also used to output multiple intermediate signals, with different values ​​of n corresponding to different intermediate signals, where n is a positive integer. The physical delay module is further configured to receive a first flag signal, the first flag signal representing the value of the clock cycle, and to receive one of the plurality of intermediate signals according to the first flag signal and adjust the second delay duration so that the sum of the first delay duration corresponding to the received intermediate signal and the second delay duration is equal to the target duration.

3. The signal generation circuit according to claim 1, characterized in that, The clock cycle is one of a plurality of different values, and the first delay duration varies according to the value of the clock cycle; the physical delay module is further configured to adjust the second delay duration according to the first delay duration, so that the sum of the first delay duration and the second delay duration is equal to the target duration.

4. The signal generation circuit according to claim 2, characterized in that, The clock cycle includes a first clock cycle or a second clock cycle; the clock delay module is at least used to output a first intermediate signal and a second intermediate signal, wherein the first delay duration corresponding to the first intermediate signal is equal to x clock cycles, and the first delay duration corresponding to the second intermediate signal is equal to y clock cycles, where x and y are positive integers; the physical delay module includes: A first delay unit is configured to receive the first intermediate signal, wherein the preset delay duration of the first delay unit and x first clock cycles are equal to the target duration. The second delay unit is used to receive the second intermediate signal, wherein the preset delay duration of the second delay unit and the sum of y second clock cycles equals the target duration; A first signal selector has a first input terminal connected to the output terminal of the first delay unit, a second input terminal connected to the output terminal of the second delay unit, and an output terminal connected to the input terminal of the generation module. It is used to receive a first flag signal. If the first flag signal indicates that the clock period is the first clock period, then the output terminal of the first signal selector is connected to the first input terminal; if the first flag signal indicates that the clock period is the second clock period, then the output terminal of the first signal selector is connected to the second input terminal.

5. The signal generation circuit according to claim 4, characterized in that, The first flag signal represents the delay between adjacent column address strobe signals.

6. The signal generation circuit according to claim 4, characterized in that, y>x; The clock delay module includes: a first clock unit, the output of which is connected to the input of the first delay unit, for receiving the initial pulse signal and outputting the first intermediate signal; The second clock unit is connected between the first clock unit and the second delay unit, and is used to receive and delay the first intermediate signal and output the second intermediate signal.

7. The signal generation circuit according to claim 6, characterized in that, The first clock unit consists of x delay units connected in series. The delay units are used to receive and delay signals, and the delay duration of the delay units is equal to one clock cycle. The second clock unit consists of yx delay units connected in series.

8. The signal generation circuit according to claim 7, characterized in that, The pulse width of the initial pulse signal is equal to the clock period, the rising edge of the initial pulse signal is the same as the rising edge of the clock signal, the delay unit is a D flip-flop, the triggering mode of the D flip-flop is edge-triggered, and the trigger input terminal of the D flip-flop is used to receive the clock signal.

9. The signal generation circuit according to claim 4, characterized in that, The clock cycle further includes a third clock cycle, a fourth clock cycle, or a fifth clock cycle; the clock delay module is used to output at least a third intermediate signal, a fourth intermediate signal, and a fifth intermediate signal, wherein the first delay duration corresponding to the third intermediate signal is equal to a clock cycles, the first delay duration corresponding to the fourth intermediate signal is equal to b clock cycles, and the first delay duration corresponding to the fifth intermediate signal is equal to c clock cycles, where a, b, and c are positive integers; The physical delay module also includes: The third delay unit is used to receive the third intermediate signal, and the preset delay duration of the third delay unit and the sum of a third clock cycles equals the target duration. The fourth delay unit is used to receive the fourth intermediate signal, and the preset delay duration of the fourth delay unit and b of the fourth clock cycles are equal to the target duration. The fifth delay unit is used to receive the fifth intermediate signal, and the preset delay duration of the fifth delay unit and the sum of c fifth clock cycles equals the target duration; The third input terminal of the first signal selector is connected to the output terminal of the third delay unit, the fourth input terminal of the first signal selector is connected to the output terminal of the fourth delay unit, and the fifth input terminal of the first signal selector is connected to the output terminal of the fifth delay unit. The first flag signal is also used to characterize the three clock cycles, the fourth clock cycle, or the fifth clock cycle, and the first signal selector is also used to control the output terminal of the first signal selector to be connected to the output terminal of the third delay unit, the output terminal of the fourth delay unit, or the output terminal of the fifth delay unit according to the first flag signal.

10. The signal generation circuit according to claim 1, characterized in that, The latch has a first input terminal and a second input terminal. The first input terminal is used to receive the initial pulse signal, and the second input terminal is used to receive the target signal or the original signal. If the level of the first input terminal is detected to become high, the latch continuously outputs a high-level signal until the level of the second input terminal is detected to become high, at which point the output high level of the latch changes back to low level.

11. The signal generation circuit according to claim 1, characterized in that, The physical delay module is composed of m inverters connected in series, where m is an even number. Each inverter has a preset output hysteresis, and the sum of the m preset output hysteresis is equal to the second delay duration. The smaller m is, the narrower the first preset range.

12. The signal generation circuit according to claim 1, characterized in that, The functional pulse signal is a column address strobe signal.

13. A memory, characterized in that, The signal generation circuit includes any one of claims 1 to 12.

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