Array switch circuitry and switch circuit

Abstract

An array switch circuit system includes a plurality of contact units arranged in an array, wherein each contact unit includes a conductive pad, a first row channel, a first column channel, a bridge channel, a second row channel, and a second column channel. The first row channel is provided with a first switch element. The first column channel is connected to the first row channel and is provided with a second switch element. The bridge channel connects the conductive pad to the first row channel or the first column channel. The second row channel is connected to the conductive pad through a third switch element. The second column channel is connected to the conductive pad through a fourth switch element. The first row channels of the contact units having the same row position are connected to each other and the second row channels are connected to each other. The first column channels of the contact units having the same column position are connected to each other and the second column channels are connected to each other.

Description

Technical Field

[0001] This invention relates to an array switch circuit system, and more particularly to an array switch circuit system applicable to system packaging. Background Technology

[0002] System-on-a-Package (SoC) integrates multiple chips into a single integrated circuit (IC). In modern SoCs, the connections between chips and the input / output pins are routed using redistribution layers (RDLs). Once the RDL routing design is complete, it is sent to a packaging company for manufacturing and packaging. After packaging, it is then sent to a testing company for IC testing. Because all redistribution layers are custom-produced by the packaging company, if modifications to the redistribution routing or replacement of chips are discovered after testing, the redistribution layer must be redesigned, increasing product development time and costs. Furthermore, packaging companies are less willing to accept orders for products with low production volume. Summary of the Invention

[0003] In view of the above, the present invention provides an array switch circuit system and a switch circuit that can be applied to system packaging. By controlling the switching elements in the array switch circuit system, different winding combinations can be formed with the wire redistribution layer, so that the wire redistribution layer no longer needs to be customized, and the situation of needing to redesign the wire redistribution layer during the research and development process can be avoided, thereby shortening the product development time and reducing the research and development cost.

[0004] An array switch circuit system according to an embodiment of the present invention includes a plurality of contact units arranged in an array, wherein each contact unit includes a conductive pad, a first row channel, a first column channel, a connecting channel, a second row channel, and a second column channel. A first row channel is provided with a first switching element. A first column channel is connected to the first row channel and is provided with a second switching element. A connecting channel connects the conductive pad to either the first row channel or the first column channel. A second row channel is connected to the conductive pad via a third switching element. A second column channel is connected to the conductive pad via a fourth switching element. Specifically, the first row channels of each of the plurality of contact units having the same row position are connected to each other; the second row channels of each of the plurality of contact units having the same row position are connected to each other; the first column channels of each of the plurality of contact units having the same column position are connected to each other; and the second column channels of each of the plurality of contact units having the same column position are connected to each other.

[0005] A switching circuit according to an embodiment of the present invention includes a transmission gate and a base voltage control sub-circuit. The transmission gate has an input terminal, an output terminal, two gate control terminals, and two base control terminals, and is used to turn the input terminal and the output terminal on or off according to the voltage of the two gate control terminals. The base voltage control sub-circuit is connected to the input terminal and the base control terminals of the transmission gate, and is used to adjust the voltage of the base control terminals according to the voltage of the input terminal when the input terminal and the output terminal are on, so that the voltage difference between the input terminal and the base control terminals is less than a preset value.

[0006] With the above structure, the array switch circuit system disclosed in this invention integrates both checkerboard and high-speed channel architectures, allowing selection of the optimal signal transmission path based on signal characteristics. Furthermore, the system package can be configured with a single conductor routing layer to provide various winding combinations, thereby shortening product development time and reducing development costs. In addition, the switch circuit disclosed in this invention has a sub-circuit that dynamically tracks the input signal voltage to control the base voltage, providing a wider channel bandwidth compared to traditional transmission gate switches.

[0007] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the system package structure according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram of an array switch circuit system according to an embodiment of the present invention.

[0010] Figure 3A This is a schematic diagram of a contact unit in an array switch circuit system according to another embodiment of the present invention.

[0011] Figure 3B This is a schematic diagram of a contact unit in an array switch circuit system according to another embodiment of the present invention.

[0012] Figure 4 For the reason Figure 3B The diagram shows a schematic of an array switch circuit system formed by contact units.

[0013] Figure 5 This is a schematic diagram of an array switch circuit system according to another embodiment of the present invention.

[0014] Figure 6 for Figure 5 A schematic diagram of a portion of the array switch circuit system is shown.

[0015] Figure 7This is a functional block diagram of an array switch circuit system according to another embodiment of the present invention.

[0016] Figure 8 This is a schematic diagram of a switching circuit according to an embodiment of the present invention.

[0017] Figure 9 This is a circuit diagram of a switching circuit according to an embodiment of the present invention.

[0018] In the attached figures, the following labels are used:

[0019] A System Encapsulation

[0020] A1 Conductor Relay Layer

[0021] A2 Through-hole layer

[0022] A3 Silicon Through-Hole Layer

[0023] C1 First Chip

[0024] C2 Second Chip

[0025] C3 Connector Chip

[0026] C11, C12, C21, C22 pins

[0027] P position

[0028] TMV through-hole

[0029] TSV (Through Silicon Via)

[0030] SB solder balls

[0031] 1, 1', 1”, 3 array switch circuit system

[0032] 11, 11', 11" contact units

[0033] Conductive pads 111, 111a~111d

[0034] 131 First line of passage

[0035] 133 First Switching Element

[0036] 135 Connecting Channel

[0037] 151 First Aisle

[0038] 153 Second Switching Element

[0039] 171 Second row of channels

[0040] 173 Third Switching Element

[0041] 191 Second Channel

[0042] 193 Fourth Switching Element

[0043] 132 Third line channel

[0044] 134 Fifth Switching Element

[0045] 137 Connecting switch element

[0046] 152 Third Channel

[0047] 154 Sixth Switching Element

[0048] 172 Fourth row channel

[0049] 174 Seventh Switching Element

[0050] 192 Fourth Aisle

[0051] 194 Eighth Switching Element

[0052] Switching elements 133a, 134a, 137a, 193a, 193c, 137d, 154d

[0053] 10 Array Areas

[0054] 20a~20d Extended pin area

[0055] 31-Switch Array

[0056] 33 Switch control circuit

[0057] 35. Memory

[0058] 37 Microcontrollers

[0059] 39 Pre-written circuit

[0060] 6 Partial Areas

[0061] 211 Extended Conductive Pad

[0062] 213 Switchgear

[0063] 500 Switching Circuit

[0064] 501 First Transmission Gate

[0065] 503 Base Voltage Control Sub-circuit

[0066] P1 First Input Terminal

[0067] P2 First Output Terminal

[0068] P3, P4 First gate control terminals

[0069] P5, P6 base control terminals

[0070] SW control terminal

[0071] M1 to M8 transistors

[0072] Vdd operating voltage Detailed Implementation

[0073] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0074] Please refer to Figure 1 , Figure 1 This is a schematic diagram illustrating the structure of system package A according to an embodiment of the present invention. Figure 1 As shown, system package A includes a first chip C1, a second chip C2, a redistribution layer (RDL) A1, a connector chip C3, a through-hole layer A2, a silicon via layer A3, and a ball grid array (BGA) formed by multiple solder balls SB. The connector chip C3 and the through-hole layer A2 are disposed between the redistribution layer A1 and the silicon via layer A3. The first chip C1 and the second chip C2 are disposed on the opposite sides of the connecting chip C3 and the through-hole layer A2 on the redistribution layer A1, and the solder balls SB are disposed on the opposite sides of the connecting chip C3 and the through-hole layer A2 on the silicon via layer A3.

[0075] The first chip C1 has multiple pins C11 and C12, and the second chip C2 has multiple pins C21 and C22. The wiring redistribution layer A1 may contain multiple unconnected wire lines. The connection chip C3 includes an array switch circuit system, which comprises multiple conductive pads and multiple switching elements. The switching elements can be controlled to conduct channels between different combinations of conductive pads; that is, the connection chip C3 is a programmable chip. The detailed architecture of the array switch circuit system of the connection chip C3 will be described later. The through-hole layer A2 contains multiple through-hole (TMV) vias. The through-silicon via (TSV) layer A3 contains multiple through-silicon vias. Pins C11 and C12 of the first chip C1 and pins C21 and C22 of the second chip C2 can be connected to conductive pads at different locations P of the connection chip C3 via multiple wire lines in the wiring redistribution layer A1. The switching element of the connecting chip C3 is controlled to conduct the conductive pads connected to pin C11 and C21, the conductive pad connected to pin C12 and another conductive line (the first conductive line) in the conductor redistribution layer A1, and the conductive pad connected to pin C22 and yet another conductive line (the second conductive line) in the conductor redistribution layer A1. The first and second conductive lines are then connected to the solder ball SB through through-hole vias (TMV) in through-hole layer A2 and through-silicon vias (TSV) in through-silicon via layer A3, respectively.

[0076] Figure 1 The conductive path shown is merely an example. The switching element in the connecting chip C3 can also be controlled to open channels between different conductive pads, and other winding combinations can be provided in conjunction with the wire redistribution layer A1. In other words, a single-circuit design wire redistribution layer, combined with the connecting chip, can provide multiple winding combinations. In this way, for different chip system packages, it is not necessary to design wire redistribution layers with different wire lines, thereby shortening product development time and reducing development costs. Furthermore, Figure 1 The number of chip pins, wire lines, and vias shown are merely examples and are not intended to limit the scope of this invention.

[0077] The following will describe several embodiments of the architecture of the array switch circuit system connected to chip C3. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of an array switch circuit system 1 according to an embodiment of the present invention. Figure 2 As shown, the array switch circuit system 1 includes a plurality of contact units 11 arranged in an array. Each contact unit 11 includes a conductive pad 111, a first row channel 131, a first column channel 151, a connecting channel 135, a second row channel 171, and a second column channel 191, wherein the plurality of channels can be implemented by wires.

[0078] The first row channel 131 is provided with a first switching element 133. The first column channel 151 is connected to the first row channel 131 and is provided with a second switching element 153. The connecting channel 135 connects the conductive pad 11 to the first row channel 131 or the first column channel 151. Figure 2 Taking the connection to the first row channel 131 as an example. The second row channel 171 is connected to the conductive pad 111 via a third switching element 173. The second column channel 191 is connected to the conductive pad 111 via a fourth switching element 193. In the array, each contact unit 11 has a row position and a column position, wherein the first row channels 131 of contact units 11 with the same row position are connected to each other, the second row channels 171 of contact units 11 with the same row position are connected to each other, the first column channels 151 of contact units 11 with the same column position are connected to each other, and the third column channels 191 of contact units 11 with the same column position are connected to each other.

[0079] Specifically, the first row channel 131, the first switching element 133, the first column channel 151, the second switching element 153, and the connecting channel 135 of the contact unit 11 can together form a checkerboard architecture, while the second row channel 171, the third switching element 173, the second column channel 191, and the fourth switching element 193 can together form a high-speed channel architecture. The checkerboard architecture is suitable for general signal transmission, while the high-speed channel architecture is suitable for signal transmission between contact units 11 that are spaced far apart (e.g., more than five contact units 11 apart) or for signals requiring high-speed transmission. In other words, the array switch circuit system 1 integrates both checkerboard and high-speed channel architectures, allowing for optimal selection based on signal characteristics.

[0080] Please refer to Figure 3A and 3B ,in Figure 3A This is a schematic diagram of a contact unit 11' in an array switch circuit system according to another embodiment of the present invention. Figure 3B This is a schematic diagram of contact unit 11" in an array switch circuit system according to another embodiment of the present invention. Figure 3A and 3B As shown, contact unit 11' / 11" except Figure 2In addition to the conductive pad 111, the first row channel 131, the first column channel 151, the connecting channel 135, the second row channel 171, and the second column channel 191 shown, the system further includes a third row channel 132, a third column channel 152, a fourth row channel 172, and a fourth column channel 192, wherein the multiple channels can be implemented with wires. The third row channel 132 is provided with a fifth switching element 134. The third column channels 152 are respectively connected to the third row channel 132, and each is provided with a sixth switching element 154. The fourth row channel 172 is connected to the conductive pad 111 via a seventh switching element 174. The fourth column channel 192 is connected to the conductive pad 111 via an eighth switching element 194.

[0081] Figure 3A and 3B The illustration exemplarily depicts the first channel in the third row 132 connected to the first row 131 via a connecting switch element 137, with the other third row channels 132 sequentially connected via connecting switch elements 137. In other embodiments, the connecting switch element 137 may be disposed between the third column channels 152 and the first column channels 151; that is, the first channel in the third column channels 152 is connected to the first column channels 151 via connecting switch element 137, and the other third column channels 152 are sequentially connected via connecting switch elements 137. It should also be noted that... Figure 3A and 3B The number of the third row channel 132, the third column channel 152, the fourth row channel 172, the fourth column channel 192, the fifth switch element 134, the sixth switch element 154, the seventh switch element 174, the eighth switch element 194, and the connecting switch element 137 shown is merely an example, and the present invention is not limited thereto.

[0082] In an array composed of multiple contact units 11' / 11" arranged together, each contact unit 11' / 11" has a row position and a column position. For contact units 11' / 11" with the same row position, their first row channels 131 are connected to each other, their second row channels 171 are connected to each other, their third row channels 132 are connected to each other, and their fourth row channels 172 are connected to each other. For contact units 11' / 11" with the same column position, their first column channels 151 are connected to each other, their second column channels 191 are connected to each other, their third column channels 152 are connected to each other, and their fourth column channels 192 are connected to each other.

[0083] Specifically, Yu You Figure 3AIn the array of contact units 11', the first row channel 131, the first switching element 133, the first column channel 151, the second switching element 153, the third row channel 132, the fifth switching element 134, the third column channel 152, the sixth switching element 154, the connecting channel 135, and the connecting switching element 137 of the contact units 11' can together form a checkerboard structure, while the second row channel 171, the third switching element 173, the second column channel 191, the fourth switching element 193, the fourth row channel 172, the seventh switching element 174, the fourth column channel 192, and the eighth switching element 194 can together form a high-speed channel structure; Figure 3B In the array of 11" contact units, the chessboard-like structure is composed of the same elements as those in the array. Figure 3A The grid-like architecture is formed by an array of 11' contact units, while the high-speed channel architecture, in addition to... Figure 3A The high-speed channel architecture is composed of an array of contact units 11' arranged in an array, and further includes a first row channel 131 and a connecting channel 135. The connecting channel 135 connects the conductive pad 111 and the first row channel 131, and also connects the first row channel 131 with the third and seventh switching elements 173 and 174.

[0084] As mentioned earlier, the checkerboard architecture is suitable for general signal transmission, while the high-speed channel architecture is suitable for signal transmission between widely spaced contact units 11' / 11 (e.g., more than 5 contact units 11' / 11") or for signals requiring high-speed transmission. By integrating the checkerboard and high-speed channel architectures, the array switching circuit system can arbitrarily combine the connections between contact units through control signals and can make optimal selections based on signal characteristics. Furthermore, the checkerboard and high-speed channel architectures proposed in the aforementioned embodiments of the present invention both exhibit excellent signal transmission speeds. Experiments using 20 contact units as the transmission distance show that the checkerboard architecture can achieve a transmission speed of 100 Mb / s, while the high-speed channel architecture can achieve a transmission speed of 2 Gb / s.

[0085] The following example illustrates the operation of an array switching circuit system. Please refer to... Figure 4 , Figure 4 For the reason Figure 3B The diagram shows an array switch circuit system 1' formed by the contact unit 11". For Figure 4In the array switch circuit system 1' shown, when the circuit design requires conductive pad 111a to be electrically connected to conductive pad 111b, switch element 133a can be turned on to open the channel between conductive pad 111a and conductive pad 111b; when the circuit design requires conductive pad 111a to be electrically connected to conductive pad 111c, switch elements 193a and 193c can be turned on to open the channel between conductive pad 111a and conductive pad 111c; when the circuit design requires conductive pad 111a to be electrically connected to conductive pad 111d, switch elements 137a, 134a, 154d and 137d can be turned on to open the channel between conductive pad 111a and conductive pad 111d.

[0086] Please refer to Figure 5 ,in Figure 5 This is a schematic diagram of an array switching circuit system 1” according to another embodiment of the present invention. Figure 5 As shown, the array switch circuit system 1” includes an array region 10 and extension pin regions 20a, 20b, 20c, and 20d respectively connected to the four sides of the array region 10. The array region 10 is provided with an array of contact units, and the extension pin regions 20a, 20b, 20c, and 20d each have multiple extended conductive pads, which are connected to the contact units located on the sides of the array via multiple wires and multiple extended switching elements. It should be noted that… Figure 5 The diagram exemplarily illustrates that each of the four sides of the array region 10 is provided with extension pin regions 20a, 20b, 20c, and 20d; however, in other embodiments, only one to three of these may be provided. Furthermore, please refer to... Figure 5 and Figure 6 ,in Figure 6 for Figure 5 A schematic diagram of a portion 6 of the array switch circuit system 1” shown. Figure 6 As shown, array region 10 is provided with Figure 3B The array shown is composed of contact units 11”, but it is only an example. The array area 10 may be provided with Figure 2 The contact unit 11 shown or Figure 3A The array of contact units 11' shown. Each of the extended pin areas 20a and 20b is provided with a plurality of extended conductive pads 211 and a switch group 213 containing a plurality of extended switching elements. The extended conductive pads 211 are connected to the respective channel groups of the contact units 11" located on the side of the array through the switch group 213.

[0087] Taking extended pin area 20a as an example, the channel group is composed of column channels of contact unit 11", namely, the first row channel, the second row channel, the third row channel, and the fourth row channel mentioned above. Taking extended pin area 20b as an example, the channel group is composed of column channels of contact unit 11", namely, the first column channel, the second column channel, the third column channel, and the fourth column channel. The architectures of extended pin areas 20c and 20d are symmetrical to the architectures of extended pin areas 20a and 20b, respectively, and will not be described in detail here. As mentioned above, the contact units provided in array area 10 can also be Figure 2 In this embodiment, the contact unit 11 shown comprises a channel group consisting of a first row of channels and a second row of channels connected to the extended pin regions 20a and 20c, and a channel group consisting of a first column of channels and a second column of channels connected to the extended pin regions 20b and 20d. That is, the number of extended conductive pads 211 and the number of extended switching elements in the extended pin regions 20a and 20c are the same as the number of row channels in the array region 10, and the number of extended conductive pads 211 and the number of extended switching elements in the extended pin regions 20b and 20d are the same as the number of column channels in the array region 10. In this way, each signal path has an independent extended pin, and thus has the characteristic of being independently connectable.

[0088] By utilizing the architecture of one or more of the extended pin areas 20a to 20d, multiple interconnecting chips, each equipped with an array switch circuit system 1", can be interconnected to achieve cross-chip input / output (I / O) connections. For example, the conductive pad 211 in the extended pin area 20a of one array switch circuit system 1" can be connected to the conductive pad 211 in the extended pin area 20c of another array switch circuit system 1"; the conductive pad 211 in the extended pin area 20b of one array switch circuit system 1" can be connected to the conductive pad 211 in the extended pin area 20d of another array switch circuit system 1". Furthermore, by utilizing the switch groups 213 in the extended pin areas 20a to 20d, the combination of multiple array switch circuit systems 1" can control whether to enable the cross-chip signal transmission function as needed, providing great design flexibility.

[0089] Specifically, in any of the above embodiments, the switching elements in the array switching circuit system can be controlled by an external control device (e.g., a microcontroller), or the array switching circuit system can further include a memory connected to the control terminals of each switching element. The memory, for example, is a non-volatile memory such as a read-only memory or flash memory, which can store control signals written by the external control device (e.g., a microcontroller) to control the switching state of each switching element, and can read and record the switching state of each switching element. In one embodiment, the aforementioned external control device may be included in the array switching circuit system.

[0090] Please refer to Figure 7 , Figure 7 This is a functional block diagram of an array switching circuit system according to another embodiment of the present invention. Figure 7 As shown, the array switch circuit system 3 includes a switch array 31, a switch control circuit 33, a memory 35, a microcontroller 37, and a pre-write circuit 39. The switch control circuit 33 is connected to the switch array 31, and the memory 35 is connected to both the switch control circuit 33 and the microcontroller 37. The microcontroller 37 is connected to the switch control circuit 33 not only through the memory 35 but also through the pre-write circuit 39 (not through the memory 35). Furthermore, the memory 35 can be connected to the control terminals of the switching elements in the switch array 31 via the switch control circuit 33, and the microcontroller 37 can be connected to the control terminals of the switching elements in the switch array 31 via the switch control circuit 33. It should be noted that… Figure 7 The connection relationship between the components / circuits of the array switch circuit system 3 is illustrated by a single line, without intending to limit the number of connection lines between the components / circuits.

[0091] The switch array 31 can be an array composed of any or more contact units described in the foregoing embodiments, or it can include... Figure 5 The array area and extended pin area described in the embodiment. The switch control circuit 33 can receive control signals from the memory 35 or the microcontroller 37 and control the switching elements in the switch array 31 accordingly. For example, the switch control circuit 33 may include control elements such as a D flip-flop, a decoder, and an SR flip-flop, and its circuit configuration can be designed as needed by those skilled in the art to which this invention pertains, and this invention is not limited thereto. The memory 35 can be a one-time programmable (OTP) memory or a multiple-time programmable (MTP) memory. The microcontroller 37 is used to write instructions (e.g., program code) for controlling the switch array 31 into the memory 35, so that the memory 35 can control the switching state of the switching elements in the switch array 31 through the switch control circuit 33 according to the instructions. The pre-write circuit 39 may include one or more lines. In one embodiment, the microcontroller 37 can control the switch array 31 and perform AC testing using the pre-write circuit 39 and switch control circuit 33 before writing the instructions for controlling the switch array 31 into the memory 35. After the AC test is passed, the instructions are then written into the memory 35. Furthermore, the pre-write operation and AC test can be performed by an operator controlling the microcontroller 37.

[0092] In this way, for the array switch circuit system 3 that uses OTP memory as memory 35, the problem of having to discard the entire system due to errors only being discovered in subsequent testing stages after directly writing control instructions into memory 35 can be avoided, thus reducing testing costs. In particular, the microcontroller 37 and the pre-write circuit 39 can be removed from the array switch circuit system 3 after the control instructions are written into memory 35.

[0093] This invention also provides a switching circuit with a base voltage control capability, and it can be applied to any of the switching elements in the foregoing embodiments. That is, any of the switching elements in the foregoing embodiments can be implemented using this switching circuit. Embodiments of this switching circuit will be described below. Please refer to... Figure 8 , Figure 8 This is a schematic diagram of a switching circuit according to an embodiment of the present invention. Figure 8 As shown, the switching circuit 500 includes a first transmission gate 501 and a base voltage control sub-circuit 503. The first transmission gate 501 has a first input terminal P1, a first output terminal P2, two first gate control terminals P3 and P4, and two base control terminals P5 and P6. The first transmission gate 501 is used to turn the first input terminal P1 and the first output terminal P2 on or off according to the voltages of the first gate control terminals P3 and P4. The base voltage control sub-circuit 503 is connected to the first input terminal P1 and the base control terminals P5 and P6, and is used to adjust the voltages of the base control terminals P5 and P6 according to the voltage of the first input terminal P1 when the first input terminal P1 and the first output terminal P2 are on, so that the voltage difference between the input terminal P1 and any one of the two base control terminals P5 and P6 is less than a preset value, specifically equal to 0.

[0094] For a further explanation of the circuit architecture of the 500 switching circuit, please refer to [link / reference]. Figure 9 , Figure 9 This is a circuit diagram of one embodiment of the switching circuit 500. (See diagram below.) Figure 9 As shown, the switching circuit 500 includes transistors M1 to M8, where transistors M1 and M2 constitute a first transmission gate 501, and transistors M3 to M8 constitute a base voltage control sub-circuit 503. The drain of transistor M1 and the source of transistor M2 are connected to each other as a first input terminal P1, the source of transistor M1 and the drain of transistor M2 are connected to each other as a first output terminal P2, the gates of transistors M1 and M2 are respectively used as first gate control terminals P3 and P4, and the bases of transistors M1 and M2 are respectively used as base control terminals P5 and P6. The first gate control terminals P3 and P4 of the first transmission gate 501 can be connected to an external control circuit to control the switching state of transistors M1 and M2. The external control circuit may include, for example,... Figure 9The inverter shown and the aforementioned memory can be connected to the control terminal SW of the switching circuit 500 (i.e., the first gate control terminal P3 of the first transmission gate 501) for write / read operations, that is, to control / store the switching state of the switching circuit 500, but the present invention is not limited thereto. For example, when the voltage of the first gate control terminal P3 is 1.5V and the voltage of the first gate control terminal P4 is 0V, the switching circuit 500 is in the ON state; when the voltage of the first gate control terminal P3 is 0V and the voltage of the first gate control terminal P4 is 1.5V, the switching circuit 500 is in the OFF state.

[0095] The base voltage control sub-circuit 503 includes a second transmission gate composed of transistors M3 and M4, a third transmission gate composed of transistors M5 and M6, a first transistor M7, and a second transistor M8. The second transmission gate has a second input terminal, a second output terminal, and two second gate control terminals. Specifically, the drain of transistor M3 and the source of transistor M4 are connected to each other as a second input terminal, connected to the first input terminal P1 of the first transmission gate 501; the source of transistor M3 and the drain of transistor M4 are connected to each other as a second output terminal, connected to the base control terminal P5; the gates of transistors M3 and M4 serve as the two second gate control terminals and are respectively connected to the first gate control terminals P3 and P4. The third transmission gate has a third input terminal, a third output terminal, and two third gate control terminals. The drain of transistor M5 and the source of transistor M6 are connected to each other as a third input terminal, which is connected to the first input terminal P1 of the first transmission gate 501; the source of transistor M5 and the drain of transistor M6 are connected to each other as a third output terminal, which is connected to the base control terminal P6; the gates of transistors M5 and M6 are respectively the third gate control terminals, and are respectively connected to the first gate control terminals P3 and P4.

[0096] The first transistor M7 has a fourth input terminal, a fourth output terminal, and a fourth control terminal. The fourth input terminal is the drain of the first transistor M7, connected to the second output terminal of the second transmission gate and the base control terminal P5 of the first transmission gate 501; the fourth output terminal is the source of the first transistor M7, used to connect to the lowest potential (ground voltage); the fourth control terminal is the gate of the first transistor M7, connected to the first gate control terminal P4 of the first transmission gate 501. The second transistor M8 has a fifth input terminal, a fifth output terminal, and a fifth control terminal. The fifth input terminal is the source of the second transistor M8, used to receive the highest potential (operating voltage Vdd); the fifth output terminal is the drain of the second transistor M8, connected to the third output terminal of the third transmission gate and the base control terminal P6 of the first transmission gate 501; the fifth control terminal is the gate of the second transistor M8, connected to the first gate control terminal P3 of the first transmission gate 501.

[0097] It should be noted that the above Figure 9 The embodiments described herein use N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement transistors M3, M5, and M7 in the base voltage control sub-circuit 503, and use P-channel MOSFETs to implement transistors M4, M6, and M8 for illustration purposes, but the present invention is not limited thereto.

[0098] With the above circuit architecture, the base voltage control sub-circuit 503 can dynamically adjust the base voltages of the two transistors of the first transmission gate 501 according to the switching state of the first transmission gate 501. Furthermore, when the first transmission gate 501 is in the ON state, the base voltage control sub-circuit 503 synchronizes the base voltages of transistors M1 and M2 of the first transmission gate 501 with the voltage of the input signal (less than a preset value, or even equal to 0). As shown in the following transistor critical voltage formula (1), when the source voltage is higher than the base voltage, making the voltage difference Vsb positive, the critical voltage Vth will rise; as shown in the following transistor current formula (2), when the critical voltage Vth rises, the drain current Id will decrease. At this time, the drain voltage Vd remains unchanged, and the switch on-resistance Ron will rise. In other words, traditional transmission gate switches experience an increase in on-resistance when on due to the difference between the base voltage and the input signal voltage.

[0099]

[0100]

[0101] In contrast, the switching circuit 500 of this embodiment, through the aforementioned architecture that synchronizes the substrate voltage with the input signal voltage, can reduce or prevent the rise of the critical voltage Vth, thus achieving a lower switching on-resistance Ron. Furthermore, as shown in the following time constant formula (3), when the switching on-resistance decreases, the charging and discharging speed of the transistor increases, thereby improving the channel bandwidth. In other words, the switching circuit proposed in this invention can solve the problem of increased switching on-resistance caused by the difference between the base voltage and the input signal voltage when a conventional transmission gate switch is turned on, thus achieving a lower switching on-resistance and consequently a wider channel bandwidth.

[0102] τ=RC (3)

[0103] Furthermore, when the first transmission gate 501 is in the OFF state, the base voltage control sub-circuit 503 adjusts the base voltages of transistors M1 and M2 of the first transmission gate 501 to the operating voltage and ground voltage, respectively, thereby avoiding the problem of base leakage. In addition, the area occupied by the switching circuit 500 in the circuit wiring is similar to that of a conventional transmission gate switch. In other words, the switching circuit 500 has superior characteristics and a comparable area to a conventional transmission gate switch, giving it a comparative advantage.

[0104] With the above structure, the array switching circuit system disclosed in this invention integrates both checkerboard and high-speed channel architectures. It can select the optimal signal transmission path based on signal characteristics and can be applied to system packaging. By controlling the switching state of the switching elements to form different winding combinations with the conductor redistribution layer, the conductor redistribution layer no longer needs customization, and the need to redesign the conductor redistribution layer during development can be avoided, thereby shortening product development time and reducing development costs. Furthermore, the switching circuit disclosed in this invention has a sub-circuit that dynamically tracks the input signal voltage to control the base voltage, which can provide a wider channel bandwidth compared to traditional transmission gate switches.

[0105] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. An array switching circuit system, characterized in that, It comprises a plurality of contact units arranged in an array, wherein each contact unit comprises: A conductive pad; The first channel is equipped with a first switching element; A first column channel is connected to the first row channel, and a second switching element is provided thereon; A connecting channel connects the conductive pad to the first row channel or the first column channel; A second row of channels is connected to the conductive pad via a third switching element; as well as A second column of channels is connected to the conductive pad via a fourth switching element; In this plurality of contact units, the first row channel of each having the same row position is connected to each other, the second row channel of each having the same row position is connected to each other, the first column channel of each having the same column position is connected to each other, and the second column channel of each having the same column position is connected to each other. At least one of the first switching element, the second switching element, the third switching element, and the fourth switching element includes: A first transmission gate includes a first input terminal, a first output terminal, two first gate control terminals, and two base control terminals, and is used to turn the input terminal and the output terminal on or off according to the voltage of the two first gate control terminals; and A base voltage control sub-circuit is connected to the first input terminal and the second base control terminal, and is used to adjust the voltage of the second base control terminal according to the voltage of the first input terminal when the first input terminal and the first output terminal are turned on, so that the voltage difference between the first input terminal and the second base control terminal is less than a preset value. The base voltage control sub-circuit includes: A second transmission gate has a second input terminal, a second output terminal and two second gate control terminals, wherein the second input terminal is connected to the first input terminal, the second output terminal is connected to one of the two base control terminals, and the two second gate control terminals are respectively connected to the two first gate control terminals. A third transmission gate has a third input terminal, a third output terminal and two third gate control terminals, wherein the third input terminal is connected to the first input terminal, the third output terminal is connected to the second of the two base control terminals, and the two third gate control terminals are respectively connected to the two first gate control terminals. A first transistor has a fourth input terminal, a fourth output terminal, and a fourth control terminal, wherein the fourth input terminal is connected to the second output terminal, the fourth output terminal is grounded, and the fourth control terminal is connected to a first of the two first gate control terminals; and A second transistor has a fifth input terminal, a fifth output terminal, and a fifth control terminal, wherein the fifth input terminal is used to receive an operating voltage, the fifth output terminal is connected to the third output terminal, and the fifth control terminal is connected to the second of the two first gate control terminals. The first transmission gate, the second transmission gate, and the third transmission gate each include a plurality of N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and a plurality of P-channel MOSFETs. The gates of the plurality of N-channel MOSFETs are connected to each other, and the gates of the plurality of P-channel MOSFETs are connected to each other. The base of the N-channel MOSFET belonging to the first transmission gate is the first of the two base control terminals, the gate of the N-channel MOSFET of the first transmission gate is the second of the two first gate control terminals, the base of the P-channel MOSFET belonging to the first transmission gate is the second of the two base control terminals, and the gate of the P-channel MOSFET of the first transmission gate is the first of the two first gate control terminals.

2. The array switch circuit system as described in claim 1, characterized in that, Each of the plurality of contact units further comprises: A fifth switching element is provided in the third row channel; A third column channel is connected to the third row channel, and a sixth switching element is provided thereon; A fourth channel is connected to the conductive pad via a seventh switching element; as well as A fourth channel is connected to the conductive pad via an eighth switching element; The third row channel is connected to the first row channel via a connecting switch element, or the third column channel is connected to the first column channel via the connecting switch element; The third row channel of each of the plurality of contact units having the same row position is connected to each other, the fourth row channel of each of the plurality of contact units having the same row position is connected to each other, the third column channel of each of the plurality of contact units having the same column position is connected to each other, and the fourth column channel of each of the plurality of contact units having the same column position is connected to each other.

3. The array switch circuit system as described in claim 1, characterized in that, It also includes: Multiple extended conductive pads are respectively connected to a channel group of multiple contact units located on one side of the array through multiple extended switching elements; The channel group consists of the first row of channels and the second row of channels, or the first column of channels and the second column of channels.

4. The array switch circuit system as described in claim 2, characterized in that, It also includes: Multiple extended conductive pads are respectively connected to a channel group of multiple contact units located on one side of the array through multiple extended switching elements; The channel group consists of the first row channel, the second row channel, the third row channel, and the fourth row channel, or it consists of the first column channel, the second column channel, the third column channel, and the fourth column channel.

5. The array switch circuit system as described in claim 1, characterized in that, It further includes a memory connected to multiple control terminals of the first switching element, the second switching element, the third switching element and the fourth switching element, wherein the memory is used to control and record the switching states of the first switching element, the second switching element, the third switching element and the fourth switching element.

6. The array switch circuit system as described in claim 1, characterized in that, It also includes: A memory, connected to multiple control terminals of the first switching element, the second switching element, the third switching element, and the fourth switching element; and A microcontroller is connected to the memory and the plurality of control terminals. The microcontroller is used to control the plurality of control terminals according to a control instruction and perform an AC test. After the AC test is passed, the control instruction is written to the memory.

7. A switching circuit, characterized in that, Include: A transmission gate has an input terminal, an output terminal, two gate control terminals, and two base control terminals, and is used to turn the input terminal and the output terminal on or off according to the voltage of the two gate control terminals; and A base voltage control sub-circuit is connected to the input terminal and the two base control terminals, and is used to adjust the voltage of the two base control terminals according to the voltage of the input terminal when the input terminal and the output terminal are turned on, so that the voltage difference between the input terminal and the two base control terminals is less than a preset value. Wherein, the transmission gate is a first transmission gate, the input terminal is a first input terminal, the output terminal is a first output terminal, the two gate control terminals are two first gate control terminals, and the base voltage control sub-circuit includes: A second transmission gate has a second input terminal, a second output terminal and two second gate control terminals, wherein the second input terminal is connected to the first input terminal, the second output terminal is connected to one of the two base control terminals, and the two second gate control terminals are respectively connected to the two first gate control terminals. A third transmission gate has a third input terminal, a third output terminal and two third gate control terminals, wherein the third input terminal is connected to the first input terminal, the third output terminal is connected to the second of the two base control terminals, and the two third gate control terminals are respectively connected to the two first gate control terminals. A first transistor has a fourth input terminal, a fourth output terminal, and a fourth control terminal, wherein the fourth input terminal is connected to the second output terminal, the fourth output terminal is grounded, and the fourth control terminal is connected to a first of the two first gate control terminals; and A second transistor has a fifth input terminal, a fifth output terminal, and a fifth control terminal, wherein the fifth input terminal is used to receive an operating voltage, the fifth output terminal is connected to the third output terminal, and the fifth control terminal is connected to the second of the two first gate control terminals. The first transmission gate, the second transmission gate, and the third transmission gate each include a plurality of N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and a plurality of P-channel MOSFETs. The gates of the plurality of N-channel MOSFETs are connected to each other, and the gates of the plurality of P-channel MOSFETs are connected to each other. The base of the N-channel MOSFET belonging to the first transmission gate is the first of the two base control terminals, the gate of the N-channel MOSFET of the first transmission gate is the second of the two first gate control terminals, the base of the P-channel MOSFET belonging to the first transmission gate is the second of the two base control terminals, and the gate of the P-channel MOSFET of the first transmission gate is the first of the two first gate control terminals.

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