A PAM-4 signal level decision threshold shifting device and electronic equipment

Abstract

The application provides a PAM-4 signal level decision threshold shift device and electronic equipment. After the PAM-4 signal is shifted, the threshold values of three eye diagrams of the PAM-4 signal are all shifted to 0V, the nonlinearity of an equalizer has a smaller influence on the eye diagram with the threshold value of 0V, and then the equalizer only needs to satisfy a certain output swing, thereby the requirement for linearity is reduced, and the problem that the output swing and the linearity are mutually restricted is solved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to a shifting device and electronic device for a PAM-4 signal level decision threshold. Background Technology

[0002] High-speed serial communication has many advantages, such as saving transmission media and reducing the complexity of system interconnection, and has been widely used in network transmission, backplane connection, I / O interface and other fields.

[0003] Currently, with serial port data rates reaching 56Gb / s and above, traditional NRZ (Non-Return to Zero) modulation faces a sharp increase in channel loss, making it difficult to compensate for channel attenuation through simple equalization.

[0004] Based on this, PAM-4 (Four-level Pluse Amplitude Modulation) modulation can transmit two bits of signal using four levels within a unit symbol, which not only doubles the data rate but also halves the Nyquist frequency, reducing the channel loss. Therefore, it has replaced NRZ modulation as the mainstream modulation method for high-speed serial ports.

[0005] However, PAM-4 modulation currently has many problems that need to be solved by those skilled in the art. For example, the fixed and uniformly spaced thresholds used in PAM-4 modulation cannot correctly determine the level. Summary of the Invention

[0006] In view of this, to solve the above problems, the present invention provides a shifting device and electronic device for PAM-4 signal level decision threshold, the technical solution of which is as follows:

[0007] A shifting device for determining a PAM-4 signal level threshold, the shifting device comprising at least: a shifter;

[0008] The shifter is configured to receive a first input signal, a second input signal, a third level shift signal, a fourth level shift signal, a fifth level shift signal, a sixth level shift signal, and a seventh common-mode level signal.

[0009] The shifter is used to shift the thresholds of the three eye diagrams formed by the first input signal and the second input signal to 0V based on the first level shift signal, the second level shift signal, the third level shift signal, the fourth level shift signal, and the common-mode level signal.

[0010] Preferably, in the above-described shifting device, the shifter includes: first to sixth capacitors and first to sixth resistors;

[0011] Wherein, the first end of the first capacitor is connected to the first end of the second capacitor, and the connection node is used to receive the first input signal;

[0012] The second terminal of the first capacitor is connected to the first terminal of the first resistor, and the connection node serves as one output terminal of the shifter; the second terminal of the second capacitor is connected to the first terminal of the second resistor, and the connection node serves as the other output terminal of the shifter.

[0013] The second end of the first resistor is used to receive the first level shift signal, and the second end of the second resistor is used to receive the third level shift signal;

[0014] The first terminal of the third capacitor is connected to the first terminal of the fourth capacitor, and the connection node is used to receive the second input signal;

[0015] The second terminal of the third capacitor is connected to the first terminal of the third resistor, and the connection node serves as another output terminal of the shifter; the second terminal of the fourth capacitor is connected to the first terminal of the fourth resistor, and the connection node serves as another output terminal of the shifter.

[0016] The second end of the third resistor is used to receive the second level shift signal, and the second end of the fourth resistor is used to receive the fourth level shift signal;

[0017] The first terminal of the fifth capacitor is used to receive the first input signal, and the second terminal of the fifth capacitor is connected to the first terminal of the fifth resistor, with the connection node serving as another output terminal of the shifter.

[0018] The first terminal of the sixth capacitor is used to receive the second input signal, and the second terminal of the sixth capacitor is connected to the first terminal of the sixth resistor, with the connection node serving as another output terminal of the shifter.

[0019] The second end of the fifth resistor and the second end of the sixth resistor are connected, and the connection node is used to receive the common-mode level signal.

[0020] Preferably, in the above-described shifting device, the shifting device further includes: an equalizer;

[0021] The equalizer is used to receive the signal output by the shifter and perform equalization and amplification.

[0022] Preferably, in the above-described shifting device, the shifting device further includes: a sampling decision unit;

[0023] The sampling decision unit is used to make a level decision on the signal output by the equalizer.

[0024] Preferably, in the above-described shifting device, the shifting device further includes: an encoder;

[0025] The encoder is used to encode the level decision result of the sampling decision device.

[0026] Preferably, in the above-described shifting device, the shifting device further includes: a splitter;

[0027] The splitter is used to deserialize the level decision result of the encoding process and convert it into a serial signal.

[0028] Preferably, in the above-described shifting device, the shifting device further includes: a first threshold detector and a second threshold detector;

[0029] The first threshold detector is used to receive the first output signal of the splitter and determine whether the level shift of the first output signal meets the preset requirements;

[0030] The second threshold detector is used to receive the second output signal of the splitter and determine whether the level shift of the second output signal meets the preset requirements.

[0031] Preferably, in the above-mentioned shifting device, the shifting device further includes: a first voter, a second voter, a first filter, and a second filter;

[0032] The first voter and the first filter are used to convert the judgment result of the first threshold detector into a first control signal;

[0033] The second voter and the second filter are used to convert the judgment result of the second threshold detector into a second control signal.

[0034] Preferably, in the above-described shifting device, the shifting device further includes: a first DAC and a second DAC;

[0035] The first DAC is used to output the first level shift signal and the second level shift signal according to the first control signal;

[0036] The second DAC is used to output the third level shift signal and the fourth level shift signal according to the second control signal.

[0037] An electronic device comprising the shifting device described in any of the preceding claims.

[0038] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0039] The present invention provides a shifting device for a PAM-4 signal level decision threshold, comprising at least a shifter; wherein the first end of the shifter is used to receive a first input signal, the second end is used to receive a second input signal, the third end is used to receive a first level shift signal, the fourth end is used to receive a second level shift signal, the fifth end is used to receive a third level shift signal, the sixth end is used to receive a fourth level shift signal, and the seventh end is used to receive a common-mode level signal; the shifter is used to shift the thresholds of the three eye diagrams formed by the first input signal and the second input signal to 0V based on the first level shift signal, the second level shift signal, the third level shift signal, the fourth level shift signal, and the common-mode level signal.

[0040] In other words, after the shifting device provided by the present invention shifts the PAM-4 signal, the thresholds of the three eye diagrams of the PAM-4 signal are all shifted to 0V. Since the nonlinearity of the equalizer has little impact on the eye diagram with a threshold of 0V, the equalizer only needs to meet a certain output swing, which reduces the requirement for linearity and solves the problem of mutual constraint between output swing and linearity. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a shifting device for determining the PAM-4 signal level decision threshold provided in an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of a shifter provided in an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of the structure of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of the structure of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention;

[0047] Figure 6This is a schematic diagram of the structure of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention;

[0048] Figure 7 This is a schematic diagram of the structure of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of level shifting provided in an embodiment of the present invention;

[0050] Figure 9 This is another schematic diagram of level shifting provided in an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of the structure of a first threshold detector provided in an embodiment of the present invention;

[0052] Figure 11 This is a schematic diagram of the structure of a second threshold detector provided in an embodiment of the present invention;

[0053] Figure 12 This is a schematic diagram of the structure of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention;

[0054] Figure 13 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] In the process of inventing this invention, the inventors discovered that even though PAM-4 modulation has been widely used, its application presents new challenges to serial port receivers, specifically as follows:

[0057] First, there is the challenge to the equalizer CTLE (Continuous Time Linear Equalizer).

[0058] Since PAM-4 modulation uses four levels to transmit signals, the threshold for level decision increases to three, but the level interval is only 1 / 3 of NRZ, which will cause a signal-to-noise ratio loss of 9.5dB. Therefore, the equalizer CTLE needs to provide sufficient output swing to compensate for the lost signal-to-noise ratio.

[0059] However, for the equalizer CTLE, its output swing affects the tail current source through the channel length modulation effect, making it unable to remain constant when the output level changes. This leads to uneven level intervals, causing eye diagram compression and offsetting the signal-to-noise ratio improvement effect of increasing the output swing.

[0060] In other words, there is a mutually restrictive relationship between the output swing and linearity of the equalizer CTLE.

[0061] Secondly, in addition to the challenge to the equalizer CTLE, PAM-4 modulation also increases the difficulty of receiver level decision.

[0062] The NRZ signal has only two levels. At the receiving end, a fixed threshold of 0V can be used to determine the level of the differential signal.

[0063] However, PAM-4 signals require three threshold values ​​for judgment. Of these three thresholds, only the middle threshold is fixed at 0V; the other two thresholds vary with the signal amplitude and level interval. In actual operation, the received signal amplitude changes under different data rates and channels. Nonlinearities caused by the non-ideal characteristics of the device and the channel can result in uneven PAM-4 level intervals. Therefore, using fixed and uniformly spaced thresholds cannot correctly determine the level.

[0064] Based on this, the present invention provides a shifting device and electronic device for the PAM-4 signal level decision threshold. By shifting the PAM-4 signal, the thresholds of the three eye diagrams of the PAM-4 signal are all shifted to 0V. Since the nonlinearity of the equalizer has little impact on the eye diagram with 0V as the threshold, the equalizer only needs to meet a certain output swing, which reduces the requirement for linearity and solves the problem of mutual constraint between output swing and linearity.

[0065] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] refer to Figure 1 , Figure 1 This is a schematic diagram of a shifting device for determining the PAM-4 signal level threshold, provided in an embodiment of the present invention.

[0067] The shifting device includes at least: a shifter 11;

[0068] The shifter 11 is configured to receive a first input signal Vip, a second input signal Vin, a third level shift signal HP, a fourth level shift signal HN, a fifth level shift signal LP, a sixth level shift signal LN, and a seventh common-mode level signal Vcm.

[0069] The shifter 11 is used to shift the thresholds of the three eye diagrams formed by the first input signal Vip and the second input signal Vin to 0V based on the first level shift signal HP, the second level shift signal HN, the third level shift signal LP, the fourth level shift signal LN, and the common-mode level signal Vcm.

[0070] In this embodiment, by shifting the PAM-4 signal, the thresholds of the three eye diagrams of the PAM-4 signal are all shifted to 0V. Since the nonlinearity of the equalizer has little impact on the eye diagram with a threshold of 0V, the equalizer only needs to meet a certain output swing, which reduces the requirement for linearity and solves the problem of mutual constraint between output swing and linearity.

[0071] Among them, the level shift value represented by the first level shift signal HP and the second level shift signal HN is the high threshold VTH of the PAM-4 signal.

[0072] The level shift values ​​represented by the third level shift signal LP and the fourth level shift signal LN are the low threshold VTL of the PAM-4 signal.

[0073] Furthermore, based on the above embodiments of the present invention, refer to Figure 2 , Figure 2 This is a schematic diagram of a shifter provided in an embodiment of the present invention.

[0074] The shifter 11 includes: first to sixth capacitors and first to sixth resistors;

[0075] Wherein, the first end of the first capacitor C1 is connected to the first end of the second capacitor C2, and the connection node is used to receive the first input signal Vip;

[0076] The second end of the first capacitor C1 is connected to the first end of the first resistor R1, and the connection node serves as one output terminal of the shifter 11; the second end of the second capacitor C2 is connected to the first end of the second resistor R2, and the connection node serves as the other output terminal of the shifter 11.

[0077] The second end of the first resistor R1 is used to receive the first level shift signal HP, and the second end of the second resistor R2 is used to receive the third level shift signal LP;

[0078] The first terminal of the third capacitor C3 is connected to the first terminal of the fourth capacitor C4, and the connection node is used to receive the second input signal Vin.

[0079] The second end of the third capacitor C3 is connected to the first end of the third resistor R3, and the connection node serves as another output terminal of the shifter 11; the second end of the fourth capacitor C4 is connected to the first end of the fourth resistor R4, and the connection node serves as another output terminal of the shifter 11.

[0080] The second end of the third resistor R3 is used to receive the second level shift signal HN, and the second end of the fourth resistor R4 is used to receive the fourth level shift signal LN;

[0081] The first terminal of the fifth capacitor C5 is used to receive the first input signal Vip, and the second terminal of the fifth capacitor C5 is connected to the first terminal of the fifth resistor R5, and the connection node serves as another output terminal of the shifter 11.

[0082] The first terminal of the sixth capacitor C6 is used to receive the second input signal Vin, and the second terminal of the sixth capacitor C6 is connected to the first terminal of the sixth resistor R6, and the connection node serves as another output terminal of the shifter 11.

[0083] The second end of the fifth resistor R5 is connected to the second end of the sixth resistor R6, and the connection node is used to receive the common-mode level signal Vcm.

[0084] In this embodiment, the first input signal Vip and the second input signal Vin are filtered out by AC coupling to remove the DC component, and then a new DC component is added by the first level shift signal HP and the second level shift signal HN, or the third level shift signal LP and the fourth level shift signal LN, respectively, thereby realizing level shifting.

[0085] It should be noted that when using the 0V threshold for level determination, no level shifting is required. Therefore, the shift control level can be directly connected to the common-mode level to obtain the common-mode level signal Vcm.

[0086] Furthermore, based on the above embodiments of the present invention, refer to Figure 3 , Figure 3 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0087] The shifting device further includes: an equalizer CTLE;

[0088] The equalizer CTLE is used to receive the signal output by the shifter 11 and perform equalization and amplification.

[0089] In this embodiment, the equalizer CTLE is mainly used to equalize and amplify the amplitude and frequency of the signal output by the shifter 11.

[0090] Since the thresholds of the three eye diagrams of the PAM-4 signal are all shifted to 0V after the PAM-4 signal is shifted, and the nonlinearity of the equalizer CTLE has little impact on the eye diagram with a threshold of 0V, the equalizer CTLE only needs to meet a certain output swing, which reduces the requirement for linearity and solves the problem of mutual constraint between output swing and linearity.

[0091] Furthermore, based on the above embodiments of the present invention, refer to Figure 4 , Figure 4 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0092] The shifting device further includes: a sampling decision unit 12;

[0093] The sampling decision unit 12 is used to make a level decision on the signal output by the equalizer CTLE.

[0094] Furthermore, based on the above embodiments of the present invention, refer to Figure 5 , Figure 5 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0095] The shifting device further includes: encoder 13;

[0096] The encoder 13 is used to encode the level decision result of the sampling decision unit 12.

[0097] Furthermore, based on the above embodiments of the present invention, refer to Figure 6 , Figure 6 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0098] The shifting device further includes: a splitter 14;

[0099] The splitter 14 is used to deserialize the level decision result of the encoding process and convert it into a serial signal.

[0100] Furthermore, based on the above embodiments of the present invention, refer to Figure 7 , Figure 7 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0101] The shifting device further includes: a first threshold detector PD_VTH and a second threshold detector PD_VTL;

[0102] The first threshold detector PD_VTH is used to receive the first output signal of the splitter 14 and determine whether the level shift of the first output signal meets the preset requirements.

[0103] The second threshold detector PD_VTL is used to receive the second output signal of the splitter 14 and determine whether the level shift of the second output signal meets the preset requirements.

[0104] In this embodiment, reference Figure 8 , Figure 8 A schematic diagram of level shifting provided in an embodiment of the present invention; Reference Figure 9 , Figure 9 This is another schematic diagram of level shifting provided in an embodiment of the present invention.

[0105] Let's take the first threshold detector PD_VTH as an example for explanation:

[0106] The first threshold detector PD_VTH uses the two transition edges of VTH at the crossover point as a basis to determine whether the level HP-HN is too low or too high.

[0107] Once the sampling clock has recovered to the optimal sampling point, if the threshold VTH is set too high (indicating that the input differential signal level has shifted down too much), such as Figure 8 As shown, the sampled value of edge E will always be lower than VTH, and the decision result will remain "0".

[0108] Similarly, if VTH is set too low (indicating that the input differential signal level is shifted down too little), such as Figure 9 As shown, the sampled decision value of edge E will always be higher than VTH, and the decision result will remain "1".

[0109] Therefore, it can be concluded that, among the two transition edges with the crossover point located at VTH, the sampled value of edge E can be used as the basis for determining whether the level shift is too high or too low.

[0110] Further reference Figure 10 , Figure 10 This is a schematic diagram of the structure of a first threshold detector provided in an embodiment of the present invention; see reference. Figure 11 , Figure 11 This is a schematic diagram of the structure of a second threshold detector provided in an embodiment of the present invention.

[0111] The first threshold detector PD_VTH includes: a first NAND gate P1, a second NAND gate P2, a first AND gate M1, a second AND gate M2, a first NOR gate K1, a second NOR gate K2, and a third NOR gate K3.

[0112] The first input of the first NAND gate P1 is used to receive the high-order DMSB of the decision result of the previous bit. <n>The second input is used to receive the edge decision result E with VTH as the threshold. <n>The third input is used to receive the high-order DMSB of the decision result of the current data.<n+1> The output terminal is connected to the first input terminal of the second NOR gate K2.

[0113] The first input of the second NAND gate P2 is used to receive the high-order DMSB of the decision result of the previous bit. <n>The second input is used to receive the edge decision result E with VTH as the threshold. <n>The inverted signal, the third input terminal is used to receive the high-order DMSB of the decision result of the current data.<n+1> The output terminal is connected to the first input terminal of the third NOR gate K3.

[0114] The first input of the first AND gate M1 is used to receive the low-order DLSB of the decision result of the previous bit. <n>The second input is used to receive the low-order DLSB of the decision result of the current data.<n+1> The inverted signal is output and connected to the first input of the first NOR gate K1.

[0115] The first input of the second AND gate M2 is used to receive the low-order DLSB of the decision result of the previous bit. <n>The inverted signal, the second input terminal is used to receive the low-order DLSB of the decision result of the current data.<n+1> The output terminal is connected to the second input terminal of the first NOR gate K1.

[0116] The output of the first NOR gate K1 is connected to the second input of the second NOR gate K2 and the second input of the third NOR gate K3, respectively.

[0117] The output terminal of the second NOR gate K2 outputs the flag bit YL. <n>The output terminal of the third NOR gate K3 outputs the flag bit YH. <n>YH=1 indicates that the level shift is too large (meaning the threshold is too high), and YL=1 indicates that the level shift is too small (meaning the threshold is too low).

[0118] Similarly, the second threshold detector PD_VTL includes: a third NAND gate P3, a fourth NAND gate P4, a third AND gate M3, a fourth AND gate M4, a fourth NOR gate K4, a fifth NOR gate K5, and a sixth NOR gate K6.

[0119] The first input of the third NAND gate P3 is used to receive the high-order DMSB of the decision result of the previous bit. <n>The inverted signal, the second input terminal is used to receive the edge decision result E with VTH as the threshold. <n>The inverted signal, the third input terminal is used to receive the high-order DMSB of the decision result of the current data.<n+1> The inverted signal is output and connected to the first input of the fifth NOR gate K5.

[0120] The first input of the fourth NAND gate P4 is used to receive the high-order DMSB of the decision result of the previous bit. <n>The inverted signal, the second input terminal is used to receive the edge decision result E with VTH as the threshold. <n>The third input is used to receive the high-order DMSB of the decision result of the current data.<n+1> The inverted signal is output and connected to the first input of the sixth NOR gate K6.

[0121] The first input of the third AND gate M3 is used to receive the low-order DLSB of the decision result of the previous bit. <n>The inverted signal, the second input terminal is used to receive the low-order DLSB of the decision result of the current data.<n+1> The output terminal is connected to the first input terminal of the fourth NOR gate K4.

[0122] The first input of the fourth AND gate M4 is used to receive the low-order DLSB of the decision result of the previous bit. <n>The second input is used to receive the low-order DLSB of the decision result of the current data.<n+1> The inverted signal is output and connected to the second input of the fourth NOR gate K4.

[0123] The output of the fourth NOR gate K4 is connected to the second input of the fifth NOR gate K5 and the second input of the sixth NOR gate K6, respectively.

[0124] The output terminal of the fifth NOR gate K5 outputs a flag bit YL. <n>The output terminal of the sixth NOR gate K6 outputs the flag bit YH. <n>YH=1 indicates that the level shift is too large (meaning the threshold is too high), and YL=1 indicates that the level shift is too small (meaning the threshold is too low).

[0125] The second threshold detector PD_VTL uses the two transition edges of VTL at the crossover point as the basis to determine whether the shift level LP-LN is too low or too high.

[0126] Furthermore, based on the above embodiments of the present invention, refer to Figure 12 , Figure 12 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0127] The shifting device further includes: a first voter 15, a second voter 16, a first filter 17, and a second filter 18;

[0128] The first voter 15 and the first filter 17 are used to convert the judgment result of the first threshold detector PD_VTH into a first control signal;

[0129] The second voter 16 and the second filter 18 are used to convert the judgment result of the second threshold detector PD_VTL into a second control signal.

[0130] Furthermore, based on the above embodiments of the present invention, refer to Figure 13 , Figure 13 This is a schematic diagram of another PAM-4 signal level decision threshold shifting device provided in an embodiment of the present invention.

[0131] The shifting device further includes: a first DAC19 (Digital Analog Converter) and a second DAC20;

[0132] The first DAC19 is used to output the first level shift signal HP and the second level shift signal HN according to the first control signal;

[0133] The second DAC20 is used to output the third level shift signal LP and the fourth level shift signal LN according to the second control signal.

[0134] In this embodiment, the first control signal is the control signal of the first DAC, and the second control signal is the control signal of the second DAC. Based on the outputs of the first DAC and the second DAC, the level shift value is continuously adjusted until the correct level decision is achieved.

[0135] As can be seen from the above description, the PAM-4 signal level decision threshold shifting device provided by the present invention can reduce the requirements for the linearity of the equalizer, thereby reducing the design difficulty and effectively solving the problem of level decision difficulty caused by the nonlinearity of the equalizer.

[0136] Furthermore, this shifter is a passive structure that consumes no power, has a simple structure, and also has the advantage of high linearity, which will not damage the linearity of the signal during the level shifting process.

[0137] Furthermore, the first and second threshold detectors rely on the deserialized decision structure instead of the full-speed data stream, resulting in a lower operating speed and reduced power consumption.

[0138] Furthermore, based on all the above embodiments of the present invention, another embodiment of the present invention also provides an electronic device, which includes the shifting device described in the above embodiments.

[0139] In this embodiment, the electronic device includes, but is not limited to, a PAM-4 receiver.

[0140] It should be noted that the equalizer CTLE, sampling decision unit, encoder, and splitter can be multiplexed with the CDR (Clock and Data Recovery) in the receiver. The voter and filter can also adopt the same structure as in the CDR, which greatly reduces the design difficulty and saves design time.

[0141] The above provides a detailed description of a shifting device and electronic device for determining the PAM-4 signal level threshold provided by the present invention. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0142] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0143] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0144] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shifting device for determining the PAM-4 signal level decision threshold, characterized in that, The shifting device includes at least one shifter, wherein the shifter is a passive structure; The shifter is configured to receive a first input signal, a second input signal, a third level shift signal, a fourth level shift signal, a fifth level shift signal, a sixth level shift signal, and a seventh common-mode level signal. The shifter is used to shift the thresholds of the three eye diagrams formed by the first input signal and the second input signal to 0V based on the first level shift signal, the second level shift signal, the third level shift signal, the fourth level shift signal and the common-mode level signal; The shifter includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; Wherein, the first end of the first capacitor is connected to the first end of the second capacitor, and the connection node is used to receive the first input signal; The second end of the first capacitor is connected to the first end of the first resistor, and the connection node serves as the first output terminal of the shifter; the second end of the second capacitor is connected to the first end of the second resistor, and the connection node serves as the second output terminal of the shifter. The second end of the first resistor is used to receive the first level shift signal, and the second end of the second resistor is used to receive the third level shift signal; The first terminal of the third capacitor is connected to the first terminal of the fourth capacitor, and the connection node is used to receive the second input signal; The second terminal of the third capacitor is connected to the first terminal of the third resistor, and the connection node serves as the third output terminal of the shifter; the second terminal of the fourth capacitor is connected to the first terminal of the fourth resistor, and the connection node serves as the fourth output terminal of the shifter. The second end of the third resistor is used to receive the second level shift signal, and the second end of the fourth resistor is used to receive the fourth level shift signal; The first terminal of the fifth capacitor is used to receive the first input signal, and the second terminal of the fifth capacitor is connected to the first terminal of the fifth resistor, with the connection node serving as the fifth output terminal of the shifter. The first terminal of the sixth capacitor is used to receive the second input signal, and the second terminal of the sixth capacitor is connected to the first terminal of the sixth resistor, with the connection node serving as the sixth output terminal of the shifter. The second end of the fifth resistor and the second end of the sixth resistor are connected, and the connection node is used to receive the common-mode level signal.

2. The shifting device according to claim 1, characterized in that, The shifting device further includes: an equalizer; The equalizer is used to receive the signal output by the shifter and perform equalization and amplification.

3. The shifting device according to claim 2, characterized in that, The shifting device further includes: a sampling decision unit; The sampling decision unit is used to make a level decision on the signal output by the equalizer.

4. The shifting device according to claim 3, characterized in that, The shifting device further includes: an encoder; The encoder is used to encode the level decision result of the sampling decision device.

5. The shifting device according to claim 4, characterized in that, The shifting device further includes: a splitter; The splitter is used to deserialize the level decision result of the encoding process and convert it into a serial signal.

6. The shifting device according to claim 5, characterized in that, The shifting device further includes: a first threshold detector and a second threshold detector; The first threshold detector is used to receive the first output signal of the splitter and determine whether the level shift of the first output signal meets the preset requirements; The second threshold detector is used to receive the second output signal of the splitter and determine whether the level shift of the second output signal meets the preset requirements.

7. The shifting device according to claim 6, characterized in that, The shifting device further includes: a first voter, a second voter, a first filter, and a second filter; The first voter and the first filter are used to convert the judgment result of the first threshold detector into a first control signal; The second voter and the second filter are used to convert the judgment result of the second threshold detector into a second control signal.

8. The shifting device according to claim 7, characterized in that, The shifting device further includes: a first DAC and a second DAC; The first DAC is used to output the first level shift signal and the second level shift signal according to the first control signal; The second DAC is used to output the third level shift signal and the fourth level shift signal according to the second control signal.

9. An electronic device, characterized in that, The electronic device includes the shifting device according to any one of claims 1-8.

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