一种同步时钟产生电路模块、功能芯片和多片同步装置
By combining a phase-locked loop circuit with a clock generation circuit, and multiplying and dividing the clock signal, the problem of limited clock synchronization speed in multi-chip systems is solved, and efficient multi-chip synchronization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 迅芯微电子(苏州)股份有限公司
- Filing Date
- 2022-07-18
- Publication Date
- 2026-07-17
AI Technical Summary
In the prior art, the clock synchronization speed of multi-chip systems is limited by the processing speed of the FPGA, and the transmission of clock signals is limited by the distance of the circuit board, resulting in low synchronization efficiency.
By combining a phase-locked loop (PLL) circuit with a clock generation circuit, the PLL circuit multiplies the master clock input signal to a high-frequency master clock signal, and triggers the synchronization clock input signal as an intermediate synchronization clock signal based on the high-frequency master clock signal. The clock generation circuit divides the high-frequency master clock signal into a divided clock signal, and triggers the intermediate synchronization clock signal as a synchronization clock signal based on the divided clock signal, thus achieving clock signal synchronization.
It improves the processing efficiency of clock signals, shortens the data transmission distance, reduces transmission limitations, and achieves efficient synchronization of multi-chip systems.
Smart Images
Figure CN115133927B_ABST