Multi-chip key negotiation method and multi-chip identity authentication method

Abstract

The present invention provides a multi-chip key negotiation method, which is applied to one of the multiple chips participating in the key negotiation, including: when the current chip is the first chip with the first temporary key, determining the target chip from the second chip with the second temporary key; the current chip exchanges public keys with the target chip, and forms a third temporary key according to the exchanged public keys; incrementing the number of negotiations, and judging whether the current number of negotiations is less than the predetermined number of negotiations; when the current number of negotiations is less than the predetermined number of negotiations, updating the third temporary key to the first temporary key of the current chip, updating the parameters of the next key negotiation according to the first temporary key, and entering the next key negotiation; when the current number of negotiations is not less than the predetermined number of negotiations, determining the current third temporary key as a shared key. The multi-chip key negotiation method and multi-chip identity authentication method provided by the present invention can improve the efficiency of multi-processor key negotiation.

Description

Technical Field

[0001] The present invention relates to the technical field of information encryption, and in particular to a multi-chip key negotiation method and a multi-chip identity authentication method. Background Art

[0002] In a multi-chip processor environment, firstly, due to the limited internal resources of the processor, it is impossible for the processor manufacturer to assign a public-private key pair to all the chips it produces, and then centrally record the public keys of all chips inside each processor for querying the public key of the communication peer during the startup process; secondly, the processor is in an information island state during the startup process, and it is impossible to obtain the public key certificate of the communication peer by communicating with a public key certificate issuing agency such as the "Digital Certificate Authority". Therefore, during the startup of the processor, it is necessary to determine the shared key by key negotiation. In the prior art, the key negotiation process usually adopts a serial method, which is applicable when the number of processors is small. In the key negotiation process of a large number of processors, due to its extremely low efficiency, its availability is lost. Summary of the invention

[0003] The multi-chip key negotiation method and the multi-chip identity authentication method provided by the present invention can improve the efficiency of multi-processor key negotiation and quickly complete the negotiation of the shared key of the multi-processor.

[0004] In a first aspect, the present invention provides a multi-chip key negotiation method, which is applied to one of multiple chips participating in key negotiation, and includes:

[0005] When the current chip is a first chip having a first temporary key, determining a target chip from a second chip having a second temporary key; wherein the first temporary key is formed by the first chip participating in a previous round of negotiation, and the second temporary key is formed by the second chip participating in a previous round of negotiation;

[0006] The current chip exchanges public keys with the target chip, and forms a third temporary key through negotiation based on the exchanged public keys;

[0007] Incrementing the negotiation times and determining whether the current negotiation times is less than the predetermined negotiation times;

[0008] When the current negotiation number is less than the predetermined negotiation number, the third temporary key is updated to the first temporary key of the current chip, the parameters of the next key negotiation are updated according to the first temporary key, and the next key negotiation is started;

[0009] When the current negotiation number is not less than the predetermined negotiation number, the current third temporary key is determined as the shared key.

[0010] Optionally, before the next key negotiation is performed, the following steps are further included:

[0011] The negotiation status of all chips corresponding to the current negotiation times is obtained, and it is determined that the negotiation status of all chips is in the completed state.

[0012] Optionally, forming the third temporary key according to the exchanged public key negotiation includes: determining the third temporary key according to the private key of the current chip and the public key of the target chip.

[0013] Optionally, updating parameters for next key negotiation according to the first temporary key includes:

[0014] deriving a private key required for the next key negotiation based on the first temporary key;

[0015] Based on the private key, a public key required for the next key negotiation is determined.

[0016] Optionally, before the first negotiation process starts, the method further includes randomly generating a public-private key pair, wherein the public-private key pair is used to participate in the negotiation calculation of the first negotiation process.

[0017] Optionally, forming a third temporary key through negotiation based on the exchanged public key includes:

[0018] Use public key encryption to exchange random information with the target chip;

[0019] A third temporary key is determined according to the random information of the current chip and the random information of the target chip.

[0020] Optionally, updating the parameters of the next key negotiation according to the first temporary key includes: updating the random information of the current chip according to the first temporary key.

[0021] Optionally, before the first negotiation process starts, it also includes randomly generating a public-private key pair and random information, wherein the public-private key pair is used for exchanging random information in the first negotiation process, and the random information is used for participating in the negotiation calculation in the first negotiation process.

[0022] Optionally, determining the target chip from the second chip having the second temporary key includes:

[0023] When the number of the first chips is the same as the number of the second chips, the current chip determines the target chip according to a one-to-one correspondence between the first chip and the second chip.

[0024] Optionally, the current chip determines the target chip according to a one-to-one correspondence relationship including:

[0025] According to the order of the current chips in the first chip, the corresponding order of the target chips in the second chip is determined.

[0026] Optionally, determining the target chip from the second chips having the second temporary key includes: taking a chip having a logical number continuous with that of the first chip as the second chip.

[0027] Optionally, determining the corresponding order of the target chips in the second chip includes:

[0028] Determine the difference in logic numbers between the current chip and the target chip according to the number of the first chip and the second chip;

[0029] The logic number of the target chip is determined based on the logic number of the current chip and the difference between the logic numbers.

[0030] Optionally, determining the target chip from the second chip having the second temporary key includes:

[0031] When the first chip quantity is greater than the second chip quantity;

[0032] The current chip determines the current corresponding relationship;

[0033] When the current chip has a corresponding second chip, the corresponding chip is used as the target chip;

[0034] When the current chip does not have a corresponding second chip, any second chip is selected as the target chip.

[0035] Optionally, the current chip determines the current corresponding relationship including:

[0036] According to the order of the current chips in the first chip, determining whether there are chips in the corresponding order in the second chip;

[0037] When the second chip has a chip of corresponding order, the current chip has a corresponding second chip;

[0038] When the second chip does not have a chip of a corresponding sequence, the current chip does not have a corresponding second chip.

[0039] Optionally, determining the target chip from the second chips having the second temporary key includes: taking a chip having a logical number continuous with that of the first chip as the second chip.

[0040] Optionally, determining whether there is a chip in a corresponding order in the second chip includes:

[0041] Determine the difference in logic numbers between the current chip and the target chip according to the number of the first chip;

[0042] Determine the target logic number based on the logic number of the current chip and the difference between the logic numbers;

[0043] Determine whether there is a chip with a target logic number;

[0044] When there is a chip with the target logical number, the current chip has a corresponding second chip;

[0045] When there is no chip with the target logic number, the current chip does not have a corresponding second chip.

[0046] Optionally, selecting any second chip as the target chip includes: decreasing the target logical number in sequence until there is a second chip with the target logical number, and then selecting the chip with the target logical number as the target chip.

[0047] In a second aspect, the present invention provides a multi-chip identity authentication method, which is applied to any chip that uses any of the above methods for key negotiation, comprising:

[0048] Determine the target chip of the current chip based on the one-to-one correspondence;

[0049] Calculate the authentication information of the target chip based on the shared secret shared by all chips, the shared key of all chips, and the logic number of the target chip;

[0050] Acquire the identity information of the target chip, and verify the identity information according to the identity authentication information;

[0051] When the verification is passed, the verification pass status is synchronized to all chips.

[0052] Optionally, determining the target chip of the current chip according to the one-to-one correspondence includes:

[0053] The target logic number is determined according to the logic number of the current chip and the predetermined interval.

[0054] Optionally, after determining the target logical number, the method further includes:

[0055] Determine the corresponding state of the target logical number;

[0056] When there is a chip with the target logic number, the chip with the target logic number is used as the target chip;

[0057] When there is no chip having the target logical number, the target logical number is changed.

[0058] Optionally, after determining the target chip of the current chip according to the one-to-one correspondence, the method further includes:

[0059] It is determined whether the current chip is a preset chip. If the current chip is a preset chip, the chip whose target logic number needs to be changed is added as the target chip of the current chip.

[0060] Optionally, changing the target logical number includes: changing the target logical number to a preset target logical number.

[0061] Optionally, the method further includes calculating the identity information of the current chip based on the shared secret shared by all chips, the shared keys of all chips and the logical number of the current chip, and publicizing the identity information of the current chip to all chips.

[0062] In the technical solution provided by the present invention, through the negotiation between the first chip and the second chip, the first chip and the second chip have the same third temporary key. In the next round of negotiation, the third temporary key is updated to the first temporary key, so that the first chip and the second chip in this round of negotiation will all become the first chip in the next round of negotiation, that is, the number of chips with the same temporary key will increase by a power of 2, so that the negotiation rounds can be greatly reduced and the negotiation efficiency can be improved. At the same time, since the shared key is calculated separately during the key negotiation process and does not need to be transmitted, the confidentiality of the shared key can be ensured. During the identity authentication process, the shared key participates in the calculation of the identity authentication process. Therefore, if the message is tampered with during the negotiation process, the tampered message will cause the chip to fail to generate the same shared key and fail to pass the identity authentication. If a third party obtains the public key of the chip during the key negotiation process and participates in the entire shared key calculation process, although the final shared key can be obtained, during the identity authentication process, since the third party cannot know the shared secret, the identity authentication will not pass at all. During the identity authentication process, although the shared secret and the chip logic number remain fixed, they are not involved in the calculation of the shared key; each time the key is negotiated, all chips use a random number as the shared key. Therefore, even if the shared secret and the calculation method of the chip logic number are leaked, the data encrypted with the old shared key is still safe due to the complexity of the asymmetric cryptographic algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 This is a flow chart of a multi-chip key negotiation method according to an embodiment of the present invention;

[0064] Figure 2 This is a flow chart of updating public and private keys in a multi-chip key negotiation method according to another embodiment of the present invention;

[0065] Figure 3 A flowchart of determining a third temporary key in a multi-chip key agreement method according to an embodiment of the present invention;

[0066] Figure 4 A flowchart of determining a target logical number in a multi-chip key negotiation method according to another embodiment of the present invention;

[0067] Figure 5This is a flow chart of determining a corresponding relationship in a multi-chip key negotiation method according to another embodiment of the present invention;

[0068] Figure 6 This is a flow chart of a multi-chip key agreement method according to another embodiment of the present invention for determining whether the second chip has a chip in a corresponding order;

[0069] Figure 7 This is a flowchart of a multi-chip key agreement method according to another embodiment of the present invention for determining whether there is a chip with a target logical number in the second chip;

[0070] Figure 8 This is an exemplary flow chart of a multi-chip key negotiation method according to another embodiment of the present invention;

[0071] Fig. 9 for Figure 8 Calculate the initial key sharing state;

[0072] Fig.10 for Figure 8 Calculate the key sharing state at the end of negotiation round number 0;

[0073] Fig.11 for Figure 8 Calculate the key sharing state at the end of negotiation round number 1;

[0074] Fig.12 An exemplary flow chart of a multi-chip key negotiation method according to another embodiment of the present invention;

[0075] Fig.13 for Fig.12 Calculate the initial key sharing state;

[0076] Fig.14 for Fig.12 Calculate the key sharing state at the end of negotiation round number 0;

[0077] Fig.15 for Fig.12 Calculate the key sharing state at the end of negotiation round number 1;

[0078] Fig.16 A flowchart of a multi-chip identity authentication method according to an embodiment of the present invention;

[0079] Fig.17 A flowchart of a multi-chip identity authentication method for determining a corresponding state of a target logic number according to an embodiment of the present invention;

[0080] Fig.18 The figure is an exemplary flow chart of a multi-chip identity authentication method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0082] An embodiment of the present invention provides a multi-chip key negotiation method, which is applied to one of the multiple chips participating in the key negotiation, such as Figure 1 As shown, including:

[0083] When the current chip is a first chip with a first temporary key, determine the target chip from a second chip with a second temporary key; wherein the first temporary key is formed by the first chip participating in a previous round of negotiation, and the second temporary key is formed by the second chip participating in a previous round of negotiation; in some embodiments, the first temporary key and the second temporary key are different temporary keys, and the first chip includes more than one chip with the same key, that is, each first chip has the first temporary key; the second chip includes more than one chip with the same key, that is, each second chip has the second temporary key. In this step, the second temporary key is only used to distinguish from the first temporary key, that is, it indicates that the second temporary key is a temporary key different from the first temporary key.

[0084] The current chip exchanges public keys with the target chip, and a third temporary key is negotiated based on the exchanged public keys; in some embodiments, the current chip exchanges public keys with the target chip, that is, both the current chip and the target chip use an asymmetric encryption algorithm to generate public keys, and the negotiation of the third temporary key is achieved through the exchange of public keys. During the negotiation of the third temporary key, the third temporary key can be calculated directly based on the public key, or the third temporary key can be calculated based on the exchange of secret information based on the public key. In this step, the third temporary key is only used to distinguish from the first temporary key and the second temporary key, that is, the third temporary key is a temporary key different from the first temporary key and the second temporary key.

[0085] The number of negotiation times is incremented, and it is determined whether the current number of negotiation times is less than the predetermined number of negotiation times; in some embodiments, different values ​​can be selected for the predetermined number of negotiation times according to different starting values ​​of the number of negotiation times. For example, when the starting value of the number of negotiation times is 0, the number of negotiation times can be obtained by performing a logarithmic operation on the number of chips by 2, and then rounding up to obtain the predetermined number of negotiation times. For another example, when the starting value of the number of negotiation times is 1, the number of negotiation times can be obtained by performing a logarithmic operation on the number of chips by 2, and then rounding up to obtain the predetermined number of negotiation times by adding 1.

[0086] When the current negotiation times are less than the predetermined negotiation times, the third temporary key is updated to the first temporary key of the current chip, the parameters of the next key negotiation are updated according to the first temporary key, and the next key negotiation is entered; in some embodiments, since after each negotiation, the first chip and the second chip in the current negotiation will have a common third temporary key, in the next negotiation, the first chip and the second chip in the current negotiation will be transformed into the first chip of the next negotiation. Under the aforementioned calculation rules, the number of first chips will increase by a power of 2 for each negotiation. When the above negotiation times are not reached, it indicates that all current chips are divided into multiple parts, and the chips in each part have the same temporary key.

[0087] When the current number of negotiations is not less than the predetermined number of negotiations, the current third temporary key is determined as the shared key. In some embodiments, since after each negotiation, the first chip and the second chip in the current negotiation will have a common third temporary key, in the next negotiation, the first chip and the second chip in the current negotiation will be transformed into the first chip for the next negotiation. Under the aforementioned calculation rules, the number of first chips will increase by a power of 2 for each negotiation. Therefore, after reaching the above-mentioned predetermined number of negotiations, it indicates that all current chips already have the same third temporary key. Since all chips already have the same third temporary key, at this time, the third temporary key is used as the current shared key.

[0088] In the technical solution provided by the embodiment of the present invention, through the negotiation between the first chip and the second chip, the first chip and the second chip have the same third temporary key. In the next round of negotiation, the third temporary key is updated to the first temporary key, so that the first chip and the second chip in this round of negotiation will all become the first chip in the next round of negotiation, that is, the number of chips with the same temporary key will increase by a power of 2, thereby greatly reducing the negotiation rounds and improving the negotiation efficiency. At the same time, since the shared key is calculated separately during the key negotiation process and does not need to be transmitted, the confidentiality of the shared key can be ensured.

[0089] As an optional implementation, before the next key negotiation is performed, it also includes: obtaining the negotiation status of all chips corresponding to the current number of negotiations, and determining that the negotiation status of all chips is completed. In some embodiments, during the key negotiation process, a one-to-one negotiation between the first chip and the second chip is required, so that the first chip and the second chip have the same third temporary key after the negotiation is completed, and in the next negotiation, the number of chips with the same third temporary key continues to be expanded in the same way. Therefore, in each negotiation process, it should be determined that the first chips have the same first temporary key and the second chips have the same second temporary key; otherwise, different third temporary keys will appear between the first chip and the second chip during the negotiation process, and will be passed back in the subsequent negotiation process, resulting in the failure of the key negotiation.

[0090] As an optional implementation, the negotiation of forming the third temporary key based on the exchanged public key includes: determining the third temporary key based on the private key of the current chip and the public key of the target chip. In some embodiments, in the process of generating the public key from the private key, the public key is generated in a manner that conforms to the exchange law, and in the process of calculating the third temporary key, a calculation method that conforms to the exchange law is also used, and the third temporary key jointly owned by the private key of the current chip and the public key of the target chip can be negotiated, for example, it can be implemented by the Diffie-Hellman key exchange method, that is, the DH key exchange method.

[0091] As an optional implementation, Figure 2 As shown, the parameters for the next key negotiation are updated according to the first temporary key, including:

[0092] Based on the first temporary key, the private key required for the next key negotiation is derived; in some embodiments, after the current negotiation is completed, the first chip and the second chip in the current negotiation are transformed into the first chip in the next negotiation. At this time, the first chip in the next negotiation has the same first temporary key. Since the public key needs to be used in the calculation of the third temporary key in the next negotiation, in order to enable each first chip to obtain the same third temporary key in the next calculation process, the first chip in the next negotiation should have the same public-private key pair, so the first temporary key is used to derive the same private key.

[0093] According to the private key, the public key required for the next key negotiation is determined. In some embodiments, the first chip of the next negotiation obtains the same private key in the previous step, and then obtains the public key through the same private key, so that the first chip of the next negotiation obtains the same public key.

[0094] In this embodiment, the same first temporary key is used to calculate the private key and further obtain the public key, so that the chips with the same first temporary key can obtain the same public-private key pair. During the negotiation process, the first chip and the second chip can obtain the same third temporary key by negotiating one by one. That is, each chip only needs to participate in the calculation once during each negotiation process, so that the first chip and the second chip in the current negotiation can have the same third temporary key.

[0095] As an optional implementation, before the first negotiation process begins, it also includes randomly generating a public-private key pair, which is used to participate in the negotiation calculation of the first negotiation process. During the first negotiation process, since all keys do not have the same temporary key, it is necessary to randomly generate a public-private key pair to participate in the calculation of the first negotiation process.

[0096] As an optional implementation, Figure 3 As shown, the negotiation of forming a third temporary key based on the exchanged public key includes:

[0097] Public key encryption is used to exchange random information with the target chip. In some embodiments, public key encryption is used to exchange random information, so that the current chip and the target chip can obtain each other's random information, and asymmetric encryption can also prevent others from obtaining random information.

[0098] The third temporary key is determined based on the random information of the current chip and the random information of the target chip. In some embodiments, during the calculation process of the current chip and the target chip, the current chip uses the random information of the current chip and the random information of the target chip for calculation; the target chip also uses the random information of the current chip and the random information of the target chip for calculation. That is, the two chips use the same information to obtain the same third temporary key.

[0099] As an optional implementation, updating the parameters of the next key negotiation based on the first temporary key includes: updating the random information of the current chip based on the first temporary key. In some embodiments, since the first chip and the second chip form a common third temporary key in the current negotiation and use it as the first temporary key for the next negotiation, when the random information is updated based on the first temporary key, the first chip and the second chip in the current negotiation can have the same random information. In the next calculation process, each chip has the same random information, so that the first chip and the second chip perform one-to-one random information exchange and calculation, even if all the first chips and the second chips have the same third temporary key.

[0100] As an optional implementation, before the first negotiation process begins, it also includes randomly generating a public-private key pair and random information, wherein the public-private key pair is used for exchanging random information in the first negotiation process, and the random information is used for participating in the negotiation calculation in the first negotiation process. In some embodiments, during the negotiation process, since each chip does not have the same random information, it is necessary to randomly generate random information, and during the exchange process, it is also necessary to encrypt the random information with a public key, therefore, it is necessary to randomly generate a public-private key pair.

[0101] As an optional implementation, determining the target chip from the second chip with the second temporary key includes: when the number of first chips is the same as the number of second chips, the current chip determines the target chip based on the one-to-one correspondence between the first chip and the second chip. In some embodiments, the target chip is determined by a one-to-one correspondence between the first chip and the second chip, that is, a first chip only negotiates with one second chip, which can reduce the amount of calculation in the key negotiation process and improve the efficiency of key negotiation. In this implementation, when the number of chips is a power of 2, the number of first keys and second keys is the same each time the negotiation is performed. Therefore, this implementation is particularly suitable for the calculation process in which the number of chips is a power of 2. When the number of chips is not a power of 2, it is possible that the number of first chips and second chips is not equal, but at least part of the number of first chips and second chips is equal. For the equal part of the first chip and the second chip, the key negotiation can still be realized in the above-mentioned one-to-one correspondence manner, thereby reducing the overall amount of calculation and improving efficiency.

[0102] As an optional implementation, the current chip determines the target chip according to a one-to-one correspondence, including: determining the corresponding order of the target chip in the second chip according to the order of the current chip in the first chip. In some embodiments, in order to reduce the complexity of the chip correspondence, the correspondence can be performed according to the order, for example, the first first chip corresponds to the first second chip.

[0103] As an optional implementation, determining the target chip from the second chip with the second temporary key includes: using a chip whose logical number is continuous with that of the first chip as the second chip. In some embodiments, the logical number of the second chip is determined to be continuous with that of the first chip, so that the key negotiation process can be more convenient. For example, when the key negotiation is performed for the first time, the chip with the logical number 0 is used as the first chip, and the chip with the logical number 1 is used as the second chip. After the negotiation is completed, when the key negotiation is performed for the second time, the chips with the logical numbers 0 and 1 are used as the first chip, and the chips with the logical numbers 2 and 3 are used as the second chip.

[0104] As an optional implementation, Figure 4 As shown, determining the corresponding order of the target chips in the second chip includes:

[0105] Based on the number of first chips and second chips, determine the difference in logical numbers between the current chip and the target chip; in some embodiments, the number of first chips and the second chips is directly related to the current number of negotiations. For example, when the key negotiation is performed for the first time, all chips do not have the same first temporary key, that is, the number of first chips and the number of second chips are both 1. At this time, the difference in logical numbers between the current chip and the target chip is 1.

[0106] The logical number of the target chip is determined according to the logical number of the current chip and the difference of the logical number. In some embodiments, during the calculation process, in order to form a corresponding relationship between the current chip and the target chip, the power value of the current negotiation number of 2 is taken, and the logical number is divided by the power value to determine the target direction. For example, the chip with the logical number of 0, in the 0th negotiation process, the value obtained by the above calculation is 0, 0 is an even number, and its target direction is backward. At this time, the logical number of 0 is added to the difference to obtain the logical number of the target chip, that is, the logical number of the target chip is 1. Similarly, the chip with the logical number of 1 will obtain an odd number 1 during the calculation process, and its target direction is forward. At this time, the logical number is subtracted from the difference to obtain the logical number of the target chip, which is 0. In some embodiments, if the number of negotiations starts from 1, the number of negotiations should be reduced by 1 and then included in the calculation; if the chip logical number starts from 1, the chip logical number should be reduced by 1 and included in the calculation.

[0107] As an optional implementation, Figure 5 As shown, determining the target chip from the second chip having the second temporary key includes:

[0108] When the first chip quantity is greater than the second chip quantity; in some embodiments, when the total number of all chips is not a power of 2, a situation will occur where the first chip quantity is greater than the second chip quantity.

[0109] The current chip determines the current corresponding relationship; in some embodiments, determining the corresponding relationship of the current chip refers to determining whether the corresponding chip of the current chip exists after sequentially determining the corresponding chip for the first chip in the aforementioned one-to-one corresponding manner.

[0110] When the current chip has a corresponding second chip, the corresponding chip is used as the target chip; in some embodiments, since the correspondence relationship is determined in a one-to-one correspondence manner, it is the method with the least amount of calculation for each chip. Therefore, when the corresponding chip exists, using the corresponding chip as the target chip is beneficial to reducing the amount of calculation and improving calculation efficiency.

[0111] When the current chip does not have a corresponding second chip, any second chip is selected as the target chip. In some embodiments, since the first chip has the first temporary key and the second chip has the second temporary key, for the first chip that has no corresponding chip, obtaining the random information or public key of any second chip to calculate the third temporary key can obtain the correct third temporary key.

[0112] In this implementation, a method for obtaining a target chip is provided for the case where the number of first chips and second chips is different, which can reduce the amount of calculation and ensure that all chips obtain the same third temporary key.

[0113] As an optional implementation, Figure 6 As shown, the current chip determines the current corresponding relationship including:

[0114] According to the order of the current chip in the first chip, determine whether there is a chip with a corresponding order in the second chip; in some embodiments, in order to simplify the calculation process in the correspondence between the first chip and the second chip, the order of the first chip and the order of the second chip are corresponded without additional calculation.

[0115] When the second chip has a chip of corresponding order, the current chip has a corresponding second chip;

[0116] When the second chip does not have a chip of a corresponding sequence, the current chip does not have a corresponding second chip.

[0117] In this embodiment, the order of the first chips and the order of the second chips are used as the corresponding relationship between the two, which can be determined without additional calculation and can be implemented in the software or hardware implementation process without complex model design.

[0118] As an optional implementation, Figure 7 As shown, determining the target chip from the second chip with the second temporary key includes: determining the chip with a continuous logical number with the first chip as the second chip. In some embodiments, the logical number of the second chip is determined to be continuous with the logical number of the first chip, and the key negotiation process can be more convenient. For example, when the key negotiation is performed for the first time, the chip with a logical number of 0 is used as the first chip, and the chip with a logical number of 1 is used as the second chip. After the negotiation is completed, when the key negotiation is performed for the second time, the chips with logical numbers 0 and 1 are used as the first chip, and the chips with logical numbers 2 and 3 are used as the second chip.

[0119] As an optional implementation manner, determining whether there are chips in a corresponding order in the second chip includes:

[0120] Based on the number of first chips, the difference in logical numbers between the current chip and the target chip is determined; in some embodiments, the number of first chips and the second chips is directly related to the current number of negotiations. For example, when the key negotiation is performed for the first time, all chips do not have the same first temporary key, that is, the number of first chips and the number of second chips are both 1. At this time, the difference in logical numbers between the current chip and the target chip is 1.

[0121] The target logical number is determined according to the logical number of the current chip and the difference between the logical numbers. In some embodiments, in the calculation process, in order to form a corresponding relationship between the current chip and the target chip, the power of the current negotiation times of 2 is taken, and the logical number is divided by the power to determine the target direction. For example, the chip with the logical number of 0, in the 0th negotiation process, the value obtained by the above calculation is 0, 0 is an even number, and its target direction is backward. At this time, the logical number of 0 is added to the difference to obtain the logical number of the target chip, that is, the logical number of the target chip is 1. Similarly, the chip with the logical number of 1 will obtain an odd number 1 during the calculation process, and its target direction is forward. At this time, the logical number is subtracted from the difference to obtain the logical number of the target chip, which is 0. In some embodiments, if the negotiation times are counted from 1, the negotiation times should be subtracted by 1 and then included in the calculation; if the chip logical number starts from 1, the chip logical number should be subtracted by 1 and included in the calculation.

[0122] Determine whether there is a chip with a target logical number; in some embodiments, when determining whether there is a chip with a target logical number, the target logical number can be compared with the total number of chips. When the target logical number is greater than the total number of chips, there must be no chip with the target logical number. This can also be achieved by maintaining an array corresponding to the logical number and recording whether the logical number exists in the array.

[0123] When there is a chip with the target logical number, the current chip has a corresponding second chip;

[0124] When there is no chip with the target logic number, the current chip does not have a corresponding second chip.

[0125] As an optional implementation, selecting any second chip as the target chip includes: the target logic number is sequentially decreased until there is a second chip with the target logic number, and the chip with the target logic number is used as the target chip. In some embodiments, the decrease of the target logic number can find the second chip with the target logic number faster than random selection.

[0126] Figure 8 An exemplary implementation of the present invention is shown, which is a negotiation process when the total number of chips is a power of 2, and is specifically as follows:

[0127] Step 1: Give each chip in the entire system a logical number, starting from 0;

[0128] Step 2, assuming that the number of chips in the entire system is N = 2^M, that is, the logical numbers are 0, 1, 2...N-1;

[0129] Step 3, assuming that the logic number of the current chip is X;

[0130] Step 4: Randomly generate a public-private key pair<Kx,Ky> , and make the public key public to other chips;

[0131] Step 5, randomly generate random information Rx;

[0132] Step 6, initially set the variable L recording the number of shared key calculation rounds to 0;

[0133] Step 7: Participate in the synchronization operation of all chips in the entire system to confirm that all chips have completed the calculation of the temporary shared key in the previous round;

[0134] Step 8: Get the chip logic number The public key Py announced by the chip; in some embodiments, "<<" represents a left shift in binary. Represents XOR operation. Using the calculation method in this step, the number of chips with the same temporary key can be determined according to the current number of negotiations, and the XOR operation can determine the corresponding direction. At this time, the chip with the logical number Y is the target chip. The random information of the current chip is the first temporary key of the current negotiation round, and the random information of the target chip is the second temporary key of the current round;

[0135] Step 9, encrypt Rx using the public key Py to obtain ENC-Rx;

[0136] Step 10, send ENC-Rx to the chip with logical number Y, and obtain ENC-Ry from it;

[0137] Step 11, decrypt ENC-Ry using the private key Kx to obtain Ry;

[0138] Step 12, based on the random information Rx and Ry, a temporary shared key SK is sent. A typical implementation is SK=HASH(Rx||Ry), where the symbol “||” represents data concatenation; the SK in this step is the third temporary key.

[0139] Step 13, complete a round of shared key calculation, and increase L by 1;

[0140] Step 14: If L is equal to M, the key calculation is completed, the process ends, and jumps to step 16; otherwise, execute step 15;

[0141] Step 15: Use SK as the new Rx and jump back to step 7 to start the next round of shared key calculation;

[0142] Step 16: Shared key negotiation is completed, and the temporary shared key SK of the last round is the shared key.

[0143] In the above exemplary embodiment, step 8 is the process of determining the target chip, and steps 9-12 are the process of exchanging public keys and exchanging random information using public key encryption, and further negotiating to form a third temporary key. Those skilled in the art should be able to understand that the above steps 9-12 can also be replaced by the DH key exchange method to achieve the negotiation of the third temporary key. In the above exemplary embodiment, the key derivation process based on random information Rx and Ry may include other information in addition to using Rx and Ry, as long as the calculation method of chip X and chip Y is the same. The derivation method may not be a hash, but an encryption method, for example, using Rx to encrypt Ry, or a combination of hash and encryption, for example, calculating a hash for Rx, and then using Ry to encrypt the hash value, as long as chip X and chip Y use the same derivation method and random information Rx and Ry are both involved in the calculation.

[0144] In this implementation, taking 8 chips for key negotiation as an example, during the negotiation process, the key sharing range changes as follows: Figure 9-11 As shown in the figure, the corresponding chips in each round of negotiation are as follows:

[0145] First, each chip generates a public and private key pair, N = 8, M = 3. Fig. 9 As shown, no two chips have the same first temporary key.

[0146] L=0, in the 0th round of key negotiation, when each chip is used as the current chip, its target chip is as follows:

[0147]

[0148] After this round of key negotiation is completed, as shown in FIG10 , the chips framed by thin dotted lines have the same third temporary key and publish the same public key.

[0149] L=1, during the first round of key negotiation, the target chips of each chip are as follows:

[0150]

[0151] After this round of key negotiation is completed, Fig.11 As shown, the chip framed by the thin dotted line has the same third temporary key and publishes the same public key.

[0152] L=2. During the second round of key negotiation, the target chips of each chip are as follows:

[0153]

[0154]

[0155] After this round of key negotiation is completed, all chips have the same shared key.

[0156] Fig.12 An exemplary implementation of the present invention is shown, which is a negotiation process when the total number of chips is not a power of 2, and is specifically as follows:

[0157] Step 1: Give each chip in the entire system a logical number, starting from 0;

[0158] Step 2, assuming that the number of chips in the entire system is N, that is, the logical numbers are 0, 1, 2...N-1;

[0159] Step 3, the value of M is log(2,N) rounded up (for example, if N=4, then M=2; if N=5, then M=3);

[0160] Step 4, assuming that the logic number of the current chip is X;

[0161] Step 5: Randomly generate a public-private key pair<Kx,Ky> , and make the public key public to other chips;

[0162] Step 6, initially set the variable L recording the number of shared key calculation rounds to 0;

[0163] Step 7: Participate in the synchronization operation of all chips in the entire system to confirm that all chips have published their latest public keys;

[0164] Step 8: Get the chip logic number The public key Py announced by the chip; in this step, the public key of the current chip is the first temporary shared key, the chip with the logical number Y is the target chip, and the public key of the target chip is the second temporary shared key;

[0165] Step 9, calculate the temporary shared key SK according to Py and Kx; in this step, the temporary shared key SK is the third temporary shared key. The calculation of SK uses, for example, the elliptic curve public key cryptography algorithm, then SK = Kx*Py, where the symbol "*" represents point multiplication;

[0166] Step 10, complete a round of shared key calculation, and increase L by 1;

[0167] Step 11, if L is equal to M, the key calculation is completed, the process ends, and jumps to step 16; otherwise, execute step 12;

[0168] Step 12: derive a new private key Kx' based on the temporary shared key SK, calculate the corresponding public key Py', and use Kx' and Py' as the new key pair<Kx,Ky> ; The new private key derivation process may adopt a hash algorithm, for example, Kx'=Hash(SK);

[0169] Step 13, publicize the latest public key Px to other chips;

[0170] Step 15, jump back to step 7 and start the next round of shared key calculation;

[0171] Step 16: shared key negotiation is completed, and the temporary shared key S of the last round is the shared key.

[0172] In the above exemplary embodiment, step 8 is the process of determining the target chip, and step 9 is the DH key exchange method to realize the negotiation of the third temporary key. Those skilled in the art should be able to understand that the above step 9 can also be replaced by the process of exchanging public keys and exchanging random information using public key encryption, and further negotiating to form the third temporary key. In this embodiment, the method of calculating the temporary shared key S based on Kx and Py can be changed arbitrarily, but these two data must be used, and the calculation method of each chip is the same. The method of deriving a new private key Kx' based on the temporary shared key S can be changed arbitrarily, but the temporary shared key must be obtained, and the calculation method of each chip is the same.

[0173] In this implementation, taking five chips for key negotiation as an example, during the negotiation process, the key sharing range changes as follows: Figure 13-15 As shown in the figure, the corresponding chips in each round of negotiation are as follows:

[0174] First, each chip generates a public and private key pair, N = 5, M = 3, such as Fig.13 As shown, no two chips have the same temporary shared key; each chip maintains an array Status with a length of T = 2^M, which is used to record the key negotiation status of the current chip and other chips; the entire Status is initialized to 0; Status[X] is initialized to 1, indicating that the key negotiation with itself has been completed; Status[N...T-1] is initialized to 2, indicating that the chips corresponding to these logical numbers do not exist; the logical number of the chip that needs to be negotiated for the key in the current round is calculated as Check the value of Status[Y]. If Status[Y] is 2, then reduce the logical number Y by 1 in a loop, and continue to check the value of Status[Y] until the value of Status[Y] is not 2. At this time, if Status[Y] is 1, it is considered that the key negotiation for the current round has been completed, and the process directly jumps to L+1 to enter the next round of key negotiation; if Status[Y] is 0, obtain the public key announced by the chip with the logical number Y, and perform the key negotiation for the current round. After the negotiation is completed, if Status[Y] is 0, modify it to 1. That is, in this embodiment, an array is used to record whether the target logical number has a corresponding chip. When the target logical number does not have a corresponding chip, the target chip is determined by using the target logical number in a descending manner.

[0175] Initialize the Status array of each new chip, the results are as follows:

[0176] Chip serial number St[0] St[1] St[2] St[3] St[4] St[5] St[6] St[7] 0 1 0 0 0 0 2 2 2 1 0 1 0 0 0 2 2 2 2 0 0 1 0 0 2 2 2 3 0 0 0 1 0 2 2 2 4 0 0 0 0 1 2 2 2

[0177] L=0, during the 0th round of key negotiation, the target chips of each chip are as follows

[0178]

[0179] There is no corresponding chip for the target logical number 5 of chip 4, Status[5] is 2, and Status[4] is 1 after decrementing. Chip 4 believes that the key negotiation for the current round has been completed and directly enters the next round of key negotiation. During the process of decrementing the target logical number, if there is a corresponding chip for the target logical number, the chip should be a chip with the second temporary shared key. When decrementing to the target logical number 4, St[4] is 1, which means that the current chip has already negotiated keys with the chip and has a common key, so there is no need for repeated negotiation. Therefore, the current chip skips this round of calculation. This is because when the status of the target logical number is 1, it indicates that the temporary shared key of the target logical chip is the first temporary key, which means that the range of the second target chip has been exceeded during the decrement process, so this round of calculation is skipped.

[0180] After this round of key negotiation is completed, Fig.14 As shown, the chips framed by thin dotted lines have the same shared key and publish the same public key.

[0181] After this round of key negotiation, the status array of each chip is as follows:

[0182] Chip serial number St[0] St[1] St[2] St[3] St[4] St[5] St[6] St[7] 0 1 1 0 0 0 2 2 2 1 1 1 0 0 0 2 2 2 2 0 0 1 1 0 2 2 2 3 0 0 1 1 0 2 2 2 4 0 0 0 0 1 2 2 2

[0183] L=1, during the first round of key negotiation, the target chips of each chip are as follows

[0184]

[0185] There is no corresponding chip for the target logic number 6 of chip 4, and Status[6] is 2. After decrementing, it is found that Status[5] is also not 1. After continuing to decrement, it is found that Status[4] is 1. Chip 4 believes that the current round of key negotiation has been completed and directly enters the next round of key negotiation.

[0186] After this round of key negotiation is completed, Fig.15 As shown, the chip framed by the thin dotted line has the same third temporary key and publishes the same public key.

[0187] After this round of key negotiation, the status array of each chip is as follows:

[0188] Chip serial number St[0] St[1] St[2] St[3] St[4] St[5] St[6] St[7] 0 1 1 1 0 0 2 2 2 1 1 1 0 1 0 2 2 2 2 1 0 1 1 0 2 2 2 3 0 1 1 1 0 2 2 2 4 0 0 0 0 1 2 2 2

[0189] L=2, during the second round of key negotiation, the target chips of each chip are as follows

[0190]

[0191] There is no corresponding chip for the target logic number 5 of chip 1, Status[5] is 2, and Status[4] is found to be 0 after decrementing. The shared key of this round is calculated using the public key of chip 4.

[0192] There is no corresponding chip for the target logic number 6 of chip 2. Status[6] is 2. After decrementing, it is found that Status[5] is 2. After decrementing again, it is found that Status[4] is 0. The public key of chip 4 is used to calculate the shared key for this round.

[0193] There is no corresponding chip for the target logic number 7 of chip 3. Status[7] is 2. After decrementing, it is found that Status[6] and Status[5] are both 2. After decrementing again, it is found that Status[4] is 0. The public key of chip 4 is used to calculate the shared key for this round.

[0194] After this round of key negotiation is completed, all chips have the same shared key.

[0195] After this round of key negotiation, the status array of each chip is as follows:

[0196] Chip serial number St[0] St[1] St[2] St[3] St[4] St[5] St[6] St[7] 0 1 1 1 0 1 2 2 2 1 1 1 0 1 1 2 2 2 2 1 0 1 1 1 2 2 2 3 0 1 1 1 1 2 2 2 4 1 0 0 0 1 2 2 2

[0197] The embodiment of the present invention also provides a multi-chip identity authentication method, which is applied to any chip that uses any of the above methods to perform key negotiation, such as Fig.16 As shown, including:

[0198] Based on a one-to-one correspondence, the target chip of the current chip is determined; in some embodiments, the current chip and the target chip have a one-to-one correspondence, that is, all chips are formed into a verification combination in pairs, and the chips are verified with each other during the verification process. This method can realize the identity verification of all chips with the least amount of calculation.

[0199] The identity authentication information of the target chip is calculated based on the shared secret shared by all chips, the shared key of all chips and the logical number of the target chip; in some embodiments, all chips have the same shared secret, the same shared key and the public logical number, so the identity authentication information of any chip can be directly generated without other interactive information.

[0200] Obtain the identity information of the target chip, and verify the identity information according to the identity verification information; in some embodiments, the target chip calculates its own identity information according to the shared key, the shared secret and its own logical number. Since the current chip and the target chip use the same data and the same information for calculation, the identity information and the identity verification information should be consistent.

[0201] When the verification is passed, the verification status is synchronized to all chips. In some embodiments, after the current chip verifies the target chip, other chips are not sure whether the identity authentication of the target chip is passed. At this time, the current chip needs to synchronize the verification status to all chips.

[0202] In the technical solution provided in this embodiment, during the identity authentication process, the shared key participates in the calculation of the identity authentication process. Therefore, if the message is tampered with during the negotiation process, the tampered message will cause the chip to be unable to generate the same shared key and fail the identity authentication. If a third party obtains the public key of the chip during the key negotiation process and participates in the entire shared key calculation process, although the final shared key can be obtained, during the identity authentication process, since the third party cannot know the shared secret, the identity authentication will not pass at all. During the identity authentication process, although the shared secret and the chip logic number remain fixed, they do not participate in the calculation of the shared key; each time the key is negotiated, all chips use a random number as the shared key. Therefore, even if the shared secret and the chip logic number calculation method are leaked, the data encrypted with the old shared key is still safe due to the complexity of the asymmetric cryptographic algorithm.

[0203] As an optional implementation, determining the target chip of the current chip based on a one-to-one correspondence includes: determining the target logical number based on the logical number of the current chip and a predetermined interval. In some embodiments, when forming a check combination between two chips, it can be formed in a random manner. However, maintaining a one-to-one correspondence while randomly selecting will lead to a complicated calculation process, and the model will also be more complicated during the software or hardware implementation. In order to simplify the calculation process and implementation method, this embodiment is implemented by setting a predetermined interval. For example, when the logical number starts from 0, the corresponding direction of the chip with an even logical number is determined to be backward correspondence, and the corresponding direction of the chip with an odd logical number is forward correspondence, and the corresponding interval is set to 1. For example, it can be used The target logic number is determined by the method of, where Y is the target logic number, X is the logic number of the current chip, It is the binary exclusive OR operation.

[0204] As an optional implementation, Fig.17 As shown, after determining the target logical number, it also includes:

[0205] Determine the corresponding state of the target logic number; in some embodiments, the corresponding state of the target logic number refers to whether there is a chip with the target logic number.

[0206] When there is a chip with a target logic number, the chip with the target logic number is used as the target chip; in some embodiments, when the total number of chips is an even number, all chips have corresponding chips, that is, when the current chip is any chip, there is a corresponding chip for its target logic number, at this time, the chip corresponding to the target logic number is used as the target chip. When the total number of chips is an odd number, there will be a chip with a target logic number that does not have a corresponding chip, that is, there is no chip with the target logic number.

[0207] When there is no chip with the target logic number, the target logic number is changed. In some embodiments, when there is no chip with the target logic number, in order to enable other chips to verify the identity of the current chip, the target logic chip needs to be changed.

[0208] As an optional implementation, after determining the target chip of the current chip based on a one-to-one correspondence, it also includes: determining whether the current chip is a preset chip. When the current chip is a preset chip, the chip whose target logical number needs to be changed is added as the target chip of the current chip. In some embodiments, when the total number of all chips is an odd number, one chip needs to be verified once more. Since two chips need to interact during the verification process, it is necessary to pre-set rules to determine which chip is to be verified. In some embodiments, the preset chip can be selected in a random manner, but all chips should obtain the preset information so that any chip can complete the identity authentication interaction with the preset chip when it is used as the remaining chip.

[0209] As an optional implementation, changing the target logical number includes: changing the target logical number to a preset target logical number. In some embodiments, when the total number of all chips is an odd number, there will inevitably be one chip left in the process of forming a verification combination in pairs. When the current chip is the remaining chip, the preset chip is selected for identity authentication to complete the verification of the security of the current chip by other chips.

[0210] As an optional implementation, it also includes calculating the identity information of the current chip based on the shared secret shared by all chips, the shared key of all chips and the logical number of the current chip, and announcing the identity of the current chip to all chips. The identity of the current chip mentioned above can be calculated in the following way: IDx = Hash (shared secret S|| shared key SK|| logical number X of the current chip). Of course, the identity authentication information of the target chip also needs to be calculated in the same way: IDy = Hash (shared secret S|| shared key SK|| logical number Y of the current chip). In addition, the calculation method of the identity information IDx can be changed arbitrarily, but the three data of shared secret S, shared key SK, and logical number X of the chip must be used, and the calculation method of each chip is the same. Similarly, the identity authentication information should also be calculated in the same way.

[0211] Fig.18 An exemplary embodiment of the present invention is shown, which is an identity authentication process when the total number of chips is a multiple of 2, and is specifically as follows:

[0212] Step 1, all chips have shared secret information S;

[0213] Step 2, calculate the identity IDx of the current chip based on "shared secret S+shared key SK+chip logical number X"; in this step, the identity IDx is the identity information of the current chip. After the identity of the current chip is calculated and sent out, the target chip verifies the identity of the current chip; wherein X is the logical number of the current chip, and the shared key SK is the shared key negotiated by the aforementioned multi-chip key negotiation method.

[0214] Step 3, based on "shared secret S + shared key SK + chip logical number "Calculate the identity IDy' of the chip to be verified; in this step, use The target logical number is determined by the method of, that is, the logical number of the target chip having a one-to-one correspondence with the current chip is determined, where X is the logical number of the current chip, is a binary XOR operation. The identity IDy' is the identity authentication information of the target chip;

[0215] Step 4, publicizing one's own identity information IDx to other chips; publicizing one's own identity information to other chips is to enable other chips to complete the identity authentication of the current chip.

[0216] Step 5: Participate in the synchronization operation of all chips in the entire system to confirm that all chips have made their identity information public;

[0217] Step 6: Get the chip logic number The identity information IDy disclosed by the chip; the identity authentication information of the target chip is calculated in step 3, that is, the target chip having a corresponding relationship with the current chip has been determined in step 3. In this step, the identity authentication information of the target chip is obtained to realize the identity authentication of the target chip.

[0218] Step 7, compare IDy and IDy'. If they are not equal, the key negotiation fails and the current chip is suspended; otherwise, participate in the synchronization operation of all chips in the entire system to confirm that the identity authentication has been completed. When IDy and IDy' are equal, it means that the authentication has passed. At this time, the status of the authentication passing is synchronized to all chips.

[0219] In this embodiment, the identity authentication process is described by taking the case where the number of chips is a multiple of 2 as an example. The relationship between the logic number of the current chip and the logic number of the target chip is determined in this way. It should also be considered that when the number of chips is not a multiple of 2, the above calculation method will result in a chip that does not have a one-to-one corresponding target chip. At this time, the remaining chips can complete an identity verification with any chip. In the verification process of the remaining chip, in order to smoothly implement the verification, a chip can be preset. When the target logical number calculated by the method does not have a corresponding chip, the target logical number is changed to a preset target logical number. For the preset logical number, the remaining chip needs to be used as the target chip, that is, the preset chip needs to complete identity verification with the two chips.

[0220] Those skilled in the art can understand that all or part of the processes in the above method embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes in the above method embodiments. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0221] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A multi-chip key negotiation method, characterized in that: Applicable to one of the multiple chips involved in key negotiation, including: When the current chip is a first chip having a first temporary key, determining a target chip from a second chip having a second temporary key; wherein the first temporary key is formed by the first chip participating in a previous round of negotiation, and the second temporary key is formed by the second chip participating in a previous round of negotiation; The current chip exchanges public keys with the target chip, and forms a third temporary key through negotiation based on the exchanged public keys; Incrementing the negotiation times and determining whether the current negotiation times is less than the predetermined negotiation times; When the current negotiation number is less than the predetermined negotiation number, the third temporary key is updated to the first temporary key of the current chip, the parameters of the next key negotiation are updated according to the first temporary key, and the next key negotiation is started; When the current negotiation number is not less than the predetermined negotiation number, the current third temporary key is determined as the shared key.

2. The method according to claim 1, characterized in that Before the next key negotiation, the following steps are also performed: The negotiation status of all chips corresponding to the current negotiation times is obtained, and it is determined that the negotiation status of all chips is in the completed state.

3. The method according to claim 1, characterized in that Negotiating and forming a third temporary key based on the exchanged public key includes: determining the third temporary key based on a private key of the current chip and a public key of the target chip.

4. The method according to claim 3, characterized in that The parameters for the next key negotiation are updated according to the first temporary key and include: deriving a private key required for the next key negotiation based on the first temporary key; Based on the private key, a public key required for the next key negotiation is determined.

5. The method according to claim 3, characterized in that: Before the first negotiation process starts, the method further includes randomly generating a public-private key pair, wherein the public-private key pair is used for participating in the negotiation calculation of the first negotiation process.

6. The method according to claim 1, characterized in that Negotiating the formation of a third temporary key based on the exchanged public key includes: Use public key encryption to exchange random information with the target chip; A third temporary key is determined according to the random information of the current chip and the random information of the target chip.

7. The method according to claim 6, characterized in that Updating the parameters of the next key negotiation according to the first temporary key includes: updating the random information of the current chip according to the first temporary key.

8. The method according to claim 6, characterized in that Before the first negotiation process begins, the method also includes randomly generating a public-private key pair and random information, wherein the public-private key pair is used for exchanging random information in the first negotiation process, and the random information is used for participating in the negotiation calculation in the first negotiation process.

9. The method according to any one of claims 1 to 8, characterized in that: Determining the target chip from the second chip having the second temporary key includes: When the number of the first chips is the same as the number of the second chips, the current chip determines the target chip according to a one-to-one correspondence between the first chip and the second chip.

10. The method according to claim 9, characterized in that The current chip determines the target chip based on a one-to-one correspondence including: According to the order of the current chips in the first chip, the corresponding order of the target chips in the second chip is determined.

11. The method according to claim 10, characterized in that Determining the target chip from the second chips having the second temporary key includes: using a chip having a logical number continuous with the first chip as the second chip.

12. The method according to claim 11, characterized in that Determining the corresponding order of the target chips in the second chip includes: Determine the difference in logic numbers between the current chip and the target chip according to the number of the first chip and the second chip; The logic number of the target chip is determined based on the logic number of the current chip and the difference between the logic numbers.

13. The method according to any one of claims 1 to 8, characterized in that: Determining the target chip from the second chip having the second temporary key includes: When the first chip quantity is greater than the second chip quantity; The current chip determines the current corresponding relationship; When the current chip has a corresponding second chip, the corresponding chip is used as the target chip; When the current chip does not have a corresponding second chip, any second chip is selected as the target chip.

14. The method according to claim 13, characterized in that The current chip determines the current corresponding relationship including: According to the order of the current chips in the first chip, determining whether there are chips in the corresponding order in the second chip; When the second chip has a chip of corresponding order, the current chip has a corresponding second chip; When the second chip does not have a chip of a corresponding sequence, the current chip does not have a corresponding second chip.

15. The method according to claim 14, characterized in that Determining the target chip from the second chips having the second temporary key includes: using a chip having a logical number continuous with the first chip as the second chip.

16. The method according to claim 15, characterized in that Determining whether there is a chip in the corresponding order in the second chip includes: Determine the difference in logic numbers between the current chip and the target chip according to the number of the first chip; Determine the target logic number based on the logic number of the current chip and the difference between the logic numbers; Determine whether there is a chip with a target logic number; When there is a chip with the target logical number, the current chip has a corresponding second chip; When there is no chip with the target logic number, the current chip does not have a corresponding second chip.

17. The method according to claim 16, characterized in that Selecting any second chip as the target chip includes: decreasing the target logic number in sequence until there is a second chip with the target logic number, and then taking the chip with the target logic number as the target chip.

18. A multi-chip identity authentication method, characterized in that: Applied to any chip that uses the method described in any one of claims 1 to 17 to perform key negotiation, comprising: Determine the target chip of the current chip based on the one-to-one correspondence; Calculate the authentication information of the target chip based on the shared secret shared by all chips, the shared key of all chips, and the logic number of the target chip; Acquire the identity information of the target chip, and verify the identity information according to the identity authentication information; When the verification is passed, the verification pass status is synchronized to all chips.

19. The method according to claim 18, characterized in that According to the one-to-one correspondence, the target chip of the current chip is determined to include: The target logic number is determined according to the logic number of the current chip and the predetermined interval.

20. The method according to claim 19, characterized in that After determining the target logical number, it also includes: Determine the corresponding state of the target logical number; When there is a chip with the target logic number, the chip with the target logic number is used as the target chip; When there is no chip having the target logical number, the target logical number is changed.

21. The method according to claim 20, characterized in that After determining the target chip of the current chip according to the one-to-one correspondence, the following steps are also included: It is determined whether the current chip is a preset chip. If the current chip is a preset chip, the chip whose target logic number needs to be changed is added as the target chip of the current chip.

22. The method according to claim 20, characterized in that Changing the target logical number includes: changing the target logical number to a preset target logical number.

23. The method according to claim 18, characterized in that It also includes calculating the identity information of the current chip based on the shared secret shared by all chips, the shared key of all chips and the logical number of the current chip, and publicizing the identity information of the current chip to all chips.

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