Dynamic random access memory pass transistor designed using statistical variations in leakage current

Abstract

A design of a dynamic random access memory (DRAM) pass transistor is provided via simulating a first plurality of transistor leakage currents by simulating different dopant configurations in the transistor, simulating a second plurality of transistor leakage currents by simulating a single trap insertion in the transistor for each of the different dopant configurations, fitting the first and second plurality of transistor leakage currents to a first leakage current distribution and a second leakage current distribution, combining the first and second leakage current distributions to produce a third leakage current distribution, generating a third plurality of statistically generated leakage currents for a specified trap density of the transistor based on the first leakage current distribution, the second leakage current distribution, and the specified trap density, and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Description

Technical Field

[0001] This disclosure generally relates to electronic design automation (EDA) systems. In particular, this disclosure relates to designing DRAM (Dynamic Random Access Memory) transfer transistors using computer simulation and by utilizing statistical changes in leakage current. Background Technology

[0002] The one-transfer transistor / one-capacitor (1T1C) DRAM cell design is one in which the design has evolved from planar techniques to complex non-planar structures for the included transfer transistor and capacitive storage node. This evolution has enabled continuous reduction in the size of DRAM cells, thereby increasing the memory density per chip while maintaining good scalability, with a single memory cell occupying an area close to 6F per cell. 2 Where F is the smallest feature size in the cell (typically the gate pitch). It has been proposed to improve scaling efficiency to 4F. 2 A vertical all-around gate solution. To enable these scaling trends, both the storage capacitors and transfer transistors used in the DRAM cells are designed and manufactured to provide very low leakage current, resulting in a longer bit retention time than the bit refresh time. Higher refresh rates result in higher power consumption. Summary of the Invention

[0003] In one embodiment, this disclosure provides a system including a processor and a memory, the memory including instructions that, when executed by the processor, perform operations including: generating a first plurality of transistor leakage currents by simulating different dopant configurations in transistors; generating a second plurality of transistor leakage currents by simulating a single trap insertion in the transistors for each dopant configuration in the different dopant configurations; fitting the first plurality of transistor leakage currents to a first leakage current distribution; fitting the second plurality of transistor leakage currents to a second leakage current distribution; generating a third plurality of leakage currents for a specified trap density of transistors based on the first and second leakage current distributions; converting the third plurality of leakage currents into model parameters for a DRAM cell including transistors; and evaluating the DRAM cell including transistors based on the model parameters.

[0004] In one embodiment, this disclosure provides a method comprising: generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating a single trap insertion in the transistor for each dopant configuration in the different dopant configurations; fitting the first plurality of transistor leakage currents to a first leakage current distribution; fitting the second plurality of transistor leakage currents to a second leakage current distribution; combining the first leakage current distribution and the second leakage current distribution to generate a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density of the transistor based on the first leakage current distribution, the second leakage current distribution, and a specified trap density of the transistor; mapping the third plurality of statistically generated leakage currents to model parameter values ​​for circuit simulation of a DRAM cell including a transistor; and evaluating the DRAM cell including the transistor based on the model parameters.

[0005] In one embodiment, this disclosure provides a non-transitory computer-readable storage medium including instructions that, when executed by a processor, perform operations including: evaluating a statistical compaction model of a DRAM cell having a first trap density to determine whether a response refresh time for a simulated transfer transistor included in the DRAM cell satisfies a threshold; in response to determining that the response refresh time does not satisfy the threshold: selecting a different second trap density for the DRAM cell; re-evaluating the statistical compaction model of the DRAM cell having the second trap density to determine whether a response refresh time for a simulated transfer transistor included in the DRAM cell satisfies the threshold; and in response that the response refresh time satisfies the threshold, indicating that the DRAM cell is acceptable; wherein: the statistical compaction model is generated via a first plurality of statistical simulations of the DRAM cell and a second plurality of statistical simulations of the DRAM cell, the first plurality of statistical simulations producing a first leakage current distribution representing a baseline leakage current, and the second plurality of statistical simulations producing a second leakage current distribution representing an additional leakage current distribution, wherein the first leakage current distribution and the second leakage current distribution are combined to create a third leakage current distribution representing induced drain leakage in the DRAM cell; and the third leakage current distribution is extrapolated based on a specified trap density to describe the statistical leakage current of the DRAM cell at the specified trap density. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments thereof. The drawings are provided to give knowledge and understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these particular embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0007] Figure 1The illustration shows a schematic structure of a DRAM cell according to various embodiments of the present disclosure. For TCAD simulation, the schematic structure of the DRAM cell is obtained through process emulation and process simulation.

[0008] Figure 2 This is a circuit diagram illustrating a circuit model of a DRAM cell according to various embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart of a method for optimizing the design of a transmission transistor according to various embodiments of the present disclosure.

[0010] Figure 4 The diagram illustrates the TCAD results of leakage current in a DRAM cell according to various embodiments of the present disclosure, the leakage current being caused by random discrete dopants and also by a single random trap in the presence of random discrete dopants.

[0011] Figure 5A and Figure 5B These are waveform diagrams according to various embodiments of the present disclosure, illustrating the waveform excitation (voltage) applied to the DRAM cell circuitry during various operating phases.

[0012] Figure 6 This is a graph showing the statistical circuit simulation results according to various embodiments of the present disclosure, illustrating the storage node voltage distribution for a given refresh time in three different trap density scenarios.

[0013] Figure 7 This is a flowchart of a method for performing simulation format transformation according to various embodiments of the present disclosure.

[0014] Figure 8 The figure is based on an embodiment of the present disclosure and illustrates a comparison of leakage current obtained from a compact model statistically generated for several trap density distributions with leakage obtained from TCAD simulation.

[0015] Figure 9 Flowcharts depict various processes used during the design and manufacture of integrated circuits according to some embodiments of this disclosure.

[0016] Figure 10 A diagram depicts an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0017] Embodiments of this disclosure provide a novel simulation flow that proceeds from technical computer-aided design (TCAD) data to circuit simulation using a circuit simulator such as SPICE (a simulation program with integrated circuit focus) to predict the statistical dispersion of leakage current in transport transistors that limit the refresh time of DRAM.

[0018] Due to the high aspect ratio and small area of ​​each cell, there are physical limitations to increasing the capacitance of the storage capacitor. Therefore, the focus is on designing and fabricating transport transistors to increase retention, which typically relies on applications with non-zero substrate bias and on optimized doping profiles and gate-drain overlap. Designing and fabricating transport transistors in this way is a multidimensional and difficult task, potentially requiring several very expensive experiments on a silicon wafer. Furthermore, because these leakage currents are on the order of attoamperes, it is impossible to physically measure the leakage current from a single cell experimentally. Therefore, leakage measurements can only be performed on large cell arrays, thus preventing a physical understanding of the mechanisms governing the random retention of individual defective cells.

[0019] The simulation of leakage current due to defects in the semiconductor region of the device can be performed using three-dimensional technology computer-aided design (TCAD) drift-diffusion simulation, which includes carrier generation / recombination. Carrier recombination / generation is typically described by the Shockley-Read-Hall equation according to Equation [1], where the lifetime is modified according to the auxiliary Hurkx equation according to Equations [2] and [3] to describe the effects of trap-assisted tunneling.

[0020]

[0021] σ=σ0(1+γ TAT [2]

[0022]

[0023] Although this TCAD simulation determines the transistor leakage current, the solution of the additional composite equation (i.e., Equations [1-3]) significantly increases the TCAD simulation time and reduces the TCAD simulation output due to the non-convergence of the iterative solution scheme.

[0024] The technical advantages and improved / extended functionality offered by this approach include: enabling a physical understanding of the leakage mechanisms of individual defective cells; allowing cell optimization at a negligible fraction of the cost of wafer-based optimization; and improved ease of use across any existing platform characterized by TCAD simulators, circuit model extractors, and circuit simulators. Because the process is implemented based on the output of a physical TCAD simulation tool, it can also be extended to other simulable variation mechanisms related to refresh time, including but not limited to: write current variations, capacitance variations, capacitor leakage variations, sense amplifier variations, and supply voltage fluctuations.

[0025] The analysis system uses post-processing methods on TCAD simulations to enable fast and accurate simulation of leakage current in DRAM transfer transistors even in the presence of a single randomly located trap. The analysis system fits data on single-trap-induced leakage from the TCAD simulation (from post-processing) using a multi-functional probability density to correctly capture the statistical variability associated with random discrete dopants and the tail of the statistical distribution associated with randomly located discrete traps. The analysis system extracts compact model parameters based on the target TCAD data and the fast and accurate generation of a statistically compact model for arbitrary trap density values. The analysis system performs statistical circuit simulations (e.g., using a SPICE simulator) using the statistically compact model. The embodiments discussed herein enable an understanding of leakage mechanisms in individual DRAM cells and enable prediction of the statistical distribution of leakage current in DRAM cells. When employed within a Design of Experiments (DOE) framework or within a design optimization cycle, this disclosure enables improvements to transfer transistor designs compared to silicon wafer fabrication-based optimizations, thereby minimizing leakage and maximizing refresh time at negligible cost and duration.

[0026] In general, this disclosure includes a method that implements a simulation-based process to predict the statistical variability of leakage current in a transmission transistor (which limits the refresh time of advanced DRAM) and, where statistical variability exists, enables optimization of the transmission transistor design. As used in the art and as understood by one of ordinary skill in the art, “optimization”, “optimize”, “optimizing”, and its variations refer to a mathematical formula for selecting some improvements (if available) to some identified characteristics or constraints, and does not imply an absolute or globally optimal improvement to the characteristic or constraint (as the term may be used more commonly). Thus, in some cases, optimization may determine a minimum, where the minimum may be a local minimum rather than a global minimum. For example, a first design optimized for a reduced footprint may consume more power than a second design optimized for low power consumption. In another example, a first design optimized for reduced wire length may have a lower total wire length over the entire circuit than a second design (e.g., the first design exhibits a global minimum of wire length), but may also have longer individual wire lengths between the first and second elements than in the second design (e.g., the second design exhibits a local minimum). Therefore, “optimization” designs are created or updated to improve the overall metrics of one or more actively specified constraints and / or objectives, and can represent multiple hierarchical design considerations among various optimization priorities.

[0027] Figure 1 The illustration shows a schematic structure 100 of a DRAM cell according to various embodiments of the present disclosure. For TCAD simulation, the schematic structure 100 of the DRAM cell is obtained through process emulation and process simulation. Figure 1 This illustrates a typical 6F process that can be obtained through process simulation or process modeling. 2 The DRAM cell transistor structure 100 represents nanoscale generation. Figure 1 The TCAD design can be used as input to a statistical drift-diffusion simulator, where continuous doping is randomly discretized into individual dopant atoms (shown as circular inclusions as dopant 170), and hundreds of statistical instances of the nominal device are simulated to obtain a statistical dispersion of transistor performance.

[0028] As shown, the TCAD structure 100 is a shared design, which connects two memory node contacts 120a and 120b via a shared bit line contact 130, which in turn connects to corresponding memory capacitors (not shown). Two transfer transistors 110a and 110b are connected to the bit line contact 130 via a shared bit line post 140, wherein the first transfer transistor 110a is connected to the first memory node contact 120a via a first memory post 150a, and the second transfer transistor 110b is connected to the second memory node contact 120b via a second memory post 150b. Furthermore, gate contacts 160a and 160b are shown for the gate regions of the corresponding transfer transistors 110a and 110b, with gate oxide 165 between the gate contacts 160a and 160b and the transfer transistors 110a and 110b. Although illustrated as a shared design, this disclosure can be applied to single capacitor / transistor designs with various configurations and geometries of individual components (e.g., having a memory capacitor, memory post, and gate contact).

[0029] In each of pillars 140, 150a, and 150b, several dopants 170 are illustrated, and a lower concentration of dopants 170 is illustrated in the bulk of transfer transistors 110a and 110b. When structure 100 is simulated, the analysis system generates traps 190a-190c (generally or collectively referred to as traps 190) at random locations in regions of interest (such as the framed region 180 in the first storage pillar 150a). Trap 190 represents an undesirable defect or blemish in the associated base material that allows current to leak from the storage capacitor. Other regions of interest (e.g., in the bulk of the second storage pillar 150b, bit line pillar 140, or transfer transistors 110a and 110b) are possible. The definition of trap 190 specifies the density within the volume of silicon (trap / cm² in this example). 3 Or trap·cm -3 Furthermore, for a given volume, the average number of traps can be determined based on a known or chosen density value. In one embodiment, the distribution of the number of traps 190 conforms to a Poisson distribution, so the average number of traps 190 represents the average value of the Poisson distribution.

[0030] The number of traps 190 placed in the region of interest affects the refresh time of the transmission transistor 110a (or 110b), and the placement and effects of these traps 190 typically require significant computational resources to calculate, or need to be experimentally determined using physical experiments on a silicon prototype of the design. This disclosure provides improvements in the computational efficiency and speed of this simulation and offers the ability to avoid the need for experimentation on a physical prototype, thereby allowing users to quickly and accurately explore options in the design of the TCAD structure 100 by calculating the leakage current distribution, which can be extrapolated from a single trap to various user-defined trap densities in the region of interest.

[0031] Figure 2 This is a circuit diagram illustrating an integrated circuit model 200 (e.g., a SPICE model) of a DRAM cell according to an embodiment of the present disclosure. In the integrated circuit model 200, the components and connections between the memory pillar 150a and the bit line pillar 140 include: a bit line voltage supply 205, representing the applied bit line voltage (V). BL ); Bit line resistance 210, indicating the resistance (R) in the bit line. BL Bit line capacitance 215 indicates the capacitance between bit lines (C). BL ); and bit line contact resistance 220, representing the resistance (R) between contact 130 in bit line post 140 and the contact in storage capacitor. BL_Contact Bit line capacitor 215 is modeled as being connected between intermediate node 225 (located between bit line resistor 210 and bit line contact resistor 220) and ground 270. Bit line voltage source 205 is modeled as being connected between ground 270 and bit line resistor 210.

[0032] The first node 230 is represented in model 200 as a transmission transistor 235 used for measurement / simulation (e.g., ...). Figure 1 The input voltage (V) of one of the transfer transistors 110a and 110b in the transfer transistors Nl The input voltage is modeled using a controllable gate voltage supply 240, which is configured to apply a gate voltage (V) to the gate of the transfer transistor 235. Gate ). Represents the resistance (R) in the source / drain or storage pillar 150a. sc_Contact The source / drain contact resistance 245 is modeled between the source of the transfer transistor 235 and the second node 250. The second node 250 is represented in model 200 as the point of contact between the capacitor source 260 (V...). CAP The leakage current is applied to the storage capacitor 255 of the DRAM cell. When using the statistical compact model, from the perspective of... Figure 3The described method 300 involves randomly selecting a value of any leakage current (as a junction leakage parameter) from a statistically determined set of potential leakage currents. Each analyzed model 200 has unique parameters assigned according to the statistical set, meaning that each transistor can be analyzed using different leakage characteristics. (See also: Regarding...) Figure 7 and Figure 8 In more detail, the leakage characteristics are correlated with different trap densities, allowing for the analysis of several values ​​of the leakage current during simulation, and the probability of selecting a given value is related to... Figure 3 The described method 300 matches the probability distribution determined by the method.

[0033] Figure 3 This is a flowchart of a method 300 for optimizing a transmission transistor design according to various embodiments of the present disclosure. Method 300 can be performed via an iterative loop method or via a design of experiments (DoE) method. When method 300 uses the DoE method, method 300 begins at 310, where the analysis system performs multiple N process splits (one iteration for each process split) before performing N iterations from 320 to 370, and selects (either directly or via response surface-based interpolation) the result of the optimal split as the final output of method 300. When method 300 uses the iterative loop method, each iteration begins at 320, and the result of a given iteration is used to initiate a new iteration, restarting from 320 until an optimization criterion or a runtime threshold is reached to provide the final output of method 300.

[0034] At 320, the system performs a TCAD-based post-processing simulation / emulation of the leakage current in the nominal device. During the TCAD-based post-processing simulation, the system creates the TCAD design of the DRAM cell to be analyzed (such as...). Figure 1 As shown in the diagram, to determine the leakage current distribution of the design (in 330 and 340).

[0035] At 330, the system simulates X TCAD designs (e.g., such as...). Figure 1As shown in the figure, and performs X statistical simulations on these statistical designs, where each of the X simulations is characterized by a corresponding discrete random set of dopants in the source / drain regions of the transfer transistor. In various embodiments, the value of X is a user-configurable parameter, which is typically on the order of hundreds of simulations (e.g., X = 95, 100, 200, 107, etc.), but various simulations can use a variety of different numbers of simulations. In one embodiment, the analysis system performs these simulations using the principal drift-diffusion equation, but not using the composite formulas described above [1-3]. Each of these X simulations provides the corresponding leakage current of the transfer transistor. Note that the leakage current in the DRAM transfer transistor is small enough that omitting the composite formulas [1-3] during the initial X simulations does not significantly interfere with the solution of the principal drift-diffusion equation.

[0036] At 340, the system simulates the TCAD design to perform Y post-processing simulations on the X initial statistical simulations identified in 330. In various embodiments, the value of Y is a user-configurable parameter, typically on the order of thousands of simulations (e.g., Y = 950, 1000, 2000, 1007, etc.), but various simulations can use a variety of different numbers of simulations. For example, when the system performs one hundred simulations in 330 (e.g., X = 100) and the user selects to perform one thousand post-processing simulations on them (e.g., Y = 1000), the system performs one hundred thousand post-processing simulations in 340 (e.g., X*Y = 100000). Each of these Y post-processing simulations introduces a single discrete trap at a random location near the drain of the transfer transistor (where the drain of the transfer transistor is coupled to a capacitive storage node). The analysis system uses composite formulas [1-3] to determine the corresponding transfer transistor leakage current for each of these post-processing simulations.

[0037] 340 uses the output of each statistical simulation from the set of X to calculate Y leaks (via decoupled post-processing) according to formulas [1-3]. Because random traps and random dopants are treated as statistically independent entities here, the system is able to simulate Y random trap configurations for each statistically random doping configuration, where variation is provided only by the trap location for each of the X dopant levels. In various embodiments, to focus attention on the statistical tail of the leak distribution (e.g., the portion of the leak distribution above 5σ of the average), random traps are generated in a finite region of interest around the memory node contacts, such as... Figure 1 As schematically shown, the box indicates the region 180 where a random discrete trap 190 can be placed. Figure 4 The results of this process are presented in the document. Figure 4The complementary cumulative distribution of leakage current for 5,000,000 statistical configurations of a single random trap (where Y = 50,000 configurations) is shown in the presence of random discrete dopants (where X = 100 configurations).

[0038] Compared to previous methods, methods 330 and 340 offer a dual advantage in terms of not degrading convergence and simulation yield. Furthermore, methods 330 and 340 can be performed in a similar timeframe to previous methods because the post-processing evaluation time for the Y composite terms is negligible relative to the primary X simulations of the DRAM device. The relatively short evaluation time allows for the running of hundreds of statistical TCAD simulations (according to 330) characterized by discrete random dopants via a drift-diffusion simulator, and further allows for the addition of even more orders of magnitude of post-processing simulations characterized by discrete traps (according to 340). In this way, method 300 can be used to readily obtain a large statistical set for leakage currents, enabling the study of the tails of the statistical distribution, which is ultimately essential for the optimized design of DRAM devices with statistical variability.

[0039] At 360, the system generates a statistically compact model for use in circuit simulation. Compared to the standard compact model for circuit elements in simulation tools (which provides an average, nominal, or idealized set of response characteristics for the modeled element), the statistically compact model allows for variations in the set of response characteristics. This variation in the statistically compact model representing the transistor has response characteristics (including leakage current) that differ from the average / nominal / idealized set of response characteristics and match the simulation behavior profiles developed in 330 and 340.

[0040] According to various embodiments of this disclosure, method 300 discusses TCAD simulation only for the case of a single random trap. TCAD simulation enables physical insight and accuracy of results, but it is several orders of magnitude slower than integrated circuit simulation. Therefore, the goal is to obtain basic statistical components via TCAD simulation, and then perform the remaining procedures via compact modeling and integrated circuit simulation. In doing so, the system first obtains the statistical distribution of leakage current due to an arbitrary number of traps. The statistical distribution can be obtained via TCAD simulation, but according to this disclosure, the statistical distribution is obtained quickly and accurately via statistical methods by obtaining an accurate analytical description of the leakage distribution of a single trap.

[0041] To obtain the best fit to the statistical distribution while focusing on the minimal tail of leakage events, the system uses an automated algorithm to fit the leakage current of the transmission transistor calculated in 330 to a first curve / distribution 415. This automated algorithm selects the optimal distribution function and optimal parameters to provide the best fit. According to various embodiments, an automated process is used to select the optimal distribution function and optimal parameters of that distribution function to fit the data. Examples of possible distribution functions may include, but are not limited to: Beta, Cauchy, Exponential, Gamma, Gaussian, Generalized Pareto, Johnsons, Pareto, Poisson, Rice, Weibull, etc.

[0042] refer to Figure 4 This allows for a better understanding of curve fitting. Figure 4 The illustration shows a graph of TCAD results for leakage current in an advanced DRAM cell according to various embodiments of the present disclosure, the leakage current being caused by random discrete dopants and also by a single random trap in the presence of random discrete dopants. Figure 4 In the process, the first data point 410 (illustrated as a diamond-shaped data point) of the leakage current of the transmission transistor calculated in 330 is analyzed to fit the first curve 415. Figure 4 A first curve 415 is shown for fitting the first data point 410. The first curve 415 is obtained via a Rice distribution with parameters a = 0.608, b = -17.642, and c = 0.162. As will be understood, other embodiments may use different parameters and different distribution functions depending on the nature and value of the first data point 410. The set of first data points 420 is monotonically decreasing on the 1-CDF value (shown on the Y-axis), but may vary on the measured current (on the X-axis) due to statistical noise.

[0043] Furthermore, the system uses a combination of multiple distribution functions to fit the transmission transistor leakage current calculated in 340 to a second curve / distribution 425. In various embodiments, multiple distributions are used for better fitting due to the wide variation and diverse statistical behavior of the data. According to various embodiments, the system first identifies a threshold 450 in the complementary cumulative distribution of the data points, the threshold 450 defining the boundary between the “body” and the “tail” of the distribution.

[0044] Refer again Figure 4A second data point 420 (illustrated as a circular data point) of the leakage current from the transmission transistor 340 is analyzed to fit a second curve 425. A threshold 450 (which can be user-selectable or predefined) defines the boundary between the main region 430 and the tail region 440 of the distribution of the second data points 420 on the second curve 425. The main region 430 describes the total number of second data points 420 grouped above a threshold percentage, where the “main body” of the data (e.g., 99% of the data points) resides, while the tail region 440 describes the remaining data points. Similar to the set of first data points 410, the set of second data points 420 monotonically decreases on the 1-CDF value (shown on the Y-axis), but can vary on the measured current (on the X-axis) due to statistical noise.

[0045] In various embodiments, the analysis system can set various thresholds to distinguish between the main region 430 and the tail region 440 of complementary cumulative probabilities. Based on threshold 450, a second data point 420 located within the main region 430 is included in the “main” of the distribution, and a data point 420 located within the tail region 440 is included in the “tail” of the distribution. The system can use two different distribution patterns or statistical models to fit the second data point 420 to a second curve 425 in each of the main region 430 and the tail region 440.

[0046] For example, using the same procedure described above for the first data point 410, the second data point 420 in the "body" of the distribution is fitted to the second curve 425, while using the same procedure described above for the first data point 410 (but modified to use a complementary cumulative distribution as the target for fitting), the second data point 420 in the "tail" of the distribution is fitted to the distribution curve. Note that because high leakage conditions are important for more accurately representing the leakage current, additional effort is made to correctly fit the upper tail of the leakage distribution (i.e., the portion of the second curve 425 in the tail region 440). To achieve this, the system uses a complementary cumulative distribution for fitting, as this distribution emphasizes the upper tail.

[0047] In the example shown, the automated process found that the main region 430 of the second data point 420 was best fitted using a Johnson distribution with parameters a = -7.1, b = 1.59, c = -241.1, and d = 226.3, and the tail region 440 of the second data point 420 was best fitted using a Weibull distribution with parameters a = 0.91, b = -15.07, and c = 0.21. As will be understood, other embodiments may use different parameters and different distribution functions depending on the properties and values ​​of the second data point 420.

[0048] In various embodiments, the first curve 415 represents the baseline leakage current distribution of the design under test, while the second curve 425 represents the additional leakage current distribution caused by the presence of more than one trap 190 in the design. The system calculates a third distribution based on the baseline leakage current distribution and the additional leakage current distribution (e.g., a third distribution) to represent the drain leakage induced by a single trap, which is used to extrapolate leakage current for various trap densities in the transmission transistor in a statistically compact model.

[0049] At 360°, the system generates a statistically compact model to represent the combination of the baseline leakage current distribution and the additional leakage current distribution. In various embodiments, the system adds a first curve 415 to a second curve 425 to produce a distribution of leakage induced by a single trap. The system identifies or creates a relationship between the distribution of leakage induced by a single trap and a parameter in the static compact model (which nominally represents the average leakage current), which is related to... Figure 7 Method 700 and Figure 8 The diagrams are described in more detail. This disclosure provides for generating leakage current values, not model parameters.

[0050] At 370, the system uses a statistically compact model generated at 360 to simulate statistical circuits, such as those simulated via integrated circuits. Engineers can then quickly evaluate the performance of the DRAM cell circuitry and apply modifications to the physical design to explore different physical designs of the DRAM cell circuitry for use in larger design layouts, without having to develop and test prototypes on silicon.

[0051] Figure 5A These are waveform diagrams according to various embodiments of the present disclosure, illustrating the waveform excitation (voltage) applied to the DRAM cell circuitry during a write operation. For one time period, the gate voltage 510 (V) Gate A bit line voltage of 520 (V) is applied to the gate of the transmission transistor 235. BL A bit line input is applied to generate an input voltage of 530 (V). N1 ) and the storage voltage 540V in the DRAM cell N2 ).

[0052] Figure 5B These are waveform diagrams according to various embodiments of the present disclosure, illustrating the voltage of a DRAM cell circuit in a constant state during the hold period. As will be understood, during the hold period, the gate voltage 510 (V) Gate The gate is removed or otherwise set below the gate threshold to turn the transfer transistor 235 off. Because the transfer transistor 235 is off during the hold period, the bit line voltage 520 (V) BL ) and input voltage 530 (VN1 The precise value is fixed to the pre-charge voltage, without affecting the storage voltage of 540V. N2 Storage voltage 540V N2 This is also known as the capacitor voltage of the storage capacitor. However, due to transistor leakage current, the storage voltage is 540 (V). N2 The leakage current decreases over time during the holding period. Integrated circuit simulation was performed on all leakage currents determined by 320 to determine the storage voltage 540 (V). N2 How does the leakage current at a specified trap density decrease over time?

[0053] Figure 6 This is a graph illustrating statistical circuit simulation results of memory node voltage distribution for a given refresh time in three different trap density scenarios, according to various embodiments of this disclosure. More specifically, Figure 6 The figure illustrates curves 610a-610c, which represent different trap densities (e.g., 1x10⁻⁶, respectively). 16 Trap / cm 3 1x10 17 Trap / cm 3 and 1x10 18 Trap / cm 3 ), capacitor node voltage V CAP Simulated voltage drop after a holding time of 20 ms.

[0054] Curves 610a-610c show the log-normal dependence of refresh time on leakage current, and Figure 6 The results are used to determine whether a TCAD transistor design is acceptable (e.g., meets a refresh time threshold or other threshold) or should be modified. An operator (e.g., a user or system) can set various values ​​for the refresh time threshold, for which the transistor design is modified (or marked as acceptable) when the refresh time (i.e., the time it takes for bits stored in memory to remain readable without being read back into memory) does not meet the specified threshold. For example, an operator can take various actions to modify the underlying design to improve refresh time, including changing: the concentration or type of dopant used, the transistor size, the gate material used to build the transistor, the transistor geometry, the transistor bias, the layout of circuit elements including the transistor, etc.

[0055] Figure 7 Various embodiments of this disclosure are used to perform TCAD to circuit transformation (such as in relation to...) Figure 3The flowchart of method 700 (discussed in method 300, 360) is shown. In various embodiments, the analysis system responds to receiving a leakage distribution induced by a single trap (e.g., as an output from method 300, 340, and is shown as...). Figure 4 The curve 425 in the figure is used to execute method 700 to generate a statistical leakage compact SPICE model for use in SPICE simulation to calculate the statistical leakage current (e.g., as input to method 370 of method 300).

[0056] At 710, the analysis system receives the analysis distribution fit and the trap density. The analysis distribution fit is a single-trap leakage current distribution generated according to method 300, which includes both the baseline leakage current distribution (415) and the induced leakage current distribution (425). In various embodiments, the trap density can be any value selected for analysis or a user-defined value. The trap density is used as a multiplier to increase the average number of traps in previously performed single-trap simulations and to match the single-trap-induced leakage current distribution to the specified trap density.

[0057] At 720, the analysis system generates a statistical leakage current based on the leakage current distribution induced by a single trap for a given trap density. To analyze the transmission transistor for a given trap density, a statistical simulation is performed. However, two levels of randomization may exist: the actual number of traps 190 (calculated by trap density * silicon volume = average number of traps, which is still treated as a distribution rather than a discrete value by the processing system), and the leakage current from a single trap (as described by the leakage current distribution induced by a single trap). Therefore, for a given trap density, the leakage current distribution induced by a single trap can be used to generate multiple different currents (e.g., such as...). Figure 8 (As shown in the diagram). For each trap density, and for each circuit instance, the analysis system generates the actual number of traps and the random leakage current for each trap described therein, based on a single trap current distribution (second curve 425). The total trap current is added to the baseline leakage current distribution (first curve 415) to give the random leakage current for that instance of the cell.

[0058] Figure 8 The diagrams are based on various embodiments of the present disclosure, illustrating statistical generation from a compact model for several trap density distributions (i.e., Figure 7 The leakage current distribution curves 810a-810e obtained from the 720 output are compared with those obtained from TCAD simulation. More specifically, Figure 8 This demonstrates the use of arbitrary trap density or user-defined trap density (e.g., 1x10). 16 Trap / cm 3 5x10 16Trap / cm 3 1x10 17 Trap / cm 3 5x10 17 Trap / cm 3 and 1x10 18 Trap / cm 3 The leakage current distribution curves 810a-810e were obtained from the statistical generation of the compact model. Therefore, Figure 8 This indicates that the compact model simulation accurately reproduces the leakage current distribution generated from the TCAD simulation.

[0059] In various embodiments, the system obtains a third, plurality of leakage currents on leakage current distribution curves (e.g., 810a-810e) by manipulating two statistically selected variables to influence the current fitted to a statistically distributed distribution. Based on the baseline leakage current distribution (e.g., curve 415), the value of a first variable to influence the leakage current observed in the statistically compact model is randomly selected. Based on an additional leakage current distribution (e.g., curve 425), the value of a second variable to influence the leakage current observed in the statistically compact model is randomly selected. In various embodiments, the final operation is repeated N times, where N is the number of traps (190) in the transistor (e.g., based on a specified trap density and transistor volume). The N random values ​​of the leakage current are summed to obtain the total leakage current.

[0060] return Figure 7 At 730, the analysis system transforms the statistical leakage current distribution (generated from 720) into integrated circuit model parameters. For example, the statistical leakage current curves are converted from a first description language generated in a TCAD application to a second description language used in an integrated circuit simulator (e.g., SPICE). The statistical range of the leakage current distribution allows the integrated circuit model to act as a statistically compact model, rather than a statically compact model with only one value for each parameter.

[0061] At 740, the analysis system uses a statistical compact model to perform integrated circuit simulation, which employs integrated circuit model parameters based on a statistical leakage current distribution. Note that after extracting the baseline static compact model (i.e., the basic characteristics of the DRAM cells, excluding trap-based leakage effects), a very large number of statistical compact models can be obtained for any number of traps. Therefore, the leakage current is randomized based on a trap leakage distribution fit. Each random leakage current sample is considered an updated compact model (which is actually the baseline static compact model plus the randomized leakage value). The parameters in the statistical compact model allow it to produce different leakage currents, where the associated probability of occurrence corresponds to the range of leakage currents described by the statistical leakage current distribution.

[0062] At 750, the analysis system generates a statistical leakage current in the SPICE circuit simulation. This statistical leakage current is provided to the user for evaluating the current design of the DRAM cell. In some embodiments, the statistical leakage current is used to evaluate the refresh time, such that when the refresh time falls below a threshold (e.g., when the statistical leakage current exceeds a threshold), the user is prompted to select new parameters or a new set of parameters for the DRAM cell design. Using a statistically compact model, the user can select new parameters for re-evaluation and can quickly re-evaluate the DRAM cell using these new parameters.

[0063] Figure 9 The illustration depicts an example set of processes 900 used during the design, verification, and manufacturing of articles such as integrated circuits to transform and verify design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These processes begin with the creation of a product concept 910 using information provided by a designer, which is then transformed to create an article of art using a set of EDA processes 912. Upon completion of the design, it is tape-out 934, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing plant to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are fabricated 936, and packaging and assembly processes 938 are performed to produce the finished integrated circuit 940.

[0064] The specifications of circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Using hardware description languages ​​(“HDLs”) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera, circuits and systems can be designed using high-level representations. HDL descriptions can be translated into logic-level register-transfer-level (“RTL”) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of representation (i.e., a more detailed description) adds more useful details to the design description, such as more details about the modules included in that description. Higher levels of detail (i.e., more representative descriptions) can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify lower levels of representation language for more detailed descriptions is SPICE, used for detailed descriptions of circuits with many analog components. Descriptions at each representation level are enabled for use by the corresponding tools at that layer (e.g., formal verification tools). The design process can use… Figure 9 The sequence described herein. The described process is enabled by an EDA product (or tool).

[0065] During the system design phase 914, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0066] During logic design and functional verification (916), modules or components in a circuit are specified in one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components, referred to as a “simulator” or “prototype system,” is used to accelerate functional verification.

[0067] During synthesis and design (918) for testing, HDL code is converted into a netlist. In some embodiments, the netlist can be a graphical structure, where edges of the graphical structure represent components of the circuit, and nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are layered products of manufacturing, which can be used by EDA products to verify whether the integrated circuit performs according to a specified design when it is manufactured. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the specifications.

[0068] During netlist verification (920), the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning (922), the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0069] During layout or physical implementation 924, physical placement (placement of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) are performed, and cells can be selected from a library to enable specific logic functions. As used herein, the term "cell" can specify a collection of transistors, other components, and interconnects that provides Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled for both physical structure and simulation. Parameters such as size are specified for the selected cells (based on "standard cells") and made accessible in a database for use in EDA products.

[0070] During the analysis and extraction phase 926, circuit functionality is verified at the layout level, which allows for improvements to the layout design. During physical verification 928, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, and lithographic constraints) are correct and that the circuit functionality matches the HDL design specifications. During resolution enhancement 930, the layout geometry is transformed to improve how the circuit design is manufactured.

[0071] During the tape-out process, data is created for use (if appropriate, after applying lithographic enhancement) in the production of a photomask. During mask data preparation 932, the "tape-out" data is used to generate a photomask for the production of the finished integrated circuit.

[0072] The storage subsystem of a computer system (such as computer system 500 in Figure 5) may be used to store programs or data structures used by some or all of the EDA products described herein, and by products used for developing libraries as well as products used for physical and logical designs that use the libraries.

[0073] Figure 10 An example machine of computer system 1000 is illustrated, in which a set of instructions can be executed to cause the machine to perform any or one of the methods discussed herein. In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client computer in a cloud computing infrastructure or environment.

[0074] A machine can be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, web device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or other instructions) specifying the actions to be performed by that machine. Furthermore, while a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that, individually or collectively, execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0075] Example computer system 1000 includes processing device 1002, main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), static memory 1006 (e.g., flash memory, static random access memory (SRAM) etc.) and data storage device 1018, which communicate with each other via bus 1030.

[0076] Processing device 1002 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1002 may be configured to execute instructions 1026 to perform the operations and steps described herein.

[0077] The computer system 1000 may further include a network interface device 1008 for communication via a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a video processing unit 1028, and an audio processing unit 1032.

[0078] Data storage device 1018 may include machine-readable storage medium 1024 (also referred to as non-transitory computer-readable medium) storing one or more instruction sets 1026 or software embodying any or more methods or functions described or functionally described herein. During execution of the instructions 1026 by computer system 1000, the instructions 1026 may also reside wholly or at least partially in main memory 1004 and / or in processing device 1002, which also constitute machine-readable storage media.

[0079] In some embodiments, instruction 1026 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 1024 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) for storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine and processing device 1002 to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0080] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that lead to a desired result. These operations are operations that require physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0081] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise expressly indicated in this disclosure, it should be understood that throughout this description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities within the registers of the computer system into other data, which are similarly represented as physical quantities within the computer system's memory or registers or other such information storage devices.

[0082] This disclosure also relates to means for performing the operations described herein. Such means may be specifically configured for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithm and display presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program based on the teachings herein, or it may be proven easy to construct more specialized devices to execute the method. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0084] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0085] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements may be labeled with the same reference numerals. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A system for evaluation, comprising: processor; as well as The memory includes instructions that, when executed by the processor, perform operations including: By simulating different dopant configurations in transistors, the first plurality of transistor leakage currents are generated; By simulating a single trap insertion in the transistor for each of the different dopant configurations, a second plurality of transistor leakage currents are generated. Fit the leakage current of the first plurality of transistors to the first leakage current distribution; Fit the leakage current of the second plurality of transistors to the second leakage current distribution; Based on the first leakage current distribution and the second leakage current distribution, a third plurality of leakage currents are generated for a specified trap density for the transistor; The third plurality of leakage currents are converted into model parameters for a DRAM cell including the transistors; and Based on the model parameters, the DRAM cell including the transistor is evaluated.

2. The system of claim 1, wherein the DRAM cell is modeled as a statistically compact model, and the third plurality of leakage currents are statistically obtained from a combination of the first leakage current distribution and the second leakage current distribution and the specified trap density.

3. The system of claim 1, wherein the traps are randomly distributed in the transistor according to the specified trap density.

4. The system of claim 1, wherein the first plurality of transistor leakage currents are generated using a master drift-diffusion equation instead of a composite equation, and wherein each of the second plurality of transistor leakage currents is generated using the composite equation.

5. The system of claim 1, wherein the first leakage current distribution is fitted to the leakage current of the first plurality of transistors using a single statistical model, and wherein the second leakage current distribution is fitted to the leakage current of the second plurality of transistors using two statistical models, wherein the main region of the second leakage current distribution is fitted to the leakage current of the second plurality of transistors using the first statistical model, and the tail region of the second leakage current distribution is fitted to the leakage current of the second plurality of transistors using the second statistical model, wherein the main region represents the total number of leakage currents of the second plurality of transistors that are above a threshold percentage.

6. The system of claim 1, wherein the specified trap density represents the Poisson distribution of defects in the source or drain region of the transistor.

7. A method for evaluation, comprising: By simulating different dopant configurations in transistors, the first plurality of transistor leakage currents are generated; By simulating a single trap insertion in the transistor for each of the different dopant configurations, a second plurality of transistor leakage currents are generated. Fit the leakage current of the first plurality of transistors to the first leakage current distribution; Fit the leakage current of the second plurality of transistors to the second leakage current distribution; The first leakage current distribution and the second leakage current distribution are combined to generate a third leakage current distribution; Based on the first leakage current distribution and the second leakage current distribution and a specified trap density for the transistor, a third plurality of statistically generated leakage currents are generated for the specified trap density; The third plurality of statistically generated leakage currents are mapped to model parameter values ​​for circuit simulation of DRAM cells including the transistors; as well as The DRAM cell, including the transistor, is evaluated based on the model parameter values.

8. The method of claim 7, wherein the DRAM cell is modeled as a statistically compact model, and the third plurality of statistically generated leakage currents are obtained from the combination of the first leakage current distribution and the second leakage current distribution and the specified trap density.

9. The method of claim 7, wherein the traps are randomly distributed in the transistor according to the specified trap density.

10. The method of claim 7, wherein the first plurality of transistor leakage currents are generated using a master drift-diffusion equation instead of a composite equation, and wherein each of the second plurality of transistor leakage currents is generated using the composite equation.

11. The method of claim 7, wherein combining the first leakage current distribution and the second leakage current distribution to generate a third leakage current distribution for the specified trap density further comprises: The statistically distributed third type of statistically generated leakage current is obtained by summing the following terms: A first variable, the first variable having a first value statistically selected based on the first leakage current distribution; and N additional variables, each having independent values ​​randomly sampled from the second leakage current distribution, where N is the number of traps simulated in the transistor.

12. The method of claim 7, wherein the first leakage current distribution is fitted to the leakage current of the first plurality of transistors using a single statistical model, and wherein the second leakage current distribution is fitted to the leakage current of the second plurality of transistors using two statistical models, wherein the main region of the second leakage current distribution is fitted to the leakage current of the second plurality of transistors using a first statistical model, and the tail region of the second leakage current distribution is fitted to the leakage current of the second plurality of transistors using a second statistical model, wherein the main region represents the total number of leakage currents of the second plurality of transistors that are above a threshold percentage.

13. The method of claim 12, wherein the second statistical model implements a complementary cumulative distribution.

14. The method of claim 7, wherein the specified trap density represents the Poisson distribution of defects in the source or drain region of the transistor.

15. A non-transitory computer-readable storage medium, comprising instructions that, when executed by a processor, perform operations including: The statistical compact model of a DRAM cell with a first trap density is evaluated to determine whether the refresh time simulated for the transfer transistors included in the DRAM cell meets the threshold. In response to determining that the refresh time does not meet the threshold: Different second trap densities are selected for the DRAM cells; The statistical compact model of the DRAM cell with the second trap density is re-evaluated to determine whether the refresh time simulated for the transmission transistors included in the DRAM cell meets the threshold. In response to the refresh time meeting the threshold, it is indicated that the DRAM cell is acceptable; in: The statistical compact model is generated via a first plurality of statistical simulations of the DRAM cell and a second plurality of statistical simulations of the DRAM cell. The first plurality of statistical simulations produce a first leakage current distribution representing a baseline leakage current, and the second plurality of statistical simulations produce a second leakage current distribution representing an additional leakage current distribution. The first and second leakage current distributions are combined to create a third leakage current distribution representing induced drain leakage in the DRAM cell. The third leakage current distribution is extrapolated based on a specified trap density to describe the statistical leakage current of the DRAM cell at the specified trap density.

16. The non-transitory computer-readable storage medium of claim 15, wherein the first plurality of statistical simulations are performed using a master drift-diffusion equation instead of a composite equation.

17. The non-transitory computer-readable storage medium of claim 15, wherein each of the second plurality of statistical simulations is performed using a compound equation.

18. The non-transitory computer-readable storage medium of claim 15, wherein the second plurality of statistical simulations is performed based on each of the first plurality of statistical simulations.

19. The non-transitory computer-readable storage medium of claim 15, wherein the first plurality of statistical simulations generate a first transmission transistor leakage current, the first transmission transistor leakage current being fitted to the first leakage current distribution using a single statistical model, and wherein the second plurality of statistical simulations generate a second transmission transistor leakage current, the second transmission transistor leakage current being fitted to the second leakage current distribution using two statistical models, wherein a main region of the second transmission transistor leakage current is fitted to the second leakage current distribution using a first statistical model, and a tail region of the second transmission transistor leakage current is fitted to the second leakage current distribution using a second statistical model, wherein the main region represents the total number of second transmission transistor leakage currents exceeding a threshold percentage.

20. The non-transitory computer-readable storage medium of claim 15, wherein the first plurality of statistical simulations are performed using a master drift-diffusion equation instead of a composite equation, and wherein each of the second plurality of statistical simulations is performed using a composite equation.

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