Vertical fin field effect transistors, vertical fin field effect transistor arrangements, and methods for forming vertical fin field effect transistors

Abstract

A vertical-fin field-effect transistor (100) is provided. The vertical-fin field-effect transistor has: a semiconductor fin (14); an n-doped source region (30); an n-doped drift region (10); an n-doped channel region vertically disposed in the semiconductor fin (14) between the source region (30) and the drift region (10); at least one gate region (24) horizontally adjacent to the channel region; a gate dielectric (32) electrically insulating the gate region (24) from the channel region, wherein the interface between the gate dielectric (32) and the channel region has a negative interface charge; p A doped gate shielding region is arranged below the gate region (24) such that, in a vertical projection, the gate shielding region lies within an area bounded by the gate dielectric (32); a source contact (28) is electrically connected to the source region (30); and a conductive region (18, 20) is located between the gate region (24) and the n-doped gate shielding region; wherein the p-doped gate shielding region is electrically connected to the source contact (28) via the conductive region (18, 20).

Description

Technical Field

[0001] The present invention relates to a vertical fin field-effect transistor (FinFET), a vertical fin field-effect transistor arrangement, and a method for forming a vertical fin field-effect transistor. Background Technology

[0002] For applications of wide-bandgap semiconductors (such as SiC or GaN) in power electronics, power MOSFETs with vertical channel regions are typically used. Here, the channel region is formed adjacent to the trench, making this type of MOSFET also known as a trench MOSFET (TMOSFET). By appropriately selecting the geometry and doping concentration of the epitaxial region, channel region, and shielding region, relatively low on-resistance and relatively high breakdown voltage can be achieved.

[0003] According to existing technology, power trench MOSFETs have a deep p+ injection as a shielding region and trenches, which are periodically alternated to form a cell field composed of multiple individual MOSFETs, also referred to as a cell. The ratio of trenches, p+ shielding regions, and channel regions formed therein, which are switchable by means of an insulated gate, is determined by the following requirements: achieving the lowest possible on-resistance, the lowest possible maximum field load on the gate dielectric, the lowest possible saturation current under short-circuit conditions, and the highest possible breakdown voltage. The pitch between similar structures of adjacent MOSFETs is limited by the technical possibilities of forming trenches, contacting different regions, and achieving p+ injection.

[0004] The channel resistance of a TMOSFET is determined by the charge carrier distribution and mobility within the channel. These two parameters are determined either by the interface charge at the interface between the semiconductor material in the channel region and the gate dielectric, or by the charge in the gate dielectric and by channel doping. The cell pitch is determined by the p+ shielding region, because the fabrication of the p+ shielding region requires high-energy injection, which in turn requires a sufficiently thick mask. The thickness of this mask limits the minimum size that can be opened, and through it, limits the cell pitch. Summary of the Invention

[0005] In various embodiments, a vertical fin field-effect transistor (vertical FinFET, abbreviated as FinFET; in the case of FinFET, the switchable component consists of narrow semiconductor fins) is provided, having trench contacts for a shielding structure. Intuitively, in the case of a vertical fin field-effect transistor, the shielding structure is disposed directly below the trench and electrically connected to conductive contacts formed in the trench.

[0006] Through its geometry and by appropriately selecting the material and manufacturing process of the gate dielectric, exceptionally low channel resistance can be achieved.

[0007] Extremely small unit pitch can be achieved through the grooved contact shielding structure.

[0008] FinFETs can be used, for example, as power FinFETs. Therefore, in different embodiments, the on-resistance of a power FinFET with trench contacts can be significantly lower than that of a silicon carbide (SiC) or gallium nitride (GaN) based MOSFET or MISFET according to the prior art. This results in lower losses throughout the device's operation.

[0009] In various embodiments, a power FinFET with trench contacts having a shielding structure is provided. The dimensions, doping, and interface charge on the gate dielectric (e.g., gate oxide) can be configured (as explained in more detail below) to achieve low on-resistance, high breakdown voltage, low short-circuit current, and low maximum field load on the gate dielectric.

[0010] Furthermore, a method for forming such a FinFET is provided, wherein the relative positioning of the trench and the shielding structure is self-aligned. This means that high relative positioning accuracy can be achieved with simple manufacturing processes. Attached Figure Description

[0011] Extensions to these aspects are set forth in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and explained in more detail in the following description. The drawings show:

[0012] Figure 1 A schematic cross-sectional view of a vertical FinFET according to different embodiments is shown;

[0013] Figure 2A A graph showing the relationship between the threshold voltage in a FinFET and the channel doping concentration and interface charge;

[0014] Figure 2BA graph showing the relationship between the on-resistance of a FinFET and the channel doping concentration and interface charge;

[0015] Figure 3A The relationship between the current density and cumulative current density in FinFET and the spacing to the SiC / oxide interface is shown.

[0016] Figure 3B The relationship between current density and cumulative current density in a FinFET according to different embodiments and the spacing to the SiC / oxide interface is shown.

[0017] Figure 3C The relationship between electron mobility, electron density, and conductivity in FinFET and the spacing to the SiC / oxide interface is shown.

[0018] Figure 3D The relationship between electron mobility, electron density, and conductivity in FinFETs according to different embodiments and the spacing to the SiC / oxide interface is shown.

[0019] Figures 4A to 4S Schematic illustrations of methods for forming a vertical FinFET according to different embodiments are shown;

[0020] Figure 5 Schematic perspective front and rear views of a FinFET according to different embodiments are shown;

[0021] Figure 6 A flowchart illustrating a method for forming a vertical FinFET according to different embodiments is shown. Detailed Implementation

[0022] Figure 1 The diagram shows a schematic cross-sectional view of a vertical FinFET 100 according to different embodiments.

[0023] The vertical fin field-effect transistor 100 may have an n-doped semiconductor fin 14 (hereinafter referred to as a fin) that extends vertically between the n-doped source region 30 of the FinFET (above or in the upper part of the fin 14) and the n-doped drift regions 10, 12 (below the fin 14). The drift regions 10, 12 may have an n-doped drift region 10 and an n-doped diffusion region (propagation region) 12. In various embodiments, the doping concentration in the propagation region 12 may be higher than the doping concentration in the drift region 10 disposed below it, and higher than the doping concentration in the n-channel region disposed above it in the semiconductor fin 14. In one embodiment, for example, the doping may be 10 in the drift region 10. 16 cm -3 In transmission zone 12, the number is 10. 17 cm -3And in the channel region of fin 14, it is 4.10 16 cm -3 The n-doped semiconductor material of drift regions 10, 12 and fin 14 can be provided / provided as an epitaxial growth material, for example, grown on a substrate, and may have a buffer layer disposed between drift regions 10, 12 and the substrate. Drain contacts may be disposed on the back side of the substrate. The substrate, drain contacts and possible buffer layers can be fabricated in known or substantially known manners.

[0024] The vertical fin field-effect transistor 100 may also have at least one gate region 24 horizontally adjacent to the channel region. (From...) Figure 1 In one embodiment, two gate regions 24 are formed horizontally adjacent to the fin 14. These two gate regions are electrically insulated from the fin 14 by a gate dielectric 32 and from the source contact 28 disposed above it by an additional dielectric 26. The gate regions 24 may be made of a conductive material, such as polysilicon. In different embodiments, an additional dielectric 26 may be formed on the surface of the gate region by re-oxidation as an insulating portion from the source contact 28.

[0025] Negative interface charge may exist at the interface between the gate dielectric 32 and the channel region 14 or in the gate dielectric 32 itself.

[0026] Figure 2A and 2B as well as Figures 3A to 3D The characteristics of a FinFET with this configuration 100 are shown in the figure.

[0027] exist Figure 2A In Figure 200, the relationship between the threshold voltage Vt in a FinFET and the channel doping concentration and interface charge is shown. Figure 2B The graph 202 shows the relationship between the on-resistance of a FinFET and the channel doping concentration and interface charge. Figure 3A The diagram shows the relationship between the current density (top) and cumulative current density (bottom) in a FinFET and the spacing to the SiC / oxide interface for the case of p-channel doping and positive interface charge (quadrant I in Figure 2) (as this channel is used in TMOSFETs according to the prior art). Figure 3B The diagram shows the relationship between the current density and cumulative current density in the FinFET and the spacing to the SiC / oxide interface, for the case of n-channel doping and negative interface charge (quadrant III in Figure 2), according to different embodiments. Figure 3C Showing with Figure 3A The relationship between the corresponding electron mobility, electron density, and conductivity and the spacing to the SiC / oxide interface; and Figure 3D Showing with Figure 3BThe relationship between the corresponding electron mobility, electron density, and conductivity and the spacing to the SiC / oxide interface.

[0028] When from p-doped inversion channel (as described in the prior art) Figure 2A and Figure 2B The middle section is shown on the right and in Figure 3A and Figure 3C As shown in the diagram, it transforms into an n-doped cumulative channel (Akkumulationskanal) (the n-doped cumulative channel in...). Figure 2A and Figure 2B The middle section is shown on the left and in the middle. Figure 3B and Figure 3D When (as shown in the figure), the channel resistance can be significantly reduced.

[0029] exist Figure 2B In the diagram, the parameter field of channel doping and interface charge for a FinFET with a fin width of 300 nm and a cell pitch of 800 nm symbolically represents the on-resistance, i.e., the FinFET in the on-state. If silicon dioxide tempered in a nitride atmosphere is used as the gate oxide (as in the prior art), an inversion channel with a positive interface charge is formed. This corresponds to... Figure 2A and Figure 2B Circle 36 in the upper right quadrant of the first quadrant. If instead of forming an accumulated channel with a positive interface charge (circle 34 in the upper left fourth quadrant), the on-resistance is reduced by approximately half. However, FinFETs with n-channel doping and a positive interface charge have a threshold voltage <0V, as... Figure 2A As can be seen in the upper left of the fourth quadrant. This relates to the following: positive interface charge shifts the threshold voltage to a smaller value. A channel semiconductor material / gate dielectric interface with negative interface charge can be created by selecting the gate dielectric or gate dielectric stack, or by using appropriate pre-processing or post-processing methods, or negative charge can be built into the gate dielectric.

[0030] This can lead to the following combinations of determineable interface charge and channel doping: these combinations not only provide a suitable positive threshold voltage (e.g., 3V), Figure 2B (The black line in the middle) and provides a lower on-resistance than FinFETs with a SiC / gate dielectric interface according to the prior art. For example, these combinations can be found not only for inversion (second quadrant) but also for accumulation (third quadrant) in the second and third quadrants, for example along the black line in the second or third quadrant.

[0031] In particular, FinFETs that should be assigned to the third quadrant (e.g., those with parameters marked there by two asterisks 38) have the aforementioned advantages. In the FinFET 100 according to different embodiments, the interface charge and channel doping concentration can be selected based on simulation results shown in the third quadrant, taking into account the desired threshold voltage, for example, 3V along the black line.

[0032] In different embodiments, a hot oxide wet-oxidized at 1150°C (which may be post-treated by NO tempering at 1150°C) or a gate dielectric stack consisting of SiO2 and Si3N4 or SiO2 and Al2O3 can be used as gate dielectric 32.

[0033] As mentioned above, one reason for the reduced on-resistance is the charge carrier distribution and mobility in the channel. This is based on a comparison of an inversion channel with a threshold voltage of 3V in the cross-section of fin 14 ( Figure 3A , Figure 3C ) and cumulative channels ( Figure 3B , Figure 3D The current density becomes intuitive.

[0034] In the reverse channel ( Figure 3A , Figure 3C The current density in the accumulation channel is carried only within the first 5-10 nm to the SiC / gate oxide interface, i.e., only there is it significant, while in the accumulation channel... Figure 3B , Figure 3D The current distribution in fin 14 penetrates deeper into the fin. There, as in... Figure 3C and 3D As can be seen in the lower center, the conductivity is significantly higher. This results in higher conductivity in the channel, which extends almost the entire width wC of the fin (see...). Figure 1 ).

[0035] The vertical fin field-effect transistor 100 may also have a p-doped gate shielding region 16, which is arranged below the gate region 24 such that, in the case of vertical projection, the gate shielding region 16 is at least partially, for example, mostly, almost completely, or completely (e.g., at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95% of its projected area) within the area bounded by the gate dielectric 32. The gate shielding region 16 can be used to shield the gate dielectric 32 at the bottom of the trench from the effects of excessive electric fields.

[0036] The source contact 28 can be electrically connected to the source region 30, and conductive regions 18 and 20 can be arranged between the gate region 24 and the p-doped gate shield region 16, wherein the p-doped gate shield region 16 can be electrically connected to the source contact 28 via the conductive regions 18 and 20.

[0037] The second parameter that can affect the channel resistance is the cell pitch (pitch) P, where a smaller pitch P reduces the channel resistance.

[0038] According to existing techniques, the shielding region is typically achieved through deep p-implantation. This type of implantation requires a relatively thick oxide mask (e.g., about 1.5 μm), which limits the minimum achievable opening and thus the pitch P.

[0039] In various embodiments, a method for manufacturing a FinFET 100 having a reduced cell pitch P is provided. This method provides a shielding structure in which, instead of performing a photolithography process to limit the cell pitch between two trenches, a gate shielding region 16 is constructed below the trenches.

[0040] In different embodiments, the same mask can be used for trench formation and for shielding implantation. This means that the trench is formed first, and then implantation (p-doping) is performed into the trench. Therefore, a gate shielding region 16 can be formed below the trench.

[0041] This means that, according to different embodiments, the gate shielding region 16 can be formed in a self-adjusting manner by means of a simple method, so that the bottom of the fin 14 and the corner of the trench are protected.

[0042] During the doping process used to form the gate shielding region 16, a p-doped layer may also be formed in the trench sidewalls. In different embodiments, this p-doped layer may be oxidized away in a subsequent fin formation process, so that no p-doping is retained in the actual fin 14. Alternatively, a narrow (e.g., tens of nm thick) p-doped region may be retained on the edge of the fin 14.

[0043] The area ratio of the p-doped gate shielding region 16 to the n-doped propagation region 12, their doping concentrations and geometric arrangements, and the thickness (depth) of the gate shielding region 16 can be determined by a trade-off between shielding (maximum field in the gate dielectric 32, sufficiently small short-circuit current, and sufficiently high breakdown voltage) and conductivity (at low on-resistance). In particular, in one embodiment, the propagation region 12 can have multiple different doping concentrations, for example, 2.10 below and around the lower region of the shielding region 16. 17 cm -3 And between the shielding area below fin 14 and 5.10 17 cm -3 This is in Figure 1The optional second propagation region 12a is marked in the middle, for example, extending to the dashed line. This can help find a suitable trade-off between low on-resistance (high doping between shielding regions) and high breakdown voltage (low doping below the shielding region).

[0044] Furthermore, in one embodiment, the propagation region 12 may extend into the lower region of the fin 14, particularly into the region adjacent to the conductive regions 18, 20 of the contact gate shielding region 16. Due to the higher doping in this region, it is also conductive when the gate is turned off, and therefore does not necessarily need to be connected by the electric field of the gate 24.

[0045] In various embodiments, the p-doped gate shielding region 16 can be directly connected to the source potential (source contact 28) via contacts—conductive regions 18, 20—at the bottom of the trench. In various embodiments, conductive regions 18, 20 can have a contact layer 18 (e.g., nickel silicide). The contact layer 18, or more generally, the conductive regions 18, 20, can be connected to the source metal via a conductive material (e.g., doped or in-situ doped polysilicon). In various embodiments, conductive regions 18, 20 can be electrically insulated from the gate region 24 via a dielectric layer 22. In various embodiments, the dielectric layer 22 can be an oxide layer, which can be formed or be formed, for example, by means of thermal oxidation of the conductive regions 20, for example, in the case where the conductive regions 20 have polysilicon. In various embodiments, the connection to the source metal (not shown) can be implemented at the end of the cell field via so-called supercell leads, similar to known methods in gate connections.

[0046] In different embodiments, it may be advantageous to keep the lead-out of the connection from the gate shield region 16 to the source contact 28 as short as possible to reduce resistance. This has the advantages of reducing Joule heating and keeping the charging and discharging time constants of the shield region small. Both improve the performance efficiency of the component. The latter is particularly advantageous for rapid component switching.

[0047] Furthermore, the current path from the source contact 28 through the conductive region 20, the shielding region 16, to the drift region 10 represents a diode, which must carry current during diode operation. Therefore, for the normal operation of this so-called body diode, the low resistance caused by the short leads connected through the shielding region can also be helpful.

[0048] In different embodiments, the conductive regions 18, 20 may be formed entirely of metal (e.g., copper or a copper alloy). In this case, the metal layers 18, 20 and the gate region 24 can be separated from each other by a dielectric 22 deposited (e.g., at low temperatures). The metal layers 18, 20 may be deposited, for example, either according to or by reference to a known damascene process. The FinFET 100 with conductive regions 18, 20 can have improved robustness to high current densities.

[0049] In order to achieve better shielding at high drain voltages and, in particular, higher resistance, and thus lower short-circuit current, Figure 5 The vertical Fin-FET 100 shown may also have a buried p-doped layer 56 in different embodiments. The buried p-doped layer 56 may contact the gate shielding region 16. The shielding below the trench is therefore composed of the gate shielding region 16 and the buried layer 56. Thus, for example, a total depth of approximately 1 μm in the vertical direction of the shielding structures 16, 56 can be achieved without increasing the cell pitch P by combining the approximately 500 nm thickness of the gate shielding region 16 with the approximately 500 nm thickness of the buried layer 56.

[0050] Furthermore, in different embodiments, a vertical FinFET arrangement having multiple vertical FinFETs 100 as described above for different embodiments can be provided. This has already been... Figure 1 , Figures 4A to 4S and Figure 5 The image is shown through multiple fins 14, grooves, etc.

[0051] The fins 14 (and correspondingly the trenches and the gate shielding region 16 formed thereunder) can be arranged parallel to each other. They can have an elongated geometry and be arranged parallel to each other along their longitudinal axis. The fins 14, trenches, and gate shielding region 16 can extend in a first direction.

[0052] To avoid alignment issues between the buried layer 56 and the FinFET 100 structure, the buried p-doped region 56 may have at least one elongated region, such as multiple parallel elongated regions 56, extending in a second direction different from the first direction. In other words, the buried region 56 may periodically extend in a direction different from the direction in which the trench periodically continues (see example...). Figure 5 (Here, the angle between the first direction and the second direction is 90°).

[0053] Figures 4A to 4SA schematic illustration is shown of a method for forming a vertical FinFET 100 according to one embodiment. Here, the characteristics and other features of the elements may correspond to those described above with reference to the vertical FinFET 100.

[0054] Figure 4A First, for example, an n-doped drift region 10, an n-doped propagation region 12, and an n-doped region (from which a fin 14 is later formed) are provided via epitaxy. In different embodiments, the fin 14 may extend into the propagation region 12. A meaningful doping concentration may be, for example, 10 in the drift region 10. 16 cm -3 10 out of 12 transmission zones 17 cm -3 and the channel region of fin 14 in 4.10 16 cm -3 This is followed by a flat n-contact region (source region 30), for example, having, for example, 10 19 cm -3 The doping concentration is either injected into the channel region or provided as an epitaxial layer. Figure 4B Then, using an etching process, trenches 42 with a width of approximately 800 nm and a depth of approximately 1.4 μm are fabricated using a structured mask 40 (e.g., an oxide hard mask). These trenches either extend into the propagation region 12 or stop before the propagation region. A portion of the mask 40 can be removed during this process. Figure 4C The remaining thickness of approximately 800 nm can be used as an implantation mask, thus enabling self-aligned implantation of the gate shielding region 16 through trench 42. An implantation depth of approximately 500 nm and a 5.10 nm penetration depth in trench 42 can be achieved using 0° implantation. 19 cm -3 The doping. Subsequently, the mask 40 can be removed and the contact metal 18 (e.g., nickel) can be deposited and alloyed in a surface manner (e.g., NiSi contact formed by means of an established RTA process).

[0055] Figure 4D To form fin 14, protection for the bottom can first be provided by: creating a structure through Si3N4 (reference numeral 44), polysilicon (reference numeral 46) deposition and polysilicon 46 etching back. Figure 4E This structure then allows for wet etching of Si3N4 44, leaving only Si3N4 remaining at the bottom of the trench. Figure 4E Then, similarly, remove polysilicon 46 ( Figure 4FNow, if the alloyed contact metal is oxidizable (e.g., NiSi), the trenches 42 can be laterally expanded by alternating oxidation and oxide etching, so that only the fins 14 between the trenches 42 remain. In the case of non-oxidizable contact metals, this step can be performed before ( Figure 4G The alloyed contact metal is selectively removed (e.g., by wet etching) relative to Si3N4 and wafer materials (e.g., SiC). Since Si3N4 44 acts as an oxide barrier at the bottom of the trench, and oxidizes significantly more slowly than SiC, the contacts 18 on the bottom remain protected. Etching of the oxide regions also simultaneously removes the oxide p-implanted regions on the wafer surface and at the trench sidewalls, which is undesirable. Figure 4G , Figure 4H Subsequently, the Si3N4 protection 44 on the bottom of the trench is selectively removed and the gate dielectric 32 is fabricated. Figure 4I ).

[0056] The opening used to connect to the p shield 16 requires some additional processing steps. Figure 4J , Figure 4K Si3N4 can be deposited in such a way (preferably by PECVD or sputtering) that protrusions are created on fin 14. 54. This is a known method with well-known process windows (process gas, process gas guide, process pressure, generator frequency, and power) to construct near-surface protrusions 54 on a freestanding structure with a defined aspect ratio. The gate oxide 32 in the bottom of the trench 42 can then be opened by means of directional etching (where the collimator effect is fully utilized, such as reactive ion etching (RIE) or ion beam etching (IBE)). Figure 4L Alternatively, operation can be performed using a polysilicon mask 52 within trench 42 to alter the aspect ratio of trench 42. This allows for a better fit of the protrusion 54 and improved protection of the trench sidewalls. To expand the contact area at the bottom of the trench, alternative processes can be used (therefore...). Figure 4M (Seen in gray) For a period of time, wet etching only opens the gate oxide 32 through the channel region on the bottom of trench 42 until most of the bottom (but not yet the sidewalls) is exposed.

[0057] After removing the Si3N4 54 and possibly the polysilicon mask 52, the contacts to the gate shielding region 16 and the gate 24, along with the insulating layers 22 and 26, can be introduced into the trench 42. Figures 4O to 4S This can be performed, for example, by means of double polysilicon deposition, polysilicon etch-back, polysilicon re-oxidation, or, for example, by means of a damascene process. Finally ( Figure 4S ), forming a front contact portion 28 and a rear contact portion. For this purpose, pre- ( Figure 4RRemove oxides above source region 30.

[0058] Figure 6 This is a flowchart 600 of a method for forming a vertical FinFET according to different embodiments.

[0059] The method may include: forming a plurality of trenches in an n-doped semiconductor region such that a semiconductor fin having an n-doped channel region is formed between two trenches, the semiconductor fin extending between an n-doped drift region and an n-doped source region (610); p-doping the semiconductor region on the corresponding bottom of the trench to form a p-doped shielding region (620); forming a dielectric layer on the sidewall of the trench (630); disposing a conductive material in the trench, the conductive material being in conductive contact with a corresponding shielding region disposed below it (640); and forming gate regions in the trench above the conductive material and electrically insulated from the conductive material (650).

Claims

1. A vertical fin field-effect transistor (100) having: - Semiconductor fin (14); - n-doped source pole region (30); - n-doped drift region (10); - An n-doped channel region arranged vertically between the source region (30) and the drift region (10) in the semiconductor fin (14); - At least one gate region (24) that is horizontally adjacent to the channel region. - Gate dielectric (32), the gate dielectric electrically insulates the gate region (24) from the channel region, wherein the interface between the gate dielectric (32) and the channel region and / or the gate dielectric (32) has a negative interface charge; - p-doped gate shielding region (16), the gate shielding region being arranged below the gate region (24) such that, in the case of vertical projection, the gate shielding region (16) is at least partially located within the area bounded by the gate dielectric (32); - Source contact portion (28), which is electrically connected to the source region (30); and - Conductive regions (18, 20) between the gate region (24) and the p-doped gate shielding region (16); - Wherein, the p-doped gate shielding region (16) is electrically connected to the source contact (28) via the conductive regions (18, 20).

2. The vertical fin field-effect transistor (100) according to claim 1. in, The conductive regions (18, 20) have polycrystalline silicon and / or have a conductive layer (18) having metal or nickel silicide.

3. The vertical fin field-effect transistor (100) according to claim 1 or 2. in, The semiconductor fin (14) has silicon carbide and / or gallium nitride.

4. The vertical fin field-effect transistor (100) according to any one of claims 1 to 3. in, The channel region has a width in the range of 50 nm to 400 nm, wherein the doping concentration in the channel region is 10. 15 cm -3 Up to 10 17 cm -3 Within the range.

5. The vertical-fin field-effect transistor (100) according to any one of claims 1 to 4, wherein the vertical-fin field-effect transistor further comprises: At least one propagation region (12, 12a) is more n-doped than the drift region (10).

6. The vertical fin field-effect transistor (100) according to claim 5. in, The at least one propagation region (12, 12a) has a first propagation region (12) arranged below and around the lower region of the gate shielding region (16), and has a second propagation region (12a) laterally adjacent to the gate shielding region (16) and above the first propagation region (12), wherein the second propagation region (12a) is more doped than the first propagation region (12).

7. The vertical fin field-effect transistor (100) according to claim 6. in, The second propagation region (12a) extends into the lower region of the semiconductor fin (14).

8. The vertical fin field-effect transistor (100) according to claim 7. in, The second propagation region (12a) extends into the region adjacent to the conductive regions (18, 20).

9. A fin field-effect transistor arrangement, comprising: A plurality of vertical fin field-effect transistors (100) according to any one of claims 1 to 4, the vertical fin field-effect transistors being arranged parallel to each other such that the respective p-doped gate shielding regions (16) of the vertical fin field-effect transistors extend in a first direction.

10. The fin field-effect transistor arrangement according to claim 9, wherein the fin field-effect transistor arrangement further comprises: Multiple buried p-doped regions (56) are arranged below and in contact with the p-doped gate shielding region (16), and are parallel to each other. The buried p-doped regions extend in a second direction. The second direction may optionally be different from the first direction.

11. A method for forming a vertical fin field-effect transistor (100), the method comprising: - A plurality of trenches are formed in an n-doped semiconductor region, such that semiconductor fins having n-doped channel regions are formed between two trenches, the semiconductor fins extending between an n-doped drift region and an n-doped source region; - The semiconductor region at the corresponding bottom of the trench is p-doped to form a p-doped shielding region; - A dielectric layer is formed on the sidewall of the trench; - A conductive material is arranged in the trench, and the conductive material is in conductive contact with a corresponding shielding area arranged below the conductive material; - Gate regions (24) are formed in the trench above the conductive material and electrically insulated from the conductive material. Wherein, the interface between the dielectric layer and the channel region and / or the dielectric layer has a negative interface charge. The p-doped shielding region is electrically connected to the source contact portion via the conductive material, and the source contact portion is electrically connected to the source region.

12. The method according to claim 11, in, The arrangement of the conductive material includes: forming a conductive layer having a metal or nickel silicide, and / or forming a polycrystalline silicon region in the trench.

13. The method according to claim 11 or 12, wherein, The trenches extend parallel to each other in a first direction, and the method further includes: - Forming the lower n-doped semiconductor region; - At least one elongated region in the lower n-doped semiconductor region is p-doped, the elongated region extending in the second direction; - An n-doped semiconductor region is formed on the lower n-doped semiconductor region and the elongated region; - Wherein, the first direction is different from the second direction; - In this process, p-doping of the semiconductor region at the corresponding bottom of the trench is performed such that the p-doped shielding region contacts the elongated region.

Images