MOSFET with saturated contact and method for forming a MOSFET with saturated contact
Patent Information
- Application Number
- CN202180015769.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-02-19
- Filing Date
- 2021-02-15
- Publication Date
- 2026-09-08
- Estimated Expiration
- 2041-02-15
AI Technical Summary
低的接通电阻RON通常导致,饱和电流相应地大并且作为结果会损坏短路强度
[0009] One advantage of MOSFETs with saturation contacts is that they offer advantages over MOSFETs without saturation contacts in terms of optimizing parameters such as saturation current (and therefore short-circuit strength) and R. ON They can be optimized or optimized independently. Therefore, it is possible to achieve low Rs while maintaining high short-circuit strength (low saturation current). ON .
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Figure CN115136322B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a MOSFET having saturation contacts and a method for forming a MOSFET having saturation contacts. Background Technology
[0002] To utilize wide-bandgap semiconductors (such as silicon carbide (SiC) or gallium nitride (GaN)) in power electronic devices, power MOSFETs with vertical channel regions (TMOSFETs) or power MOSFETs with lateral channel regions (VDMOSFETs) are typically used. The turn-on voltage and the resistance in the on-state (turn-on resistance R) can be adjusted, particularly through the design parameters of the channel region. ON And saturation current (short-circuit strength). The channel region of such a power MOSFET is typically combined with another doped region forming a JFET (JMOSFET) to provide better shielding and thus a higher breakdown voltage. In the case of SiC, nickel alloyed to form nickel silicide is typically used as the source contact.
[0003] In VDMOSFETs, TMOSFETs, or JMOSFETs based on existing technologies, the lowest possible Ro ON Minimizing saturation current as an optimization objective may be antagonistic. Low on-resistance R ON This typically results in a correspondingly large saturation current, which in turn weakens the short-circuit strength. Accordingly, a sufficiently low R may be required. ON A compromise must be found between the current and the saturation current, which is still low enough. Summary of the Invention
[0004] In various embodiments, a MOSFET is provided having a contact structure (also referred to as a saturated contact because the contact structure exhibits saturation characteristics at high voltages) that can have a resistance significantly lower than the resistance in the channel of the MOSFET at low voltages and a resistance significantly higher than the channel resistance at high voltages.
[0005] Therefore, these two optimization objectives can be decoupled from each other, since the channel can now be optimized to achieve the lowest possible R0. ON Furthermore, saturated contacts can be used to limit current under high voltage.
[0006] In various embodiments, graphene can be used in the contact structure of semiconductor materials (e.g., SiC) for contacting MOSFETs to achieve such saturated contact characteristics. Due to the high mobility of the two-dimensional electron gas (2DEG) in graphene, very low resistance can be achieved at low voltages. However, because the drift velocity of charge carriers (electrons) in the 2DEG has a very low saturation voltage, their mobility drops sharply from the critical voltage. Therefore, at high voltages, the current through the MOSFET (e.g., a power MOSFET) can be effectively limited by the resistance of the contact structure.
[0007] Figure 1 The diagram shows the analog output characteristics of a (power) MOSFET with a graphene contact structure compared to a conventional TMOSFET (dashed line) and a pure graphene resistor (dotted line). This graphene contact structure connects the source contact to the MOSFET channel (solid line). At low voltages, the current is limited by the resistance of the MOSFET channel, while at high voltages, the contact resistance determines the current limitation.
[0008] In this document, “low voltage,” “small voltage,” or “weak voltage” should be understood as a voltage that is on the order of magnitude of the MOSFET’s operating voltage, such as a few volts, or up to about 10V. “High voltage” or “large voltage” should be understood as a voltage that is many times the operating voltage, such as two or more times, or about 20V or more.
[0009] One advantage of MOSFETs with saturation contacts is that they offer advantages over MOSFETs without saturation contacts in terms of optimizing parameters such as saturation current (and therefore short-circuit strength) and R. ON They can be optimized or optimized independently. Therefore, it is possible to achieve low Rs while maintaining high short-circuit strength (low saturation current). ON . Attached Figure Description
[0010] Extensions to the described aspects are set forth in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and further explained in the following description. The drawings show:
[0011] Figure 1 The simulated transfer characteristic curves of MOSFETs with graphene contact structures according to different embodiments are shown compared with prior art TMOSFETs and pure graphene resistors.
[0012] Figure 2 A schematic cross-sectional view of a MOSFET with saturation contacts according to different embodiments is shown;
[0013] Figure 3Equivalent circuit diagrams of MOSFETs with saturation contacts according to different embodiments are shown;
[0014] Figure 4A and Figure 4B Schematic cross-sectional views of MOSFETs with saturation contacts according to different embodiments are shown respectively;
[0015] Figure 5A , Figure 5B and Figure 5C Schematic diagrams of methods for forming a MOSFET with saturation contacts according to different embodiments are shown respectively; and
[0016] Figure 6 A flowchart illustrating a method for forming a MOSFET with saturation contacts according to different embodiments is shown. Detailed Implementation
[0017] Figure 2 , Figure 4A and Figure 4B Schematic cross-sectional views of MOSFETs with saturated contact 200 according to different embodiments are shown respectively. Even though a JMOSFET with a vertical channel region is described below for illustrative purposes, it should be understood that the embodiments also involve MOSFETs with other structures, such as MOSFETs (TMOSFETs) with a vertical channel region that do not form a JMOSFET, or MOSFETs (VDMOSFETs) with a lateral channel region, for example.
[0018] The MOSFET having a saturated contact 200 may have an n-doped source region 16, a source contact 22, a contact structure 20, a barrier layer 32, and a dielectric layer 18. The contact structure extends from the source contact 16 to the n-doped source region 16, forms a first conductive connection with the source contact 22, and forms a second conductive connection with the n-doped source region 16.
[0019] The MOSFET with saturation contact 200 may also have other structures, such as a p-doped channel region 14, an n-doped drift region 12, a substrate 10, a drain connection 16, a gate region 28, and a gate dielectric 30, which may be formed in a substantially conventional manner for MOSFETs.
[0020] The MOSFET having saturated contact 200 can be a semiconductor material (which is doped or has been doped to form, for example, an n-doped source region 16, a p-doped channel region 14 and an n-doped drift region 12) and / or a substrate 10 having, for example, silicon carbide and / or gallium nitride and / or other suitable semiconductor materials (e.g. for power MOSFETs).
[0021] In different embodiments, the doping concentration in the n-doped source region 16 can be higher than the doping concentration in the n-doped drift region 12. For example, the source region 16 can be doped with approximately 1E19 / cm. 3 Furthermore, drift region 12 can be doped with approximately 1E16 / cm². 3 For simplicity, we will use the term "n-doped" below.
[0022] The contact structure 20 may have a segment between the first conductive connection and the second conductive connection, the segment being embedded between the barrier layer 32 and the dielectric layer 18 and configured such that a two-dimensional electron gas is formed or can be formed in the segment.
[0023] The construction of a two-dimensional electron gas (2DEG) can result in segments of the contact structure 20 having voltage-dependent resistance. For example, when the operating voltage of the MOSFET is applied (or a voltage approximately as high as the operating voltage, such as between approximately 0V and approximately 10V), the voltage-dependent resistance can be small, for example, less than the resistance of the p-doped channel region 14. When a voltage higher than the operating voltage is applied (e.g., several times or more than the operating voltage), the voltage-dependent resistance can be high, for example, higher than the resistance of the p-doped channel region 14.
[0024] In various embodiments, the contact structure 20 may have a graphene layer, a layer system having at least one gallium nitride layer and at least one aluminum gallium nitride layer, a molybdenum disulfide layer, or another layer or another layer system adapted to form a two-dimensional electron gas. Here, the layers or the layer structure may be formed, for example, in terms of the layer thickness, number, and relative positions of individual layers in the layer system, to achieve the construction of a 2DEG. The configuration parameters to be considered for constructing a 2DEG are known or substantially known to those skilled in the art.
[0025] Contact structure 20 can be fully (as exemplarily in) Figure 2 , Figure 4A , Figure 4B and Figures 5A to 5C (Presented in the middle) extends over the n-doped source region 16, or (not presented) covers only a portion of the surface of the n-doped source region 16.
[0026] Contact structure 20 can be fully (as exemplarily in) Figure 2 , Figure 4A , Figure 4B and Figures 5A to 5C (As shown in the image) extends below the source contact 22, for example, only below a portion of the source contact 22 (not shown), and / or has an opening in its surface, for example. Figure 4B ).
[0027] In different embodiments, the MOSFET having the saturated contact 200 may also have a p-doped shielding region 24, which may be arranged adjacent to the n-doped source region 16 below the contact structure 20. In this case, a segment of the contact structure 20 may be located above the p-doped shielding region 24.
[0028] In different embodiments, for example, where the contact structure 20 has graphene, the n-doped source region 16 has n-doped silicon carbide, and the p-doped shielding region 24 has p-doped silicon carbide, the graphene can form a low-resistance contact with the n-doped silicon carbide. The conductivity of the contact between the contact structure 20 and the p-doped shielding region 24 can be inherently so poor that the barrier layer 32 is formed in the p-doped shielding region 24 without any other measures, for example, in a surface adjacent to the surface of the p-doped shielding region 24. This in Figure 2 As shown in the diagram. In other words, the barrier layer 32 may be part of the p-doped shielding region 24.
[0029] In the region where the contact structure 20 (e.g., graphene or, if necessary, another material that inherently poorly contacts the p-doped shielding region 24) contacts the source contact 22, in various embodiments, a metal contact 42 may be formed between the contact structure 20 and the p-doped shielding region. This metal contact also forms good contact with the p-doped SiC (i.e., with low resistance). The metal contact 42 may be made of, for example, nickel, titanium, aluminum, or compounds thereof. For example, the nickel contact may be alloyed to form nickel silicide. The p-doped shielding region 24 can be simultaneously connected using the metal contact 42.
[0030] Because a barrier layer 32 is formed at the interface between graphene 20 and the p-doped shielding region (e.g., p-SiC region) 24, a two-dimensional electron gas (2DEG) is formed in the graphene layer 20 on the p-doped shielding region 24. This 2DEG behaves almost like an ideal saturated contact. The mobility of the 2DEG is several orders of magnitude higher than that in SiC at low voltages, allowing only R to be supplied at low voltages. ON A negligible resistor was added. See also [reference needed] for details. Figure 3 The equivalent circuit diagram is shown in the figure. At higher voltages, the graphene layer 20 immediately saturates and only allows a constant current density over a wide voltage range (see [reference]). Figure 1This current density can be higher than the current density at the operating point of the MOSFET, but much lower than its saturation current density. Within the linear range of the output characteristic curve of the MOSFET with saturation contact 200, the current flow through graphene 20 is therefore unrestricted, while conversely restricted in the saturation region of the MOSFET with saturation contact 200. Thus, the total current is effectively limited under short-circuit conditions, thereby improving short-circuit strength without compromising the conduction characteristics of the MOSFET 200 with saturation contact.
[0031] In other words, the MOSFET has a strong voltage-dependent resistance, known as a "saturation contact," between the source region 16 / contact structure 20-contact portion and the source contact 22 / contact structure 20-contact portion. Ideally, this resistance is minimal at low voltages, but significantly greater than the channel resistance (i.e., the resistance in the p-doped channel region 14) or the resistance of the MOSFET's drift region 12 at high voltages.
[0032] In various embodiments, such as when the contact structure 20 has a material or combination of materials that can form good conductive contacts with both the n-doped source region 16 and the p-doped shielding region 24, the barrier layer 32 can be formed as a single barrier layer 32, such as an oxide layer or a nitride layer. This is exemplarily shown in Figure 4A and Figure 4B Presented in the middle.
[0033] As long as the barrier layer (different from) Figure 4A and Figure 4B As shown in the diagram, the barrier layer 32 extends below the source contact 22, and if necessary, it can be opened at various locations (e.g., at regular intervals perpendicular to the drawing plane, i.e., along the trenches constructed in the gate of the TMOSFET) to also contact the p-doped shielding region 24.
[0034] Figure 5A , Figure 5B and Figure 5C Schematic diagrams of methods for forming a MOSFET having a saturation contact 200 according to different embodiments are shown respectively.
[0035] Figure 5AThis illustration describes the formation of a TMOSFET with saturated contacts 200 using graphene saturated contacts 20. After implantation of, for example, p-doped channel region 14, n-doped source region 16, and p-doped shielding region 24, and after implantation activation (Figure a), graphene can be grown at approximately 1700°C, for example, grown over its entire surface (Figure b). Subsequently, a channel (trench) 50 can be formed and post-processed (e.g., chamfered) (at approximately 1400°C; Figure c). All other processes, such as deposition of gate dielectric 30 (e.g., gate oxide), annealing, deposition of polysilicon as gate electrode 28, etc., can also be performed subsequently (Figure d) and can be limited to a maximum temperature of 1400°C.
[0036] Alternatively, such as in Figure 5B As shown in the figure, trench 50 can be formed first and then post-processed (e.g., chamfered) (Figure a), followed by the growth of graphene 20 (Figure b). In subsequent processes, the graphene 20 in the trench 50 must be locally removed again in this case (Figure c). Further processes can be performed as shown in... Figure 5A The implementation is as described in the diagram (d).
[0037] exist Figure 5C In another variation described, trench 50 is filled with a carbon capping 52 after its formation and post-processing, a process known as "carbon capping" (Figure a). The carbon capping 52 can then be etched back, leaving it only within trench 50 (Figure b). Graphene 20 is then grown. The trench 50 filled with carbon capping 52 remains free of graphene 20 (Figure c). Finally, the carbon capping 52 is removed by plasma etching. It is ensured that the etching used removes only the carbon capping 52, leaving the graphene 20 intact. For this purpose, oxygen plasma can be used, for example (Figure d).
[0038] Figure 6 A flowchart illustrating a method 600 for forming a MOSFET with saturated contacts according to various embodiments is shown. The method may include: forming an n-doped source region (in 610); forming a barrier layer (in 620); forming a contact structure that makes conductive contact with the n-doped source region, the contact structure extending laterally at least over a portion of the n-doped source region and over a portion of the barrier layer (in 630); and forming a dielectric layer over a segment of the contact structure disposed over the barrier layer, wherein the contact structure is configured in said segment such that a two-dimensional electron gas is formed in said segment (in 640).
Claims
1. A MOSFET (200) having: n-doped source region (16). Source contact (22); A contact structure (20) extends from the source contact portion (22) to the n-doped source region (16), forming a first conductive connection with the source contact portion (22) and a second conductive connection with the n-doped source region (16), wherein the source region is laterally arranged next to the source contact portion (22); A barrier layer (32) is arranged adjacent to the source region (16); as well as An insulating layer (18) extends over the section of the contact structure (20) above the barrier layer (32); The contact structure (20) extends laterally at least over a portion of the n-doped source region (16) and over a portion of the barrier layer (32); The contact structure (20) has a segment between the first conductive connection and the second conductive connection, wherein the segment is embedded between the barrier layer (32) and the insulating layer (18) and configured such that a two-dimensional electron gas is formed in the segment. The section has a voltage-dependent resistance. Wherein, when the operating voltage of the MOSFET is applied, the voltage-related resistance is less than the sum of all other resistances of the MOSFET, and Specifically, when a voltage higher than the operating voltage is applied, the voltage-related resistance is higher than that of at least one resistive component of the MOSFET.
2. The MOSFET (200) according to claim 1. in, When a voltage several times greater than the operating voltage is applied, the voltage-related resistance is higher than that of at least one resistive component of the MOSFET.
3. The MOSFET (200) according to claim 1 or 2. in, The contact structure (20) has a configuration from a set of configurations, the set of configurations having: Graphene layer; A layer system having at least one gallium nitride layer and at least one aluminum gallium nitride layer; and molybdenum disulfide layer.
4. The MOSFET (200) according to claim 1 or 2, further comprising: A p-doped shielding region (24) is arranged adjacent to the n-doped source region (16) below the contact structure (20). in, The barrier layer (32) is part of the p-doped shielding region (24).
5. The MOSFET (200) according to claim 4, further comprising: The metal contact (42) makes the source contact (22) and the p-doped shielding region (24) at least partially electrically connected.
6. The MOSFET (200) according to claim 5. in, The metal contact portion (42) has nickel, titanium, aluminum or a compound thereof.
7. The MOSFET (200) according to claim 1 or 2. in, The barrier layer (32) has a dielectric layer.
8. The MOSFET (200) according to claim 7. in, The dielectric layer includes oxides or nitrides.
9. The MOSFET (200) according to claim 7, further comprising: A p-doped shielding region (24) is arranged adjacent to the n-doped source region (16) below the barrier layer (32). in, The barrier layer (32) has at least one opening, through which the source contact (22) and the p-doped shielding region (24) are electrically connected.
10. The MOSFET (200) according to claim 1 or 2. in, The n-doped source region (16) has silicon carbide and / or gallium nitride.
11. The MOSFET (200) according to claim 1 or 2, further comprising: Channel area; in, The trench area is formed horizontally or vertically.
12. A method for forming a MOSFET, the method comprising: Forming source electrode contact portion (22); An n-doped source region (16) is formed, which is laterally arranged next to the source contact (22); A barrier layer (32) is formed adjacent to the source region (16); A contact structure (20) is formed to make conductive contact with the n-doped source region (16), the contact structure extending laterally over at least a portion of the n-doped source region (16) and over a portion of the barrier layer (32); An insulating layer (18) is formed above the section of the contact structure (20) arranged above the barrier layer (32); The contact structure (20) forms a first conductive connection with the source contact portion (22) and a second conductive connection with the n-doped source region (16). The contact structure (20) has a segment between the first and second conductive connections that is embedded between the barrier layer (32) and the insulating layer (18) and configured such that a two-dimensional electron gas is formed within the segment. The section has a voltage-dependent resistance. Wherein, when the operating voltage of the MOSFET is applied, the voltage-related resistance is less than the sum of all other resistances of the MOSFET, and Specifically, when a voltage higher than the operating voltage is applied, the voltage-related resistance is higher than that of at least one resistive component of the MOSFET.
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