Silicon-based liquid crystal panel and preparation method thereof

Abstract

The application provides a preparation method of a silicon-based liquid crystal panel, comprising the following steps: providing a wafer substrate manufactured in a wafer level, wherein the wafer substrate comprises a plurality of die regions with active circuits; forming a frame glue on the wafer substrate and pressing a transparent substrate to realize the packaging of a liquid crystal space; manufacturing a via hole penetrating through a silicon substrate and a conductive interface on a second surface of each die region with a relatively thick size, so that the active circuit is electrically connected to the back of the wafer substrate through the via hole and the conductive interface; and cutting the wafer substrate and the transparent substrate to obtain a plurality of silicon-based liquid crystal panels. According to the technical scheme, the integrated circuit manufacturing, the liquid crystal space packaging and the circuit packaging are all carried out in a wafer level process, especially the circuit packaging is carried out in a wafer level process, so that the production efficiency is improved and the production cost is reduced. The application further provides a silicon-based liquid crystal panel prepared by the preparation method, wherein the silicon-based liquid crystal panel has a relatively thick silicon substrate, the back of the silicon substrate is provided with a conductive interface, and the silicon-based liquid crystal panel has a relatively small area size and better optical flatness.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a liquid crystal on silicon (LCoS) panel and its preparation method. Background Technology

[0002] Wafer-level packaging (WLP) technology is an effective method for mass production of chips. Compared with simple integrated circuit chips, LCoS panels include not only integrated circuits but also liquid crystal packaging structures. To build a complete LCoS wafer-level packaging production line, it is necessary to include not only the integrated circuit packaging part but also the liquid crystal packaging part.

[0003] Currently, the mass production steps for LCoS are as follows: 1) Fabricating hundreds of integrated circuit dies on a wafer; 2) Applying sealant to each die and then laminating them with a transparent substrate; 3) Misaligning and cutting the wafer substrate and transparent substrate to form hundreds of independent units, exposing pre-reserved solder pads on the front edge of the wafer substrate of each unit; 4) Filling in liquid crystal through holes left on the side of the sealant and sealing; 5) Circuit packaging, bonding wires to the solder pads of each unit to lead out a flexible printed circuit (FPC) and connecting it to a control circuit board. In this technical solution, only the manufacturing of integrated circuits and the transparent substrate packaging are wafer-level processes, while liquid crystal filling and circuit packaging (excluding integrated circuit manufacturing) are die-level processes. This results in low production efficiency and requires more manpower and resources, leading to a high cost per LCoS unit and making it difficult to demonstrate an advantage over DMD (Digital Micromirror Device).

[0004] Therefore, to reduce the mass production cost of LCoS, two approaches are needed: firstly, process improvements should be made by introducing more advanced large-scale production processes; secondly, the yield per wafer should be increased, which requires filling more dies into standard wafers and reducing the die design size. However, in traditional LCoS, the bonding pads are concentrated on one edge of the front side of the wafer substrate. If the size is reduced while the number of bonding pads / leads remains the same, wire bonding or thin-film printed circuit wiring will become increasingly difficult and time-consuming. More importantly, the signal transmission lines become thinner, preventing an increase in signal processing speed.

[0005] Therefore, it is necessary to develop a new mass production solution for silicon-based liquid crystal panels and a corresponding silicon-based liquid crystal panel structure. Summary of the Invention

[0006] This invention provides a method for fabricating a silicon-based liquid crystal panel, comprising the following steps: Step A, providing a wafer substrate, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting dividing lines, each die region including an active circuit disposed on the first surface, the active circuit including at least a pixel circuit region and a peripheral circuit region; Step B, on the wafer substrate, forming a frame adhesive on one side of the first surface in each die region, such that the frame adhesive at least surrounds the pixel circuit region of the active circuit, the frame adhesive defining the liquid crystal space of the die region in which it is located; providing a surface having a transparent... A transparent substrate with a transparent conductive layer is bonded to a wafer substrate using a frame adhesive. Step C involves thinning the silicon substrate to a first thickness, ranging from 220 μm to 500 μm. On the wafer substrate, multiple vias penetrating the first and second surfaces are fabricated in each die region. Multiple conductive interfaces are fabricated on the second surface, with each conductive interface corresponding to a via. Each conductive interface is electrically connected to the active circuit of its corresponding die region through its corresponding via. Step D involves cutting the wafer substrate along the dividing line and correspondingly cutting the transparent substrate to obtain multiple silicon-based liquid crystal panels.

[0007] The fabrication method of this silicon-based liquid crystal panel, by employing through-silicon via (TSV) technology on the wafer substrate, brings process advantages, making it possible to separate the circuit packaging and liquid crystal spatial packaging processes into two independent parts. Specifically, the liquid crystal spatial packaging process is mainly performed on the front side of the wafer substrate (i.e., the first surface side), which neither damages nor obstructs the circuit packaging structure, nor requires additional circuit packaging processes on the front side of the wafer substrate during the liquid crystal spatial packaging process. The circuit packaging process is mainly performed on the back side of the wafer substrate, using TSV technology to create vias (metallized holes) that penetrate the silicon substrate, electrically connecting the active circuits on the wafer substrate to the conductive interfaces on the back side of the wafer substrate (i.e., the second surface), thus completing the circuit packaging. Once the liquid crystal spatial packaging and circuit packaging are completed, the wafer can be diced to obtain individual silicon-based liquid crystal panels. Further die-level circuit packaging of the silicon-based liquid crystal panel is not required; downstream OEMs can simply install it directly onto an external circuit board to obtain a silicon-based liquid crystal module. In summary, this makes cost control, production planning, and yield improvement much easier.

[0008] Moreover, the via fabrication process of this application is carried out on a relatively thick silicon substrate (220μm~500μm), which on the one hand reduces the difficulty of via fabrication and improves the mass production yield; on the other hand, the thicker silicon substrate helps to ensure the flatness of the reflective electrode layer of the active circuit during the fabrication process and operation of the silicon-based liquid crystal panel (since the silicon-based liquid crystal panel is an image modulation device, optical flatness has a great impact on the uniformity of image transmission, which is also the biggest difference between the silicon-based liquid crystal panel and other integrated circuit devices).

[0009] Furthermore, employing through-silicon via (TSV) technology on the wafer substrate to form vias penetrating the silicon substrate allows the silicon-based liquid crystal panel to be directly connected to an external circuit board via a conductive interface on the back. This results in the most compact silicon-based liquid crystal module packaging structure, reducing overall size while improving signal processing speed, leading to lower signal distortion and lower total power consumption. This technology eliminates the need for FPC lines to connect the silicon-based liquid crystal panel to the external circuit board, enabling mass production at a more cost-effective material level. Moreover, the current flow of this structure is perpendicular to the panel direction, allowing for thinner thicknesses. It essentially consists of only three layers: a transparent substrate layer, a liquid crystal layer, and a wafer substrate layer, eliminating the need for redundant metal plates and heat sinks on the back. This makes it suitable for applications such as head-mounted displays and micro-projectors.

[0010] In one embodiment of the preparation method, the order of steps B and C is reversed. Since the liquid crystal space encapsulation process in step B and the circuit encapsulation process in step C are relatively independent and have little mutual influence, their order can be reversed. Both B-then-C and C-then-B have advantages and disadvantages. Specifically, B-then-C allows for the initial protection of the pixel circuit area of ​​the active circuit using the formed liquid crystal space. Furthermore, the thicker silicon substrate before thinning makes it less prone to deformation, preventing damage to the wafer substrate during the bonding of the transparent substrate and the wafer substrate, and ensuring consistent liquid crystal space thickness across all die areas. C-then-B prevents contamination (such as organic volatiles) from the sealant in step B from affecting the equipment in step C. If liquid crystal has already been injected into the liquid crystal space in step B, it also prevents the liquid crystal from bursting out during step C. This is especially important if the equipment is not specifically used for the preparation and production of this application, as it may cause cross-contamination in the preparation of other products.

[0011] In one embodiment of the fabrication method, step B, after forming the frame adhesive and before bonding the transparent substrate, further includes a step of injecting liquid crystal into the liquid crystal space. The liquid crystal injection method can be One Drop Filling (ODF) technology. This ODF process can significantly reduce the liquid crystal injection time and improve liquid crystal utilization. Performing the liquid crystal injection in step B makes the liquid crystal injection wafer-level, which can further improve production efficiency. This step of injecting liquid crystal into the liquid crystal space can be adapted to either the above-described B-then-C production process or the above-described C-then-B production process.

[0012] In one embodiment of the fabrication method, step D, after dicing the wafer substrate and the transparent substrate, further includes a step of injecting liquid crystal into the liquid crystal space. In this technical solution, step B only forms the liquid crystal space without injecting liquid crystal. Currently, the equipment cost of ODF technology is high, and for small-sized LCoS with small liquid crystal space dimensions, the droplet control process of ODF is difficult to control, which is not conducive to startups to quickly achieve low-cost mass production. Therefore, this technical solution is a more economical and feasible technical route that combines actual production. Under this technical solution, although liquid crystal filling is at the die level, 90% of the overall production process of silicon-based liquid crystal panels is at the wafer level, still satisfying the advantages of large-scale mass production. The step of injecting liquid crystal into the liquid crystal space after dicing can be adapted to either the above-mentioned B-then-C production process or the above-mentioned C-then-B production process.

[0013] In one embodiment, the aspect ratio of the via ranges from 5:1 to 10:1.

[0014] In one embodiment, step C, the via fabrication step includes first forming a blind via on a silicon substrate using laser drilling, and then performing reactive ion etching at the blind via.

[0015] In one embodiment of the fabrication method, step C, the via fabrication step, includes first forming a trench on the second surface of the silicon substrate, and then forming a plurality of vias within the trench. This technical solution reduces the difficulty of via fabrication by dividing the via fabrication process into two steps. Especially in the manufacturing process of silicon-based liquid crystal panels with dozens of vias, forming the trench first allows multiple vias to share a single trench, which can improve manufacturing efficiency.

[0016] In one embodiment of the fabrication method, in step C, for each die region, the projections of the fabricated vias onto the wafer substrate are arranged to avoid and surround the pixel circuit region. Since the size of a single pixel circuit in the pixel circuit region directly affects the pixel size of the silicon-based liquid crystal panel, the pixel circuit region needs to be designed very densely. This technical solution places the vias connected to the input / output terminals of the active circuits outside the pixel circuit region. This avoids occupying a compact pixel area, which is beneficial for increasing pixel density. Furthermore, it avoids the via process damaging the stability of the pixel circuit, which is beneficial for improving process feasibility.

[0017] In one embodiment of the fabrication method, during the wafer-level packaging step, for each die region, the projections of the fabricated vias onto the wafer substrate are arranged to avoid and surround the peripheral circuit area. This technical solution avoids the influence of vias on the peripheral circuit and reduces the process difficulty of through-silicon via (TSV) technology, thus offering better process feasibility.

[0018] In one embodiment of the fabrication method, the active circuit includes multiple metal layers, each metal layer having multiple input / output terminals located at different positions. Each via is perpendicularly connected to a different input / output terminal of a metal layer, thereby achieving an electrical connection with the active circuit.

[0019] In one embodiment of the fabrication method, step C, the step of fabricating vias, includes: fabricating a via through a first surface and a second surface in each die region, the via exposing an input / output terminal; fabricating a dielectric layer covering the wall of the via and at least a portion of the second surface; etching the dielectric layer to ensure that the input / output terminal is exposed, thereby obtaining a patterned dielectric layer; fabricating a patterned conductive layer covering at least a portion of the patterned dielectric layer, and extending the patterned conductive layer from one side of the second surface to cover the input / output terminal, with at least a portion of the patterned conductive layer extending to one side of the second surface; and fabricating a patterned passivation layer covering at least a portion of the patterned conductive layer from one side of the second surface.

[0020] In one embodiment of the fabrication method, in step C, a conductive interface is fabricated in the region of the patterned conductive layer that is not covered by the patterned passivation layer.

[0021] In one embodiment of the fabrication method, the conductive interface includes at least one of a ball grid array packaging structure, a pin grid array structure, and a grid array packaging structure.

[0022] In one embodiment of the fabrication method, the conductive interface is electrically connected to an external circuit board by welding, and the welding temperature of the conductive interface material is selected to avoid damage to the liquid crystal.

[0023] In one embodiment of the fabrication method, the conductive interface is electrically connected to the external circuit board via mechanical pressing or mechanical coupling. This technical solution significantly reduces the bonding temperature between the silicon-based liquid crystal panel and the external circuit board compared to methods such as welding, thus avoiding the impact of excessively high temperatures from welding on the liquid crystal molecules.

[0024] In one embodiment of the fabrication method, within each die region, for at least a portion of a via, there exists a corresponding and electrically connected conductive pad, and the projections of each conductive pad and its corresponding via on the wafer substrate overlap. This technical solution reduces the number of input / output terminals that need to be placed on the metal layer, which is beneficial for reducing the overall die size.

[0025] In a preferred embodiment, within each die region, each via has a corresponding conductive pad, and the corresponding via is electrically connected to the conductive pad. This technical solution allows for testing the functionality of all active circuits connected by the vias using the conductive pads, greatly improving the testing convenience during the manufacturing process.

[0026] In one embodiment of the fabrication method, the sealant does not cover the conductive pad during the liquid crystal encapsulation step. This technique allows the performance of the active circuit to be tested through the conductive pad after the sealant is formed.

[0027] In another aspect, the present invention provides a silicon-based liquid crystal panel, comprising: a wafer substrate, the wafer substrate including a silicon substrate having opposing first and second surfaces, an active circuit on the first surface, a plurality of conductive interfaces on the second surface, and a plurality of vias penetrating the first and second surfaces, wherein the conductive interfaces correspond one-to-one with the vias, and each conductive interface is electrically connected to the active circuit through its corresponding via, the active circuit including at least a pixel circuit region and a peripheral circuit region; the thickness of the silicon substrate is in the range of 220 μm to 500 μm; a transparent substrate having a transparent conductive layer on its surface, disposed opposite to the wafer substrate; a sealant located between the wafer substrate and the transparent substrate, the sealant at least surrounding the pixel circuit region of the active circuit and defining a liquid crystal space; and liquid crystal located within the liquid crystal space; the silicon-based liquid crystal panel can be electrically connected to an external circuit substrate through the conductive interfaces.

[0028] The current flow of this silicon-based liquid crystal panel is perpendicular to the panel direction, which allows for a thinner thickness. It has only a three-layer structure consisting of a transparent substrate layer, a liquid crystal layer, and a wafer substrate layer. It does not require redundant metal plates and heat sinks on the back, and can be applied in fields such as head-mounted displays and micro projectors.

[0029] In one embodiment, the projections of multiple vias on the wafer substrate avoid and surround the pixel circuit area. This technical solution positions the vias at the input / output terminals of the active circuit outside the pixel circuit area. On the one hand, this avoids occupying a compact pixel area, which is beneficial for increasing pixel density. On the other hand, it avoids the through-hole process from damaging the stability of the pixel circuit, which is beneficial for improving process feasibility.

[0030] In one embodiment, the projections of multiple vias on the wafer substrate avoid and surround the peripheral circuit area.

[0031] In one embodiment, the active circuit includes multiple metal layers, each metal layer including multiple input / output terminals located at different positions. Each via is vertically connected to a different input / output terminal of the metal layer, thereby achieving electrical connection with the pixel circuit area and / or the peripheral circuit area.

[0032] In one embodiment, the wafer substrate further includes a plurality of conductive pads spaced apart on the first surface. The conductive pads are electrically connected to active circuits, and for at least a portion of the vias, there is a corresponding conductive pad that is electrically connected. This technical solution facilitates testing the wafer before / during liquid crystal packaging without damaging the conductive interfaces (e.g., without needing to solder the conductive interfaces to the testing device), and the testing can be performed from the front side of the wafer (one side of the first surface), making the operation more convenient.

[0033] In one embodiment, the thickness of the silicon substrate ranges from 300 μm to 400 μm.

[0034] In one embodiment, the aspect ratio of the via ranges from 5:1 to 10:1.

[0035] In one embodiment, the frame adhesive includes at least one closed liquid crystal injection port disposed on one side of the silicon-based liquid crystal panel. Attached Figure Description

[0036] Figure 1 This is a schematic flowchart of the method for preparing a silicon-based liquid crystal panel according to Embodiment 1 of the present invention;

[0037] Figure 2 This is a cross-sectional view of the silicon-based liquid crystal panel of the present invention.

[0038] Figure 3 for Figure 1 A top view of the structural schematic diagram of the wafer substrate provided in step A;

[0039] Figure 4 for Figure 3 A schematic diagram showing the section cut along line II;

[0040] Figure 5 for Figure 1A top view of the structural diagram of each specific process in step B;

[0041] Figure 6 for Figure 5 Schematic diagram of the structure cut along line II-II;

[0042] Figure 7a for Figure 1 A sectional view of the partial structure of step C1, C2, and C3 in the detailed process of step C;

[0043] Figure 7b for Figure 1 A sectional view of the partial structure of steps C4, C5, and C6 in step C;

[0044] Figure 8 for Figure 7a A partial structural schematic diagram of step C2', a modified implementation of C2, is shown in cross-sectional view.

[0045] Figure 9 for Figure 1 A schematic diagram of the structure of step D in the middle section;

[0046] Figure 10 A schematic diagram of a silicon-based liquid crystal panel mounted on an external circuit board;

[0047] Figure 11 This is a schematic flowchart of the method for preparing a silicon-based liquid crystal panel according to Embodiment 2 of the present invention;

[0048] Figure 12 for Figure 11 The flowchart in the diagram corresponds to a partial structural diagram.

[0049] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0051] In this invention, a die refers to the part of a silicon-based liquid crystal panel that does not include the liquid crystal packaging structure (liquid crystal, transparent substrate, frame adhesive, etc.), mainly including a wafer (silicon substrate + active circuit) and a circuit packaging structure (via + conductive interface, etc.); a silicon-based liquid crystal panel refers to a die + liquid crystal packaging structure, which can be sold as an independent product; a silicon-based liquid crystal module refers to a silicon-based liquid crystal panel + external circuit board, which can be obtained by downstream OEMs combining the silicon-based liquid crystal panel onto the PCB board of the product, or it can be packaged and sold after the silicon-based liquid crystal panel is produced. The functional integrity of the silicon-based liquid crystal panel is not limited by the external circuit board.

[0052] Figure 1 This is a schematic flowchart illustrating the method for fabricating a silicon-based liquid crystal panel according to Embodiment 1 of the present invention. Figure 1 As shown, the method for manufacturing this silicon-based liquid crystal panel includes the following steps.

[0053] Step A: Provide a liquid crystal substrate. The wafer substrate includes a silicon substrate having opposing first and second surfaces. The wafer substrate is divided into multiple die regions by intersecting dividing lines. Each die region includes active circuitry disposed on the first surface. The active circuitry includes at least a pixel circuitry region and a peripheral circuitry region.

[0054] Step B, Liquid Crystal Space Packaging. On the wafer substrate, in each die region, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit area of ​​the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located; a transparent substrate with a transparent conductive layer on its surface is provided, and the surface of the transparent substrate with the transparent conductive layer is bonded to the wafer substrate by the frame adhesive.

[0055] Step C, Circuit Packaging. The silicon substrate is thinned to a first thickness, ranging from 220 μm to 500 μm. On the wafer substrate, in each die region, multiple vias penetrating the first and second surfaces are fabricated. Multiple conductive interfaces are fabricated on the second surface, with each conductive interface corresponding to a via. Each conductive interface is electrically connected to the active circuitry of its corresponding die region through its corresponding via. The term "penetration" in this invention refers to penetration through the silicon substrate, not through the entire wafer substrate. There is an active circuit layer containing the active circuitry on the first surface of the silicon substrate. The vias connect to the active circuitry but do not penetrate it.

[0056] Step D, Singulation. The wafer substrate is cut along the dividing line, and the transparent substrate is cut accordingly to obtain multiple silicon-based liquid crystal panels.

[0057] When the silicon-based liquid crystal panel obtained by the method of the present invention is applied to a product, it further includes the step of: mounting the silicon-based liquid crystal panel, which electrically connects the silicon-based liquid crystal panel to an external circuit substrate to obtain a silicon-based liquid crystal module. This step is not necessarily considered a necessary step in the method of preparing the silicon-based liquid crystal panel.

[0058] The following describes the fabrication method of this silicon-based liquid crystal panel with reference to the accompanying drawings.

[0059] Step A: Provide a wafer substrate.

[0060] In this invention, the diameter of the wafer substrate is, for example, 8 inches (200 mm) or 12 inches (300 mm). The provided wafer substrate can be obtained by integrated circuit manufacturing before or during step A. This integrated circuit manufacturing process can be carried out in a wafer fab (typically TSMC, Samsung, UMC, GlobalFoundries, SMIC, etc.).

[0061] like Figure 3 As shown, the wafer substrate 10 includes a silicon substrate 11. The wafer substrate 10 is divided into multiple die regions 10a by multiple intersecting dividing lines L (represented by dashed lines in the figure; the dividing lines can be actual scribe lines or virtual lines). Each die region includes active circuitry 12, which includes at least a pixel circuit region (mainly the pixel storage circuit for controlling the liquid crystal) and a peripheral circuit region (mainly logic circuits, timing control circuits, buffer circuits, signal conversion circuits, etc.).

[0062] Specifically, such as Figure 4 As shown, the silicon substrate 11 has a first surface 112 (also referred to as the front side of the silicon substrate) and a second surface 114 (also referred to as the back side of the silicon substrate). Silicon substrates shipped from wafer fabs are generally quite thick, typically ranging from 800 μm to 1000 μm. The material of the silicon substrate 11 may be, for example, monocrystalline silicon, polycrystalline silicon, silicon germanium, or silicon carbide.

[0063] Active circuitry 12 is disposed on the first surface 112. Specifically, active circuitry 12 includes an active display driving matrix composed of multiple metal-oxide-semiconductor (MOS) transistors (not shown) and multiple reflective electrodes. The reflective electrodes are located at the outermost layer of active circuitry 12, i.e., the position farthest from the first surface 112, and are used for light reflection from the silicon-based liquid crystal panel, typically including a reflective aluminum film layer. Active circuitry 12 includes a metal layer... Figure 4 In the embodiment shown, only two metal layers are shown. Figure 4(The part filled with slashes " / ") indicates that, in other embodiments of the present invention, the active circuit may also have more metal layers. Multiple metal layers can be stacked along a direction perpendicular to the silicon substrate 11. Dielectric layers (such as silicon glass) are disposed between different metal layers for electrical insulation. A dielectric layer (not shown in the figure) is also disposed between the metal layers and the silicon substrate 11. The metal layers can be electrically connected to each other through vias. The active circuit 12 includes multiple input / output terminals 13, serving as ports for various functional circuits. The input / output terminals 13 can also be considered part of the active circuit 12 and are simultaneously etched during integrated circuit manufacturing. The active circuit 12 is connected to external circuit structures through the input / output terminals 13. The input / output terminals 13 of each metal layer can be simultaneously etched during the manufacturing of the functional circuits of each metal layer of the active circuit 12. In this invention, the number of input / output terminals 13 within each die region 10a is not limited.

[0064] like Figure 4 As shown, in this embodiment, the wafer substrate 10 further includes a plurality of conductive pads 17 spaced apart on one side of the first surface. The conductive pads 17 are electrically connected to the active circuit 12, and can also be considered as a component of the active circuit 12. In terms of manufacturing process, when the wafer substrate 10 is provided in step A, a plurality of conductive pads 17 spaced apart on the first surface 112 are obtained in each die region 10a. The conductive pads 17 can be manufactured simultaneously when manufacturing the metal layer containing the reflective electrode. The conductive pads 17 can be used to test the active circuit 12 in subsequent fabrication processes (such as before and after liquid crystal space packaging, before and after circuit packaging), and the testing can be performed from the front side of the wafer (one side of the first surface), making the operation more convenient.

[0065] Specifically, the application / structure of the conductive pad 17 will be described in detail in the subsequent section on embodiments of silicon-based liquid crystal panels, and will not be repeated here. It is understood that in some embodiments of the present invention, it may not be necessary to manufacture the conductive pad 17.

[0066] Between steps A and B, a step of cleaning the wafer substrate 10 is included, which may specifically include deionized water cleaning, plasma cleaning, etc. After the cleaning step, a step of forming an alignment layer on the wafer substrate 10 is also included. The alignment layer is used to give the liquid crystal molecules an initial orientation, so that the liquid crystal molecules at different positions have consistent orientation in the non-working state. The material of the alignment layer can be, for example, silicon oxide (SiOx), prepared by electron beam evaporation; or, the material of the alignment layer can be, for example, polyimide, first formed by spraying, chemical vapor deposition, or atomic layer deposition, and then several alignment trenches are formed on the surface of the alignment material coating by rubbing or laser processing, thus obtaining an alignment layer with alignment capability. Since alignment layers are needed on both the upper and lower surfaces of the liquid crystal layer, the layer below the liquid crystal layer (i.e., the side closer to the wafer substrate 10) is defined as the first alignment layer, and the layer above the liquid crystal layer (the side closer to the transparent substrate) is defined as the second alignment layer. Since alignment films are also required on the two transparent substrates of a TFT (Thin Film Transistor) liquid crystal panel to position the liquid crystal molecules, in one embodiment, the step of cleaning the wafer substrate 10 can be performed on a conventional liquid crystal display panel production line.

[0067] Step B: Liquid Crystal Space Encapsulation. Liquid crystal spaces are formed in each die region on the wafer substrate using sealant and a transparent substrate. Please refer to [link to relevant documentation]. Figure 5 and Figure 6 On the wafer substrate 10, in each die region 10a, a frame adhesive 20 is formed on one side of the first surface 112, such that the frame adhesive 20 at least surrounds the pixel circuit region of the active circuit 12, providing a transparent substrate 40, so that the transparent substrate 40 and the wafer substrate 10 are bonded together by the frame adhesive 20.

[0068] In one embodiment, the frame adhesive 20 can be applied by screen printing or injection molding.

[0069] The frame adhesive 20 defines the liquid crystal space 30 of the die region 10a in which it is located; the transparent substrate 40 includes a transparent substrate layer 41 (the material of the transparent substrate layer 41 is, for example, glass) and a transparent conductive layer 42 (the material of the transparent conductive layer 42 is, for example, indium tin oxide (ITO), fluorine-doped tin oxide (SnO2:F, FTO), aluminum-doped zinc oxide (ZnO:Al, ZAO) or an oxide of indium / antimony / zinc / cadmium), and the surface of the transparent substrate 40 having the transparent conductive layer 42 is pressed together with the wafer substrate 10 by the frame adhesive 20.

[0070] exist Figure 5 and Figure 6In the illustrated embodiment, the sealant 20 formed on each die region 10a is annular in structure. This annular structure, together with the wafer substrate 10 and the transparent substrate 40, forms a closed space (or leaves only a small liquid crystal injection port), which can be used to enclose the liquid crystal within the liquid crystal space 30. The sealant 20 at least surrounds the pixel circuit region of the active circuit, so that the light emitted by the pixels of the silicon-based liquid crystal panel can exit within the area enclosed by the sealant 20. Optionally, the peripheral circuit region of the active circuit can also be located below the sealant 20. In this invention, for each die region 10a, the width of the sealant 20 is 400 μm to 1000 μm.

[0071] The adhesive 20 can be made of thermosetting adhesive and / or UV-curable adhesive, etc. In one embodiment, it can also be both thermosetting and UV-curable, so as to use thermosetting to compensate for the areas of adhesive 20 not irradiated by UV light, and avoid the problem of insufficient curing in the area of ​​adhesive 20. The adhesive 20 may also contain rigid microspheres or other spacers (such as those made of plastic, silicon oxide, glass, resin or other similar mixtures) to maintain a certain suitable thickness of adhesive layer 22 when it is pressed together. In addition to bonding the wafer substrate 10 and the transparent substrate 40 together, the adhesive 20 also serves to resist the intrusion of external environment such as moisture.

[0072] The steps for bonding the transparent substrate 40 specifically include bonding the transparent substrate 40 to the wafer substrate 10 under vacuum using a laminator, followed by curing the frame adhesive 20.

[0073] In this invention, to ensure the liquid crystal within the liquid crystal space 30 has an initial orientation, alignment layers (not shown in the figure) are also provided on the upper and lower sides of the liquid crystal. Specifically, this includes a first alignment layer on one side of the wafer substrate 10 and a second alignment layer on one side of the transparent substrate 40. The preparation of the first alignment layer has been described above. The preparation of the second alignment layer can be referred to the preparation of the first alignment layer: it includes providing a transparent substrate 40 with a size equivalent to the wafer substrate 10, cleaning the transparent substrate (e.g., cleaning with deionized water followed by plasma cleaning), forming an alignment material coating on the transparent conductive layer 42 of the transparent substrate 40 through processes such as evaporation, coating, or deposition, and then forming several alignment trenches on the surface of the alignment material coating through a wiping process to obtain the second alignment layer. The second alignment layer is located on the surface of the transparent conductive layer 42. The thickness range of the transparent substrate 40 in this invention can be selected from 200μm to 750μm, and a thinner transparent substrate can be obtained through a thinning process.

[0074] Step C: Circuit packaging, thinning the silicon substrate by 11 to a first thickness, and fabricating vias and conductive interfaces in each die area of ​​the wafer substrate. For example... Figure 7a and Figure 7bAs shown, on the wafer substrate obtained in step B, after the silicon substrate is thinned, a plurality of vias 50 (metallized vias) penetrating the first surface and the second surface are formed in each die region 10a, and a plurality of conductive interfaces 14 are formed on the second surface. The conductive interfaces 14 correspond one-to-one with the vias 50, and each conductive interface 14 is electrically connected to the active circuit 12 of the die region 10a in which it is located through its corresponding via 50.

[0075] Specifically, step C includes steps C1, C2, C3, C4, C5, and C6, as follows:

[0076] Step C1 involves thinning the silicon substrate 11 to a first thickness, ranging from 220 μm to 500 μm. This thinning can be achieved through methods such as grinding, chemical mechanical polishing, and wet etching. A thinner silicon substrate is easier to perforate and reduces the overall thickness of the silicon-based liquid crystal panel. However, excessive thinness leads to a decrease in the mechanical properties of the silicon substrate 11, potentially causing it to crack during perforation or adversely affecting the active circuitry 12. Furthermore, excessive thinness reduces the optical flatness of the silicon substrate 11, making it prone to slight bending, which can cause significant shifts or deformations in the imaging of reflected light at distant locations. Therefore, this invention chooses to fabricate vias on a thicker silicon substrate, which ensures product yield and improves the optical flatness of the silicon-based liquid crystal panel.

[0077] In one embodiment of the present invention, preferably, the first thickness ranges from 300 μm to 400 μm.

[0078] Step C2 involves fabricating a via 55 penetrating the first surface 112 and the second surface 114 from one side of the second surface 114 of the silicon substrate 11, exposing the input / output terminal 13. Since the silicon substrate 11 of this invention has a relatively large thickness, optionally, in this embodiment, a blind via is first formed on the silicon substrate 11 using laser drilling, and then reactive ion etching is performed at the blind via to expose the input / output terminal 13 of the active circuit 12. This embodiment, which combines laser drilling with reactive ion etching, utilizes laser drilling to create a hole with a large aspect ratio while avoiding damage to the input / output terminal 13 during laser drilling.

[0079] In this invention, the aspect ratio of the via is in the range of 5:1 to 10:1.

[0080] For each die region, the projection of the manufactured via 55 on the wafer substrate 10 avoids and surrounds the pixel circuit region, thereby causing the projection of the via on the wafer substrate 10 to avoid and surround the pixel circuit region.

[0081] Because some embodiments of the silicon-based liquid crystal panel of this invention contain a large number of vias, approximately dozens, during the manufacturing of the vias, trenches can be first formed on the second surface of the silicon substrate, and then multiple vias can be formed within the trenches. This maintains the relatively thick silicon substrate while reducing the drilling depth required to manufacture a single via, thus lowering the process difficulty and improving production efficiency. For details, please refer to... Figure 8 First, a trench 56 is formed on one side of the second surface of the silicon substrate. Then, multiple vias 55' are formed within the trench 56 to create vias. In this embodiment, due to the presence of the trench 56, the aspect ratio of the via portion 55' can be relatively small, such as 5:1 to 7:1. For the embodiment without the trench described above, the via depth is larger, and the via aspect ratio is preferably in the range of 8:1 to 10:1.

[0082] Step C3: Fabricate a dielectric layer 51 covering the wall of the via 55 and at least part of the second surface 114, etch the dielectric layer 51 to ensure that the input / output terminal 13 is exposed, and obtain a patterned dielectric layer 51.

[0083] Step C4 involves fabricating a patterned conductive layer 52 that covers at least a portion of the patterned dielectric layer 51, and ensuring that the patterned conductive layer 52 extends from one side of the second surface 114 to cover the input / output terminal 13, thus establishing an electrical connection with the input / output terminal 13. At least a portion of the patterned conductive layer 52 extends to one side of the second surface 114. The material of the patterned conductive layer 52 may be, for example, copper, or other metals or metal alloys. Specifically, fabricating the patterned conductive layer 52 in step C4 may include depositing a metal conductive layer followed by patterned etching, or it may be directly patterned by deposition.

[0084] In step C5, a patterned passivation layer 53 is fabricated on one side of the second surface 114 of the silicon substrate 11, covering at least a portion of the patterned conductive layer 52. This patterned passivation layer 53 serves to insulate the patterned conductive layer 52, preventing short circuits caused by external devices. Specifically, the patterned passivation layer 53 may be composed of a dielectric material, such as polyimide (PI) or epoxy resin.

[0085] Step C6: A conductive interface 14 is fabricated in the area of ​​the patterned conductive layer 52 that is not covered by the patterned passivation layer 53. The via 50 consists at least of a patterned dielectric layer 51, a patterned conductive layer 52, and a patterned passivation layer 53 within a via 55, and extends to one side of the second surface 114, electrically connecting to the conductive interface 14 through the patterned conductive layer 52. Each via 50 is perpendicularly connected to a different input / output terminal 13 of the metal layer of the active circuit 12, thereby achieving electrical connection between the active circuit 12 and the via 50.

[0086] The conductive interface 14 includes at least one of a Ball Grid Array (BGA), a Pin-Grid Array (PGA), and a Land Grid Array (LGA) structure. The material of the first conductive interface is, for example, one or more of the following: tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony, and may include an active agent. This type of packaging structure allows the silicon-based liquid crystal panel to be vertically connected to an external circuit board.

[0087] Step D: Cutting. Cut the transparent substrate and the wafer substrate to obtain multiple silicon-based liquid crystal panels.

[0088] like Figure 9 As shown, in step D, the transparent substrate and the wafer substrate are cut along the dividing line to obtain multiple silicon-based liquid crystal panels 100.

[0089] Specifically, a direct cutting method can be used, where the silicon substrate and the transparent substrate are cut directly using cutting equipment, including physical cutting and laser cutting; alternatively, a method can be used, where a fracture groove is first sawed (not completely cut off) or diced, and then the substrate is physically separated.

[0090] In this embodiment, the cutting lines of the wafer substrate and the transparent substrate coincide in a direction perpendicular to the wafer substrate, rather than in the staggered arrangement of traditional processes. This ensures that the cut transparent substrate does not protrude relative to the wafer substrate, and also eliminates the need for the transparent substrate to expose the front side (first surface of the silicon substrate) of the wafer substrate.

[0091] To protect the conductive interface 14 and other structures on the back side of the wafer substrate 10, a carrier plate can be designed to hold the wafer substrate 10. The carrier plate has a groove structure corresponding to the conductive interface 14. On the one hand, it can protect the back side structure of the wafer substrate 10 from being crushed, and on the other hand, it is convenient for dicing and cutting.

[0092] In step D of this embodiment, after cutting the wafer substrate 10 and the transparent substrate 40, a step of filling liquid crystal into the liquid crystal space is also included. Specifically, this can be achieved by vacuum siphoning. After the liquid crystal filling is completed, the liquid crystal filling port reserved by the frame sealant is sealed to achieve sealing of the liquid crystal.

[0093] This technical solution is a more economical and feasible approach combined with actual production. Under this technical solution, although liquid crystal filling is at the die level, 90% of the overall production process of silicon-based liquid crystal panels is at the wafer level, especially circuit packaging (step C), which is at the wafer level, still satisfying the advantages of large-scale mass production.

[0094] In this invention, the total thickness of the obtained silicon-based liquid crystal panel ranges from 400μm to 1300μm, mainly comprising the thickness of the transparent substrate layer, the liquid crystal layer, and the wafer substrate layer. In terms of size, the dimensions after cutting, i.e., the dimensions of the silicon-based liquid crystal panel 100, are the same as the die size; that is, the packaging process of this invention is CSP (chip scale package). The reduction in the overall size of the silicon-based liquid crystal panel 100 makes it more suitable for applications in head-mounted displays and micro-projection fields.

[0095] After the silicon-based liquid crystal panel 100 is prepared in the above steps (AD), it can be shipped directly as a product. Downstream customers can mount the silicon-based liquid crystal panel 100 onto an external circuit board (such as a PCB board) for application in their systems. Specifically, the external circuit board may include multiple modules, such as an FPGA module, a power supply module, and a display chip module. The silicon-based liquid crystal panel 100 prepared by this invention can be installed in the slot of the display chip module or soldered onto it.

[0096] Figure 10 The diagram illustrates a silicon-based liquid crystal panel 100 electrically connected to an external circuit board 120. The external circuit board 120 can be a flexible circuit board or a printed circuit board. The silicon-based liquid crystal panel 100 is electrically connected to the external circuit board 120 via conductive interfaces 14, allowing active circuitry 12 to be electrically connected to the external circuit board 120 through multiple input / output terminals 13, multiple vias 50, and multiple conductive interfaces 14 for signal input and output. Specifically, the silicon-based liquid crystal module 100 defines multiple pixels (not shown), and an active display driving matrix provides a set of MOS transistors for each pixel. Each set of MOS transistors in the active display driving matrix can control the electric field of the liquid crystal molecules corresponding to each pixel by controlling the voltage applied to the reflective electrodes, thereby adjusting the rotation angle of the liquid crystal molecules corresponding to each pixel, and thus controlling the polarization state of the light emitted from the region corresponding to each pixel. This, in conjunction with a polarization beam splitter, enables image modulation.

[0097] The above-described Embodiment 1 and its various specific modifications provide a method for fabricating a silicon-based liquid crystal panel. Under the same inventive concept, there is another modified embodiment of the method for fabricating a silicon-based liquid crystal panel. The difference between this technical solution and the above embodiment lies only in the interchange of steps B and C. For example... Figure 11 and Figure 12 As shown, in Embodiment 2, circuit packaging is performed first, followed by liquid crystal space packaging.

[0098] For a description of each step and structure in Embodiment 2, please refer to the description in the corresponding specification and drawings of Embodiment 1, which will not be repeated here. Since the liquid crystal space packaging process in step B and the circuit packaging process in step C are relatively independent and have little mutual influence, their order can be changed. Both B-then-C and C-then-B have advantages and disadvantages. Specifically, B-then-C allows the formed liquid crystal space to protect the pixel circuit area of ​​the active circuit; C-then-B prevents contamination (such as organic matter volatilization) generated by the frame adhesive in step B from affecting the equipment in step C. This is especially important if the equipment is not specifically used for the production of this application, as cross-contamination may occur in the production of other products.

[0099] In both Embodiment 1 and Embodiment 2 described above, the liquid crystal injection process is performed after cutting the wafer substrate and the transparent substrate in step D. In other embodiments of the present invention, regardless of the order of steps B and C, liquid crystal can be injected in step B. In step B, after forming the frame adhesive and before bonding the transparent substrate, a step of injecting liquid crystal into the liquid crystal space is included. Specifically, this includes injecting liquid crystal using a one-drop filling (ODF) process. This ODF process can be performed before bonding the transparent substrate, significantly reducing the liquid crystal injection time, improving liquid crystal utilization, and can be performed at the wafer level, making the entire silicon-based liquid crystal panel fabrication method wafer-level, greatly improving mass production capability. However, it also presents difficulties such as expensive ODF equipment and the need for liquid crystal droplet preparation processes.

[0100] An embodiment of the present invention also provides a silicon-based liquid crystal panel and a silicon-based liquid crystal module obtained by the above-described methods for preparing silicon-based liquid crystal panels. The silicon-based liquid crystal module includes an electrically connected silicon-based liquid crystal panel and an external circuit board, and the silicon-based liquid crystal panel is electrically connected to the external circuit board through a conductive interface. Figure 2 As shown, the silicon-based liquid crystal panel 100 includes a wafer substrate 10 and a transparent substrate 40 disposed opposite to each other.

[0101] The wafer substrate 10 includes a silicon substrate 11 having opposing first surfaces 112 and second surfaces 114. The wafer substrate 10 also includes active circuitry 12 located on the first surface 112, a plurality of conductive interfaces 14 located on the second surface 114, and a plurality of vias 50 penetrating the first and second surfaces 112. Each conductive interface 14 corresponds one-to-one with a via 50, and each conductive interface 14 is electrically connected to the active circuitry 12 through its corresponding via 50. The active circuitry includes a pixel circuitry region and a peripheral circuitry region.

[0102] Specifically, the pixel circuit area includes multiple pixel circuits, each corresponding to a liquid crystal pixel in the silicon-based liquid crystal panel. The deflection of the liquid crystal molecules is controlled by controlling the electric field of the liquid crystal molecules in the liquid crystal pixels. The peripheral circuit area is connected to the pixel circuit area through circuitry and is used to process the input image signals, power signals and other control signals, thereby outputting control signals for the pixel circuits to the pixel circuit area.

[0103] In this invention, the thickness of the silicon substrate 11 ranges from 220 μm to 500 μm. This dimension balances mechanical reliability and optical flatness, and also helps to reduce potential damage to the active circuit 12 and the silicon substrate 11 during the fabrication of the via 50. Further, this thickness range is preferably 300 μm to 400 μm.

[0104] The transparent substrate 40 includes a transparent substrate layer 41 and a transparent conductive layer 42, which is disposed opposite to the wafer substrate 10. The wafer substrate 10 and the transparent substrate 40 are connected by a frame adhesive 20 disposed between them. The frame adhesive 20 at least surrounds the pixel circuit area of ​​the active circuit 12 and defines a liquid crystal space 30. That is, the frame adhesive 20, the wafer substrate 10, and the transparent substrate 40 together form a closed space for filling liquid crystal to form a liquid crystal layer. The thickness of the transparent substrate 40 ranges from 200 μm to 750 μm.

[0105] The transparent substrate layer 41 is, for example, glass with good light transmittance, especially good light transmittance in the visible light range with little variation with wavelength, so as to reduce light loss when incident light enters the liquid crystal space and when outgoing light is emitted. The glass substrate layer 41 can be quartz glass.

[0106] The transparent conductive layer 42 is made of materials such as indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, or indium / antimony / zinc / cadmium oxide. The transparent conductive layer 42 is electrically connected to the active circuit 12. The active circuit 12 controls the level of the entire transparent conductive layer 42 by outputting a voltage, thereby forming an electric field between the transparent conductive layer 42 and the reflective electrode of the active circuit 12, and controlling the orientation of the liquid crystal molecules.

[0107] In this embodiment, a first alignment layer 113 and a second alignment layer 43 are respectively provided on the upper and lower sides of the liquid crystal layer. The first alignment layer 113 is part of the wafer substrate 10 and is located above the active circuit 12; the second alignment layer 43 is part of the transparent substrate 40 and is located below the transparent conductive layer 42. The first alignment layer 113 and the second alignment layer 43 are used for the initial orientation of liquid crystal molecules within the liquid crystal space 30. The material of the alignment layers is, for example, polyimide or silicon oxide.

[0108] In one embodiment, the frame adhesive 20 has a plurality of spacers to provide sufficient mechanical support.

[0109] In one embodiment, the sealant 20 includes at least one closed liquid crystal filling port disposed on one side of the silicon-based liquid crystal panel 100. This embodiment corresponds to the liquid crystal filling technique in step D of the above-described preparation method.

[0110] This silicon-based liquid crystal panel has a wafer substrate 10 with vias 50 penetrating a silicon substrate 11. The vias 50, input / output terminals 13, and active circuitry 12 are connected via conductive interfaces 14 located on the back of the wafer substrate 10. This allows the silicon-based liquid crystal panel to be manufactured using a passive liquid crystal display panel production line, performing liquid crystal space packaging from the front of the wafer substrate 10, reducing equipment investment costs. Furthermore, by employing through-silicon via (TSV) technology on the wafer substrate 10 to form vias 50 penetrating the silicon substrate 11, the silicon-based liquid crystal panel 100 can be directly connected to an external circuit board via the conductive interfaces 14, eliminating the need for FPC lines, thus improving signal processing speed and saving costs.

[0111] In this embodiment, the via 50 includes at least a patterned dielectric layer 51, a patterned conductive layer 52, and a patterned passivation layer 53. Figure 2 In the via 50, a patterned passivation layer 54 is also included, which is disposed on one side of the second surface 114 of the silicon substrate 11. A protrusion is formed on one side of the second surface 114 to support the patterned conductive layer 52 and the conductive interface 14.

[0112] In this embodiment, the aspect ratio of the via 50 ranges from 5:1 to 10:1.

[0113] like Figure 2 As shown, the projection of the via 50 on the wafer substrate 10 avoids and surrounds the pixel circuit region of the active circuit 12 (which can be considered as at least avoiding the area below the liquid crystal space 30). In the case of multiple vias, each via avoids the pixel circuit region. In terms of manufacturing process, in the embodiment of the above-described fabrication method, in the circuit packaging step (i.e., step C), for each die region 10a, the projections of the manufactured multiple vias 50 on the wafer substrate 10 are arranged to avoid and surround the pixel circuit region.

[0114] In some embodiments of the present invention, the projection of the via 50 on the wafer substrate 10 avoids and surrounds the peripheral circuit area. For example... Figure 2 As shown, the portion of the active circuit 12 located directly below the frame adhesive 20 can be considered as part of the peripheral circuit. The two vias 50 shown in the figure both avoid this portion of the peripheral circuit. In terms of the manufacturing process, in the embodiment of the above-described fabrication method, in step C of circuit packaging, for each die region 10a, the projections of the manufactured vias 50 on the wafer substrate 10 are arranged to avoid and surround the peripheral circuit region.

[0115] In a modified embodiment of the present invention, some vias can be located in the peripheral circuit area. This technical solution makes the peripheral circuit layout design more flexible and is also conducive to improving the transmission rate of the circuit corresponding to these vias.

[0116] In another embodiment, in the above-described method for fabricating a silicon-based liquid crystal panel, the active circuit 12 includes multiple metal layers, each metal layer including multiple input / output terminals 13 located at different positions, and each via 50 is vertically connected to a different input / output terminal 13 of the metal layer, thereby achieving electrical connection with the pixel circuit area and / or the peripheral circuit area.

[0117] like Figure 2 As shown, the wafer substrate 10 also includes a plurality of conductive pads 17 spaced apart on one side of the first surface 112 of the silicon substrate 11. The conductive pads 17 are electrically connected to the active circuits 12, and for at least a portion of the vias 50, there is a corresponding conductive pad 17 that is electrically connected. In terms of manufacturing process, the conductive pads 17 can be used to test the active circuits 12 during the fabrication of the silicon-based liquid crystal panel. This technical solution is advantageous for testing the active circuits 12 without damaging the conductive interface 14 (e.g., without needing to solder the conductive interface to the testing device), and the testing can be performed from the front side of the wafer (the first surface side), making the operation more convenient.

[0118] In some embodiments of the present invention, for each via 50, there is a unique conductive pad 17 electrically connected to it. Therefore, the circuits corresponding to each conductive interface 14 can be tested for proper functioning by using the conductive pad 17 as an input / output interface.

[0119] In some embodiments, a separate conductive pad 17 is also included, such as Figure 2 The conductive pad 17 shown on the right is electrically connected to the active circuit 12 on one side and electrically connected to the transparent conductive layer 42 of the transparent substrate 40 through conductive adhesive 60 on the other side, thereby acting as a conductor to provide voltage to the transparent conductive layer 42.

[0120] In some embodiments of the present invention, for at least a portion of the vias 50, there is a corresponding and electrically connected conductive pad 17, and the projections of each conductive pad 17 and its corresponding via 50 on the wafer substrate 10 are staggered. This technical solution makes the physical connection between the conductive pad and the active circuit relatively independent of the physical connection between the via and the active circuit, making the circuit layout more flexible.

[0121] In another embodiment, the projections of each conductive pad 17 and its corresponding via 50 on the wafer substrate 10 overlap (e.g., Figure 2(The conductive pad and via on the left side). This technical solution reduces the number of input / output terminals 13 that need to be set on the metal layer, so that the conductive pad 17 and via 50 can be connected to the same input / output terminal 13 at the same time, which helps to reduce the overall size of the silicon-based liquid crystal panel 100.

[0122] In this invention, the conductive interface 14 includes at least one of BGA, PGA, and LGA. This type of packaging structure allows the silicon-based liquid crystal panel 100 to be connected to an external circuit board in the vertical direction. Since the BGA mounting method involves a heating process, which may damage the liquid crystal, a PGA or LGA connection method is preferred.

[0123] From the perspective of the mounting temperature of the silicon-based liquid crystal panel 100, the manufacturing method of the present invention preferably employs a lower-temperature mounting method. In one embodiment of the present invention, the conductive interface 14 is electrically connected to the external circuit board through mechanical pressing or mechanical coupling. Furthermore, the silicon-based liquid crystal panel and the external circuit board can be further fixed by clips, improving the reliability of the mechanical pressing or mechanical coupling connection.

[0124] In this embodiment, at least a portion of the conductive interfaces 14 are projected onto the wafer substrate 10 closer to the center of the silicon-based liquid crystal panel 100 than the projection of the vias 50 corresponding to the conductive interfaces 14 onto the wafer substrate. By connecting the vias 50 and the conductive interfaces 14 via circuits on the second surface 114 of the silicon substrate 11 of the wafer substrate 10, a portion of the conductive interfaces 14 can be distributed at the positions of the pixel circuit areas corresponding to the active circuits 12, avoiding excessive crowding of the conductive interfaces 14 at the edges. This also allows for a larger size of the conductive interfaces 14, resulting in higher transmission efficiency. The arrangement of the conductive interfaces 14 on the second surface 114 can be a uniform array or a non-uniform arrangement; examples will not be provided here.

[0125] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a silicon-based liquid crystal panel, comprising the following steps: Step A: Provide a wafer substrate, the wafer substrate including a silicon substrate having opposing first and second surfaces, the wafer substrate being divided into multiple die regions by intersecting multiple dividing lines, each die region including an active circuit disposed on the first surface, the active circuit including at least a pixel circuit region and a peripheral circuit region. Step B: On the wafer substrate, in each of the die regions, a frame adhesive is formed on one side of the first surface, such that the frame adhesive at least surrounds the pixel circuit region of the active circuit, and the frame adhesive defines the liquid crystal space of the die region in which it is located. A transparent substrate with a transparent conductive layer on its surface is provided, and the surface of the transparent substrate with the transparent conductive layer is bonded to the wafer substrate by the frame adhesive; Step C: Thin the silicon substrate to a first thickness, the first thickness being 220μm~500μm. On the wafer substrate, in each die region, a plurality of vias penetrating the first surface and the second surface are formed, and a plurality of conductive interfaces are formed on the second surface. The conductive interfaces correspond one-to-one with the vias, and each conductive interface is electrically connected to the active circuit of the die region in which it is located through its corresponding via. Step D: Cut the wafer substrate along the dividing line, and correspondingly cut the transparent substrate to obtain multiple silicon-based liquid crystal panels; In step C, for each die region, the projections of the plurality of vias manufactured on the wafer substrate are arranged to avoid and surround the pixel circuit region.

2. The method for preparing a silicon-based liquid crystal panel as described in claim 1, characterized in that, The order of step B and step C is reversed.

3. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, In step B, after the frame adhesive is formed and before the transparent substrate is attached, the step of injecting liquid crystal into the liquid crystal space is further included.

4. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, In step D, after cutting the wafer substrate and the transparent substrate, the step further includes filling the liquid crystal space with liquid crystal.

5. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The aspect ratio of the via is in the range of 5:1 to 10:

1.

6. The method for preparing a silicon-based liquid crystal panel as described in claim 5, characterized in that, In step C, the step of manufacturing the via includes first forming a blind via on the silicon substrate using laser drilling, and then performing reactive ion etching at the blind via.

7. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, In step C, the step of manufacturing the via includes first forming a trench on the second surface of the silicon substrate, and then forming a plurality of vias within the trench.

8. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The active circuit includes multiple metal layers, each metal layer including multiple input / output terminals located at different positions. Each via is perpendicularly connected to a different input / output terminal of the metal layer, thereby achieving electrical connection with the active circuit.

9. The method for preparing a silicon-based liquid crystal panel as described in claim 8, characterized in that, In step C, the step of manufacturing the via includes: in each die region, manufacturing a through-hole penetrating the first surface and the second surface, the through-hole exposing the input / output terminal; manufacturing a dielectric layer covering the wall surface of the through-hole and at least a portion of the second surface, etching the dielectric layer to ensure that the input / output terminal is exposed, thereby obtaining a patterned dielectric layer; manufacturing a patterned conductive layer covering at least a portion of the patterned dielectric layer, and having the patterned conductive layer cover the input / output terminal from one side of the second surface, with at least a portion of the patterned conductive layer extending to one side of the second surface; and manufacturing a patterned passivation layer covering at least a portion of the patterned conductive layer from one side of the second surface.

10. The method for preparing a silicon-based liquid crystal panel as described in claim 9, characterized in that, In step C, the conductive interface is fabricated in the area of ​​the patterned conductive layer that does not cover the patterned passivation layer.

11. The method for preparing a silicon-based liquid crystal panel as described in claim 1 or 2, characterized in that, The conductive interface includes at least one of a ball grid array packaging structure, a pin grid array structure, and a grid array packaging structure.

12. A silicon-based liquid crystal panel, characterized in that, include: A wafer substrate includes a silicon substrate having opposing first and second surfaces, an active circuit on the first surface, a plurality of conductive interfaces on the second surface, and a plurality of vias penetrating the first and second surfaces. Each conductive interface corresponds one-to-one with a via, and each conductive interface is electrically connected to the active circuit via its corresponding via. The active circuit includes at least a pixel circuit region and a peripheral circuit region. The projections of the plurality of vias onto the wafer substrate avoid and surround the pixel circuit region. The thickness of the silicon substrate ranges from 220 μm to 500 μm. A transparent substrate with a transparent conductive layer on its surface is disposed opposite to the wafer substrate; A frame adhesive is located between the wafer substrate and the transparent substrate, and the frame adhesive at least surrounds the pixel circuit area of ​​the active circuit and defines a liquid crystal space; as well as Liquid crystal, located within the liquid crystal space; The silicon-based liquid crystal panel can be electrically connected to an external circuit board through the conductive interface.

13. The silicon-based liquid crystal panel as described in claim 12, characterized in that, The thickness of the silicon substrate ranges from 300 μm to 400 μm.

14. The silicon-based liquid crystal panel as described in claim 12, characterized in that, The aspect ratio of the via is in the range of 5:1 to 10:

1.

15. The silicon-based liquid crystal panel as described in claim 12, characterized in that, The frame adhesive includes at least one closed liquid crystal injection port disposed on one side of the silicon-based liquid crystal panel.

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