System, method, device, processor and storage medium for realizing high-speed mixed acquisition function of multi-channel analog signals or digital signals

Abstract

The present invention relates to a system for realizing a high-speed mixed acquisition function of multiple analog signals or digital signals, including a body domain main chip and multiple peripheral chips, the body domain main chip is respectively connected to the multiple peripheral chips, the body domain main chip has multiple control pins and multiple sampling ports, each control pin is simultaneously connected to multiple peripheral chips, and each sampling port is correspondingly connected to a peripheral chip; each peripheral chip has multiple interfaces, and each peripheral chip controls the connection between the interface of the peripheral chip and the corresponding sampling port through the control signal transmitted by the body domain main chip. The present invention also relates to a method for realizing a high-speed mixed acquisition function of multiple analog signals or digital signals. The system, method, device, processor and storage medium thereof for realizing a high-speed mixed acquisition function of multiple analog signals or digital signals of the present invention can collect analog and digital quantities together, reduce the overall acquisition time and peripheral chips, reduce the resource consumption of MCU, and save hardware costs.

Description

Technical Field

[0001] The present invention relates to the field of automotive electronic control technology, in particular to the field of vehicle body domain controller, and specifically refers to a system, method, device, processor and storage medium thereof for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals. Background Art

[0002] As an important part of automotive electronics, the body domain controller has many controlled objects. It also samples the feedback of these controlled objects using AD analog signals to obtain voltage or current values ​​to detect the state of the controlled objects. There are also many digital quantities, which are generally only high and low level switch inputs.

[0003] Due to the reduction in the production capacity of automotive chips, in order to ensure production, it is necessary to use high-capacity, low-configuration chips from the same series as replacements. Generally, the number of pins available for analog sampling in low-configuration MCUs will be reduced, and in order to ensure the consistency of vehicle functions, the input quantity to be collected should not be reduced, and the collection speed needs to be increased. Conventional parallel-to-serial conversion only collects one signal, and each AD switch requires a certain amount of time.

[0004] Take the example of a peripheral chip that converts 8 AD signals to 1 acquisition port. There are 28 signals in total, of which 18 are analog acquisition, 2 are three-state switch inputs (analog), and 8 are two-state switch inputs (digital). Originally, 28 sampling pins were required, including analog and digital quantities. The conventional analog merging method requires 14 pins, including 3 parallel-to-serial control ports, 3 analog acquisition ports, and 8 digital acquisition ports. In addition, the analog quantity collected in series needs to be switched constantly, which consumes a lot of time. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system, method, device, processor and storage medium thereof for realizing high-speed mixed acquisition of multiple analog signals or digital signals with low resource consumption, short acquisition time and low hardware cost.

[0006] In order to achieve the above-mentioned object, the system, method, device, processor and storage medium thereof for realizing high-speed mixed acquisition function of multiple analog signals or digital signals of the present invention are as follows:

[0007] The system for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals has the following main features: the system comprises a body domain main chip and multiple peripheral chips, the body domain main chip is respectively connected to the multiple peripheral chips, the body domain main chip has multiple control pins and multiple sampling ports, each of the control pins is simultaneously connected to the multiple peripheral chips, each of the sampling ports is correspondingly connected to a peripheral chip, the control pins are used to transmit the control signal of the body domain main chip to the peripheral chip, and the sampling ports are used to collect the input quantity of the peripheral chip; each of the peripheral chips has multiple interfaces, which are respectively connected to analog signals, three-state switch signals and digital signals, and each of the peripheral chips controls the connection between the interface of the peripheral chip and the corresponding sampling port through the control signal transmitted by the body domain main chip.

[0008] Preferably, the body domain main chip also has a plurality of digital quantity acquisition pins for sampling input digital quantities.

[0009] Preferably, the multiple peripheral chips are respectively a first peripheral chip, a second peripheral chip and a third peripheral chip, the body domain main chip has three control pins, namely a first control pin, a second control pin and a third control pin, and the first control pin, the second control pin and the third control pin are all connected to the first peripheral chip, the second peripheral chip and the third peripheral chip at the same time.

[0010] More preferably, the body domain main chip has three sampling ports, namely a first sampling port, a second sampling port and a third sampling port. The first sampling port is connected to the first peripheral chip, the second sampling port is connected to the second peripheral chip, and the third sampling port is connected to the third peripheral chip.

[0011] More preferably, the body domain main chip has four digital quantity acquisition pins, namely a first digital quantity acquisition pin, a second digital quantity acquisition pin, a third digital quantity acquisition pin and a fourth digital quantity acquisition pin.

[0012] The method for realizing the high-speed mixed acquisition function of multi-channel analog signals or digital signals by using the above system is mainly characterized in that the method comprises the following steps:

[0013] (1) Determine whether to start a new round of sampling. If yes, proceed to step (2); otherwise, proceed to step (1);

[0014] (2) Start a benchmark time slice;

[0015] (3) Execute tasks within the time slice;

[0016] (4) Determine whether there is a task in the next time slice. If yes, proceed to step (3); otherwise, proceed to step (5);

[0017] (5) No operation is performed on the idle time slice;

[0018] (6) Determine whether there are no remaining idle time slices. If so, continue with step (1); otherwise, continue with step (5).

[0019] Preferably, the step of executing the task within the time slice of step (3) includes two acquisition methods, namely, a method of directly acquiring the input quantity or a method of acquiring the input quantity through a parallel-to-serial peripheral chip. The two acquisition methods can be performed separately or simultaneously.

[0020] Preferably, the method of collecting input quantities through a parallel-to-serial peripheral chip specifically includes the following steps:

[0021] (1-1) Operate the task of the control foot and switch channels;

[0022] (1-2) Configure multiple consecutive time slices according to the stabilization time required by the circuit, and wait for the current and voltage to stabilize;

[0023] (1-3) Sample the digital or analog quantity passing through the peripheral chip.

[0024] Preferably, the acquisition method of directly acquiring the input quantity is specifically: acquiring part of the digital quantity or acquiring part of the analog quantity.

[0025] The main feature of the device for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals is that the device comprises:

[0026] a processor configured to execute computer executable instructions;

[0027] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals are implemented.

[0028] The main feature of the processor for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals is that the processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals are implemented.

[0029] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals.

[0030] The system, method, device, processor and storage medium thereof for realizing high-speed mixed acquisition of multiple analog signals or digital signals of the present invention are adopted. The mixed sampling of analog and digital quantities reduces the resource demand for MCU sampling pins and makes full use of the resources of peripheral chips. The time slice management method achieves the effect of reducing time and reducing the resource consumption of MCU. The method can reduce the overall acquisition time and peripheral chips while jointly acquiring analog and digital quantities. Thereby reducing the resource consumption of MCU and saving hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The present invention is a circuit connection diagram of a system for realizing a high-speed mixed acquisition function of multiple analog signals or digital signals.

[0032] Figure 2 The present invention is a flow chart for scheduling sampling objects of the method for realizing the high-speed mixed acquisition function of multi-channel analog signals or digital signals.

[0033] Figure 3 The diagram is a schematic diagram of tasks within a time slice of the method for realizing the high-speed mixed acquisition function of multi-channel analog signals or digital signals of the present invention. DETAILED DESCRIPTION

[0034] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0035] The system of the present invention for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals includes a body domain main chip and multiple peripheral chips, wherein the body domain main chip is respectively connected to the multiple peripheral chips, and the body domain main chip has multiple control pins and multiple sampling ports, each of the control pins is simultaneously connected to the multiple peripheral chips, and each of the sampling ports is correspondingly connected to a peripheral chip, the control pin is used to transmit the control signal of the body domain main chip to the peripheral chip, and the sampling port is used to collect the input quantity of the peripheral chip; each of the peripheral chips has multiple interfaces, which are respectively connected to analog signals, three-state switch signals and digital signals, and each of the peripheral chips controls the connection between the interface of the peripheral chip and the corresponding sampling port through the control signal transmitted by the body domain main chip.

[0036] As a preferred embodiment of the present invention, the body domain main chip also has a plurality of digital quantity acquisition pins for sampling input digital quantities.

[0037] As a preferred embodiment of the present invention, the multiple peripheral chips are respectively a first peripheral chip, a second peripheral chip and a third peripheral chip, the body domain main chip has three control pins, namely a first control pin, a second control pin and a third control pin, and the first control pin, the second control pin and the third control pin are all connected to the first peripheral chip, the second peripheral chip and the third peripheral chip at the same time.

[0038] As a preferred embodiment of the present invention, the body domain main chip has three sampling ports, namely a first sampling port, a second sampling port and a third sampling port. The first sampling port is connected to the first peripheral chip, the second sampling port is connected to the second peripheral chip, and the third sampling port is connected to the third peripheral chip.

[0039] As a preferred embodiment of the present invention, the body domain main chip has four digital quantity acquisition pins, namely a first digital quantity acquisition pin, a second digital quantity acquisition pin, a third digital quantity acquisition pin and a fourth digital quantity acquisition pin.

[0040] The method of the present invention using the above system to realize the high-speed mixed acquisition function of multiple analog signals or digital signals includes the following steps:

[0041] (1) Determine whether to start a new round of sampling. If yes, proceed to step (2); otherwise, proceed to step (1);

[0042] (2) Start a benchmark time slice;

[0043] (3) Execute tasks within the time slice;

[0044] (4) Determine whether there is a task in the next time slice. If yes, proceed to step (3); otherwise, proceed to step (5);

[0045] (5) No operation is performed on the idle time slice;

[0046] (6) Determine whether there are no remaining idle time slices. If so, continue with step (1); otherwise, continue with step (5).

[0047] As a preferred embodiment of the present invention, the step of executing the task within the time slice of step (3) includes two acquisition methods, namely, a method of directly acquiring the input quantity or a method of acquiring the input quantity through a parallel-to-serial peripheral chip. The two acquisition methods can be performed separately or simultaneously.

[0048] As a preferred embodiment of the present invention, the method of collecting input quantities by using a parallel-to-serial peripheral chip specifically includes the following steps:

[0049] (1-1) Operate the task of the control foot and switch channels;

[0050] (1-2) Configure multiple consecutive time slices according to the stabilization time required by the circuit, and wait for the current and voltage to stabilize;

[0051] (1-3) Sample the digital or analog quantity passing through the peripheral chip.

[0052] As a preferred embodiment of the present invention, the acquisition method of directly acquiring the input quantity is specifically: acquiring part of the digital quantity or acquiring part of the analog quantity.

[0053] The device for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals of the present invention comprises:

[0054] a processor configured to execute computer executable instructions;

[0055] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals are implemented.

[0056] The processor of the present invention is used to realize the high-speed mixed acquisition function of multiple analog signals or digital signals, wherein the processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the above-mentioned method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals are realized.

[0057] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the above-mentioned method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals.

[0058] In a specific embodiment of the present invention, a method for high-speed mixed acquisition of multi-channel analog / digital signals is provided, including: introducing a parallel-to-serial peripheral chip; simultaneously mixing and sampling analog quantities and digital quantities; and simultaneously performing non-mutually exclusive steps in sampling through time slice allocation.

[0059] The mixed sampling step of analog quantity and digital quantity includes the following processing procedures: a threshold judgment method for converting analog quantity to digital quantity; and a group control method for converting parallel to serial sampling.

[0060] The steps of reducing the time required for sampling by allocating time slices include the following processing procedures: direct sampling is not affected by serialization and is performed simultaneously with the steps of serial sampling; unified control pin switching of serial sampling reduces the time required for switching channels.

[0061] To achieve this function, the following processing is required:

[0062] Different signal quantities are grouped and digital signals are filled in when there is space in the parallel-to-serial peripheral chip; when the number of controlled objects changes, the number of group members is maintained;

[0063] The samples of the control objects with different time precision are grouped again, and the members of each group are numbered according to the sampling order. When the time precision of the control object changes, the number of groups is maintained;

[0064] For the control pins of parallel-to-serial conversion, they are managed together in parallel;

[0065] The sampling time with the lowest sampling accuracy is used as the sampling start time. When sampling starts, a reference time slice is started. The time slice contains four types of functions: analog input signal connected by the control pin switching, current and voltage stabilization waiting, analog quantity sampling implementation and digital quantity sampling implementation.

[0066] According to the above method, it can be seen that the time precision grouping can be configured according to actual needs, and members can also be added or deleted according to actual needs; high-precision time is executed first, and low-precision time is executed in the remaining time.

[0067] like Figure 1 Shown is a schematic diagram of external circuit connections:

[0068] S101, as a peripheral parallel-to-serial chip, is connected to three signals: analog, three-state switch, and digital. The connection between Y and sampling port Z is switched by the control signal sent by the main chip. The three control pins can have 8 values, corresponding to the connection between Y0 and sampling port Z1 to the connection between Y7 and sampling port Z1. When the control pin is 000, that is, all 7 peripherals are connected to the main chip at Y0, and are in a state that can be collected. When the control pin switches the remaining value, it represents the connection between Y2 to Y7.

[0069] S102, as the main chip of the body domain, it traverses all Y, that is, all input quantities, by sending three control signals. The original 28 sampling pins required, even the 14 pins required for the conventional parallel-to-serial conversion of the same type, are reduced to 10 pins, namely 3 control pins, 3 sampling pins supporting analog quantities, and 4 digital quantity acquisition pins.

[0070] In such Figure 1 In the illustrated embodiment, the first peripheral chip, the second peripheral chip and the third peripheral chip each receive six analog signals, the first peripheral chip and the second peripheral chip each receive one three-state switch signal, the first peripheral chip and the second peripheral chip each receive one digital signal, and the third peripheral chip receives two digital signals.

[0071] like Figure 2 The figure shows a scheduling flow chart of an AD sampling object, which includes the following steps:

[0072] S201, determine whether sampling needs to be started;

[0073] S202, when sampling starts, start a reference time slice;

[0074] S203, executing tasks within the time slice;

[0075] S204. If there are still tasks in the next time slice, return to S203;

[0076] S205, idle time slice, no operation content;

[0077] S206, no operation is performed in the remaining idle time slices of the software main cycle;

[0078] S207, waiting for the end of the main cycle of the software, that is, all idle time slices are used up and returning to S201.

[0079] like Figure 3 FIG. 1 is a schematic diagram of tasks within a time slice of the present invention, wherein the following steps are included:

[0080] S301 is direct acquisition, which is the direct acquisition of the input quantity directly connected to the MCU. Because it is a direct connection, it can be placed in any time slice, and the two operations can be collected at the same time.

[0081] S302, for the acquisition through the parallel-to-serial peripheral chip, due to the non-direct connection, the three internal operations cannot be put into the same time slice and need to be executed in sequence. The acquisition object is a mixture of digital and analog quantities.

[0082] S303 is an overview of the on-chip tasks. The two collection methods can be performed simultaneously, that is, the on-chip tasks in sampling method 1 can be put into the same time slice as any on-chip tasks in sampling method 2 to reduce the total collection time.

[0083] S304, the task of operating the control pins, if the values ​​of the three control pins are 000, the corresponding 8-to-1 peripheral chip connects the port numbered Y0 to the main chip. Figure 1 Parallel control, that is, the Y0 of all peripherals are connected to the MCU at this time.

[0084] S305, waiting for the current and voltage to stabilize. Prevent inaccurate sampling caused by the charging and discharging of capacitors and inductors when switching connections due to circuit characteristics. The waiting process can configure multiple continuous time slices according to the stabilization time required by the specific circuit. If the control signals are in parallel, the waiting time is also executed simultaneously.

[0085] S306, sampling the input quantity through the peripheral chip. Since the digital quantity also uses the analog AD sampling port, it is necessary to add a threshold judgment to convert it from analog to digital. And the threshold can be accurately adjusted or filtering can be added to adapt to the digital input in a harsh working environment. The mixed sampling of digital and analog in the same time slice speeds up the sampling speed. When all the sampling in this main cycle is completed, the remaining time is idle time, and there is no task until the main cycle is entered again to determine whether to sample again.

[0086] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0087] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0088] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0089] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0090] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0091] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0092] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0093] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] The system, method, device, processor and storage medium thereof for realizing high-speed mixed acquisition of multiple analog signals or digital signals of the present invention are adopted. The mixed sampling of analog and digital quantities reduces the resource demand for MCU sampling pins and makes full use of the resources of peripheral chips. The time slice management method achieves the effect of reducing time and reducing the resource consumption of MCU. The method can reduce the overall acquisition time and peripheral chips while jointly acquiring analog and digital quantities. Thereby reducing the resource consumption of MCU and saving hardware costs.

[0096] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for realizing a high-speed mixed acquisition function of multiple analog signals or digital signals in a system based on a high-speed mixed acquisition function of multiple analog signals or digital signals, the system comprising a body domain main chip and multiple peripheral chips, the body domain main chip being connected to the multiple peripheral chips respectively, the body domain main chip having multiple control pins and multiple sampling ports, each of the control pins being connected to the multiple peripheral chips at the same time, each of the sampling ports being connected to a corresponding peripheral chip, the control pin being used to transmit a control signal from the body domain main chip to the peripheral chip, and the sampling port being used to collect the input quantity of the peripheral chip; each of the peripheral chips having multiple interfaces, respectively connected to analog signals, three-state switch signals and digital signals, each of the peripheral chips controlling the connection between the interface of the peripheral chip and the corresponding sampling port through the control signal transmitted by the body domain main chip, characterized in that The method comprises the following steps: (1) Determine whether to start a new round of sampling. If yes, proceed to step (2); otherwise, proceed to step (1); (2) Start a benchmark time slice; (3) Execute tasks within the time slice; (4) Determine whether there is a task in the next time slice. If yes, proceed to step (3); otherwise, proceed to step (5); (5) No operation is performed on the idle time slice; (6) Determine whether there are no remaining idle time slices. If so, continue with step (1); otherwise, continue with step (5); The step of executing the task within the time slice of step (3) includes two acquisition modes, namely, a mode of directly acquiring the input quantity or a mode of acquiring the input quantity through a parallel-to-serial peripheral chip. The two acquisition modes can be performed separately or simultaneously. The method of collecting input quantities through a parallel-to-serial peripheral chip specifically includes the following steps: (1-1) Operate the task of the control foot and switch channels; (1-2) Configure multiple consecutive time slices according to the stabilization time required by the circuit, and wait for the current and voltage to stabilize; (1-3) Sample the digital or analog quantity passing through the peripheral chip.

2. The method for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals according to claim 1, characterized in that: The method of directly collecting input quantities is specifically: collecting part of the digital quantities or collecting part of the analog quantities.

3. The method for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals according to claim 1, characterized in that: The body domain main chip also has a plurality of digital quantity acquisition pins for sampling input digital quantities.

4. The method for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals according to claim 1, characterized in that: The multiple peripheral chips are respectively a first peripheral chip, a second peripheral chip and a third peripheral chip. The body domain main chip has three control pins, namely a first control pin, a second control pin and a third control pin. The first control pin, the second control pin and the third control pin are all connected to the first peripheral chip, the second peripheral chip and the third peripheral chip at the same time.

5. The method for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals according to claim 4, characterized in that: The body domain main chip has three sampling ports, namely the first sampling port, the second sampling port and the third sampling port. The first sampling port is connected to the first peripheral chip, the second sampling port is connected to the second peripheral chip, and the third sampling port is connected to the third peripheral chip.

6. The method for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals according to claim 3, characterized in that: The body domain main chip has four digital quantity acquisition pins, namely a first digital quantity acquisition pin, a second digital quantity acquisition pin, a third digital quantity acquisition pin and a fourth digital quantity acquisition pin.

7. A device for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals, characterized in that: The device comprises: a processor configured to execute computer executable instructions; A memory storing one or more computer executable instructions, wherein when the computer executable instructions are executed by the processor, the steps of the method for realizing high-speed mixed acquisition function of multiple analog signals or digital signals described in any one of claims 1 to 2 are implemented.

8. A processor for realizing high-speed mixed acquisition of multi-channel analog signals or digital signals, characterized in that: The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for realizing high-speed mixed acquisition function of multiple analog signals or digital signals described in any one of claims 1 to 2 are implemented.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for realizing the high-speed mixed acquisition function of multiple analog signals or digital signals as described in any one of claims 1 to 2.

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