Dual-mode average power tracking (APT) controller

Abstract

A dual-mode average power point tracking (APT) controller operates in a first mode to rapidly move the control voltage without regard to ripple or ringing. When this coarse adjustment brings the control voltage within the desired margin of the target, the controller can switch to a second mode, where the APT controller approaches the target more slowly but with reduced ringing or ripple. This mode is changed by altering the resistance and capacitance values ​​in the loop filter within the APT circuit. Alternatively, a pulse shaper circuit can inject pulses to force the control voltage to change more rapidly. By switching modes in this way, the control voltage can quickly reach the desired target and then remain in the second mode during the transmission time slot, ensuring the control voltage remains clean throughout.

Description

Technical Field

[0001] The technology disclosed herein generally relates to average power tracking (APT) in wireless communication devices. Background Technology

[0002] Mobile communication devices have become increasingly common in today's society. The popularity of these devices is partly driven by the many features currently enabled on them. The increased processing power in these devices means that they have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

[0003] The redefined user experience requires higher data rates provided by wireless communication technologies such as Wi-Fi, LTE, and 5G-NR. Partly due to its operating frequency, 5G-NR implements strict power control schemes and frequently changes the transmit power level. These frequent changes in transmit power level necessitate the ability to rapidly adjust the output of the power amplifier array, typically achieved through some form of envelope tracking (ET) or average power tracking (APT). Even with ET and APT methods, frequent power level changes require frequent adjustments to the control signals sent to the power amplifier array.

[0004] Traditional methods for rapidly changing control signals generated by ET and APT circuits involve altering the size of capacitors and inductors in the control circuit, specifically reducing their size, which typically results in faster control signal changes. However, reducing the size of capacitors and inductors can introduce other unwanted ripples into the control signal. Therefore, improved control techniques are necessary. Summary of the Invention

[0005] The aspect disclosed in the specific embodiment includes a dual-mode average power point tracking (APT) controller. In a first mode, the APT controller operates to rapidly move the control voltage, regardless of ripple or ringing. When this coarse adjustment brings the control voltage within the desired margin of the target, the controller can switch to a second mode, in which the APT controller approaches the target more slowly but with reduced ringing or ripple. The mode is changed by altering the resistance and capacitance values ​​in the loop filter within the APT circuit. In another aspect, a pulse shaper circuit can inject pulses to force the control voltage to change more rapidly. By switching modes in this way, the control voltage can quickly reach the desired target and then remain in the second mode during the transmission time slot, ensuring the control voltage remains clean at all times.

[0006] In one aspect, an APT circuit is disclosed. The APT circuit includes a digital-to-analog converter (DAC). The DAC includes a changing signal output and a target control voltage signal output. The APT circuit also includes conversion management circuitry coupled to the changing signal output and including a mode output configured to provide a mode signal. The APT circuit also includes a loop filter coupled to the target control voltage signal output and the mode output. A change in the mode signal causes the loop filter to switch between a first mode and a second mode, and the loop filter is configured to provide a signal. The APT circuit also includes an output circuitry system configured to provide a voltage control signal based on the signal from the loop filter.

[0007] Those skilled in the art will understand the scope of this disclosure and recognize its additional aspects after reading the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0009] Figure 1 This is a block diagram of a conventional average power point tracking (APT) circuit;

[0010] Figure 2A The control signals and frequency response for a conventional APT circuit are shown.

[0011] Figure 2B The control signals and frequency response of a conventional APT circuit used for acceleration are shown.

[0012] Figure 3 This is a block diagram of a dual-mode APT circuit according to an exemplary aspect of this disclosure;

[0013] Figure 4 Showing the use of Figure 3 The control signals and frequency response of the APT circuit;

[0014] Figure 5 This is a signal and timing diagram showing how the control signals of the dual-mode APT circuit are compared with the control signals from the conventional APT circuit;

[0015] Figure 6 It is a block diagram of a dual-mode APT circuit having a pulse shaper circuit added according to an exemplary aspect of this disclosure;

[0016] Figure 7A This is a circuit diagram of an exemplary loop filter circuit with variable resistors and capacitors modified according to a pattern, based on an exemplary aspect of this disclosure; and

[0017] Figure 7B This is a circuit diagram of an exemplary loop filter having multiple resistors and capacitors according to an exemplary aspect of this disclosure, wherein switches are selected therebetween according to a mode. Detailed Implementation

[0018] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best manner in which the embodiments are practiced. Those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts not specifically set forth herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0019] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerations.

[0020] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or extends "to another element," it may be directly on or directly extended onto the other element, or intermediate elements may also exist. In contrast, when an element is referred to as "directly on another element" or "directly extended onto another element," no intermediate elements exist. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extends over another element," it may be directly on or directly extended over the other element, or intermediate elements may also exist. In contrast, when an element is referred to as "directly on top of another element" or "extends directly over another element," no intermediate elements exist. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may exist. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0021] In this document, relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” or “vertical” may be used to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, these terms and those discussed above are intended to cover different orientations of the device.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0023] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0024] The aspect disclosed in the specific embodiment includes a dual-mode average power point tracking (APT) controller. In a first mode, the APT controller operates to rapidly move the control voltage, regardless of ripple or ringing. When this coarse adjustment brings the control voltage within the desired margin of the target, the controller can switch to a second mode, in which the APT controller approaches the target more slowly but with reduced ringing or ripple. The mode is changed by altering the resistance and capacitance values ​​in the loop filter within the APT circuit. In another aspect, a pulse shaper circuit can inject pulses to force the control voltage to change more rapidly. By switching modes in this way, the control voltage can quickly reach the desired target and then remain in the second mode during the transmission time slot, ensuring the control voltage remains clean at all times.

[0025] In this regard, Figure 1This diagram illustrates a conventional APT circuit 10. The APT circuit 10 includes a digital-to-analog converter (DAC) 12. DAC 12 includes an input 14 (which may be a well-known pin or node) that receives a digital signal 16 from an envelope tracking (ET) circuit (not shown). DAC 12 converts the digital signal 16 into an analog target control voltage signal 18. Adder 20 adds the target control voltage signal 18 to an inverting (negative) feedback signal 22. Adder 20 is coupled to a loop filter 24. Loop filter 24 may also include a controller (not shown) and / or an error amplifier (also not shown). Loop filter 24 filters the signal 26 from adder 20 to produce a signal 28. Signal 28 is provided to a switch control circuit 30, which turns switches in a switch array circuit 32 on and off based on signal 28. Switch control circuit 30 represents the function of sequencing the closing of various power switches in switch array circuit 32 to control the output of switch array circuit 32. In an exemplary aspect, the switch control circuit 30 may be a pulse width modulation (PWM) modulator. The output of the switch array circuit 32 is filtered by an inductor 34 and a capacitor 36 to provide a voltage control signal 38 (also referred to as Vcc), which is used to control a power amplifier in a transmitter (not shown). The voltage control signal 38 is also provided to a feedback circuit 40, which provides a feedback signal 22 to an adder 20.

[0026] For example, the new 5G cellular standard changes the RF output power control scheme, resulting in more frequent power changes, especially compared to previous cellular standards. For instance, 5G-NR may experience power changes within 8.3 microseconds (μs) with a subcarrier spacing (SCS) of 120 kHz. Therefore, when power level changes occur, the power amplifier voltage must stabilize very quickly. This rapid transition is challenging for an APT where Vcc should only change when a power change is required, while maintaining a stable Vcc during invariant time slots.

[0027] In a conventional system, for a given load and assuming “ideal” control of the switches in the switch array circuit 32, the limitation on how quickly Vcc can change is the capacitance of capacitor 36 and the charging rate of the capacitor (i.e., how quickly current can be “injected” into capacitor 36). The charging rate is a function of inductor 34, where the rate increases as the inductance of inductor 34 decreases. Furthermore, the larger the voltage across inductor 34, the faster the current changes. Using a conventional system may result in... Figure 2A The slow stabilization seen in Figure 50 shows that Vcc requires time Tsettle to reach a lower threshold 52, and even longer to reach the final target level 54. This slowing approach to the final target level 54 results in relatively low ringing in the frequency domain, as demonstrated by spurious emissions 56.

[0028] While one way to achieve fast APT conversion is to reduce the inductance and capacitance of inductor 34 and capacitor 36, reducing these values ​​will increase ripple or ringing at harmonics. Using this method will result in... Figure 2B The graph 60 shown illustrates this, where Vcc reaches a lower threshold 62 relatively quickly, as indicated by a small Tsettle, but exhibits ripple 64 before stabilizing at the final target level 66. Similarly, there is considerable ringing, as indicated by spurious signals 68. The presence of this ripple necessitates increasing the switching frequency to limit it. The end result of this approach negatively impacts noise performance and efficiency, making this solution commercially impractical for 5G-NR.

[0029] An exemplary aspect of this disclosure employs a dual-mode approach, wherein a first fast mode, but which may cause ringing or ripple, is used for coarse adjustment, rapidly changing Vcc to a value within a predefined threshold of the target Vcc value; and a second slowing mode is used to provide clean, non-ringing, but relatively slow Vcc fine-tuning, which changes Vcc to the final target Vcc value and cleanly maintains Vcc at this final target for the desired duration (e.g., in a "time slot"). To switch between modes, the loop filter circuitry is modified. In a particularly anticipated aspect, the resistance and / or capacitance within the loop filter are changed. In another aspect, a pulse shaper circuit may be used to inject hard pulses to help change the input of the switching control circuitry to the desired target value.

[0030] In this regard, Figure 3The diagram describes an APT circuit 80 containing a DAC 82. The DAC 82 includes an input 84 (which may be a well-known pin or node) that receives a digital signal 86 from an ET circuit (not shown). The DAC 82 converts the digital signal 86 into an analog target control voltage signal 88 at a target control voltage signal output 89 (which may also be a pin or node). An adder 90 (equivalent to an adder circuit) adds the target control voltage signal 88 to an inverting (negative) feedback signal 92. The adder 90 is coupled to a loop filter 94, and therefore the loop filter 94 is indirectly coupled to the target control voltage signal output 89. The loop filter 94 may also include a controller (not shown) and / or an error amplifier (also not shown). The loop filter 94 filters the signal 96 from the adder 90 to produce a signal 98. The signal 98 is provided to a switch control circuit 100, which turns the switches in a switch array circuit 102 on and off based on the signal 98. The switch control circuit 100 represents the function of sequencing the closing of various power switches in the switch array circuit 102 to control the output of the switch array circuit 102. In an exemplary aspect, the switch control circuit 100 may be a PWM modulator. The output of the switch array circuit 102 is filtered by an inductor 104 and a capacitor 106 to provide a voltage control signal 108 (also referred to as Vcc) at an output 109 (which may also be a pin or node). The voltage control signal 108 is used to control a power amplifier in a transmitter (not shown). The voltage control signal 108 is also provided to a feedback circuit 110, which provides a feedback signal 92 to an adder 90. The switch control circuit 100, the switch array circuit 102, and the filter formed by the inductor 104 and the capacitor 106 can be collectively considered as an output circuit system configured to provide the voltage control signal 108 based on the signal 98 at the output 109. The components of the output circuit system may be varied without departing from the scope of this disclosure.

[0031] Continue to refer to Figure 3 DAC 82 also includes a change signal output 112 (which may also be a pin or node) that provides a signal 114 indicating a change in the state of DAC 82. In an exemplary aspect, signal 114 is generated whenever the state of DAC 82 changes. Alternatively, signal 114 may be generated only when the state change exceeds a predefined threshold. Signal 114 may contain information relating not only to the presence of a state change, but also to the magnitude and direction of the change. The state change of DAC 82 indicates a desired change in voltage control signal 108, and therefore small changes required in voltage control signal 108 may not require the implementation of the fast mode of this disclosure.

[0032] A conversion management circuit 116 is coupled to a change signal output 112 to receive a signal 114. The conversion management circuit 116 is configured to provide a mode signal 118 to a loop filter 94. Based on the mode signal 118, the loop filter 94 can switch between a first mode (i.e., a fast mode) and a second mode (i.e., a slow mode). Figure 4 The difference in modes is illustrated. Specifically, graph 130 shows that Vcc rises rapidly in the first mode 132 until it reaches a threshold 134, at which point the mode signal 118 causes the loop filter 94 to change to the second mode 136. The second mode allows Vcc to slowly stabilize to the target value 138, effectively without ripple and, as demonstrated by spectrum graph 140, with very little or no problematic ringing 142.

[0033] Figure 5 Figure 150 shows exemplary test results comparing the dual-mode method of this disclosure with a conventional system, where the first mode 132 lasts for approximately 65.25 μs to 66 μs (or approximately 0.75 μs), after which the second mode 136 begins. Vcc 152 reaches the region near the target Vcc value much faster than the Vcc baseline 154 of conventional methods. A signal 114 from DAC 82 is also included to illustrate the transition relative to changes in DAC 82.

[0034] Figure 6 An alternative approach is provided, in which a pulse shaper circuit 160 is added to the APT circuit 80'. The pulse shaper circuit 160 is coupled to an adder 162 (equivalently, an adder circuit or a second adder circuit), which is located between the loop filter 94 and the switch control circuit 100. The pulse shaper circuit 160 can inject voltage spurious signals or other pulse signals 164 (positive or negative) through the adder 162 to facilitate faster changes in Vcc.

[0035] In an exemplary aspect, the pulse shaper circuit 160 is controlled by the conversion management circuit 116 and may have a programmable duration period. That is, the height and / or length of the pulse to be injected can be varied. The programmable duration period can be a function of the battery voltage and / or voltage step changes. For example, if there is a relatively small voltage step change of one volt (1V), a pulse smaller (in magnitude and / or duration) can be applied than if there is a relatively large step change of three volts (3V).

[0036] Although the loop filter 94 can take any number of forms, including, for example, type I, II, or III loop filters, most such filters include one or more resistors and one or more capacitors. Exemplary aspects of this disclosure vary these resistors and capacitors to switch between a first mode and a second mode. In the first exemplary aspect, as... Figure 7AThe description above uses a variable resistor. In the second exemplary aspect, a switch is used to switch between resistors and / or capacitors with different values, such as... Figure 7B As explained in the text.

[0037] In this regard, Figure 7A This describes a loop filter 94A with variable capacitors 180(1)-180(N) and variable resistors 182(2)-182(N). Mode signal 118 changes the value of the variable elements.

[0038] same, Figure 7B Loop filter 94B is described, which has switches 190(1)-190(N) that can be used to switch between different capacitors and resistors. It should be noted that, as described, switch 190(N) only allows switching of resistors while keeping the associated capacitor constant. Other switching arrangements are also possible. Similar to loop filter 94A, mode signal 118 causes switches 190(1)-190(N) to open and close to switch between a first mode and a second mode.

[0039] Those skilled in the art will recognize improvements and modifications to the embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. An average power point tracking (APT) circuit, comprising: Digital-to-analog converters (DACs) include: Change signal output; and Target control voltage signal output; A conversion management circuit, coupled to the change signal output and including a mode output configured to provide a mode signal; A loop filter coupled to the target control voltage signal output and the mode output, wherein changes in the mode signal cause the loop filter to switch between a first mode and a second mode, and wherein the loop filter is configured to provide a signal, wherein the first mode includes a fast mode and the second mode includes a slow mode, wherein the fast mode changes the signal faster than the slow mode; and An output circuit system configured to provide a voltage control signal based on the signal from the loop filter.

2. The APT circuit according to claim 1, wherein the output circuit system comprises: A switch control circuit coupled to the loop filter and the conversion management circuit, the switch control circuit being configured to receive the signal from the loop filter; as well as A switch array circuit includes a plurality of power switches coupled to the switch control circuit, wherein the switch control circuit is configured to control which of the plurality of power switches are turned on and which are turned off based on the signal.

3. The APT circuit according to claim 1, further comprising: An adder circuit is located between the DAC and the loop filter; as well as A feedback circuit, which is coupled to the adder circuit.

4. The APT circuit according to claim 1, further comprising a pulse shaper circuit, the pulse shaper circuit being coupled to the conversion management circuit and the target control voltage signal output.

5. The APT circuit of claim 4, further comprising a second adder circuit coupled to the loop filter and the pulse shaper circuit, wherein the pulse shaper circuit is configured to provide a pulse signal, which is added to the signal from the loop filter by the second adder circuit.

6. The APT circuit of claim 1, wherein the loop filter is configured to operate with a first resistor in the first mode and with a second resistor in the second mode, wherein the first resistor is not equal to the second resistor.

7. The APT circuit of claim 1, wherein the loop filter is configured to operate with a first capacitor in the first mode and with a second capacitor in the second mode, wherein the first capacitor is not equal to the second capacitor.

8. The APT circuit of claim 1, wherein the loop filter comprises at least one variable resistor.

9. The APT circuit of claim 1, wherein the loop filter comprises at least one variable capacitor.

10. The APT circuit of claim 1, wherein the loop filter comprises at least two resistors and a switch, the switch being configured to connect one or the other of the at least two resistors based on the signal.

11. The APT circuit of claim 1, wherein the loop filter comprises at least two capacitors and a switch, the switch being configured to connect one or the other of the at least two capacitors based on the signal.

12. The APT circuit of claim 1, wherein the conversion management circuit is configured to change the mode from the first mode to the second mode using the mode signal after one microsecond (1 μs) in the first mode.

13. The APT circuit of claim 1, wherein the conversion management circuit is configured to change the mode from the first mode to the second mode using the mode signal four microseconds (4 µs) prior to the first mode.

14. The APT circuit of claim 1, wherein the DAC further includes an input configured to receive a digital target voltage signal, and wherein the DAC is configured to provide a change signal at the change signal output when the digital target voltage signal changes.

15. The APT circuit of claim 1, wherein the DAC further includes an input configured to receive a digital target voltage signal, and wherein the DAC is configured to provide a change signal at the change signal output when the digital target voltage signal changes by more than a predefined threshold.

16. The APT circuit of claim 4, wherein the pulse shaper circuit is configured to have a programmable duration period.

17. The APT circuit of claim 16, wherein the programmable duration period is a function of the battery voltage.

18. The APT circuit of claim 16, wherein the programmable duration period is a function of a voltage step change.

19. An average power point tracking (APT) circuit, comprising: Digital-to-analog converters (DACs) include: Change signal output; and Target control voltage signal output; A conversion management circuit, coupled to the change signal output and including a mode output configured to provide a mode signal; A loop filter coupled to the target control voltage signal output and the mode output, wherein a change in the mode signal causes the loop filter to switch between a first mode and a second mode, and wherein the loop filter is configured to provide a signal; A pulse shaper circuit, the pulse shaper circuit being coupled to the conversion management circuit and the target control voltage signal output; and An output circuit system configured to provide a voltage control signal based on the signal from the loop filter.

20. An average power point tracking (APT) circuit, comprising: Digital-to-analog converters (DACs) include: Change signal output; and Target control voltage signal output; A conversion management circuit, coupled to the change signal output and including a mode output configured to provide a mode signal; A loop filter coupled to the target control voltage signal output and the mode output, wherein changes in the mode signal cause the loop filter to switch between a first mode and a second mode, and wherein the loop filter is configured to provide a signal; and An output circuit system configured to provide a voltage control signal based on the signal from the loop filter, wherein the output circuit system includes: A switch control circuit coupled to the loop filter and the conversion management circuit, the switch control circuit being configured to receive the signal from the loop filter; and A switch array circuit includes a plurality of power switches coupled to the switch control circuit, wherein the switch control circuit is configured to control which of the plurality of power switches are turned on and which are turned off based on the signal.

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