Hardware for parallel sine and cosine determination

Abstract

Apparatus and techniques for hardware for performing parallel sine and cosine determination are described herein. A first bit sequence representing an angle of a line from an origin to a unit circle is obtained. A quadrant of the unit circle for the line is determined, and two least significant bits of the first bit sequence are replaced with an encoding of the quadrant, converting the angle to a base quadrant angle, and performing sine and cosine operations on a portion of a second bit sequence (derived from the first bit sequence) to create intermediate sine and cosine solutions in the base quadrant. Then, using the quadrant encoding in the first bit sequence, final sine and cosine solutions in the quadrant are created from the intermediate solutions.

Description

[0001] Statement regarding government support

[0002] This invention was made with government support under DARPA Agreement No. HR0011-19-3-0002. The government enjoys certain rights in this invention.

[0003] Priority Claim

[0004] This patent application claims priority to U.S. Provisional Application No. 63 / 168,116, filed March 30, 2021, entitled “Hardware for Concurrent Sin and Cosine Determination”, 35 USC §119, the entire contents of which are hereby incorporated herein by reference. Technical Field

[0005] This disclosure relates to hardware for parallel sine and cosine determination. Background Technology

[0006] For example, various computer architectures based on the von Neumann architecture conventionally use shared memory for data, buses for accessing shared memory, arithmetic units, and program control units. However, moving data between the processor and memory can be time-consuming and energy-intensive, which can constrain the performance and capacity of computer systems. Given these limitations, new computing architectures and devices are needed to drive computing performance beyond the transistor scale (i.e., Moore's Law). Summary of the Invention

[0007] On one hand, this disclosure provides an apparatus comprising: a first port for a first channel having a bit width; a second port for a second channel having the same width as the first channel, wherein the apparatus is part of a Hybrid Threaded Architecture (HTF), and wherein the first channel and the second channel are channels of the HTF; and a processing circuitry configured to: obtain from the first port a first bit sequence representing the angle of a line from the origin to a unit circle; determine the quadrant of the unit circle of the line; replace the two least significant bits of the first bit sequence with an encoding of the quadrant; and, in a process of length equal to the first bit sequence... In the second bit sequence, the angle is reduced to the base quadrant angle; sine and cosine operations are performed on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant; the encoding of the quadrant in the first bit sequence is used on the intermediate sine and intermediate cosine solutions to create final sine and final cosine solutions in the quadrant; and a third bit sequence representing the final sine and final cosine solutions is output, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on the second port, and wherein the width of all channels of the HTF is equal to that of the first bit sequence.

[0008] On the other hand, this disclosure further provides a machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations including: obtaining a first bit sequence representing the angle of a line from the origin to a unit circle, wherein the processing circuitry system is part of a hybrid threaded architecture (HTF), wherein the first bit sequence is obtained from a first channel of the HTF; determining the quadrant of the unit circle of the line; replacing the two least significant bits of the first bit sequence with the encoding of the quadrant; and reducing the angle to the base quadrant in a second bit sequence of the same length as the first bit sequence. Angle; performing sine and cosine operations on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant; using the encoding of the quadrant in the first bit sequence on the intermediate sine and intermediate cosine solutions to create final sine and final cosine solutions in the quadrant; and outputting a third bit sequence representing the final sine and final cosine solutions, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on a second channel of the HTF, and wherein the width of all channels of the HTF is equal to the width of the first bit sequence. Attached Figure Description

[0009] To facilitate identification of any particular element or action, one or more of the most significant digits in the reference numerals refer to the figure number in which the element is first introduced.

[0010] Figure 1 This generally illustrates a first example of a first memory computing device in the context of a memory computing system according to an embodiment.

[0011] Figure 2 An example of a memory subsystem of a memory computing device according to an embodiment is generally shown.

[0012] Figure 3 Examples of programmable atomic units for a memory controller according to embodiments are generally shown.

[0013] Figure 4 An example of a hybrid thread processor (HTP) accelerator for a memory computing device according to an embodiment is shown.

[0014] Figure 5 An example of a representation of a hybrid thread structure (HTF) of a memory computing device according to an embodiment is shown.

[0015] Figure 6 A unit circle with an angle and quadrant relationship to sine and cosine is shown according to an embodiment.

[0016] Figure 7 An example of a data stream with a fixed width value passing through hardware used for parallel sine and cosine determination is shown according to an embodiment.

[0017] Figure 8A Examples of chiplet systems according to embodiments are generally shown.

[0018] Figure 8B Generally showing the display from Figure 8A A block diagram of the various components in an example chiplet system.

[0019] Figure 9 Examples of chiplet-based implementations for memory computing devices according to embodiments are generally shown.

[0020] Figure 10 An example of tiling of a memory computing device chip according to an embodiment is shown.

[0021] Figure 11 This is a flowchart illustrating an example of a method for determining parallel sine and cosine using hardware according to an embodiment.

[0022] Figure 12 A block diagram of an example machine is shown, which may be used, in, or through which any one or more techniques (e.g., methods) discussed herein may be implemented. Detailed Implementation

[0023] Recent advances in materials, devices, and integration technologies can be leveraged to provide memory-centric computing topologies. Such topologies enable advancements in computational efficiency and workload handling for applications constrained by size, weight, or power requirements. Topologies can facilitate low-latency computing in or near memory or other data storage elements. The approach is particularly well-suited for various computationally intensive operations utilizing sparse lookups, such as in transform computations (e.g., Fast Fourier Transform (FFT) computations), or in applications such as neural networks or artificial intelligence (AI), financial analysis, or simulation or modeling, for example, computational fluid dynamics (CFD), engineer-as-a-system (EASE) augmented acoustic simulators, integrated circuit-centric simulation programs (SPICE), etc.

[0024] The systems, apparatuses, and methods discussed herein may include or utilize memory computing systems with processors or processing capabilities provided in, near, or integrated with memory or data storage components. Such systems are generally referred to herein as compute-near-memory (CNM) systems. CNM systems can be node-based systems, where individual nodes in the system are coupled using a system-scale architecture. Especially in environments where high cache miss rates are expected, each node may include or utilize a dedicated or general-purpose processor and a user-accessible accelerator (with a custom computational architecture to facilitate intensive operations).

[0025] In this example, each node in a CNM system can have one or more host processors. Within each node, a dedicated hybrid-threaded processor can occupy discrete endpoints of the on-chip network. The hybrid-threaded processor can access some or all of the memory in a specific node of the system, or it can access the memory of a network spanning multiple nodes via a system-scale architecture. Custom computational architectures or hybrid-threaded architectures at each node can have their own processors or accelerators and can operate at higher bandwidths than the hybrid-threaded processors. Different nodes in a near-memory computing system can be configured differently, for example, with different computational capabilities, different types of memory, different interfaces, or other differences. However, nodes can be coupled together to share data and computational resources within a defined address space.

[0026] In this example, near-memory computing systems or nodes within a system can be user-configurable for custom operations. Users can provide instructions using a high-level programming language (e.g., C / C++), which can be compiled and directly mapped to the dataflow architecture of one or more nodes in the system or CNM system. That is, nodes in the system can contain hardware blocks (e.g., memory controllers, atomic cells, other client accelerators, etc.) that can be configured to directly implement or support user instructions to thereby enhance system performance and reduce latency.

[0027] In practice, near-memory computing systems are particularly well-suited for implementing hierarchical structures of instructions and nested loops (e.g., two, three, or more loop depths, or multidimensional loops). Standard compilers can be used to accept high-level language instructions and compile them directly into one or more dataflow architectures within a node. For example, nodes in the system can contain hybrid threading accelerators. These hybrid threading accelerators can execute in the user space of the CNM system and can initiate their own threads or sub-threads that can operate in parallel. Each thread can be mapped to a different loop iteration, thereby supporting multidimensional loops. Leveraging the ability to initiate such nested loops, along with other capabilities, CNM systems can achieve significant time savings and latency improvements for computationally intensive operations.

[0028] Near-memory computing systems, or nodes or components of near-memory computing systems, may include or utilize various memory devices, controllers, and interconnects, etc. In examples, the system may include various interconnect nodes, and nodes or groups of nodes may be implemented using chiplets. Chiplets are an emerging technology for integrating various processing functionalities. Typically, chiplet systems consist of discrete chips (e.g., integrated circuits (ICs) on different substrates or dies) integrated on an interposer and packaged together. This arrangement differs from a single chip (e.g., an IC) containing different blocks of devices (e.g., blocks of intellectual property (IP)) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC), or discrete packaged devices integrated on a board. Generally, chiplets offer manufacturing benefits compared to single die chips, including higher yields or reduced development costs. The following discussion... Figure 8A and Figure 8B Examples of chiplet systems, such as near-memory computing systems, are generally shown.

[0029] Near-memory computing systems are well-suited for efficiently handling a wide range of workloads, especially those involving massive amounts of computation in parallel, such as signal processing, graphics rendering, and artificial intelligence. For example, a common operation performed in signal processing is Euler's formula. In calculating Euler's formula, parallel computation of the sine and cosine is useful for reducing computation time. For the received values... In a typical processing pipeline scenario where the input is used, the parallel computation of the formula would duplicate the value to calculate the cosine and sine separately. While effective, this approach can waste communication resources between processing components (e.g., lines, channels, buses, etc.), thereby reducing the overall efficiency of the hardware implementing the Euler formula calculation.

[0030] To address the hardware inefficiency of directly implementing Euler's formula, hardware can implement a technique to quantify which quadrant of the unit circle will yield a solution (e.g., based on the input value). The angle represented (and the input value is reduced, for example, halved) so that communication for processing cosine and sine can occur simultaneously. In practice, specific hardware (e.g., blocks, cells, etc.) can implement these functions to improve throughput. In practice, a special set of hardware operations can be used to avoid explicit branching operations, as branching is extremely inefficient for Single Instruction Multiple Data (SIMD) processing architectures (e.g., HTF as described herein).

[0031] For example, an HTF may include hardware to implement the instructions TruncLsbsF64, PMulIgnore2Lsbs, and NegCF32FromTruncLsbsF64 (all described below), which can be used to perform sine and cosine operations on double-precision values ​​simultaneously. These instructions reuse the two least significant bits of the operands to store the quadrant of the angle. When performing multiplication to obtain intermediate cosine and sine results, these two bits are ignored and then used to change the position (e.g., whether to retain the intermediate cosine and sine results or toggle them to each other) and sign (e.g., positive or negative) of the resulting value to obtain the final result. Since digital signal processing typically uses sine and cosine values ​​of double precision, processing these operations quickly allows for faster and more energy-efficient hardware usage. Additional details and examples are provided below, and the discussion revolves around… Figure 6 and 7 The two diagrams were discussed, with particular attention paid to bit processing and workflow to enable simultaneous processing of cosine and sine operations.

[0032] Figure 1 A first instance of a near-memory computing system, or CNM system 102, is generally shown. The instance of CNM system 102 comprises multiple different memory computing nodes, each of which may contain various near-memory computing devices. Each node in the system can operate within its own operating system (OS) domain (e.g., in particular Linux). In this instance, the nodes may coexist in a common OS domain of CNM system 102.

[0033] Figure 1The examples include instances of the first memory compute node 104 of the CNM system 102. The CNM system 102 may have multiple nodes, for example, including different instances of the first memory compute node 104 coupled using a scaling structure 106. In the examples, the architecture of the CNM system 102 may support scales with up to n different memory compute nodes (e.g., n=4096) using the scaling structure 106. As discussed further below, each node in the CNM system 102 may be a component of multiple devices.

[0034] CNM system 102 may include a global controller for various nodes in the system, or a specific memory compute node in the system may optionally act as a host or controller for one or more other memory compute nodes in the same system. The various nodes in CNM system 102 may therefore be configured similarly or differently.

[0035] In this example, each node in CNM system 102 may include a host system using a specified operating system. The operating system may be common or different across the various nodes in CNM system 102. Figure 1 In this example, the first memory computing node 104 includes a host system 108, a first switch 110, and a first memory computing device 112. The host system 108 may include a processor, such as an x86, ARM, RISC-V, or other type of processor. The first switch 110 may be configured to facilitate communication between or between devices of the first memory computing node 104 or devices of the CNM system 102, for example, using a dedicated or other communication protocol (generally referred to herein as the Chip-to-Chip Protocol Interface (CTCPI)). That is, CTCPI may include a dedicated interface unique to the CNM system 102, or may include or use other interfaces, such as a Compute High-Speed ​​Link (CXL) interface, a Peripheral Component Interconnect High-Speed ​​(PCIe) interface, or a Chiplet Protocol Interface (CPI), etc. The first switch 110 may include switches configured to use CTCPI. For example, the first switch 110 may include a CXL switch, a PCIe switch, a CPI switch, or other types of switches. In this example, the first switch 110 may be configured to couple dissimilarly configured endpoints. For example, the first switch 110 can be configured to convert packet formats between, for example, PCIe and CPI formats.

[0036] The CNM system 102 is described herein with various example configurations (e.g., systems including nodes), and each node may include various chips (e.g., processors, switches, memory devices, etc.). In an example, the first memory computing node 104 in the CNM system 102 may include various chips implemented using chiplets. In the chiplet-based configuration of the CNM system 102 discussed below, inter-chiplet communication and additional intra-system communication may use a CPI network. The CPI network described herein is an example of CTCPI, that is, a chiplet-specific implementation of CTCPI. Therefore, the structure, operation, and functionality described below for CPI are equally applicable to structures, operations, and functions that may be implemented using non-chiplet-based CTCPI implementations. Unless otherwise expressly indicated, any discussion of CPI herein applies equally to CTCPI.

[0037] The CPI interface includes a packet network that supports virtual channels to enable flexible and high-speed interaction between chiplets, such as portions of the first memory compute node 104 or the CNM system 102. CPI can bridge intra-chiplet networks to wider chiplet networks. For example, the Advanced Extensible Interface (AXI) is a specification for intra-chip communication. However, the AXI specification covers various physical design options, such as the number of physical channels, signal timing, power, etc. Within a single chip, these options are typically selected to meet design goals, such as power consumption, speed, etc. However, to achieve the flexibility of chiplet-based memory compute systems, adapters using CPI can intersect between various AXI design options that can be implemented in various chiplets. By enabling physical-to-virtual channel mapping using packetization protocols and encapsulating time-based signaling, CPI can be used to bridge intra-chiplet networks (e.g., within a specific memory compute node) across wider chiplet networks (e.g., across the first memory compute node 104 or across the CNM system 102).

[0038] CNM system 102 is scalable to accommodate multi-node configurations. That is, multiple different instances of the first memory compute node 104 or other differently configured memory compute nodes can be coupled using scaling structure 106 to provide a scalable system. Each of the memory compute nodes can run its own operating system and can be configured to jointly coordinate resource usage within the system.

[0039] exist Figure 1In one example, a first switch 110 of the first memory compute node 104 is coupled to a scaling structure 106. The scaling structure 106 can provide switches (e.g., CTCPI switches, PCIe switches, CPI switches, or other switches) that facilitate communication among and between different memory compute nodes. In this example, the scaling structure 106 can facilitate communication between various nodes in a partitioned global address space (PGAS).

[0040] In this example, a first switch 110 from a first memory computing node 104 is coupled to one or more different memory computing devices, such as a first memory computing device 112. The first memory computing device 112 may include a chiplet-based architecture, referred to herein as a near-memory computing (CNM) chiplet. A packaged version of the first memory computing device 112 may include, for example, one or more CNM chiplets. The chiplets may be communicatively coupled using CTCPI for high bandwidth and low latency.

[0041] exist Figure 1 In an example, the first memory computing device 112 may include a network on-chip (NOC) or a first NOC 118. Typically, an NOC is an interconnect network within a device that connects a specific set of endpoints. Figure 1 In this context, the first NOC 118 can provide communication and connectivity between various memories, computing resources and ports of the first memory computing device 112.

[0042] In an example, the first NOC 118 may include a folded Clos topology, such as within each instance of a memory computing device, or as a grid coupling multiple memory computing devices in a node. Clos topologies offer various benefits, such as the ability to use multiple lower-radix cross switches to provide functionality associated with higher-radix cross switch topologies. For example, Clos topologies can present consistent latency and bi-directional bandwidth across the NOC.

[0043] The first NOC 118 can include various types of switches, including hub switches, edge switches, and endpoint switches. Each switch can be configured as a crossbar switch that provides substantially uniform latency and bandwidth between input and output nodes. In an example, endpoint switches and edge switches can contain two separate crossbar switches, one for traffic destined for the hub switch and the other for traffic destined for the hub switch. A hub switch can be configured as a single crossbar switch that switches all inputs to all outputs.

[0044] In this example, hub switches may each have multiple ports (e.g., four or six ports each) depending on whether a particular hub switch participates in inter-chip communication. The number of hub switches participating in inter-chip communication can be set by inter-chip bandwidth requirements.

[0045] The first NOC 118 can support a variety of payloads between computing elements and memory (e.g., 8 to 64 bytes of payload; other payload sizes can be used similarly). In some instances, the first NOC 118 can be optimized for relatively small payloads (e.g., 8 to 16 bytes) to efficiently handle access to sparse data structures.

[0046] In this example, the first NOC 118 may be coupled to an external host via a first physical layer interface 114, a PCIe slave module 116 or endpoint, and a PCIe master module 126 or root port. That is, the first physical layer interface 114 may include an interface to allow an external host processor to couple to the first memory computing device 112. The external host processor may optionally couple to one or more different memory computing devices, for example, using a PCIe switch or other native protocol switch. Communication with the external host processor via a PCIe-based switch limits device-to-device communication to device-to-device communication supported by the switch. In contrast, communication via a memory computing device native protocol switch, such as using CTCPI, allows for more complete communication between or among different memory computing devices, including support for partitioned global address spaces, such as for generating worker threads and sending events.

[0047] In this example, the CTCPI protocol may be used by a first NOC 118 in a first memory computing device 112, and a first switch 110 may include a CTCPI switch. The CTCPI switch may allow CTCPI packets to be transmitted, for example, from a source memory computing device of the first memory computing device 112 to (e.g., on the same or another node) different destination memory computing devices without being converted to another packet format.

[0048] In one example, the first memory computing device 112 may include an internal host processor 122. The internal host processor 122 may be configured to communicate with the first NOC 118 or other components or modules of the first memory computing device 112, for example, using an internal PCIe master module 126, which can help eliminate the time- and energy-consuming physical layer. In one example, the internal host processor 122 may be based on a RISC-VISA processor and may use a first physical layer interface 114 to communicate externally to the first memory computing device 112, for communication with other storage, networking, or other peripheral devices of the first memory computing device 112. The internal host processor 122 may control the first memory computing device 112 and may act as a proxy for operating system-related functionalities. The internal host processor 122 may include a relatively small number of purpose processing cores (e.g., 2 to 4 cores) and a host memory device 124 (e.g., including DRAM modules).

[0049] In one example, the internal host processor 122 may include a PCI root port. When the internal host processor 122 is in use, one of its root ports may be connected to a PCIe slave module 116. Another root port of the internal host processor 122 may be connected to a first physical layer interface 114 to provide communication with external PCI peripherals. When the internal host processor 122 is deactivated, the PCIe slave module 116 may be coupled to the first physical layer interface 114 to allow an external host processor to communicate with a first NOC 118. In an example of a system with multiple memory computing devices, the first memory computing device 112 may be configured to act as a system host or controller. In this example, the internal host processor 122 may be in use, and other instances of internal host processors in corresponding other memory computing devices may be deactivated.

[0050] The internal host processor 122 can be configured at power-up of the first memory computing device 112 to allow host initialization. In an example, the internal host processor 122 and its associated data paths (e.g., including the first physical layer interface 114, PCIe slave module 116, etc.) can be configured to the first memory computing device 112 from input pins. One or more of these pins can be used to enable or disable the internal host processor 122 and configure the PCI (or other) data paths accordingly.

[0051] In this example, the first NOC 118 may be coupled to scale structure 106 via scale structure interface module 136 and second physical layer interface 138. Scale structure interface module 136 or SIF facilitates communication between the first memory computing device 112 and a device space such as a Partitioned Global Address Space (PGAS). The PGA may be configured such that a particular memory computing device, such as the first memory computing device 112, may access memory or other resources on different memory computing devices (e.g., on the same or different nodes) using a load / store paradigm. Various scalable architecture technologies may be used, including CTCPI, CPI, Gen-Z, PCI, or Ethernet bridged via CXL. Scale structure 106 may be configured to support various packet formats. In this example, scale structure 106 supports out-of-order packet communication or ordered packets, for example, by using path identifiers to extend bandwidth across multiple equivalent paths. Scale structure 106 typically supports remote operations such as remote memory reads, writes, and other built-in atoms, remote memory atoms, remote memory computing device send events, and remote memory computing device call and return operations.

[0052] In this example, the first NOC 118 may be coupled to one or more different memory modules, such as including a first memory device 128. The first memory device 128 may include various types of memory devices, such as LPDDR5 or GDDR6, etc. Figure 1 In one example, the first NOC 118 may coordinate communication with the first memory device 128 via a memory controller 130, which may be dedicated to a specific memory module. In this example, the memory controller 130 may include a memory module cache and an atomic operation module. The atomic operation module may be configured to provide relatively high-volume atomic operators, such as integer and floating-point operators. The atomic operation module may be configured to apply its operators to data within a memory module cache (e.g., including an SRAM memory-side cache), thereby allowing back-to-back atomic operations using the same memory location with minimal volume degradation.

[0053] The memory module cache can provide storage for frequently accessed memory locations, such as eliminating the need to re-access the first memory device 128. In one example, the memory module cache can be configured to cache data only for specific entries of the memory controller 130. In another example, the memory controller 130 includes a DRAM controller configured to interface with, for example, the first memory device 128 containing a DRAM device. The memory controller 130 can provide access scheduling and bit error management, among other functions.

[0054] In this example, the first NOC 118 may be coupled to the hybrid thread processor (HTP 140), the hybrid thread architecture (HTF142), and the host interface and dispatch module (HIF 120). HIF 120 may be configured to facilitate access to host-based command request and response queues. In this example, HIF 120 may dispatch new execution threads on the processors or compute elements of the HTP 140 or HTF 142. In this example, HIF 120 may be configured to maintain workload balancing across the HTP 140 and HTF 142 modules.

[0055] The hybrid-threaded processor, or HTP 140, may include accelerators, such as those based on the RISC-V instruction set. The HTP 140 may contain a highly threaded event-driven processor, where threads can execute in a single instruction round to maintain high instruction throughput. The HTP 140 includes relatively few custom instructions to support low-overhead threading capabilities, event send / receive, and shared-memory atomic operators.

[0056] The hybrid thread architecture or HTF 142 may include accelerators, such as non-von Neumann coarse-grained configurable processors. The HTF 142 may be optimized for high-level language operations and data types (e.g., integers or floating-point). In an example, the HTF 142 may support dataflow computation. The HTF 142 may be configured to utilize substantially all memory bandwidth available on the first memory computing device 112, for example, when executing a memory-bound computational core.

[0057] The HTP and HTF accelerators of the CNM system 102 can be programmed using various high-level structured programming languages. For example, the HTP and HTF accelerators can be programmed using C / C++ (e.g., using the LLVM compiler framework). The HTP accelerator can leverage the open-source compiler environment, for example, through various additional custom instruction sets configured to improve memory access efficiency, provide message passing mechanisms, and manage events, etc. In an example, the HTF accelerator can be designed to be programmed using a high-level programming language, and the compiler can generate simulator configuration files or binaries that run on the HTF 142 hardware. The HTF 142 provides a mid-level language for precise and concise expression of algorithms while hiding the configuration details of the HTF accelerator itself. In an example, the HTF accelerator toolchain can use an LLVM front-end compiler and an LLVM intermediate representation (IR) to interface with the HTF accelerator back-end.

[0058] Figure 2 An example of a memory subsystem 200 of a memory computing device according to an embodiment is generally shown. The example of memory subsystem 200 includes a controller 202, a programmable atom unit 208, and a second NOC 206. The controller 202 may include or use the programmable atom unit 208 to perform operations using information in the memory device 204. In this example, the memory subsystem 200 includes components from… Figure 1 A portion of the first memory computing device 112, such as a portion of the first NOC 118 or memory controller 130.

[0059] exist Figure 2 In this example, the second NOC 206 is coupled to the controller 202, and the controller 202 may include a memory control module 210, a local cache module 212, and a built-in atom module 214. In this example, the built-in atom module 214 may be configured to handle relatively simple single-loop integer atoms. The built-in atom module 214 can perform atoms with the same processing power as, for example, a normal memory read or write operation. In this example, an atomic memory operation may include a combination of: storing data into memory, performing an atomic memory operation, and then responding by loading data from memory.

[0060] A local cache module 212, which may include, for example, an SRAM cache, can be provided to help reduce latency for repeatedly accessed memory locations. In an example, the local cache module 212 may provide a read buffer for sub-memory line access. The local cache module 212 may be particularly advantageous for computing elements with relatively small or no data cache.

[0061] For example, a memory control module 210, which may include a DRAM controller, can provide low-level request buffering and scheduling to provide efficient access to memory device 204 (e.g., which may include a DRAM device). In an example, memory device 204 may include or use a GDDR6 DRAM device, for example, with a density of 16 Gb and a peak bandwidth of 64 Gb / s. Other devices may be used similarly.

[0062] In this example, programmable atomic unit 208 may include single-loop or multi-loop operators, such as being configured to perform integer addition or more complex multi-instruction operations, such as Bloom filter insertion. In this example, programmable atomic unit 208 may be configured to perform load and store-to-memory operations. Programmable atomic unit 208 may be configured to utilize RISC-V ISA via a dedicated instruction set to facilitate interaction with controller 202 to atomically execute user-defined operations.

[0063] Programmable atomic requests received, for example, from a host on or outside the node, can be routed to programmable atomic units 208 via a second NOC 206 and controller 202. In an example, custom atomic operations (e.g., performed by programmable atomic units 208) can be identical to built-in atomic operations (e.g., performed by built-in atomic modules 214), except that the programmable atomic operations can be defined or programmed by a user rather than a system architect. In an example, programmable atomic request packets can be sent to controller 202 via the second NOC 206, and controller 202 can recognize the requests as custom atoms. Controller 202 can then forward the recognized requests to programmable atomic units 208.

[0064] Figure 3 This generally illustrates an example of a programmable atom unit 302 for use with a memory controller according to an embodiment. In this example, the programmable atom unit 302 may include or correspond to data from... Figure 2 The instance is a programmable atomic unit 208. That is to say, Figure 3 The components shown are examples of programmable atom units (PAUs) 302, such as those described above relative to... Figure 2 (e.g., in programmable atom unit 208) or relative to Figure 1 (For example, in the atomic operation module of memory controller 130) the mentioned components. Figure 3 As shown, the programmable atomic unit 302 includes a PAU processor or PAU core 306, a PAU thread control 304, an instruction SRAM 308, a data cache 310, and a memory interface 312 for interfacing with a memory controller 314. In an example, the memory controller 314 includes components from... Figure 2 An instance of controller 202.

[0065] In this example, the PAU core 306 is a pipelined processor, allowing multiple stages of different instructions to execute together per clock cycle. The PAU core 306 may contain a barrel-shaped multithreaded processor, where the thread control 304 circuitry switches between different register files (e.g., a set of registers containing the current processing state) after each clock cycle. This enables efficient context switching between currently executing threads. In this example, the PAU core 306 supports eight threads, resulting in eight register files. In this example, some or all of the register files are not integrated into the PAU core 306, but instead actually reside in the local data cache 310 or instruction SRAM 308. This reduces the circuit complexity of the PAU core 306 by eliminating the traditional flip-flops used for registers in such memories.

[0066] The local PAU memory may contain instruction SRAM 308, such as instructions for various atoms. These instructions include instruction sets to support atomic operators loaded by various applications. When an atomic operator is requested, for example, by an application chiplet, the instruction set corresponding to the atomic operator is executed by the PAU core 306. In one example, the instruction SRAM 308 can be partitioned to establish the instruction set. In this example, a specific programmable atomic operator requested by the request process can be identified by a partition number. The partition number can be established when a programmable atomic operator is registered (e.g., loaded onto) using programmable atomic unit 302. Other metadata for the programmable instructions may be stored in memory (e.g., in a partition table) within the local memory of programmable atomic unit 302.

[0067] In this example, atomic operators manipulate data cache 310, which is typically synchronized (e.g., flushed) when the thread used for the atomic operator completes. Therefore, latency can be reduced for most memory operations during the execution of the programmable atomic operator thread, except for initial loads from external memory such as memory controller 314.

[0068] If a potentially dangerous condition were to prevent a memory request, the pipeline processor (e.g., PAU core 306) could experience a problem when a thread attempts to make such a request. Here, the memory request is for retrieving data from memory controller 314, whether it comes from cache on memory controller 314 or off-die memory. To address this, PAU core 306 is configured to deny memory requests to threads. Typically, PAU core 306 or thread control 304 may contain circuitry to enable one or more thread rescheduling points in the pipeline. Here, the denial occurs at points in the pipeline outside (e.g., after) these thread rescheduling points. In this instance, the danger occurs outside the rescheduling point. Here, the danger is created by a previous instruction in the thread after the last thread rescheduling point before the memory request instruction passes through the pipeline stage where the memory request can be made.

[0069] In this example, to reject a memory request, the PAU core 306 is configured to determine (e.g., detect) the presence of a danger on the memory indicated in the memory request. Here, a danger represents any condition that would cause an inconsistent state of the thread if the memory request were allowed (e.g., executed). In this example, the danger is an ongoing memory request. Here, the existence of an ongoing memory request makes it uncertain what the data at that address in the data cache 310 should be, regardless of whether the data cache 310 contains data at the requested memory address. Therefore, the thread must wait for the ongoing memory request to complete before operating on the current data. The danger is cleared when the memory request completes.

[0070] In this example, the danger lies in a dirty cache line in data cache 310 used for the requested memory address. While a dirty cache line typically indicates that the data in the cache is current and the memory controller version of such data is not current, problems can arise with thread instructions that do not operate from the cache. Examples of such instructions use the built-in atomic operators of memory controller 314 or other separate hardware blocks. In the context of the memory controller, the built-in atomic operators may be separate from programmable atomic units 302 and do not access the data cache 310 or instruction SRAM 308 within the PAU. If a cache line is dirty, the built-in atomic operators will not operate on the latest data until data cache 310 is flushed to synchronize the cache with another or off-chip memory. The same situation can occur using other hardware blocks of the memory controller, such as encryption blocks, encoders, etc.

[0071] Figure 4An example of a hybrid thread processor (HTP) accelerator or HTP accelerator 400 is shown. HTP accelerator 400 may include a portion of a memory computing device according to an embodiment. In the example, HTP accelerator 400 may include or include components from… Figure 1 The HTP 140 is an example of this. The HTP accelerator 400 includes, for example, an HTP core 402, an instruction cache 404, a data cache 406, a translation block 408, a memory interface 410, and a thread controller 412. The HTP accelerator 400 may further include, for example, a dispatch interface 414 and an NOC interface 416 for interfacing with a NOC, the NOC being, for example, from... Figure 1 The first NOC 118 instance, from Figure 2 The second NOC 206 or other NOCs for the example.

[0072] In this example, the HTP accelerator 400 includes modules based on the RISC-V instruction set and may include a relatively small number of other or additional custom instructions for supporting low-overhead, thread-enabled hybrid threading (HT) languages. The HTP accelerator 400 may include a highly threaded processor core, HTP core 402, in which threads can execute in a single instruction round-robin to maintain high instruction throughput. In this example, threads can pause while waiting for other pending events to complete. This allows computational resources to be used efficiently for related work, rather than polling. In this example, multithreaded barrier synchronization can utilize efficient HTP-to-HTP and HTP-to / from host message passing, allowing thousands of threads to initialize or wake up in, for example, tens of clock cycles.

[0073] In an example, dispatch interface 414 may include function blocks for handling hardware-based thread management of HTP accelerator 400. That is, dispatch interface 414 can manage the dispatch of work to HTP core 402 or other accelerators. However, non-HTP accelerators are typically unable to dispatch work. In an example, work dispatched from the host may use dispatch queues residing in, for example, host main memory (e.g., DRAM-based memory). On the other hand, work dispatched from HTP accelerator 400 may use dispatch queues residing in SRAM, for example, within a dispatch for a target HTP accelerator 400 within a specific node.

[0074] In an example, HTP core 402 may include one or more cores that execute instructions on behalf of threads. That is, HTP core 402 may contain instruction processing blocks. HTP core 402 may further include or be coupled to thread controller 412. Thread controller 412 may provide thread control and state for each active thread within HTP core 402. Data cache 406 may include a cache for the host processor (e.g., for local and remote memory computing devices, including caches for HTP core 402), and instruction cache 404 may include a cache for use by HTP core 402. In an example, data cache 406 may be configured for both read and write operations, and instruction cache 404 may be configured for read-only operations.

[0075] In this example, data cache 406 provides a small cache for each hardware thread. Data cache 406 can temporarily store data for use by the owning thread. Data cache 406 can be managed by hardware or software within the HTP accelerator 400. For example, the hardware can be configured to automatically allocate or evict lines as needed when load and store operations are performed by the HTP core 402. Software, for example, using RISC-V instructions, can determine which memory access should be cached and when a line should be invalidated or written back to another memory location.

[0076] Data caching on the HTP accelerator 400 offers various benefits, including making memory controller access more efficient, thus allowing execution threads to avoid stalling. However, there are situations that can lead to inefficiency when using caching. Examples include accesses where data is accessed only once, resulting in cache line thrashing. To help address this issue, the HTP accelerator 400 can use a custom load instruction set to prompt load instructions to check for cache hits and, if a cache miss occurs, issue a memory request for the requested operand without placing the retrieved data in the data cache 406. Therefore, the HTP accelerator 400 includes various types of load instructions, including non-cached and cache line loads. If dirty data exists in the cache, non-cached load instructions use the cached data. Non-cached load instructions ignore clean data in the cache and do not write the accessed data to the data cache. The cache line load instruction can load an entire data cache line (e.g., 64 bytes) from memory into data cache 406, and can also load the addressed memory into a specified register. If clean or dirty data is in data cache 406, these loads can use the cached data. If the referenced memory location is not in data cache 406, the entire cache line can be accessed from memory. The use of cache line load instructions reduces cache misses when referencing sequential memory locations (e.g., in memory copy operations), but it can also waste memory and bandwidth at NOC interface 416 if the referenced memory data is not used.

[0077] In this example, the HTP accelerator 400 includes non-cached custom store instructions. These non-cached store instructions help avoid thrashing the data cache 406 by utilizing write data that is not sequentially written to memory.

[0078] In this example, the HTP accelerator 400 further includes a translation block 408. Translation block 408 may include a virtual-to-physical translation block for the local memory of the memory computing device. For example, a host processor in HTP core 402 may execute load or store instructions, and these instructions may generate virtual addresses. A translation table from translation block 408 may be used, for example, to translate the virtual addresses into physical addresses for the host processor. For example, memory interface 410 may include an interface between HTP core 402 and NOC interface 416.

[0079] Figure 5 An example of a hybrid threading architecture (HTF) or HTF 500 of a memory computing device according to an embodiment is shown. In the example, HTF 500 may include or include components from... Figure 1The HTF 142 is an example of this. The HTF 500 is a coarse-grained configurable computational architecture that can be optimized for high-level language operand types and operators (e.g., using C / C++ or other high-level languages). In an instance, the HTF 500 may contain a configurable n-bit-wide (e.g., 512-bit-wide) data path for interconnect-hardened SIMD arithmetic units.

[0080] In this instance, HTF 500 includes HTF cluster 502, which contains multiple HTF tiles, including instance tile 504 or tile N. Each HTF tile may contain one or more compute elements with local memory and arithmetic capabilities. For example, each tile may contain compute pipelines with support for integer and floating-point operations. In this instance, data paths, compute elements, and other infrastructure may be implemented as hardened IP to provide maximum performance while minimizing power consumption and reconfiguration time.

[0081] exist Figure 5 In this example, the tiles of HTF cluster 502 are arranged linearly, and each tile in the cluster can be coupled to one or more other tiles in HTF cluster 502. Figure 5 In this example, instance tile 504 or tile N is coupled to four other tiles, including coupling to base tile 510 (e.g., tile N-2) via a port labeled SF IN N-2, coupling to adjacent tile 512 (e.g., tile N-1) via a port labeled SF IN N-1, and coupling to tile N+1 via a port labeled SF IN N+1 and to tile N+2 via a port labeled SF IN N+2. Instance tile 504 may be coupled to the same or other tiles via corresponding output ports (e.g., ports labeled SF OUT N-1, SF OUT N-2, SF OUT N+1, and SF OUT N+2). In this example, the ordered list of names for the various tiles is a conceptual indication of the tile's location. In other examples, tiles, including HTF cluster 502, may be arranged in a grid or other configuration, where each tile is similarly coupled to one or more of its nearest neighbors in the grid. Tiles positioned at the edge of a cluster may optionally have fewer connections to adjacent tiles. For example, tiles N-2 or Figure 5 In this instance, the base tile 510 may be coupled only to the adjacent tile 512 (tile N-1) and to the instance tile 504 (tile N). Similarly, fewer or additional inter-tile connections can be used. These connections (e.g., using a port as an interface for any given tile) may be called channels. In this instance, a channel is 64 bits wide.

[0082] HTF cluster 502 may further include a memory interface module, which includes a first memory interface module 506. The memory interface module couples HTF cluster 502 to a NOC, such as a first NOC 118. In an example, the memory interface module may allow tiles within the cluster to request other locations in the memory computing system (e.g., within the same or different nodes in the system). That is, the representation of HTF 500 may include part of a larger structure that can be distributed across multiple nodes, such as having one or more HTF tiles or HTF clusters at each of the nodes. Requests can be made between tiles or nodes within the context of the larger structure.

[0083] exist Figure 5 In this example, a synchronous structure (SF) is used to couple tiles within HTF cluster 502. The synchronous structure provides communication between a specific tile in HTF cluster 502 and its neighboring tiles, as described above. Each HTF cluster 502 may further include an asynchronous structure (AF) that provides communication, for example, between tiles within the cluster, between memory interfaces within the cluster, and between dispatch interfaces 508 within the cluster.

[0084] In this example, the synchronization structure can exchange messages containing data and control information. Control information may include, among other things, instruction RAM address information or thread identifiers. Control information can be used to set up data paths, and data message fields can be selected as the source of the path. Typically, control fields can be provided or received earlier, making them available for configuring the data path. For example, to help minimize any delays through the synchronization domain pipeline in a tile, control information may arrive at the tile several clock cycles before the data fields. Various registers can be provided to help coordinate the timing of data flow in the pipeline.

[0085] In this example, each tile in HTF cluster 502 may contain multiple memories. Each memory may have the same width as the data path (e.g., 512 bits) and a specified depth, for example, ranging from 512 to 1024 features. The tile memory can be used to store data that supports data path operations. For example, the stored data may contain constants that are part of the cluster configuration of the kernel, or variables that are computed as part of a data stream. In this example, the tile memory may be written from an asynchronous structure as a data transfer from another synchronization domain, or may contain, for example, the result of a load operation initiated by another synchronization domain. Reading from the tile memory can be performed via synchronous data path instructions in the synchronization domain.

[0086] In the example, each tile in the HTF cluster 502 may have a dedicated instruction RAM (INST RAM). In an example of an HTF cluster 502 with sixteen tiles and an instruction RAM entry of 64 entries, the cluster may allow the use of up to 1024 multiply-shift and / or ALU operation mapping algorithms. Various tiles may be optionally pipelined together, for example, using a synchronous structure to allow computation with minimal memory access to the data stream, thus minimizing latency and reducing power consumption. In the example, an asynchronous structure may allow memory referencing and computation to continue in parallel, thereby providing a more efficient streaming kernel. In the example, various tiles may include built-in support for loop-based constructions and may support nested loop kernels.

[0087] Synchronization structures allow for the pipelined execution of multiple tiles, eliminating the need for data queues. Tiles participating in a synchronization domain can, for example, act as a single pipelined data path. The first or base tile of the synchronization domain (e.g., tile N-2, in...) Figure 5 In this example, worker threads can be initiated via pipelined tiles. The base tile is responsible for starting work on a predefined cadence, referred to in this document as the Spoke Count. For example, if the Spoke Count is 3, the base tile can initiate work every two clock cycles.

[0088] In this example, the synchronization domain comprises a set of connected tiles in HTF cluster 502. Thread execution can begin at the base tile of the domain and can proceed from the base tile to other tiles in the same domain via the synchronization structure. The base tile provides instructions to be executed against the first tile. The first tile may by default provide the same instructions for another connected tile to be executed. However, in some instances, the base tile or subsequent tiles may conditionally specify or use alternative instructions. Alternative instructions are selected by causing the tile's data path to produce a Boolean condition value, and then the Boolean value can be used to select between the instruction set of the current tile and the alternative instructions.

[0089] Asynchronous structures can be used to perform operations that occur asynchronously relative to synchronous domains. Each piece in the HTF cluster 502 may contain an interface to an asynchronous structure. The in interface may contain, for example, a FIFO buffer or a queue (e.g., AF IN QUEUE) to provide storage for messages that cannot be processed immediately. Similarly, the out interface of the asynchronous structure may contain a FIFO buffer or a queue (e.g., AF OUT QUEUE) to provide storage for messages that cannot be sent immediately.

[0090] In this example, messages in an asynchronous architecture can be categorized as data messages or control messages. Data messages may contain SIMD-width data values ​​written to tile memory 0 (MEM_0) or memory 1 (MEM_1). Control messages can be configured to control threads to create, release resources, or issue external memory references.

[0091] In an HTF cluster 502, tildes can perform various computational operations for HTF. These computational operations can be performed by configuring the data paths within the tilde. In this example, a tilde contains two function blocks that perform computational operations for the tilde: a multiplication and shift operation block (MS OP) and an arithmetic, logical, and bit operation block (ALB OP). Both blocks can be configured to perform pipelined operations, such as multiplication and addition, or shift and addition, etc.

[0092] In one instance, each instance of a memory computing device in the system can have a full set of supported instructions for its operator blocks (e.g., MSOP and ALB OP). In this case, binary compatibility can be achieved across all devices in the system. However, in some instances, it may be helpful to maintain a basic set of functionalities and optional instruction set categories to accommodate various design trade-offs, such as die size. The approach can be similar to how the RISC-V instruction set has a basic set and multiple optional instruction subsets.

[0093] In this example, instance tile 504 may include spoke RAM. The spoke RAM can be used to specify which input (e.g., from four SF tile inputs and a base tile input) is the master input for each clock cycle. The spoke RAM read address input may originate from a counter counting from zero to the spoke count minus one. In this example, different spoke counts can be used for different tiles, for example, within the same HTF cluster 502, to allow the performance of a particular application or instruction set to be determined by several tiles or unique tile instances used in the inner loop. In this example, the spoke RAM may specify when synchronization inputs will be written to the tile memory, for example, using multiple inputs for a particular tile instruction and the time when one of the inputs arrives before the others. The earlier arriving input can be written to the tile memory and can be read later when all inputs are available. In this example, the tile memory may be accessed as a FIFO memory, and the FIFO read and write pointers may be stored in register-based memory areas or structures within the tile memory.

[0094] The hardware of the HTF cluster 502 (HTF) or HTP accelerator 400 (HTP) can be used to implement parallel sine and cosine execution based on a single input value. For clarity, the following hardware is described from the perspective of the processing circuitry of the HTF cluster 502, but some or all of these operations can be performed by the processing circuitry of the HTP accelerator 400 or other components of a near-memory computing system (e.g., CNM system 102).

[0095] To perform parallel sine and cosine operations, the processing circuitry is configured to obtain (e.g., receive or retrieve) a first bit sequence representing the angle of a line from the origin to the unit circle. The processing circuitry may obtain the bit sequence from an interface in the processing circuitry's registers (e.g., to the NOC of the HTF or HTP) or from another storage device accessible to the processing circuitry (e.g., memory 128). In this example, the processing circuitry is an HTF (e.g., HTF cluster 502). In this example, the first bit sequence is obtained from a first channel of the HTF (e.g., a port corresponding to INN-2 in patch 504). In this example, the first bit sequence has 64 bits.

[0096] The processing circuitry is configured to define the unit circle quadrant of the line. In this example, the processing circuitry includes hardware blocks for defining the quadrant. Examples of such hardware blocks are specific instructions supported by the hardware, such as those related to... Figure 6 The described PTruncLsbsF64FromF64.

[0097] The processing circuitry is configured to replace the two least significant bits (LSBs) of the first bit sequence with quadrant-specific encoding. The encoding may follow the guidelines regarding... Figure 6 The two lsb values ​​discussed are 00 for the first quadrant, 01 for the second quadrant, 10 for the third quadrant, and 11 for the fourth quadrant. However, other encodings can be used. In this example, the substitution of the two lsb values ​​can be performed by a hardware block of the processing circuitry (e.g., as a special instruction). In this example, the same hardware block used to determine the quadrants also performs this operation. This value can be referred to as... The quadrant is encoded. Therefore, if the first bit sequence initially represents an angle... So the first sequence now represents , or angle The quadrant encoded version.

[0098] The processing circuitry is configured to reduce (e.g., convert) the angle to a base quadrant angle in a second sequence of the same length as the first sequence. Here, the base quadrant is a quadrant in which the sine and cosine operations (described below) will be performed. Figure 6In the example used, the first quadrant is the base quadrant, but the other quadrant can also be used as the base quadrant, with appropriate adjustments made to the transformation from intermediate sine and cosine solutions to the final sine and cosine solutions. In the example, reducing the angle to the base quadrant angle in the second bit sequence involves subtracting the coded quadrant multiplied by 90 degrees from the angle (e.g., This process is used to produce a result stored in the second bit sequence. At this point, the result (e.g., the second bit sequence) can be referred to as... This indicates that the angle has been quadrant-encoded and reduced to the base quadrant. Other operations can also be performed to transform the representation of the angle into a better form for subsequent work, such as squaring the base quadrant angle before storing it in the second bit sequence. Although these instances use a second bit sequence for storage... However, the first sequence can also be modified to save. As long as the quadrant encoding remains intact, manipulation of other bits in the first bit sequence will not affect the ability of the first bit sequence to communicate with the original quadrant when determining the final solution.

[0099] The processing circuitry is configured to perform sine and cosine operations (e.g., computation) on a portion of the second bit sequence to create intermediate sine and cosine solutions in the base quadrant. By performing all sine and cosine operations in a single quadrant, the base quadrant eliminates branches in the computation. Therefore, sine and cosine operations can be performed efficiently on CIMD hardware, such as HTF tiles, graphics processing units (GPUs), or other vector architectures. This allows these parallel execution units to further accelerate the intermediate sine and cosine computations.

[0100] Although it can be used Sine and cosine calculations are performed on all angle bits in the sequence, but 62-bit resolution is typically unnecessary. In fact, 32-bit precision is usually sufficient. For example, when adjusting the size of the first bit sequence based on the input interface (e.g., a channel of an HTF), more than half the angle precision of the input interface reduces parallelism because any given communication window can only transmit the angle value to perform either a sine or cosine operation. However, if the precision is reduced to half (e.g., from 64 bits to 32 bits), then this value can be copied to reside in both the first and second halves of the communication. In this way, the first 32 bits and the next 32 bits of the second bit sequence are identical.

[0101] Because all available 64 bits are used in this example, the first bit sequence cannot be reused unless quadrant encoding is maintained elsewhere. The second bit sequence can communicate, with the sine calculation performed on one half and the cosine calculation on the second half, to create intermediate sine and cosine solutions. From the perspective of the base quadrant, these solutions are complete, but they are intermediate before being converted to the original quadrant.

[0102] In this example, performing sine and cosine operations on the portion of the second bit sequence to create intermediate sine and cosine solutions in the base quadrant involves converting the second bit sequence from a higher precision value to a lower precision value—for example, converting double precision to floating point—and storing the lower precision value in the first part of the 64-bit value. The lower-resolution version (e.g., floating point) is then copied to the second part of the 64-bit value. A sine operation is performed on one portion (e.g., the first half) of the second bit sequence, and a cosine operation is performed on the other portion (e.g., the second half). In this example, the output of the sine operation replaces the first part of the 64-bit value, and the cosine operation replaces the second part of the 64-bit value. Here, the first part and the second part refer to the bits where the sine and cosine operations are performed, respectively. Therefore, if the second half of the second bit sequence is used as input for a sine calculation, then the first part storing the output is the second half of the second bit sequence.

[0103] The processing circuitry is configured to use quadrant encoding from the first bit sequence on the intermediate sine and cosine solutions to create the final sine and cosine solutions in the quadrants. Thus, the solution in the base quadrant is transformed into the solution in the original quadrant for the angle. Figure 6 Several techniques for performing this conversion are illustrated. Generally, if the base quadrant is the same as the original quadrant, then no conversion is needed, or the intermediate value is equal to the final value. Otherwise, swapping values ​​or changing the sign will achieve the conversion, and the numerical value will not change. Figure 6 In the example shown, the quadrants are the first quadrant (base quadrant) between -45 degrees (e.g., 315 degrees) and 45 degrees, the second quadrant from 45 to 135 degrees, the third quadrant from 135 to 225 degrees, and the fourth quadrant from 225 to 315 degrees. In this context, when the quadrant is the first quadrant—encoded according to the quadrant in the first bit sequence—nothing changes because this quadrant is the base quadrant. In other cases:

[0104] If the quadrant is the second quadrant, then the transformation from the intermediate to the final solution is: 1. using the intermediate cosine solution as the final sine solution; and 2. using the inverse of the intermediate sine solution as the final cosine solution, or using... Figure 6 The final solution is... and .

[0105] If the quadrant is the third quadrant, then the transformation from the intermediate to the final solution is: 1. using the inverse of the intermediate sine solution as the final sine solution; and 2. using the inverse of the intermediate cosine solution as the final cosine solution, or and .

[0106] If the quadrant is the fourth quadrant, then the transformation from the intermediate to the final solution is: 1. using the inverse of the intermediate cosine solution as the final sine solution; and 2. using the intermediate sine solution as the final cosine solution, or and .

[0107] In this example, the intermediate sine and cosine solutions are stored within the third bit sequence. In this example, the processing circuitry includes a hardware block that accepts the quadrant-encoded first and second bit sequences to create the final sine and cosine solutions. This hardware block may contain specialized instructions, such as the NegCF32FromTruncLsbsF64 described below. Implementing this functionality in hardware increases hardware complexity, but it eliminates the branching problem, which is extremely inefficient for SIMD architectures.

[0108] In this example, the first sequence represents the variables of Euler's formula, the final sine solution is the imaginary part of the solution to Euler's formula with variables, and the final cosine solution is the real part of the solution to Euler's formula with variables. As mentioned above, calculating Euler's formula is a perennial task in modern signal processing, whether processing sensor data such as images, radar, sound, or radio signals, or driving actuators (e.g., motors), graphic displays, speakers, or radios. The techniques described in this paper allow for the rapid and efficient execution of Euler's formula and the enabling of these techniques using SIMD and other architectures.

[0109] Figure 6 A unit circle with angular and quadrant relationships to the sine and cosines is shown according to an embodiment. The above description of parallel sine and cosine calculations can benefit from... Figure 6 The diagram illustrates the unit circle representing the real and imaginary parts of the complex circle. The unit circle is divided into four quadrants, each spanning an angle... When the two least significant bits of the input are replaced with quadrant codes, the quadrants are labeled by the bits used to represent them. As shown, the first quadrant (00) 602 is from Crossing to The second quadrant (01) 604 from Crossing to The third quadrant (10) 606 from Crossing to And in the fourth quadrant (11) 602 from Crossing to .

[0110] The diagram provides an input (angle). Examples are given to illustrate the nature of the manipulation. Specifically, angles... It is located in the third quadrant (10) 606. If Transformed to the first quadrant (00) 602, represented as Therefore, it is obvious that by simply changing the signs of the sine and cosine values, The sine and cosine calculations on the x-axis can be converted back to the third quadrant (10)606. The following is an extension of this example.

[0111] In the example, it can be done by finding The value makes To determine the quadrant of angle X. Once determined... Let the quadrant , where "mod" is the modulo operator. Therefore, You can start from zero and increment by 1 three or fewer times to find an acceptable one. Therefore, in the example shown, and None of them are here Within the range, but (180 degrees or) Translation) does indeed Place it in the first quadrant (00) 602.

[0112] The relationships between the sine and cosine solutions in the first quadrant (00) 602 and the other quadrants to which this transformation is performed are provided in the table below:

[0113]

[0114] Therefore, it is possible to perform sine and cosine operations in the first quadrant (00) 602 to produce intermediate results, which can then be adjusted based on the quadrant determination.

[0115] For example, to compute a sequence represented by a 64-bit sequence Use the sine and cosine of the quadrant to determine the quadrant. (as shown in the figure) Or the third quadrant (10) 606). Replace the two least significant mantissa bits with Q (e.g., 10), and... (For example, indicating) (bit sequence) converted to This indicates that the bit sequence contains a quadrant. In an example, the hardware implements the instruction PTruncLsbsF64FromF64 (described below) to perform this operation. At this point, the quadrant is determined and encoded as... The original input value.

[0116] Then, by subtracting It can Transform to the first quadrant (00) 602. This transformation can be considered as... The reduction. Therefore, by reducing the number of instances shown. minus , Reduced to The scope to create (shown as) ). Stored in the second bit sequence, rather than saved. In the bit sequence, because The encoded quadrant in the code is reserved for subsequent additional operations. In this example, the hardware implements the instruction PMulIgnore2lsbs (described below) to perform this operation.

[0117] Then you can... The reduction process involves squaring, shrinking, and copying the value into a single bit sequence. For example, in a 64-bit system where double-precision floating-point values ​​(e.g., double precision) are present, reduction might involve converting the double precision to floating-point (e.g., 32 bits). The copied value can then be placed into a single double-precision value. If the HTF channel is a double-precision value, then reduction and copying allow the angle to be transferred separately in a single operation (e.g., for separate sine and cosine calculations) to the piece. Therefore, in the angle... While sacrificing a certain level of precision, the number of communications with HTF tiles or HTP can be reduced by half. Generally, this represents a beneficial trade-off between performance and accuracy in many applications. A significant aspect of the reduction in angular precision is typically reducing the angle to the base quadrant and squaring it for Taylor series sine or cosine calculations. At this point, precision (e.g., resolution) can be safely reduced without significantly affecting the final sine or cosine value. Therefore, the precision reduction is not arbitrary but occurs at a point in the processing where a reduction in precision is tolerable.

[0118] create Then, standard techniques, such as Taylor series expansion or any other expansion, can be performed to create 32-bit sine and cosine values. These values ​​are intermediate values, not final results, because they are performed in the first quadrant (00) 602 and need to be converted to the original quadrant to complete. These intermediate results can be generated in parallel by the mosaicks in other processing circuitry systems within the HTF, HTP, or CNM system. Furthermore, by performing the computation in a single quadrant, branching in parallel processing elements (e.g., SIMD processors or HTF mosaicks) is avoided, thus providing greater efficiency when using these elements.

[0119] After obtaining the intermediate results, the table above is used to convert the intermediate results into the final results. In this example, the hardware implements the instruction PNegCF32FromTruncLsbsF64 (described below) to perform this operation.

[0120] The following pseudocode—using the hardware-specific instructions TruncLsbs64F64From64, PMulIgnore2Lsbs, and NegCF32FromTruncLsbsF64—demonstrates this process:

[0121] double X; / / value to take sin / cosine

[0122] 1&2) Xq = TruncLsbs64F64From64( RoundF64(X TWO_DIV_PI)); / / determinequadrant and set / / the two least-significant-bits / / (lsbs) to the quadrant.

[0123] 3) fsDMul = PMulIgnore2Lsbs(Xq PI_DIV_TWO); / / Ignore two lsbs ofXq

[0124] 4a) fsD = x - fsDMul; / / Translate X to the first quadrant

[0125] 4b) complex g = ( float(fsD fsD), float(fsD fsD)); / / Reduce andduplicate (g is

[0126] / / from above). In the notation

[0127] / / below, g.im refers to the imaginary

[0128] / / half of g (eg, the first thirty-two

[0129] / / bits) upon which sin will be

[0130] / / calculated and g.re refers to the

[0131] / / real half of g (e.g., the second

[0132] / / thirty-two bits) upon which cosine

[0133] / / will be calculated.

[0134] 5a) complex step2 = (fsD, 1.0); / / perform Taylor series expansion

[0135] 5b) complex step3 = (-0.0001984086154f,-0.138885249433e-2f);

[0136] 5c) complex step4 = (0.008333330973f + step3.re g.re,0.416666506699e-1f + step3.im g.im);

[0137] 5d) complex step5 = (-0.1666666660f + step4.re g.re, -0.499999998030f+ step4.im g.im);

[0138] 5e) complex step6 = (1.0f + step5.re g.re, 1.0f + step5.im g.im); / / step6 is the variable holding

[0139] / / intermediate results for the

[0140] / / sin and cosine calculations.

[0141] 6) complex SC = NegCF32FromTruncLsbsF64(step6, Xq); / / the finalresults SC is produced by

[0142] / / using the quadrant encoding from

[0143] / / Xq to convert the intermediate

[0144] / / results

[0145] The following represents the implementation of the special instructions TruncLsbs64F64From64, PMulIgnore2Lsbs, and NegCF32FromTruncLsbsF64 in hardware, assuming 64-bit double precision and 32-bit floating-point:

[0146] PTruncLsbsF64FromF64 can be defined as:

[0147] for (int i = 0; i <HTF_PACK_64_CNT; i += 1) {

[0148] alOpOut.m_f64[i] = (int) c1_alIn2.m_f64[i]&~0x3;

[0149] uint64_t n1 = (int) alOpOut.m_f64[i]&0x1 LL;

[0150] uint64_t n2 = (int) alOpOut.m_f64[i]&0x2 LL;

[0151] alOpOut.m_u64[i] |= (n1 | n2);

[0152] }

[0153] PMulIgnore2Lsbs can be defined as:

[0154] for (int i = 0; i <HTF_PACK_64_CNT; i += 1) {

[0155] msIn1.m_u64[i]&= ~0x3LL; / / Zero out 2 lsbs

[0156] msOpOut.m_f64[i] = msIn1.m_f64[i] msIn2.m_f64[i];

[0157] }

[0158] PNegCF32`FromTruncLsbsF64 can be defined as:

[0159] / / The least significant s 2 bits of op2 specify which quadrant the complex number was from.

[0160] / / Use those to selectively negate the Complex F32 in Op1

[0161] for (int i = 0; i < HTF_PACK_64_CNT; i += 1) {

[0162] bool n1 = (c1_alIn2.m_u64[i] & 0x1LL) != 0;

[0163] bool n2 = (c1_alIn2.m_u64[i] & 0x2LL) != 0;

[0164] if (n1) {

[0165] if (n2) { / / Quadrant 11

[0166] alOpOut.m_u32[i 2] = c1_alIn1.m_u32[i 2] ^ 0x00000000; / / use real portion

[0167] alOpOut.m_u32[i 2 + 1] = c1_alIn1.m_u32[i 2 + 1] ^ 0x80000000; / / negate imaginary

[0168] / / portion

[0169] } else { / / Quadrant 01

[0170] alOpOut.m_u32[i 2] = c1_alIn1.m_u32[i 2] ^ 0x80000000; / / negate real portion

[0171] alOpOut.m_u32[i 2 + 1] = c1_alIn1.m_u32[i 2 + 1] ^ 0x00000000; / / use imaginary

[0172] / / portion

[0173] }

[0174] uint32_t tmp = alOpOut.m_u32[i 2]; / / swap the real

[0175] alOpOut.m_u32[i 2] = alOpOut.m_u32[i 2 + 1]; / / portion and the

[0176] alOpOut.m_u32[i 2 + 1] = tmp; / / imaginary portion

[0177] } else {

[0178] if (n2) { / / Quadrant 10

[0179] alOpOut.m_u32[i 2] = c1_alIn1.m_u32[i 2] ^ 0x80000000; / / negatereal portion

[0180] alOpOut.m_u32[i 2 + 1] = c1_alIn1.m_u32[i 2 + 1] ^ 0x80000000; / / negate imaginary

[0181] / / portion

[0182] } else { / / Quadrant 00

[0183] alOpOut.m_u32[i 2] = c1_alIn1.m_u32[i 2] ^ 0x00000000; / / usereal portion

[0184] alOpOut.m_u32[i 2 + 1] = c1_alIn1.m_u32[i 2 + 1] ^ 0x00000000; / / use imaginary

[0185] / / portion

[0186] }

[0187] }

[0188] }

[0189] The following are additional examples of code (in C) that can be used to implement the above pseudocode:

[0190] const double TwoXDivPi = kuTmpTimesR TWO_DIV_PI; / / ord:2 op #14- Sin / Cosine 1

[0191] const double TwoXDivPiRounded = (TwoXDivPi + (TwoXDivPi>0 ? 0.5 : -0.5)); / / Special AlOp -

[0192] / / PRoundF64

[0193] trunc_f64_plus_lsbs_t nTrunc; / / ord:3 op #15 Sin / Cosine 2

[0194] / / Special AlOp - PTruncLsbsF64

[0195] / / Unary op

[0196] / / Zero fractional mantissa bits

[0197] / / Set least significant 2 mantissa bits to:

[0198] / / LSb = 2 ^ 0 mantissa bit

[0199] / / LSb+1 = 2 ^ 1 mantissa bit

[0200] / / Output is type trunc_f64_plus_lsbs_t

[0201] nTrunc.f64 = (double)(int) TwoXDivPiRounded;

[0202] int64_t nSint = (int) nTrunc.f64;

[0203] nTrunc.bits.n1 = !!((int) nSint&1);

[0204] nTrunc.bits.n2 = !!((int) nSint&2);

[0205] / / ord:4 op #16 - Sin / Cosine 3

[0206] trunc_f64_plus_lsbs_t nTruncCopy = nTrunc; / / Special MsOp -PMulIgnore2Lsbs

[0207] / / MsIn1 - type trunc_f64_plus_lsbs_t

[0208] / / MsIn2 - type F64

[0209] / / Zero 2 lsbs of mantissa

[0210] / / MulF64

[0211] / / Output is F64

[0212] nTruncCopy.bits.n1 = 0;

[0213] nTruncCopy.bits.n2 = 0;

[0214] double fsDMul = nTruncCopy.f64 PI_DIV_TWO;

[0215] double fsD = kuTmpTimesR - fsDMul;

[0216] complex g; / / ord:5 op #17 - Sin / Cosine 4

[0217] g.re = float(fsD fsD); / / F64 ->F32 conversion duplicates float

[0218] / / g.im = g.re;

[0219] complex step2; / / ord:5 op #18 - Sin / Cosine 4

[0220] step2.re = (float) fsD; / / Special AlOp - PFromF64ToF32Const

[0221] step2.im = 1.0 f; / / AlIn1 - type F64

[0222] / / AlIn2 - type F32 const in Lane 1

[0223] / / Converts AlIn1 to F32 ->Lane 0

[0224] / / of AlOut

[0225] / / Copies AlIn2 to ->Lane 1 of

[0226] / / ….AlOut.

[0227] complex step3, step4, step5, step6;

[0228] step3.re = -0.0001984086154 f;

[0229] step3.im = -0.138885249433e-2 f;

[0230] step4.re = 0.008333330973 f + step3.re g.re; / / ord:6 op #19 - Sin / Cosine 5

[0231] step4.im = 0.416666506699e-1 f + step3.im g.im;

[0232] step5.re = -0.1666666660 f + step4.re g.re; / / ord:7 op #20 - Sin / Cosine 6

[0233] step5.im = -0.499999998030 f + step4.im g.im;

[0234] step6.re = 1.0 f + step5.re g.re; / / ord:8 op #21 - Sin / Cosine 7

[0235] step6.im = 1.0 f + step5.im g.im;

[0236] complex step7;

[0237] step7.re = step6.re step2.re; / / ord:9 op #22 - Sin / Cosine 8

[0238] step7.im = step6.im step2.im;

[0239] complex matched_filter;

[0240] if (nTrunc.bits.n1) { / / Special AlOp - PF32FromF64Rounded

[0241] if (nTrunc.bits.n2) { / / AlIn1 - type F32

[0242] matched_filter.re = step7.re; / / AlIn2 - trunc_f64_plus_lsbs_t

[0243] matched_filter.im = -step7.im; / / Look at lsbs of AlIn2 n1, n2

[0244] } else { / / if (n1&&n2) negate AlOut.Lane0

[0245] matched_filter.re = -step7.re; / / if (n1&&!n2) negateAlOut.Lane1

[0246] matched_filter.im = step7.im; / / if (!n1&&n2) negate AlOut.Lanes0&1

[0247] } / / if (!n1&&!n2) no change

[0248] } else { / / AlOut output type is F32

[0249] if (nTrunc.bits.n2) {

[0250] matched_filter.re = -step7.im;

[0251] matched_filter.im = -step7.re;

[0252] } else {

[0253] matched_filter.re = step7.im;

[0254] matched_filter.im = step7.re;

[0255] }

[0256] }

[0257] These computational vector architectures (e.g., SIMD processors) use sine and cosine techniques to produce highly accurate 32-bit sine and cosine results from 64-bit angle values ​​in a SIMD-friendly manner. As shown above, the two least significant bits of the 52-bit mantissa of the IEEE 754 double precision are used to store the unit circle quadrant. Greater efficiency and ease of use can be achieved by implementing these special instructions in hardware—setting, ignoring multiplication, and correctly setting the output value and sign using these bits. For example, these special instructions can avoid the poor performance of conditional statements in vector architectures.

[0258] Figure 7 An example of a data stream with a fixed width value passing through hardware used for parallel sine and cosine determination, according to an embodiment, is shown. This data stream shows the order of values ​​in a bit sequence. The original bit sequence 702 of the angle is processed to determine which quadrant the angle is in (operation 704). After determining the quadrant, the original bit sequence is modified such that the two least significant bits 708 store the quadrant encoding, while the remaining bits 706 remain unchanged. Furthermore, the value of the angle is reduced (e.g., converted to the first quadrant) to a single quadrant and placed in a second bit sequence 710 (again, operation 704).

[0259] Compress and copy the second bit sequence 710 (operation 712) to create a cosine (real) and sine (imaginary) combination value 714 of the same length as the second bit sequence 710. The combination value 714 can be stored in the second bit sequence (e.g., overwriting the quadrant-reduced value) or in an additional bit sequence.

[0260] The combined value 714 can be transmitted to hardware (e.g., an HTF tile or other SIMD device) to calculate the sine and cosine components (operation 720), thereby producing an intermediate value 718 in the third bit sequence. The intermediate value 718 is corrected to the final value using the quadrant code 708 in the first bit sequence 702 (operation 720). These final values ​​can then be returned to the requesting party of the sine and cosine operations.

[0261] Figure 8A and Figure 8BExamples of chiplet systems that can be used to implement one or more aspects of CNM system 102 are generally shown. As similarly mentioned above, nodes in CNM system 102 or devices within nodes in CNM system 102 may contain chiplet-based architectures or near-memory computing (CNM) chiplets. Packaged memory computing devices may contain, for example, one, two, or four CNM chiplets. Chipslets may be interconnected using high-bandwidth, low-latency interconnects (e.g., using CPI interfaces). Typically, a chiplet system consists of discrete modules (each referred to as a “chiplet”) integrated on an interposer layer and, in many instances, interconnected as needed via one or more established networks to provide the desired functionality to the system. The interposer layer and the contained chiplets may be packaged together to facilitate interconnection with other components of a larger system. Each chiplet may contain one or more individual integrated circuits (ICs) or “chips”, which may be combined with discrete circuit components and may be coupled to a corresponding substrate for attachment to the interposer layer. Most or all of the chiplets in the system may be individually configured to communicate via established networks.

[0262] Chiplets, configured as individual modules within a system, differ from systems implemented on a single chip containing different blocks of devices (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC) or multiple discrete packaged devices integrated on a printed circuit board (PCB). Generally, chiplets offer better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and provide greater manufacturing benefits than a single die chip. These manufacturing benefits may include higher yields or reduced development costs and time.

[0263] A chiplet system may comprise, for example, one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between application chiplets and support chiplets is merely a reference to possible design scenarios for chiplet systems. Thus, for example, a synthetic vision chiplet system may comprise (by way of example only) application chiplets for generating synthetic vision output, and support chiplets such as memory controller chiplets, sensor interface chiplets, or communication chiplets. In typical use cases, a synthetic vision designer may design the application chiplets and obtain the support chiplets from other sources. Therefore, design costs (e.g., in terms of time or complexity) are reduced by avoiding the design and manufacture of the functionality embodied in the support chiplets.

[0264] Chiplets also support the tight integration of IP blocks that might otherwise be difficult, such as IP blocks manufactured using different processing technologies or with different feature sizes (or utilizing different contact technologies or spacing). Therefore, multiple ICs or IC components with different physical, electrical, or communication characteristics can be assembled in a modular manner to provide a component with the desired functionality. Chiplet systems also facilitate adaptation to the needs of different larger systems that will be incorporated into chiplet systems. In examples, ICs or other components can be optimized for power, speed, or heat generation for specific functions, as might be the case with sensors, and can be integrated with other devices more easily than attempting integration on a single die. Furthermore, by reducing the overall die size, chiplet yields are often higher than those of more complex single-die devices.

[0265] Figure 8A and Figure 8B Examples of chiplet systems according to embodiments are generally shown. Figure 8A This is an illustration of a chiplet system 802 mounted on a peripheral board 804, which can be connected to a wider range of computer systems, for example, via peripheral component interconnect (PCIe). The chiplet system 802 includes a package substrate 806, an interposer 808, and four chips: an application chiplet 810, a host interface chiplet 812, a memory controller chiplet 814, and a memory device chiplet 816. Other systems may include numerous additional chipsets to provide additional functionality, as will be apparent from the following discussion. The package of the chiplet system 802 is shown as a cap or cover plate 818, but other packaging techniques and structures used for chiplet systems may be used. Figure 8B This is a block diagram illustrating the components in a chiplet system for clarity.

[0266] Application chip 810 is shown as a chiplet system NOC 820 including a chiplet network 822 for supporting inter-chiplet communication. In an example embodiment, the chiplet system NOC 820 may be included on application chip 810. In an example, the chiplet network 822 may be defined in response to selected supporting chips (e.g., host interface chip 812, memory controller chip 814, and memory device chip 816). Figure 1 The first NOC 118 in this example allows designers to choose the appropriate number of chiplet network connections or switches for the chiplet system NOC 820. In this example, the chiplet system NOC 820 may reside on a single chiplet or within the interposer layer 808. In the example discussed herein, the chiplet system NOC 820 implements a chiplet protocol interface (CPI) network.

[0267] In this example, the chiplet system 802 may include or comprise a portion of the first memory computing node 104 or the first memory computing device 112. That is, various blocks or components of the first memory computing device 112 may include chiplets that can be mounted on the peripheral board 804, the package substrate 806, and the interposer 808. The interface components of the first memory computing device 112 may typically include a host interface chiplet 812, the memory and memory control-related components of the first memory computing device 112 may typically include a memory controller chiplet 814, and the various accelerator and processor components of the first memory computing device 112 may typically include an application chiplet 810 or examples thereof.

[0268] For example, the CPI interface, which can be used for communication between or within chiplets in a system, is a packet network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI bridges the chiplet network 822. For instance, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communication. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, and power. Within a single chip, these options are typically selected to meet design goals, such as power consumption and speed. However, to achieve flexibility in chiplet systems, adapters such as CPI are used to intersect between various AXI design options that can be implemented in various chiplets. By implementing a mapping from physical channels to virtual channels and encapsulating time-based signaling using packetization protocols, CPI bridges the intra-chiplet network 822.

[0269] CPI can utilize various physical layers to transmit packets. A physical layer may contain simple conductive connections, or it may contain drivers to increase voltage, or otherwise facilitate signal transmission over longer distances. Examples of such physical layers may include an Advanced Interface Bus (AIB), which in various instances can be implemented within an intermediate layer 808. The AIB uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB at Single Data Rate (SDR) or Double Data Rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. Channels can be configured with a symmetrical number of transmit (TX) and receive (RX) inputs / outputs (I / O), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). A channel may act as either the AIB body or slave depending on which chip provides the master clock. The AIB I / O unit supports three clock modes: asynchronous (i.e., non-timing), SDR, and DDR. In various instances, the non-timing mode is used for clocking and some control signals. SDR mode can use a dedicated SDR-only I / O unit or a dual-purpose SDR / DDR I / O unit.

[0270] In this example, CPI packet protocols (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O units within an AIB channel. CPI streaming protocols allow for more flexible utilization of AIB I / O units. In this example, a streaming AIB channel can be configured with I / O units as all TX, all RX, or half TX and half RX. CPI packet protocols can use AIB channels in SDR or DDR operating modes. In this example, AIB channels are configured in increments of 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O units for DDR mode. CPI streaming protocols can use AIB channels in SDR or DDR operating modes. Here, in this example, AIB channels are configured in increments of 40 I / O units for both SDR and DDR modes. In this example, a unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine paired AIB channels across neighboring chiplets. In this example, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32 to 51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0271] AIB defines a stacked group of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels, plus auxiliary channels. The auxiliary channels contain signals used for AIB initialization. All AIB channels within a column (except for the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and the same number of data I / O signals). In this example, AIB channels are numbered sequentially in ascending order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0272] Typically, the CPI interface on each chiplet may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well-suited for scenarios requiring high-speed signaling and low signal counts. However, SERDES can introduce additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or power consumption is a primary concern for ultra-short-distance chiplet-to-chiplet interconnects, parallel interfaces that allow data transmission with minimal latency can be utilized. CPIs contain elements designed to minimize both latency and power consumption in these ultra-short-distance chiplet interconnects.

[0273] For flow control, CPI employs a credit-based technique. For example, the receiver side of chip 810, or the transmitter side of memory controller chip 814, provides credits indicating available buffers. In this example, the CPI receiver contains buffers for each virtual channel for a given transmission time unit. Therefore, if the CPI receiver supports five messages and a single virtual channel in time, the receiver has five buffers arranged in five rows (e.g., one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

[0274] When a sender transmits data to a receiver, the sender decrements its available credits based on the transmission. Once the receiver has used up all its credits, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store transmissions.

[0275] When the receiver processes the received packet and releases the buffer, it sends the available buffer space back to the sender. The sender can then use this credit return to allow the transmission of additional information.

[0276] Figure 8A Examples include a chiplet mesh network 824 that uses direct chiplet-to-chiplet technology without requiring a chiplet system NOC 820. The chiplet mesh network 824 can be implemented in CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 824 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chips in the pipeline interface only interface with themselves.

[0277] Alternatively, a dedicated device interface can be used to connect devices to the chiplets, such as one or more industry-standard memory interfaces (e.g., synchronous memory interfaces, such as DDR5, DDR6). A connection between a chiplet system or individual chiplets and an external device (e.g., a larger system) can be made via a desired interface (e.g., a PCIe interface). In an example, such an external interface can be implemented via a host interface chiplet 812, which, in the depicted example, provides a PCIe interface external to the chiplet system. This type of interface is typically used when industry practice or standards have converged on such a dedicated chiplet interface 826. The illustrated example of connecting a memory controller chiplet 814 to the dual data rate (DDR) interface of a dynamic random access memory (DRAM) memory device chiplet 816 is such an industry practice.

[0278] Among the various possible supporting chiplets, the memory controller chiplet 814 is likely to be present in chiplet systems due to the ubiquitous use of storage devices for computer processing and the current level of technological sophistication of memory devices. Therefore, using the memory device chiplet 816 and the memory controller chiplet 814, produced through other technologies, allows chiplet system designers to obtain robust products from established manufacturers. Typically, the memory controller chiplet 814 provides a memory device-specific interface for reading, writing, or erasing data. Typically, the memory controller chiplet 814 can provide additional functionality such as error detection, error correction, maintenance operations, or atomic operator execution. For some types of memory, maintenance operations are often specific to the memory device chiplet 816, such as garbage collection in NAND flash or storage-class memory, or temperature regulation (e.g., cross-temperature management) in NAND flash memory. In instances, maintenance operations may involve logic-to-physical (L2P) mapping or management to provide an indirection hierarchy between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at some times by the host processor or memory controller, and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as interface chips (in this example, buffers).

[0279] Atomic operators are data manipulations that can be performed, for example, by the memory controller chiplet 814. In other chiplet systems, atomic operators can be performed by other chipsets. For example, an application chiplet 810 can specify an "increment" atomic operator in a command that includes a memory address and may include an increment value. Upon receiving the command, the memory controller chiplet 814 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 814 provides the application chiplet 810 with an indication that the command was successful. Atomic operators avoid transferring data across the chiplet mesh network 824, thereby reducing latency in executing such commands.

[0280] Atomic operators can be categorized into built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a limited set of operations that are implemented invariantly in the hardware. Programmable atoms are small programs that can be executed on programmable atom units (PAUs) (e.g., custom atom units (CAUs)) of the memory controller chip 814.

[0281] The memory device chiplet 816 may be or contain any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM), such as synchronous DRAM (SDRAM), graphics dual data rate type 6 SDRAM (GDDR6 SDRAM), and so on. Examples of non-volatile memory devices include, but are not limited to, NAND flash memory, memory-class memory (e.g., phase-change memory or memristor-based technology), ferroelectric RAM (FeRAM), and so on. The example shown includes the memory device chiplet 816 as a chiplet; however, the device may reside elsewhere, such as in different packages on peripheral board 804. For many applications, multiple memory device chipsets may be provided. In examples, these memory device chipsets may each implement one or more memory technologies and may contain an integrated computing host. In examples, the memory chiplet may contain multiple stacked memory dies of different technologies, such as one or more static random access memory (SRAM) devices stacked with or otherwise communicating with one or more dynamic random access memory (DRAM) devices. In this example, the memory controller chiplet 814 can be used to coordinate the operation between multiple memory chipsets in the chiplet system 802, for example, using one or more memory chipsets in one or more tiers of cache memory, and using one or more additional memory chipsets as main memory. The chiplet system 802 may include multiple examples of the memory controller chiplet 814, which can be used to provide memory control functions for individual hosts, processors, sensors, networks, etc. For example, the chiplet architecture in the illustrated system offers advantages in allowing adaptation to different memory storage technologies; and provides different memory interfaces through updated chiplet configurations, for example, without requiring redesign of the rest of the system architecture.

[0282] Figure 9 This section generally illustrates examples of chiplet-based implementations for a memory computing device according to embodiments. The examples include implementations having four near-memory computing (CNM) chiplets, and each of the CNM chiplets may include or include components from… Figure 1 This refers to a portion of the first memory computing device 112 or the first memory computing node 104. Various portions may contain or include corresponding chiplets. Chiplet-based implementations may include or utilize CPI-based intra-system communication, as described above in [the context of...]. Figure 8A and Figure 8B The example of System-on-Chips 802 is discussed similarly.

[0283] Figure 9An example includes a first CNM package 900, which comprises a plurality of chiplets. The first CNM package 900 includes a first chiplet 902, a second chiplet 904, a third chiplet 906, and a fourth chiplet 908 coupled to a CNM NOC hub 910. Each of the first to fourth chiplets may include instances of the same or substantially the same components or modules. For example, each chiplet may each include instances of an HTP accelerator, an HTF accelerator, and a memory controller for accessing internal or external memory.

[0284] exist Figure 9 In one example, the first chiplet 902 includes a first NOC hub edge 914 coupled to the CNM NOC hub 910. Other chipslets in the first CNM package 900 similarly include NOC hub edges or endpoints. Switches in the NOC hub edges facilitate communication within the chiplet or within the chiplet system via the CNM NOC hub 910.

[0285] The first chiplet 902 may further include one or more memory controllers 916. The memory controller 916 may correspond to a different NOC endpoint switch that interfaces with the first NOC hub edge 914. In examples, the memory controller 916 may include a memory controller chiplet 814 or a memory controller 130, or a memory subsystem 200 or other memory computing implementation. The memory controller 916 may be coupled to a different memory device, such as a first external memory module 912A or a second external memory module 912B. The external memory module may include, for example, GDDR6 memory that is selectively accessible by a different chiplet in the system.

[0286] The first chiplet 902 may further include, for example, a first HTP chiplet 918 and a second HTP chiplet 920 coupled to the edge 914 of the first NOC hub via a corresponding different NOC endpoint switch. The HTP chipsets may correspond to an HTP accelerator, for example, from... Figure 1 The instance of HTP 140 or from Figure 4 An example of an HTP accelerator 400. The HTP chiplet can communicate with the HTF chiplet 922. The HTF chiplet 922 can correspond to an HTF accelerator, for example, from... Figure 1 The instance of HTF 142 or from Figure 5 The HTF 500 instance.

[0287] The CNM NOC hub 910 can be coupled to other chiplets or other CNM packages via various interfaces and switches. For example, the CNM NOC hub 910 can be coupled to a CPI interface via multiple different NOC endpoints on the first CNM package 900. Each of the multiple different NOC endpoints can be coupled to a different node, for example, outside the first CNM package 900. In an example, the CNM NOC hub 910 can be coupled to other peripheral devices, nodes, or devices using CTCPI or other non-CPI protocols. For example, the first CNM package 900 may include a PCIe scale interface (PCIE / SFI) or a CXL interface (CXL) configured to interface the first CNM package 900 with other devices. In an example, devices coupled to the first CNM package 900 using various CPI, PCIe, CXL, or other structures can form a common global address space.

[0288] exist Figure 9 In this example, the first CNM package 900 includes a host interface 924 (HIF) and a host processor (R5). The host interface 924 may correspond to, for example, a processor from... Figure 1 The instance is HIF 120. The host processor or R5 can correspond to the one from... Figure 1 The instance includes an internal host processor 122. The host interface 924 may include a PCI interface for coupling the first CNM package 900 to other external devices or systems. In this instance, work can be initiated via the host interface 924 on the first CNM package 900 or on a chip cluster within the first CNM package 900. For example, the host interface 924 may be configured to command individual HTF chip clusters (e.g., within various chiplets in the first CNM package 900) to enter and exit power / clock gating modes.

[0289] Figure 10 An example tile of a memory computing device according to an embodiment is shown. Figure 10 In the example, the tiled chiplet instance 1000 contains instances of four different near-memory computing clusters of chips, where the clusters are coupled together. Each instance of a near-memory computing chiplet may itself contain one or more constituent chips (e.g., host processor chips, memory device chips, interface chips, etc.).

[0290] The 1000 tiled chip instances contain data from... Figure 9An example of the first CNM package 900 is one or more of its near-memory computing (CNM) clusters. For example, a tiled chiplet instance 1000 may include a first CNM cluster 1002, which includes a first chiplet 1010 (e.g., corresponding to the first chiplet 902), a second chiplet 1012 (e.g., corresponding to the second chiplet 904), a third chiplet 1014 (e.g., corresponding to the third chiplet 906), and a fourth chiplet 1016 (e.g., corresponding to the fourth chiplet 908). The chipsets in the first CNM cluster 1002 may be coupled to a common NOC hub, which may in turn be coupled to NOC hubs in one or more adjacent clusters (e.g., in the second CNM cluster 1004 or the fourth CNM cluster 1008).

[0291] exist Figure 10 In this example, the tiled chiplet instance 1000 includes a first CNM cluster 1002, a second CNM cluster 1004, a third CNM cluster 1006, and a fourth CNM cluster 1008. These different CNM chipsets can be configured in a common address space, allowing chipsets to be allocated and share resources across different tiles. In this example, chipsets within a cluster can communicate with each other. For instance, the first CNM cluster 1002 can be communicatively coupled to the second CNM cluster 1004 via the inter-chiplet CPI interface 1018, and the first CNM cluster 1002 can be communicatively coupled to the fourth CNM cluster 1008 via another or the same CPI interface. The second CNM cluster 1004 can be communicatively coupled to the third CNM cluster 1006 via the same or another CPI interface, and so on.

[0292] In the example, one of the near-memory computing chiplets in the tiled chiplet instance 1000 may contain a host interface (e.g., corresponding to a source from...). Figure 9 The host interface (924) of the instance is responsible for workload balancing across the tiled chiplet instances 1000. The host interface can facilitate, for example, access to host-based command request queues and response queues from outside the tiled chiplet instances 1000. The host interface can dispatch new execution threads using hybrid thread processors and hybrid thread architectures in one or more near-memory computing chips within the tiled chiplet instances 1000.

[0293] Figure 11 This is a flowchart illustrating an example of a method 1100 for parallel sine and cosine determination using hardware according to an embodiment. The operation of method 1100 is performed by computer hardware, for example, regarding... Figure 1-5The computer hardware described in 8A-10 and 12 includes components such as memory computing device 112, memory controller 200, PAU 208 or PAU 302, HTP 400 or HTF 500, or in various combinations thereof. The computer hardware performing the operation of method 1100 includes a processing circuitry system configured (e.g., hard-wired, via software configuration including firmware, or a combination of both) to implement the operation.

[0294] At operation 1102, a first-bit sequence representing the angle of the line from the origin to the unit circle is obtained (e.g., received or retrieved). In this example, the processing circuitry is an HTF, and the first-bit sequence is obtained from the first channel of the HTF. In this example, the first-bit sequence has 64 bits.

[0295] At operation 1104, the unit circle quadrant of the line is determined based on the angle. In this example, the processing circuitry includes hardware blocks for determining the quadrant.

[0296] At operation 1106, the two least significant bits of the first sequence are replaced with the code of the quadrant.

[0297] At operation 1108, in a second bit sequence of the same length as the first bit sequence, the angle is reduced to the base quadrant angle. In an example, reducing the angle to the base quadrant angle in the second bit sequence involves subtracting the encoded quadrant multiplied by 90 degrees from the angle (e.g., ...). This process produces the result stored in the second bit sequence. In this example, the base quadrant angles are squared before being stored in the second bit sequence.

[0298] At operation 1110, sine and cosine operations (e.g., calculations) are performed on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant. In this example, the bit length of said portion of the second bit sequence is half the bit length of the first bit sequence. In this example, said portion of the second bit sequence has 32 bits.

[0299] At operation 1112, quadrant encoding in the first-order sequence is used on the intermediate sine and intermediate cosine solutions to create the final sine and final cosine solutions in the quadrants.

[0300] At operation 1114, the output represents the third bit sequence of the final sine and cosine solutions. In this example, the third bit sequence has the same length as the first bit sequence (e.g., the channel width of the HTF). In this example, the third bit sequence is output on the second channel of the HTF. In this example, the first or second channel of the HTF is directly connected to a tile in the HTF or connected to the HTP. In this example, the HTF is contained within a memory computing device that includes the HTP. In this example, the memory computing device is contained within a memory computing node of a near-memory computing system.

[0301] Such as about Figure 6 The quadrants mentioned could be the first quadrant between -45 degrees (e.g., 315 degrees) and 45 degrees, the second quadrant between 45 and 135 degrees, the third quadrant between 135 and 225 degrees, and the fourth quadrant between 225 and 315 degrees. In this context, when the quadrant is the first quadrant—based on the quadrant encoding in the first sequence—transforming the intermediate sine and cosine solutions to create the final sine and cosine solutions involves using the intermediate sine solution as the final sine solution and using the intermediate cosine solution as the final cosine solution. That is, nothing changes here; this quadrant is the base quadrant. However, if the quadrant is, in the instance, the second quadrant, then the inverse of the intermediate cosine solution is used as the final sine solution, and the inverse of the intermediate sine solution is used as the final cosine solution. Therefore, in the instance where the quadrant is the third quadrant, the inverse of the intermediate sine solution is used as the final sine solution, and the intermediate cosine solution is used as the final cosine solution. In instances where the quadrant is the fourth quadrant, the intermediate sine solution is used as the final sine solution, and the inverse of the intermediate cosine solution is used as the final cosine solution.

[0302] In this example, performing sine and cosine operations on the portion of the second bit sequence to create intermediate sine and cosine solutions in the base quadrant involves copying the 32 most significant bits of the second bit sequence to a first portion of the 64-bit value. Then, the 32 most significant bits of the second bit sequence are copied to a second portion of the 64-bit value. A sine operation is performed on one portion of the second bit sequence (e.g., the first half), and a cosine operation is performed on the other portion (e.g., the second half). In this example, the output of the sine operation replaces the first portion of the 64-bit value, and the cosine operation replaces the second portion of the 64-bit value. Here, the first and second portions refer to the positions where the sine and cosine operations are performed, respectively. Therefore, if the second half of the second bit sequence is used as input for a sine calculation, then the first portion where the output is stored is the second half of the second bit sequence.

[0303] In this example, the intermediate sine and cosine solutions in the base quadrant are stored in the third bit sequence. Here, the processing circuitry includes hardware blocks that accept the encoded first and second bit sequences of the quadrants to create the final sine and cosine solutions. In this example, the first bit sequence represents the variables of Euler's formula, the final sine solution is the imaginary part of the solution to Euler's formula with variables, and the final cosine solution is the real part of the solution to Euler's formula with variables.

[0304] Figure 12 A block diagram of an example machine 1200 is shown, which may be used, in, or through which any one or more techniques (e.g., methods) discussed herein may be implemented. As described herein, the example may contain logic or several components or mechanisms in, or operable by, machine 1200. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in the tangible entity of machine 1200, which includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may be flexible over time. A circuit system includes components that can perform specific operations individually or in combination during operation. In the example, the hardware of the circuit system may be designed in an immutable manner to perform specific operations (e.g., hardwiring). In the example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include machine-readable media that are physically modified (e.g., invariant magnetic properties of concentrated particles, electrically movable placement, etc.) to encode instructions for specific operations. When connecting physical components, the fundamental electrical properties of the hardware components are altered, for example, from an insulator to a conductor, or vice versa. Instructions enable embedded hardware (e.g., an execution unit or loading mechanism) to hardware-create parts of a circuit system via variable connections to perform specific operations when in operation. Thus, in an example, a machine-readable medium element is part of the circuit system or communicatively coupled to other components of the circuit system during device operation. In an example, any one of the physical components can be used in more than one part of more than one circuit system. For example, in operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and reused at different times by a second circuit of the first circuit system or by a third circuit of the second circuit system. Additional examples of these components of machine 1200.

[0305] In alternative embodiments, machine 1200 may operate as a standalone device or be connectable (e.g., network-connected) to other machines. In a networked deployment, machine 1200 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 1200 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1200 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by said machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered as encompassing any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, Software as a Service (SaaS), and other computer cluster configurations.

[0306] Machine 1200 (e.g., a computer system) may include a hardware processor 1202 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 1204, static memory 1206 (e.g., memory or storage device for firmware, microcode, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.), and mass storage device 1208 (e.g., hard disk drive, tape drive, flash storage device, or other block device), some or all of which may communicate with each other via interconnect 1230 (e.g., a bus). Machine 1200 may further include a display device 1210, an alphanumeric input device 1212 (e.g., a keyboard), and a user interface (UI) navigation device 1214 (e.g., a mouse). In an example, the display device 1210, the input device 1212, and the UI navigation device 1214 may be a touchscreen display. Machine 1200 may additionally include a mass storage device 1208 (e.g., a drive unit), a signal generation device 1218 (e.g., a speaker), a network interface device 1220, and one or more sensors 1216, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 1200 may include an output controller 1228, for example, serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0307] The registers of the hardware processor 1202, main memory 1204, static memory 1206, or mass storage device 1208 may be or contain a machine-readable medium 1222, on which one or more sets of data structures or instructions 1224 (e.g., software) embodying or used by any one or more of the techniques or functions described herein are stored. The instructions 1224 may also reside wholly or at least partially in any of the registers of the hardware processor 1202, main memory 1204, static memory 1206, or mass storage device 1208 during execution by the machine 1200. In this example, one or any combination of the hardware processor 1202, main memory 1204, static memory 1206, or mass storage device 1208 may constitute the machine-readable medium 1222. Although machine-readable medium 1222 is shown as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 1224.

[0308] The term "machine-readable medium" can include any medium capable of storing, encoding, or carrying instructions for execution by machine 1200 and causing machine 1200 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable media can include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In examples, non-transitory machine-readable media includes machine-readable media having a plurality of particles having an invariant (e.g., rest) mass and therefore being composed of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not contain transiently propagating signals. Specific examples of non-transitory machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable hard disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0309] In this example, information stored or otherwise provided on the machine-readable medium 1222 may represent instructions 1224, such as instructions 1224 themselves or a format from which instructions 1224 can be derived. This format from which instructions 1224 can be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), etc. The information representing instructions 1224 in the machine-readable medium 1222 may be processed by a processing circuitry system into instructions to perform any of the operations discussed herein. For example, deriving instructions 1224 from information (e.g., processed by a processing circuitry system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, depackaging, or otherwise manipulating information into instructions 1224.

[0310] In an example, the derivation of instruction 1224 may involve assembling, compiling, or decompiling information (e.g., by processing a circuit system) to produce instruction 1224 from some intermediate or preprocessed format provided by machine-readable medium 1222. When information is provided in multiple parts, the information may be combined, decapsulated, and modified to create instruction 1224. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted when transmitted over a network and, if necessary, decrypted, decompressed, assembled (e.g., linked), and compiled or decompiled at the local machine (e.g., into a stand-alone executable library, etc.) and executed by the local machine.

[0311] The network interface device 1220 can further utilize any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive instructions 1224 on the communication network 1226 using a transmission medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., IEEE 802.11 series standards, known as Wi-Fi®; IEEE 802.16 series standards, known as WiMax®), IEEE 802.15.4 series standards, peer-to-peer (P2P) networks, etc. In examples, the network interface device 1220 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to the communication network 1226. In an example, network interface device 1220 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 1200, and containing digital or analog communication signals or other intangible media used to facilitate communication of such software. The transmission medium is a machine-readable medium.

[0312] To better illustrate the methods and apparatus described herein, a set of non-limiting exemplary embodiments are set forth below as numbered examples.

[0313] Example 1 is a device comprising: a first port for a first channel having a bit width; a second port for a second channel having the same width as the first channel, wherein the device is part of a Hybrid Threaded Architecture (HTF), and wherein the first channel and the second channel are channels of the HTF; and a processing circuitry configured to: obtain from the first port a first bit sequence representing the angle of a line from the origin to a unit circle; determine the quadrant of the unit circle of the line; replace the two least significant bits of the first bit sequence with an encoding of the quadrant; and in a second port of the same length as the first bit sequence... In the bit sequence, the angle is reduced to the base quadrant angle; sine and cosine operations are performed on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant; the encoding of the quadrant in the first bit sequence is used on the intermediate sine and intermediate cosine solutions to create a final sine and final cosine solution in the quadrant; and a third bit sequence representing the final sine and final cosine solutions is output, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on the second port, and wherein the width of all channels of the HTF is equal to that of the first bit sequence.

[0314] In Example 2, the subject of Example 1 includes, wherein the quadrant is a first quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuit system is configured to: use the intermediate sine solution as the final sine solution; and use the intermediate cosine solution as the final cosine solution.

[0315] In Example 3, the subject of Examples 1-2 includes, wherein the quadrant is the second quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuit system is configured to: use the inverse of the intermediate cosine solution as the final sine solution; and use the inverse of the intermediate sine solution as the final cosine solution.

[0316] In Example 4, the subject of Examples 1-3 includes, wherein the quadrant is the third quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuit system is configured to: use the inverse solution of the intermediate sine solution as the final sine solution; and use the intermediate cosine solution as the final cosine solution.

[0317] In Example 5, the subject of Examples 1-4 includes the quadrant being the fourth quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuit system is configured to: use the intermediate sine solution as the final sine solution; and use the inverse of the intermediate cosine solution as the final cosine solution.

[0318] In Example 6, the subject of Examples 1-5 includes the case where the first or second channel of the HTF is directly connected to a tile in the HTF or connected to a Hybrid Thread Processor (HTP).

[0319] In Example 7, the subject of Example 6 includes the HTF being included in a memory computing device containing the HTP.

[0320] In Example 8, the subject of Example 7 includes the memory computing device being included in the memory computing node of the near-memory computing system.

[0321] In Example 9, the subject of Examples 1-8 is contained, wherein the first sequence has 64 bits.

[0322] In Example 10, the subject of Examples 1-9 includes the fact that the bit length of the portion of the second bit sequence is half the bit length of the first bit sequence.

[0323] In Example 11, the subject of Example 10 includes a portion of the second bit sequence having 32 bits.

[0324] In Example 12, the subject of Example 11 includes a processing circuit system configured to: copy the 32 most significant bits of the second bit sequence to a first portion of a 64-bit value; copy the 32 most significant bits of the second bit sequence to a second portion of the 64-bit value; perform the sine operation on the first portion of the 64-bit value; and perform the cosine operation on the second portion of the 64-bit value.

[0325] In Example 13, the subject of Example 12 includes wherein the output of the sine operation replaces the first portion of the 64-bit value, and wherein the cosine operation replaces the second portion of the 64-bit value.

[0326] In Example 14, the subject of Examples 1-13 includes the processing circuit system comprising hardware blocks for determining the quadrant.

[0327] In Example 15, the subject of Examples 1-14 includes the intermediate sine solution and the intermediate cosine solution in the base quadrant being stored in the third bit sequence, and the processing circuitry system comprising a hardware block that receives the first bit sequence and the second bit sequence encoded in the quadrant to create the final sine solution and the final cosine solution.

[0328] In Example 16, the subject of Examples 1-15 includes the following: wherein the first sequence is a variable of the Euler formula, and wherein the final sine solution is the imaginary part of the solution of the Euler formula with the said variable, and wherein the final cosine solution is the real part of the solution of the Euler formula with the said variable.

[0329] In Example 17, the subject of Examples 1-16 includes the following: in order to reduce the angle to the base quadrant angle in the second bit sequence, the processing circuitry is configured to subtract the encoded quadrant multiplied by 90 degrees from the angle to produce a result stored in the second bit sequence.

[0330] In Example 18, the subject of Example 17 includes, in order to reduce the angle to the base quadrant angle in the second bit sequence, the processing circuitry is configured to square the result before storing it in the second bit sequence.

[0331] In Example 19, the subject of Examples 1-18 includes the base quadrant which is between -45 degrees and 45 degrees (inclusive).

[0332] Example 20 is a method comprising: obtaining a first bit sequence representing the angle of a line from the origin to a unit circle via a processing circuit system, wherein the processing circuit system is part of a Hybrid Threaded Trace (HTF) structure, wherein the first bit sequence is obtained from a first channel of the HTF; determining the quadrant of the unit circle of the line via the processing circuit system; replacing the two least significant bits of the first bit sequence with the encoding of the quadrant via the processing circuit system; reducing the angle to a base quadrant angle in a second bit sequence of the same length as the first bit sequence; and performing sine and cosine operations on a portion of the second bit sequence. The processing circuitry performs a chord operation to create intermediate sine and intermediate cosine solutions in the base quadrant; uses the encoding of the quadrant in the first bit sequence on the intermediate sine and intermediate cosine solutions to create final sine and final cosine solutions in the quadrant; and outputs a third bit sequence representing the final sine and final cosine solutions, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on a second channel of the HTF, and wherein the width of all channels of the HTF is equal to the width of the first bit sequence.

[0333] In Example 21, the subject of Example 20 includes, wherein the quadrant is a first quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the intermediate sine solution as the final sine solution; and using the intermediate cosine solution as the final cosine solution.

[0334] In Example 22, the subject of Examples 20-21 includes, wherein the quadrant is the second quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the inverse of the intermediate cosine solution as the final sine solution; and using the inverse of the intermediate sine solution as the final cosine solution.

[0335] In Example 23, the subject of Examples 20-22 includes, wherein the quadrant is the third quadrant, and wherein using the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the inverse solution of the intermediate sine solution as the final sine solution; and using the intermediate cosine solution as the final cosine solution.

[0336] In Example 24, the subject of Examples 20-23 includes, wherein the quadrant is the fourth quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the intermediate sine solution as the final sine solution; and using the inverse of the intermediate cosine solution as the final cosine solution.

[0337] In Example 25, the subject of Examples 20-24 includes the case where the first or second channel of the HTF is directly connected to a tile in the HTF or connected to a Hybrid Thread Processor (HTP).

[0338] In Example 26, the subject of Example 25 includes the HTF being included in a memory computing device containing the HTP.

[0339] In Example 27, the subject of Example 26 includes the memory computing device being included in a memory computing node of a near-memory computing system.

[0340] In Example 28, the subject of Examples 20-27 includes the first sequence having 64 bits.

[0341] In Example 29, the subject of Examples 20-28 includes the fact that the bit length of said portion of the second bit sequence is half the bit length of the first bit sequence.

[0342] In Example 30, the subject of Example 29 includes, wherein the portion of the second bit sequence has 32 bits.

[0343] In Example 31, the subject of Example 30 includes performing the sine and cosine operations on said portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant, which includes: copying the 32 most significant bits of the second bit sequence to a first portion of the 64-bit value; copying the 32 most significant bits of the second bit sequence to a second portion of the 64-bit value; performing the sine operation on the first portion of the 64-bit value; and performing the cosine operation on the second portion of the 64-bit value.

[0344] In Example 32, the subject of Example 31 includes wherein the output of the sine operation replaces the first portion of the 64-bit value, and wherein the cosine operation replaces the second portion of the 64-bit value.

[0345] In Example 33, the subject matter of Examples 20-32 includes, wherein the processing circuitry system comprises hardware blocks for determining the quadrant.

[0346] In Example 34, the subject of Examples 20-33 includes the intermediate sine solution and the intermediate cosine solution in the base quadrant being stored in the third bit sequence, and the processing circuitry system comprising a hardware block that receives the first bit sequence and the second bit sequence encoded in the quadrant to create the final sine solution and the final cosine solution.

[0347] In Example 35, the subject of Examples 20-34 includes the following: wherein the first sequence is a variable of the Euler formula, and wherein the final sine solution is the imaginary part of the solution of the Euler formula with the said variable, and wherein the final cosine solution is the real part of the solution of the Euler formula with the said variable.

[0348] In Example 36, the subject of Examples 20-35 includes the fact that reducing the angle to the base quadrant angle in the second bit sequence comprises subtracting the encoded quadrant multiplied by 90 degrees from the angle to produce a result stored in the second bit sequence.

[0349] In Example 37, the subject of Example 36 includes the fact that reducing the angle to the base quadrant angle in the second bit sequence includes squaring the result before storing it in the second bit sequence.

[0350] In Example 38, the subject of Examples 20-37 includes the base quadrant which is between -45 degrees and 45 degrees (inclusive).

[0351] Example 39 is a machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations including: obtaining a first bit sequence representing the angle of a line from the origin to a unit circle, wherein the processing circuitry system is part of a hybrid threaded architecture (HTF), wherein the first bit sequence is obtained from a first channel of the HTF; determining the quadrant of the unit circle of the line; replacing the two least significant bits of the first bit sequence with the encoding of the quadrant; reducing the angle to a base quadrant angle in a second bit sequence of the same length as the first bit sequence; and so on. A portion of the second bit sequence performs sine and cosine operations to create intermediate sine and intermediate cosine solutions in the base quadrant; the encoding of the quadrant in the first bit sequence is used on the intermediate sine and intermediate cosine solutions to create final sine and final cosine solutions in the quadrant; and a third bit sequence representing the final sine and final cosine solutions is output, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on the second channel of the HTF, and wherein the width of all channels of the HTF is the same as the first bit sequence.

[0352] In Example 40, the subject of Example 39 includes, wherein the quadrant is a first quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the intermediate sine solution as the final sine solution; and using the intermediate cosine solution as the final cosine solution.

[0353] In Example 41, the subject of Examples 39-40 includes, wherein the quadrant is the second quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the inverse of the intermediate cosine solution as the final sine solution; and using the inverse of the intermediate sine solution as the final cosine solution.

[0354] In Example 42, the subject of Examples 39-41 includes, wherein the quadrant is the third quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the inverse solution of the intermediate sine solution as the final sine solution; and using the intermediate cosine solution as the final cosine solution.

[0355] In Example 43, the subject of Examples 39-42 includes, wherein the quadrant is the fourth quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: using the intermediate sine solution as the final sine solution; and using the inverse of the intermediate cosine solution as the final cosine solution.

[0356] In Example 44, the subject of Examples 39-43 includes the case where the first or second channel of the HTF is directly connected to a tile in the HTF or connected to a Hybrid Thread Processor (HTP).

[0357] In Example 45, the subject of Example 44 includes the HTF being included in a memory computing device containing the HTP.

[0358] In Example 46, the subject of Example 45 includes the memory computing device being included in a memory computing node of a near-memory computing system.

[0359] In Example 47, the subject of Examples 39-46 includes the first sequence having 64 bits.

[0360] In Example 48, the subject of Examples 39-47 includes the fact that the bit length of said portion of the second bit sequence is half the bit length of the first bit sequence.

[0361] In Example 49, the subject of Example 48 includes a portion of the second bit sequence having 32 bits.

[0362] In Example 50, the subject of Example 49 includes performing the sine and cosine operations on said portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant, which includes: copying the 32 most significant bits of the second bit sequence to a first portion of the 64-bit value; copying the 32 most significant bits of the second bit sequence to a second portion of the 64-bit value; performing the sine operation on the first portion of the 64-bit value; and performing the cosine operation on the second portion of the 64-bit value.

[0363] In Example 51, the subject of Example 50 includes wherein the output of the sine operation replaces the first portion of the 64-bit value, and wherein the cosine operation replaces the second portion of the 64-bit value.

[0364] In Example 52, the subject matter of Examples 39-51 includes, wherein the processing circuitry system comprises hardware blocks for determining the quadrant.

[0365] In Example 53, the subject of Examples 39-52 includes the storage of the intermediate sine and intermediate cosine solutions in the base quadrant within the third bit sequence, and the processing circuitry system includes hardware blocks that accept the first and second bit sequences encoded in the quadrant to create the final sine and final cosine solutions.

[0366] In Example 54, the subject of Examples 39-53 includes the following: wherein the first sequence is a variable of the Euler formula, and wherein the final sine solution is the imaginary part of the solution of the Euler formula with the said variable, and wherein the final cosine solution is the real part of the solution of the Euler formula with the said variable.

[0367] In Example 55, the subject of Examples 39-54 includes the fact that reducing the angle to the base quadrant angle in the second bit sequence comprises subtracting the encoded quadrant multiplied by 90 degrees from the angle to produce a result stored in the second bit sequence.

[0368] In Example 56, the subject of Example 55 includes the fact that reducing the angle to the base quadrant angle in the second bit sequence includes squaring the result before storing it in the second bit sequence.

[0369] In Example 57, the subject of Examples 39-56 includes the base quadrant which is between -45 degrees and 45 degrees (inclusive).

[0370] Example 58 is a system comprising: components for obtaining a first bit sequence representing an angle of a line from the origin to a unit circle, wherein the system is part of a Hybrid Threaded Trace (HTF) structure, wherein the first bit sequence is obtained from a first channel of the HTF; components for determining the quadrant of the unit circle of the line; components for replacing the two least significant bits of the first bit sequence with an encoding of the quadrant; components for reducing the angle to a base quadrant angle in a second bit sequence of the same length as the first bit sequence; components for performing sine and cosine operations on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant; components for using the encoding of the quadrant in the first bit sequence on the intermediate sine and intermediate cosine solutions to create final sine and final cosine solutions in the quadrant; and components for outputting a third bit sequence representing the final sine and final cosine solutions, wherein the third bit sequence is of the same length as the first bit sequence, wherein the third bit sequence is output on a second channel of the HTF, and wherein the width of all channels of the HTF is equal to the width of the first bit sequence.

[0371] In Example 59, the subject of Example 58 includes, wherein the quadrant is a first quadrant, and wherein the component for using the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: a component for using the intermediate sine solution as the final sine solution; and a component for using the intermediate cosine solution as the final cosine solution.

[0372] In Example 60, the subject of Examples 58-59 includes, wherein the quadrant is the second quadrant, and wherein the component for using the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: a component for using the inverse solution of the intermediate cosine solution as the final sine solution; and a component for using the inverse solution of the intermediate sine solution as the final cosine solution.

[0373] In Example 61, the subject of Examples 58-60 includes, wherein the quadrant is the third quadrant, and wherein the component for using the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: a component for using the inverse solution of the intermediate sine solution as the final sine solution; and a component for using the intermediate cosine solution as the final cosine solution.

[0374] In Example 62, the subject of Examples 58-61 includes, wherein the quadrant is the fourth quadrant, and wherein the component for using the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution includes: a component for using the intermediate sine solution as the final sine solution; and a component for using the inverse solution of the intermediate cosine solution as the final cosine solution.

[0375] In Example 63, the subject of Examples 58-62 includes the case where the first or second channel of the HTF is directly connected to a tile in the HTF or connected to a Hybrid Thread Processor (HTP).

[0376] In Example 64, the subject of Example 63 includes the HTF being included in a memory computing device containing the HTP.

[0377] In Example 65, the subject of Example 64 includes the memory computing device being included in a memory computing node of a near-memory computing system.

[0378] In Example 66, the subject of Examples 58-65 includes the first sequence having 64 bits.

[0379] In Example 67, the subject matter of Examples 58-66 includes the fact that the bit length of said portion of the second bit sequence is half the bit length of the first bit sequence.

[0380] In Example 68, the subject of Example 67 includes, wherein the portion of the second bit sequence has 32 bits.

[0381] In Example 69, the subject of Example 68 includes a component for performing the sine and cosine operations on said portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in said base quadrant, comprising: a component for copying the 32 most significant bits of the second bit sequence to a first portion of a 64-bit value; a component for copying the 32 most significant bits of the second bit sequence to a second portion of the 64-bit value; a component for performing the sine operation on the first portion of the 64-bit value; and a component for performing the cosine operation on the second portion of the 64-bit value.

[0382] In Example 70, the subject of Example 69 includes wherein the output of the sine operation replaces the first portion of the 64-bit value, and wherein the cosine operation replaces the second portion of the 64-bit value.

[0383] In Example 71, the subject of Examples 58-70 includes, wherein the system includes hardware blocks for determining the quadrant.

[0384] In Example 72, the subject of Examples 58-71 includes the intermediate sine solution and the intermediate cosine solution in the base quadrant being stored in the third bit sequence, and wherein the system includes a hardware block that accepts the first bit sequence and the second bit sequence encoded in the quadrant to create the final sine solution and the final cosine solution.

[0385] In Example 73, the subject of Examples 58-72 includes the following: wherein the first sequence is a variable of the Euler formula, and wherein the final sine solution is the imaginary part of the solution of the Euler formula with the said variable, and wherein the final cosine solution is the real part of the solution of the Euler formula with the said variable.

[0386] In Example 74, the subject of Examples 58-73 includes a component for reducing the angle to the base quadrant angle in the second bit sequence, which includes a component for subtracting the encoded quadrant multiplied by 90 degrees from the angle to produce a result stored in the second bit sequence.

[0387] In Example 75, the subject of Example 74 includes a component for reducing the angle to the base quadrant angle in the second bit sequence, which includes a component for squaring the result before storing it in the second bit sequence.

[0388] In Example 76, the subject of Examples 58-75 includes the base quadrant which is between -45 degrees and 45 degrees (inclusive).

[0389] Example 77 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any one of Examples 1-76.

[0390] Example 78 is a device that includes components for implementing any one of Examples 1-76.

[0391] Example 79 is a system for implementing any one of Examples 1-76.

[0392] Example 80 is a method for implementing any of Examples 1-76.

[0393] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by means of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of those elements shown or described are provided herein. Furthermore, the inventors also contemplate examples (or aspects thereof) of any combination or arrangement of those elements shown or described relative to a particular example (or one or more aspects thereof) or relative to other examples (or one or more aspects thereof) shown or described herein.

[0394] In this document, as is common in patent documents, the term “a (or an)” is used to include one or more, regardless of any other instances or uses of “at least one” or “one or more”. In this document, unless otherwise indicated, the term “or” is used to refer to a non-exclusive “or”, such that “A or B” may include “A but not B”, “B but not A”, and “A and B”. In the appended claims, the terms “comprising” and “in which” are used as common equivalents to the corresponding terms “including” and “wherein”. Furthermore, in the following claims, the terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed in the claims following such terms is still considered to be within the scope of the claims. Additionally, in the following claims, the terms “first,” “second,” and “third,” etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0395] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the above description. It is submitted under the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Similarly, in the above detailed description, various features may be grouped together to simplify this disclosure. This should not be construed as expecting that any unclaimed disclosed features are necessary for any claim. In fact, the subject matter of the invention may consist of fewer features than all of the particular disclosed embodiments. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and these embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents granted by the claims.

Claims

1. A hardware device for parallel sine and cosine determination, comprising: A first port for a first channel, the first channel having a bit width; A second port for a second channel, the second channel having the same width as the first channel, wherein the hardware device is part of a hybrid threaded architecture, and wherein the first channel and the second channel are channels of the hybrid threaded architecture; and The processing circuit system is configured as follows: Obtain a first-order sequence representing the angle of the line from the origin to the unit circle from the first port, wherein the first-order sequence has 64 bits; Determine the quadrant of the unit circle of the line; Replace the two least significant bits of the first bit sequence with the code of the quadrant; In a second bit sequence of the same length as the first bit sequence, the angle is reduced to the base quadrant angle; The parallel processing element of the hybrid thread structure simultaneously performs sine and cosine calculations on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant, wherein the portion of the second bit sequence has a bit length that is half the bit length of the first bit sequence, and wherein, in order to perform the sine and cosine calculations on the portion of the second bit sequence to create the intermediate sine and intermediate cosine solutions in the base quadrant, the processing circuit is configured to: The second bit sequence is converted from double precision to floating point, and the floating point is stored in the first part of the 64-bit value; Store the floating point value into the second part of the 64-bit value; Perform a sine calculation on the first portion of the 64-bit value; and Perform a cosine calculation on the second part of the 64-bit value; The encoding of the quadrant in the first bit sequence is used on the intermediate sine and cosine solutions to create the final sine and cosine solutions in the quadrants; and The output represents a third bit sequence of the final sine solution and the final cosine solution, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on the second port, and wherein the width of all channels of the hybrid thread structure is equal to that of the first bit sequence.

2. The hardware device of claim 1, wherein the quadrant is a first quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuitry is configured to: The intermediate sine solution is used as the final sine solution; and The intermediate cosine solution is used as the final cosine solution.

3. The hardware device of claim 1, wherein the quadrant is a second quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuitry is configured to: The inverse solution of the intermediate cosine solution is used as the final sine solution; and The inverse solution of the intermediate sine solution is used as the final cosine solution.

4. The hardware device of claim 1, wherein the quadrant is the third quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuitry is configured to: The inverse solution of the intermediate sine solution is used as the final sine solution; and The intermediate cosine solution is used as the final cosine solution.

5. The hardware device of claim 1, wherein the quadrant is the fourth quadrant, and wherein, in order to use the encoding of the quadrant in the first bit sequence on the intermediate sine solution and the intermediate cosine solution to create the final sine solution and the final cosine solution, the processing circuitry is configured to: The intermediate sine solution is used as the final sine solution; and The inverse solution of the intermediate cosine solution is used as the final cosine solution.

6. The hardware device according to claim 1, wherein the first channel or the second channel of the hybrid thread structure is directly connected to a tile in the hybrid thread structure or connected to a hybrid thread processor.

7. The hardware device of claim 6, wherein the hybrid threading architecture is included in a memory computing device comprising the hybrid threading processor.

8. The hardware device of claim 7, wherein the memory computing device is included in a memory computing node of a near-memory computing system.

9. The hardware device of claim 1, wherein the portion of the second bit sequence has 32 bits.

10. The hardware device of claim 1, wherein the output of the sine calculation replaces the first portion of the 64-bit value, and wherein the cosine calculation replaces the second portion of the 64-bit value.

11. The hardware device of claim 1, wherein the processing circuitry includes a hardware block for determining the quadrant.

12. The hardware device of claim 1, wherein the intermediate sine solution and the intermediate cosine solution in the base quadrant are stored in the third bit sequence, and wherein the processing circuitry includes a hardware block that receives the first bit sequence and the second bit sequence encoded in the quadrant to create the final sine solution and the final cosine solution.

13. The hardware device of claim 1, wherein the first sequence is a variable of Euler's formula, wherein the final sine solution is the imaginary part of the solution of Euler's formula with the variable, and wherein the final cosine solution is the real part of the solution of Euler's formula with the variable.

14. The hardware device of claim 1, wherein, in order to reduce the angle to the base quadrant angle in the second bit sequence, the processing circuitry is configured to subtract the encoded quadrant multiplied by 90 degrees from the angle to produce a result stored in the second bit sequence.

15. The hardware device of claim 14, wherein in order to reduce the angle to the base quadrant angle in the second bit sequence, the processing circuitry is configured to square the result before storing it in the second bit sequence.

16. The hardware device of claim 1, wherein the base quadrant is between -45 degrees and 45 degrees.

17. A machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations including: A first-order sequence representing the angle of a line from the origin to the unit circle is obtained, wherein the processing circuitry is part of a hybrid thread structure, wherein the first-order sequence is obtained from a first channel of the hybrid thread structure, and wherein the first-order sequence has 64 bits. Determine the quadrant of the unit circle of the line; Replace the two least significant bits of the first bit sequence with the code of the quadrant; In a second bit sequence of the same length as the first bit sequence, the angle is reduced to the base quadrant angle; The parallel processing elements of the hybrid thread structure simultaneously perform sine and cosine calculations on a portion of the second bit sequence to create intermediate sine and intermediate cosine solutions in the base quadrant, wherein the portion of the second bit sequence has a bit length that is half the bit length of the first bit sequence, and wherein, Performing the sine and cosine calculations on the portion of the second bit sequence to create the intermediate sine solution and the intermediate cosine solution in the base quadrant includes: The second bit sequence is converted from double precision to floating point, and the floating point is stored in the first part of the 64-bit value; Store the floating point value into the second part of the 64-bit value; Perform a sine calculation on the first portion of the 64-bit value; and Perform a cosine calculation on the second part of the 64-bit value; The encoding of the quadrant in the first bit sequence is used on the intermediate sine and cosine solutions to create the final sine and cosine solutions in the quadrants; and The output represents a third bit sequence of the final sine solution and the final cosine solution, wherein the third bit sequence has the same length as the first bit sequence, wherein the third bit sequence is output on the second channel of the hybrid thread structure, and wherein the width of all channels of the hybrid thread structure is equal to the width of the first bit sequence.

18. The machine-readable medium of claim 17, wherein the quadrant is a first quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine and cosine solutions to create the final sine and final cosine solutions comprises: The intermediate sine solution is used as the final sine solution; and The intermediate cosine solution is used as the final cosine solution.

19. The machine-readable medium of claim 17, wherein the quadrant is a second quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine and intermediate cosine solutions to create the final sine and final cosine solutions comprises: The inverse solution of the intermediate cosine solution is used as the final sine solution; and The inverse solution of the intermediate sine solution is used as the final cosine solution.

20. The machine-readable medium of claim 17, wherein the quadrant is the third quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine and intermediate cosine solutions to create the final sine and final cosine solutions comprises: The inverse solution of the intermediate sine solution is used as the final sine solution; and The intermediate cosine solution is used as the final cosine solution.

21. The machine-readable medium of claim 17, wherein the quadrant is the fourth quadrant, and wherein the encoding of the quadrant in the first bit sequence on the intermediate sine and cosine solutions to create the final sine and final cosine solutions comprises: The intermediate sine solution is used as the final sine solution; and The inverse solution of the intermediate cosine solution is used as the final cosine solution.

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