An input / output (IO) module and related apparatus
By designing PCIe connectors and cascaders, and utilizing the pull-down GND signal status and cascaded connections, the problem of difficulty in identifying the location and type of IO modules caused by the increase in the number of PCIe ports was solved. This enabled flexible deployment and rapid identification of IO modules, reducing design costs and quality risks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI CLOUD COMPUTING TECHNOLOGIES CO LTD
- Filing Date
- 2021-03-30
- Publication Date
- 2026-07-07
AI Technical Summary
As the number and speed of PCIe ports increase, the design limitations of connecting via booster cards become more pronounced. The physical location of IO modules and their corresponding ports are not fixed, leading to difficulties in server configuration and maintenance, and making it difficult for the CPU motherboard to identify the type of IO module.
Employing PCIe connectors and cascade designs, the signal state is changed by pulling down GND, enabling passive configuration and management. The IO modules are connected to the CPU motherboard via cascading, avoiding hard-wired limitations, simplifying PCB design, and quickly identifying module location and type.
It enables flexible deployment of IO modules, reduces design costs, avoids quality incidents caused by the inability to accurately determine the location or type of modules, and improves the scalability and ease of maintenance of the server.
Smart Images
Figure CN115145845B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to an input / output (IO) module and related devices. Background Technology
[0002] Currently, servers typically expand their network using risers or hard drive backplanes to accommodate devices such as high-speed Serial Computer Expansion Bus (PCIe) cards or Non-Volatile Memory Express (NVMe) hard drives. Servers need to identify the location and type of the corresponding I / O modules for system configuration and maintenance. The current identification principle is as follows: the I / O modules are hard-connected to the central processing unit (CPU) motherboard via risers. The location of the riser and the connection between the CPU motherboard's PCIe ports are fixed. The server maps the physical locations of the CPU motherboard's PCIe ports to the I / O modules using a fixed mapping method. Figure 1 As shown, the physical relationship between the CPU motherboard's PCIe ports and the I / O modules is essentially established through the riser card 101. With the increasing number of CPU PCIe ports and the ever-increasing PCIe link speeds, the limitations of this riser-based design have become increasingly apparent after the evolution to PCIe 5.0. The industry trend is to directly connect the CPU motherboard to the I / O modules via PCIe cables to improve the signal integrity (SI) of high-speed signals and increase the number of PCIe port connections.
[0003] The use of PCIe cables for flexible connections introduces a problem: the physical location of I / O modules and their corresponding ports are no longer fixed. The location of each I / O module on the CPU motherboard's PCIe ports changes depending on the cable connections, causing confusion for server configuration and maintenance. Furthermore, as PCIe cables are passive devices, the CPU motherboard has difficulty identifying the type of I / O module. Summary of the Invention
[0004] This application discloses an input / output (IO) module and related devices, which can improve the flexibility of IO module deployment.
[0005] In a first aspect, embodiments of this application provide an input / output (IO) module, which includes a connector and a cascade:
[0006] The connector can be a PCIe connector, which includes a first connector and a second connector. Each of the first connector and the second connector includes x pins. The first connector and the second connector are used to connect to the central processing unit (CPU) motherboard.
[0007] The cascade includes a first cascade and a second cascade. Each of the first and second cascades includes y pins. The y pins of the first cascade are respectively connected to the (xa) pins of the first connector and the (xa) pins of the second connector. The i-th pin of the y pins of the first cascade is left floating, and the j-th pin of the y pins of the second cascade is grounded. The pins of the first cascade except for the i-th pin are connected one-to-one with the pins of the second cascade except for the j-th pin. The states of the y pins of the first cascade and the y pins of the second cascade are used by the CPU motherboard to identify the position of the IO module.
[0008] Where a is an integer equal to or greater than 0, x is an integer greater than a, i and j are both integers, and i is not equal to j.
[0009] Based on the above design, the PCB board of the I / O module changes the signal state by pulling down GND, realizing passive configuration and management on a single board, simplifying the PCB design of the I / O module and reducing design costs. Furthermore, the I / O modules are cascaded, eliminating the need for fixed restrictions on the connection between the I / O modules and the CPU motherboard. This avoids relying on hard connections from the CPU motherboard to define the physical location of each I / O module, allowing for flexible expansion of the I / O modules and preventing quality issues caused by the CPU motherboard's inability to accurately determine the I / O module location.
[0010] In conjunction with the first aspect, in one alternative scheme of the first aspect, a is an integer greater than 0;
[0011] A of the x pins of the first connector are used for grounding or floating, and a of the x pins of the second connector are used for grounding or floating. The states of the a pins of the first connector and the a pins of the second connector are used by the CPU motherboard to identify the module type of the IO module.
[0012] Based on this approach, there is no need for additional design to specify the module type of each IO module. By simply configuring some pins of the IO module to be grounded or left floating, the CPU module can quickly and accurately determine the module type of the IO module. This allows the device to flexibly expand the IO modules and avoids quality accidents caused by the inability to accurately determine the module type.
[0013] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation of the first aspect, the positions of the a pins of the first connector among the x pins of the first connector are the same as the positions of the a pins of the second connector among the x pins of the second connector.
[0014] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation of the first aspect, the arrangement of the y pins of the first cascade is the same as the arrangement of the y pins of the second cascade.
[0015] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation of the first aspect, the IO module is a first IO module, and the y pins of the first cascade of the first IO module are used to be connected one-to-one with the y pins of the second cascade of the second IO module, wherein the structure of the second IO module is the same as the structure of the first IO module.
[0016] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation of the first aspect, the IO module is a first IO module, and the y pins of the second cascade of the first IO module are used to be connected one-to-one with the y pins of the first cascade of the third IO module, wherein the structure of the third IO module is the same as the structure of the first IO module.
[0017] In combination with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation of the first aspect, y = 2*(xa).
[0018] Secondly, embodiments of this application provide a device, which includes a first input / output (IO) module and a central processing unit (CPU) motherboard, wherein:
[0019] The first IO module includes a connector and a cascade.
[0020] The connector includes a first connector and a second connector, each of the first connector and the second connector including x pins;
[0021] The CPU motherboard has two different connectors that connect to the first connector and the second connector, respectively.
[0022] The cascade includes a first cascade and a second cascade. Each of the first and second cascades includes y pins. The y pins of the first cascade are respectively connected to the (xa) pins of the first connector and the (xa) pins of the second connector. The i-th pin of the y pins of the first cascade is left floating, and the j-th pin of the y pins of the second cascade is grounded. The pins of the first cascade except for the i-th pin are connected one-to-one with the pins of the second cascade except for the j-th pin. The states of the y pins of the first cascade and the y pins of the second cascade are used by the CPU motherboard to identify the position of the IO module.
[0023] Where a is an integer equal to or greater than 0, x is an integer greater than a, i and j are both integers, and i is not equal to j.
[0024] Based on the above design, the PCB board of the I / O module changes the signal state by pulling down GND, realizing passive configuration and management on a single board, simplifying the PCB design of the I / O module and reducing design costs. Furthermore, the I / O modules are cascaded, eliminating the need for fixed restrictions on the connection between the I / O modules and the CPU motherboard. This avoids relying on hard connections from the CPU motherboard to define the physical location of each I / O module, allowing for flexible expansion of the I / O modules and preventing quality issues caused by the CPU motherboard's inability to accurately determine the I / O module location.
[0025] In conjunction with the second aspect, in one possible implementation of the second aspect, a is an integer greater than 0;
[0026] A of the x pins of the first connector are used for grounding or floating, and a of the x pins of the second connector are used for grounding or floating. The states of the a pins of the first connector and the a pins of the second connector are used by the CPU motherboard to identify the module type of the IO module.
[0027] Based on this approach, there is no need for additional design to specify the module type of each IO module. By simply configuring some pins of the IO module to be grounded or left floating, the CPU module can quickly and accurately determine the module type of the IO module. This allows the device to flexibly expand the IO modules and avoids quality accidents caused by the inability to accurately determine the module type.
[0028] In conjunction with the second aspect, or any of the above possible implementations of the second aspect, another possible implementation of the second aspect further includes a second IO module, wherein:
[0029] The structure of the second IO module is the same as that of the first IO module, and the y pins of the first cascade of the first IO module are connected one-to-one with the y pins of the second cascade of the second IO module.
[0030] In conjunction with the second aspect, or any of the possible implementations of the second aspect described above, another possible implementation of the second aspect further includes a third I / O module, wherein:
[0031] The structure of the third IO module is the same as that of the first IO module, and the y pins of the second cascade of the first IO module are connected one-to-one with the y pins of the first cascade of the third IO module.
[0032] In conjunction with the second aspect, or any of the above possible implementations of the second aspect, in yet another possible implementation of the second aspect, if the maximum number of IO modules that the device is allowed to access is N, then y = N-1, where N is a positive integer.
[0033] By implementing the embodiments of this application, the PCB board of the IO module changes the signal state by pulling down GND, realizing passive configuration and management of the single board, simplifying the PCB design difficulty of the IO module and reducing design costs. Furthermore, the cascading of IO modules eliminates the need for fixed restrictions on the connection between the IO modules and the CPU motherboard. It does not rely on hard connections from the CPU motherboard to define the physical location attributes of each IO module, nor does it require additional design to specify the module type of each IO module. This allows for flexible expansion of IO modules and avoids quality incidents caused by the inability to accurately determine the module location or type. Attached Figure Description
[0034] The accompanying drawings used in the embodiments of this application are described below.
[0035] Figure 1 This is a schematic diagram showing the location of the booster card on the CPU motherboard in existing technology;
[0036] Figure 2 This is a schematic diagram of the structure of a device provided in an embodiment of this application;
[0037] Figure 3 This is a schematic diagram illustrating the connection relationship between a CPU motherboard and an I / O module according to an embodiment of this application;
[0038] Figure 4 This is a schematic diagram illustrating the connection relationship between IO modules provided in an embodiment of this application;
[0039] Figure 5 This is a schematic diagram illustrating another connection relationship between IO modules provided in an embodiment of this application;
[0040] Figure 6 This is a schematic diagram illustrating the connection relationship between IO modules provided in another embodiment of this application. Detailed Implementation
[0041] The embodiments of this application are described below with reference to the accompanying drawings.
[0042] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a device provided in an embodiment of this application. The device can be a server (e.g., a rack server) or other device with computing capabilities. The device includes a central processing unit (CPU) motherboard 201 and an I / O module 202. The device expands its configuration with network cards, accelerator cards, hard drives, etc., by configuring the I / O module 202. Figure 2 The illustration uses three I / O modules 202 as an example. In actual applications, there may be fewer or more I / O modules, and this application does not limit this. The CPU motherboard 201 has connectors (such as PCIe connectors), and each I / O module 202 is internally configured with a printed circuit board (PCB). The PCB also includes connectors. The connectors on the CPU motherboard 201 (such as PCIe connectors) and the connectors on the I / O modules 202 (such as PCIe connectors) are connected by high-speed cables 203 (such as PCIe high-speed cables).
[0043] Please see Figure 3 , Figure 3 This is a logical connection diagram. Black squares represent connectors (such as PCIe connectors). The CPU motherboard connectors (such as PCIe connectors) and the connectors on the I / O modules (PCIe connectors) are connected via high-speed cables 302. Each I / O module includes a cascader. Figure 3 The diagram uses black dots to illustrate this. Adjacent I / O modules are connected via cascade cable 301 based on a cascader. It should be noted that... Figure 3 The number of CPUs and I / O modules shown are merely illustrative diagrams. In this embodiment, the cascade is essentially a connector, and its function is to perform cascading.
[0044] Please see Figure 4 , Figure 4This is a schematic diagram of the connection relationship of an IO module provided in an embodiment of this application. Specifically, it illustrates the cascading relationship between three IO modules. Each IO module includes a connector and a cascader. The connector may include a first connector J2 and a second connector J3. The module cascader may include a first cascader J0 and a second cascader J1. The IO module is connected to the CPU motherboard through J2 and J3, and the IO module is connected to other IO modules through J0 and J1. Optionally, the cable used between the IO module and the CPU motherboard can be a high-speed cable, and the cable used between IO modules can be a low-speed cable. Of course, other types of cables can also be used, which are not limited here.
[0045] like Figure 4 As shown, if only one IO module is configured, it is placed at position 1, and the cascaders J0 and J1 of the IO module are left floating, i.e., no connection is needed; if two IO modules are configured, the cascader J0 of IO module 2 at position 2 is connected to the cascader J1 of IO module 1 at position 1; if three IO modules are configured, the cascader J0 of IO module 3 at position 3 is cascaded to the cascader J1 of IO module 2 at position 2, and so on. Theoretically, any number of modules can be configured.
[0046] In this embodiment, the connection method of the pins of the first connector J2, the second connector J3, the first cascade J0, and the second cascade J1 is designed to control the level signal of the IO module detected on the CPU motherboard. This allows the CPU motherboard to determine the location of the IO group based on the read level signal. Optionally, the module type of the IO group can also be determined based on the level signal. For ease of understanding, the following example is used... Figure 5 The connection method of the pins of the first connector J2, the second connector J3, the first cascade J0, and the second cascade J1 is described in detail.
[0047] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating the connection relationship between I / O modules according to an embodiment of this application. The diagram includes a CPU motherboard and several I / O modules. The CPU motherboard includes a power plane 501, and a pull-up resistor 503 connects the power plane 501 to each pin (each dot on the PCIe connector represents a pin) of each PCIe connector 502 (each small square represents a PCIe connector) on the CPU motherboard. Here, by pulling up the corresponding signal on the CPU motherboard and grounding some pins of the I / O module, a passive design of the I / O module can be achieved, eliminating the need for power supplies and additional components on the I / O module. The specific design principle of the I / O module is as follows.
[0048] Taking one of the I / O modules as an example, which can be called the first I / O module, the following relationship is satisfied:
[0049] The first I / O module includes a connector (e.g., a PCIe connector) and a cascade, wherein:
[0050] Part 1: The PCIe connector includes a first connector J2 and a second connector J3, each of which includes x pins. Figure 5 The illustration uses three connectors as an example. Each dot at J2 represents one pin, and each dot at J3 represents one pin. The first connector J2 and the second connector J3 are used to connect to the central processing unit (CPU) motherboard.
[0051] Optionally, pin a of the x pins of the first connector J2 is used for grounding or floating, and pin a of the x pins of the second connector J3 is used for grounding or floating. The states of pin a of the first connector J2 and pin a of the second connector J3 are used by the CPU motherboard to identify the module type of the IO module.
[0052] For example, if a = 1, then the first connector J2 and the second connector J3 have a total of two pins that can be used to identify the module type of the first I / O module. These two pins include the following four combinations: 1. First connector J2 is grounded, and second connector J3 is grounded; 2. First connector J2 is grounded, and second connector J3 is floating; 3. First connector J2 is floating, and second connector J3 is grounded; 4. First connector J2 is floating, and second connector J3 is floating. It can be understood that when the first connector J2 and the second connector J3 are connected to the CPU motherboard, the CPU motherboard can identify these four different results by reading the pin signals at its PCIe connectors. Therefore, if these four results correspond to four different module types, then the CPU motherboard can determine the module type of the first I / O module by reading the pin signals.
[0053] Please refer to Table 1, which illustrates one possible correspondence between pin status and module type:
[0054] Table 1
[0055]
[0056] In Table 1, 0 represents grounded and 1 represents floating. According to... Figure 5In the scenarios shown, if the first I / O module is one of the three I / O modules, then we can see that the first connector J2 of the first I / O module is grounded, and the second connector J3 is floating. Therefore, the CPU can identify the type of the first I / O module as "2 x8 devices". If there are other I / O modules, such as the second I / O module and the third I / O module, and the second I / O module has the same structure as the first I / O module (specifically, the leftmost I / O module among the three I / O modules), and the third I / O module also has the same structure as the first I / O module (specifically, the rightmost I / O module among the three I / O modules), then we can see that the first connector J2 of the second I / O module is grounded, and the second connector J3 is grounded. Therefore, the CPU can identify the type of the second I / O module as "1 x16 device". The first connector J2 of the third I / O module is floating, and the second connector J3 is floating. Therefore, the CPU can identify the type of the third I / O module as "4 x4 devices or no module configuration", and so on for other cases.
[0057] It is understandable that when a=2, connectors J2 and J3 have a total of 4 pins to identify the type of IO module. These 4 pins have a total of 16 possible states, so they can represent up to 16 different module types.
[0058] Optionally, the position of pin 'a' of the first connector J2 among the x pins of the first connector J2 is the same as the position of pin 'a' of the second connector J3 among the x pins of the second connector J3. For example, when a = 1, pin 'a' is the first, second, or last pin among the x pins, etc. Similarly, when a = 2, pin 'a' is the first two, the middle two, or the last two pins among the x pins, etc.
[0059] It is understandable that for each IO module, whether pins a of the x pins of its first connector and pins a of the x pins of its second connector are left floating or grounded is set according to the module type of the IO module. The state of these pins a of the first connector and pins a of the second connector of different IO modules can be set to the same or different, depending on the module type of each IO module.
[0060] The above examples illustrate four module types. In actual applications, some or all of these module types may not be included.
[0061] Part Two: The cascade includes a first cascade J0 and a second cascade J1. Each of the first cascade J0 and the second cascade J1 includes y pins. The y pins of the first cascade J0 are respectively connected to the (xa) pins of the first connector J2 and the (xa) pins of the second connector J3. The i-th pin of the y pins of the first cascade J0 is left floating, and the j-th pin of the y pins of the second cascade J1 is grounded. The pins of the first cascade J0 except for the i-th pin are connected one-to-one with the pins of the second cascade J1 except for the j-th pin. The states of the y pins of the first cascade J0 and the y pins of the second cascade J1 are used by the CPU motherboard to identify the location of the IO module. Wherein, a is an integer equal to or greater than 0, x is an integer greater than a, i and j are both integers, and i is not equal to j.
[0062] If a second IO module exists besides the first IO module, as long as the y pins of the first cascade J0 of the first IO module are connected one-to-one with the y pins of the second cascade J1 of the second IO module, for example, the first pin of the first cascade J0 of the first IO module is connected to the first pin of the second cascade J1 of the second IO module, the second pin of the first cascade J0 of the first IO module is connected to the second pin of the second cascade J1 of the second IO module, and so on, then the state of the y pins of the first cascade J0 of the second IO module will necessarily be different from the state of the y pins of the first cascade J0 of the first IO module. Therefore, the CPU can distinguish the positional difference between the first IO module and the second IO module based on the obtained pin states of the first IO module and the second IO module.
[0063] Similarly, if there exists a third IO module other than the first IO module, as long as the y pins of the second cascade J1 of the first IO module are connected one-to-one with the y pins of the first cascade J0 of the third IO module, for example, one pin of the second cascade J1 of the first IO module is connected to one pin of the first cascade J0 of the third IO module, two pins of the second cascade J1 of the first IO module are connected to two pins of the first cascade J0 of the third IO module, and so on, then the state of the y pins of the first cascade J0 of the third IO module will necessarily be different from the state of the y pins of the first cascade J0 of the first IO module. Therefore, the CPU can distinguish the positional differences between the first IO module and the third IO module based on the obtained pin states of the first IO module and the third IO module.
[0064] To make it easier to understand, let's illustrate with an example, such as... Figure 5 As shown, x = 3, a = 1, y = 4. That is, after removing the 1 pin used to indicate the module type from the 3 pins of the first connector J2, there are 2 pins left. After removing the 1 pin used to indicate the module type from the 3 pins of the second connector J3, there are 2 pins left. Therefore, the first connector J2 and the second connector J3 have a total of 4 pins left. These 4 remaining pins are exactly connected to the 4 pins of the first cascade J0. Therefore, the state of the 4 pins of the first cascade J0 can be obtained by the CPU motherboard.
[0065] If the 4th pin of the y pins of the first cascade J0 is left floating (i.e., i=4), and the 1st pin of the y pins of the second cascade J1 is grounded (i.e., j=1), the one-to-one connection between the pins of the first cascade J0 (excluding the i-th pin) and the pins of the second cascade J1 (excluding the j-th pin) specifically means: the 1st pin of the first cascade J0 is connected to the 2nd pin of the second cascade, the 2nd pin of the first cascade J0 is connected to the 3rd pin of the second cascade, and the 3rd pin of the first cascade J0 is connected to the 4th pin of the second cascade; the first IO module is... Figure 5 The three IO modules shown are arranged as follows: the middle IO module, the left-hand IO module, and the right-hand IO module. Therefore:
[0066] The four pins of the first cascade J0 of the first IO module are in the states of "grounded, floating, floating, floating".
[0067] The four pins of the first cascade J0 of the second IO module are in the states of "floating, floating, floating, floating".
[0068] The four pins of the first cascade J0 of the third IO module are in the states of "ground, ground, floating, floating".
[0069] Therefore, the pin states of the first, second, and third IO modules read by the CPU motherboard are different, so the positions of the first, second, and third IO modules can be distinguished based on the read pin states.
[0070] As shown in Table 2, Table 2 illustrates one possible correspondence between pin status and module position:
[0071] Table 2
[0072]
[0073] In Table 2, 1 indicates floating and 0 indicates grounding. Figure 5 Taking the situation shown in Table 2 as an example, the pin status of the first IO module read by the CPU motherboard is 0111, so it can be determined that the first IO module is located at module position 2. The pin status of the second IO module read by the CPU motherboard is 1111, so it can be determined that the second IO module is located at module position 1. The pin status of the third IO module read by the CPU motherboard is 0011, so it can be determined that the first IO module is located at module position 3.
[0074] The arrangement of the y pins in the first cascade is the same as that in the second cascade. This facilitates a one-to-one correspondence between the first and second cascades for different I / O modules.
[0075] Optionally, in the embodiments of this application, y = 2*(xa) is satisfied.
[0076] Understandably, with the above connection method, any number of IO modules can be configured for the above device in theory. However, in practical applications, an upper limit can be determined according to actual needs (or experience). If the upper limit is N, then in one possible scheme, y = N-1, where N is a positive integer.
[0077] Based on the above principles, the pin connection methods of the first connector J2, the second connector J3, the first cascade J0, and the second cascade J1 are designed. If a general-purpose 1U2P rack server needs to be configured with three IO modules, IO module 1 should be configured with two x8 PCIe slots for two x8 bandwidth PCIe cards, IO module 2 should be configured with one x16 PCIe slot for one x16 bandwidth PCIe card, and IO module 3 should be configured with four x4 slots for four NVMe SSDs. For example... Figure 6 As shown, IO module 1 is configured in module position 1, IO module 2 in module position 2, and IO module 3 in module position 3. Therefore, the following connection relationships exist: IO module 1 is cascaded with IO module 2 via cascade J1 and IO module 2 via cascade J0; IO module 2 is cascaded with IO module 3 via cascade J1 and IO module 3 via cascade J0 and cascade J1. The three IO modules are connected to a PCIe cable connector on the CPU motherboard via their respective connectors J2 and J3. The pin states of cascade J0, cascade J1, connector J2, and connector J3 for each of the three IO modules, along with the corresponding module position and module type, are shown in Table 3.
[0078] Table 3
[0079]
[0080] It is understandable that once the CPU motherboard reads the pin status of each of the three I / O modules, it can uniquely determine the module location and module type of each I / O module based on the pin status of each I / O module.
[0081] Optionally, the first connector J2 and the second connector J3 in this application embodiment can also be a single connector, that is, equivalent to a single connector including the pins of the first connector J2 and the pins of the second connector J3 in this application embodiment, and the pins of the cascade J0 are also connected to this single connector instead of the first connector J2 and the second connector J3.
[0082] Based on the above design, the PCB board of the I / O module changes the signal state by pulling down GND, realizing passive configuration and management on a single board, simplifying the PCB design of the I / O module and reducing design costs. Furthermore, the I / O modules are cascaded, eliminating the need for fixed restrictions on the connection between the I / O modules and the CPU motherboard. It does not rely on hard connections from the CPU motherboard to define the physical location of each I / O module, nor does it require additional design to specify the module type for each I / O module. This allows for flexible expansion of the I / O modules and avoids quality issues caused by the inability to accurately determine module location or type.
[0083] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by hardware running a computer program, which can be stored in a computer-readable storage medium. When executed, the computer program can implement the processes as described in the above method embodiments. The aforementioned storage medium includes various media capable of storing computer program code, such as ROM or RAM, magnetic disks, or optical disks.
Claims
1. An input / output (I / O) module, characterized in that, Includes connectors and cascades, wherein: The connector includes a first connector and a second connector, each of the first connector and the second connector including x pins, and the first connector and the second connector are used to connect to the central processing unit (CPU) motherboard. The cascade includes a first cascade and a second cascade. Each of the first and second cascades includes y pins. Two (xa) pins of the y pins of the first cascade are connected one-to-one with the (xa) pins of the first connector and the (xa) pins of the second connector. The i-th pin of the y pins of the first cascade is left floating, and the j-th pin of the y pins of the second cascade is grounded. All pins of the y pins of the first cascade except the i-th pin are connected one-to-one with all pins of the y pins of the second cascade except the j-th pin. The states of the y pins of the first cascade and the y pins of the second cascade are used by the CPU motherboard to identify the position of the IO module. Where a is an integer equal to or greater than 0, x is an integer greater than a, i and j are both integers, and i is not equal to j.
2. The IO module according to claim 1, characterized in that, a is an integer greater than 0; A of the x pins of the first connector are used for grounding or floating, and a of the x pins of the second connector are used for grounding or floating. The states of the a pins of the first connector and the a pins of the second connector are used by the CPU motherboard to identify the module type of the IO module.
3. The IO module according to claim 2, characterized in that, The positions of the a pins of the first connector among the x pins of the first connector are the same as the positions of the a pins of the second connector among the x pins of the second connector.
4. The IO module according to any one of claims 1-3, characterized in that, The arrangement of the y pins of the first cascade is the same as that of the y pins of the second cascade.
5. The IO module according to any one of claims 1-3, characterized in that, The IO module is a first IO module, and the y pins of the first cascade of the first IO module are used to connect one-to-one with the y pins of the second cascade of the second IO module. The structure of the second IO module is the same as that of the first IO module.
6. The IO module according to any one of claims 1-3, characterized in that, The IO module is a first IO module. The y pins of the second cascade of the first IO module are used to connect one-to-one with the y pins of the first cascade of the third IO module. The structure of the third IO module is the same as that of the first IO module.
7. The IO module according to any one of claims 1-3, characterized in that, y=2 (for).
8. A device with computing capabilities, characterized in that, Including the first input / output I / O module and the central processing unit (CPU) motherboard, wherein: The first IO module includes a connector and a cascade. The connector includes a first connector and a second connector, each of which includes x pins; The CPU motherboard has two different connectors that connect to the first connector and the second connector, respectively. The cascade includes a first cascade and a second cascade. Each of the first and second cascades includes y pins. Two (xa) pins of the y pins of the first cascade are connected one-to-one with the (xa) pins of the first connector and the (xa) pins of the second connector. The i-th pin of the y pins of the first cascade is left floating, and the j-th pin of the y pins of the second cascade is grounded. All pins of the y pins of the first cascade except the i-th pin are connected one-to-one with all pins of the y pins of the second cascade except the j-th pin. The states of the y pins of the first cascade and the y pins of the second cascade are used by the CPU motherboard to identify the position of the IO module. Where a is an integer equal to or greater than 0, x is an integer greater than a, i and j are both integers, and i is not equal to j.
9. The device according to claim 8, characterized in that, a is an integer greater than 0; A of the x pins of the first connector are used for grounding or floating, and a of the x pins of the second connector are used for grounding or floating. The states of the a pins of the first connector and the a pins of the second connector are used by the CPU motherboard to identify the module type of the IO module.
10. The device according to claim 8 or 9, characterized in that, It also includes a second IO module, in which: The structure of the second IO module is the same as that of the first IO module, and the y pins of the first cascade of the first IO module are connected one-to-one with the y pins of the second cascade of the second IO module.
11. The device according to claim 8 or 9, characterized in that, It also includes a third IO module, in which: The structure of the third IO module is the same as that of the first IO module, and the y pins of the second cascade of the first IO module are connected one-to-one with the y pins of the first cascade of the third IO module.
12. The device according to claim 8 or 9, characterized in that, The maximum number of I / O modules that the device is allowed to access is N, then y = N-1, where N is a positive integer.