Fft processing system, processing method and dsp processor

Abstract

The application provides an FFT processing system, a processing method and a DSP processor. The FFT processing system is realized based on a soft flow technology. A pipeline control module determines a pipeline control instruction based on the number of FFT points. The pipeline control instruction includes multiple butterfly operation instructions in time sequence. A soft flow FFT calculation module receives input data and a rotation factor. According to the parallelism of butterfly operation operations corresponding to the multiple butterfly operation instructions, the soft flow FFT calculation module executes micro operations corresponding to the multiple butterfly operation instructions on the input data and the rotation factor to obtain an FFT calculation result. The FFT processing system can greatly shorten the time consumed by FFT calculation, improve the efficiency of FFT calculation, and significantly reduce the power consumption of the FFT processing system as the hardware structure of the parallel execution of the butterfly operation instructions, so that the hardware cost of the FFT processing is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to an FFT processing system, processing method, and DSP processor. Background Technology

[0002] Digital signal processing (DSP) is a microprocessor with a special structure designed specifically for real-time and high-speed implementation of various digital signal processing operations. It can perform digital signal processing such as Fast Fourier Transform (FFT), Finite Impulse Response (FIR), complex multiplication and addition, correlation, trigonometric functions, and matrix operations at high speed.

[0003] The FFT operation is a fast implementation of the Discrete Fourier Transform (DFT). The FFT algorithm can be used for spectrum analysis, fast convolution, fast correlation, large integer multiplication, etc., and is a core method in signal processing applications such as wireless communication, speech signal processing, and image processing.

[0004] The computational efficiency of FFT operations directly impacts the overall execution efficiency of the application. Currently, hardware implementations of FFT operations primarily employ parallel pipelined architectures to meet the throughput and processing power requirements of real-world systems. Typical parallel pipelined architectures include the Multipath Delay Commutator (MDC) feedforward scheme and the Multipath Delay Feedback (MDF) feedback scheme. For multi-point sequences requiring FFT operations, both the MDC feedforward and MDF feedback structures require multiple pipelined computational units to perform intra-branch parallel FFT operations on the multi-point sequences, resulting in significant hardware resource overhead and low computational efficiency. Summary of the Invention

[0005] This invention provides an FFT processing system, processing method, and DSP processor to address the deficiencies in the prior art.

[0006] This invention provides an FFT processing system based on soft pipeline technology, comprising: a pipeline control module and a soft pipeline FFT calculation module, wherein the soft pipeline FFT calculation module is connected to the pipeline control module;

[0007] The pipeline control module is used to determine pipeline control instructions based on the number of FFT points, and the pipeline control instructions include multiple timing butterfly operation instructions;

[0008] The soft-flow FFT calculation module is used to receive input data and a rotation factor, and, based on the parallelism of the butterfly operation operations corresponding to the multiple butterfly operation instructions, execute the micro-operations corresponding to the multiple butterfly operation instructions on the input data and the rotation factor to obtain the FFT calculation result.

[0009] The input data includes a sequence with a preset transform length, which is equal to the number of FFT points; the micro-operations corresponding to the multiple butterfly operation instructions are obtained by periodically splitting the butterfly operation corresponding to the multiple butterfly operation instructions.

[0010] According to the FFT processing system provided by the present invention, the soft pipeline FFT calculation module includes a first-level butterfly operation unit that performs time-decimation.

[0011] The first-level butterfly operation unit is used to receive the input data, and according to the parallelism, to perform micro-operations corresponding to four cycles in each butterfly operation instruction on the input data and the rotation factor to obtain the first-level butterfly operation result, and to determine the FFT calculation result based on the first-level butterfly operation result.

[0012] According to an FFT processing system provided by the present invention, the soft pipelined FFT calculation module further includes a bit reversal processing unit and a second-level butterfly operation unit for time decimation; the first-level butterfly operation unit, the bit reversal processing unit, and the second-level butterfly operation unit are connected in sequence;

[0013] The bit reversal processing unit is used to perform bit reversal processing on the first-level butterfly operation result to obtain the bit reversal processing result.

[0014] The second-level butterfly operation unit is used to receive the bit reversal processing result, and according to the parallelism, to perform micro-operations corresponding to six cycles in each butterfly operation instruction on the bit reversal processing result and the rotation factor to obtain the second-level butterfly operation result, and to determine the FFT calculation result based on the second-level butterfly operation result.

[0015] According to the FFT processing system provided by the present invention, a selector is further included, the selector being connected to the first-stage butterfly operation unit, the second-stage butterfly operation unit and the pipeline control module respectively;

[0016] The pipeline control command also includes a selection command determined based on the preset transformation length;

[0017] The selector is used to select either the first-level butterfly operation result or the second-level butterfly operation result as the FFT calculation result based on the selection instruction.

[0018] According to the FFT processing system provided by the present invention, both the first-level butterfly operation unit and the second-level butterfly operation unit perform butterfly operations based on the radix-2 complex FFT algorithm.

[0019] An FFT processing system provided by the present invention further includes a rotation factor module, which is connected to the soft-flow FFT calculation module;

[0020] The rotation factor module is used to store the rotation factor.

[0021] The FFT processing system provided by the present invention further includes an output buffer module for storing and outputting the FFT operation results.

[0022] The present invention also provides a processing method based on the above-described FFT processing system, comprising:

[0023] Determine the input data;

[0024] The input data is input into the FFT processing system to obtain the FFT calculation result corresponding to the input data output by the FFT processing system.

[0025] The present invention also provides a DSP processor, including the above-described FFT processing system.

[0026] According to a DSP processor provided by the present invention, it further includes: a processing unit and a storage unit, wherein the processing unit is connected to the pipeline control module and the storage unit is connected to the soft pipeline FFT calculation module;

[0027] The storage unit is used to store the input data.

[0028] The present invention provides an FFT processing system, processing method, and DSP processor. The FFT processing system is implemented based on soft pipelining technology and includes a pipeline control module and a soft pipelining FFT calculation module, which are connected to the pipeline control module. The pipeline control module can determine pipeline control instructions based on the number of FFT points, including multiple timing-sequential butterfly operation instructions. The soft pipelining FFT calculation module can receive input data and a twitch factor, and, based on the parallelism of the butterfly operation operations corresponding to the multiple butterfly operation instructions, execute the micro-operations corresponding to the multiple butterfly operation instructions on the input data and the twitch factor to obtain the FFT calculation result. This FFT processing system can not only significantly shorten the time spent on FFT calculation and improve FFT calculation efficiency, but also, as a hardware structure for parallel execution of butterfly operation instructions, significantly reduce the power consumption of FFT processing, thus significantly reducing the hardware overhead of FFT processing. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on the drawings described below without creative effort.

[0030] Figure 1 This is one of the structural schematic diagrams of the FFT processing system provided by the present invention;

[0031] Figure 2 This is a schematic diagram of the radix-2 butterfly operation of the soft pipeline FFT calculation module in the FFT processing system provided by the present invention;

[0032] Figure 3 This invention provides a pipeline diagram of the FFT loop body when the butterfly operation corresponding to each butterfly operation instruction is not split.

[0033] Figure 4 This invention provides a pipeline diagram of the FFT loop body after decomposing the butterfly operation corresponding to each butterfly operation instruction;

[0034] Figure 5 This is a schematic diagram of the operation flow of the first-level butterfly operation unit of the soft pipeline FFT calculation module in the FFT processing system provided by the present invention;

[0035] Figure 6 This is a schematic diagram of the operation flow of the second-level butterfly operation unit of the soft pipeline FFT calculation module in the FFT processing system provided by the present invention;

[0036] Figure 7 This is the second schematic diagram of the FFT processing system provided by the present invention;

[0037] Figure 8 This is the third schematic diagram of the FFT processing system provided by the present invention;

[0038] Figure 9 This is a flowchart illustrating the processing method based on the FFT processing system provided by the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0040] To address the issues of high hardware resource consumption and low computational efficiency in the hardware implementation of FFT operations in existing technologies, this invention provides an FFT processing system.

[0041] Figure 1 This is a schematic diagram of an FFT processing system provided in an embodiment of the present invention. The FFT processing system is implemented based on soft pipeline technology, such as... Figure 1 As shown, the FFT processing system includes: a pipeline control module 1 and a soft pipeline FFT calculation module 2, wherein the soft pipeline FFT calculation module 2 is connected to the pipeline control module 1;

[0042] The pipeline control module 1 is used to determine pipeline control instructions based on the number of FFT points, and the pipeline control instructions include multiple timing butterfly operation instructions.

[0043] The soft-flow FFT calculation module 2 is used to receive input data and rotation factor, and according to the parallelism of the butterfly operation operations corresponding to the multiple butterfly operation instructions, perform micro-operations corresponding to the multiple butterfly operation instructions on the input data and the rotation factor to obtain the FFT calculation result, and use the FFT calculation result as the output data.

[0044] The input data includes a sequence with a preset transform length, which is equal to the number of FFT points; the micro-operations corresponding to the multiple butterfly operation instructions are obtained by periodically splitting the butterfly operation corresponding to the multiple butterfly operation instructions.

[0045] Specifically, the FFT processing system provided in this embodiment of the invention is implemented using soft pipelining technology. Soft pipelining is an optimization scheduling technique during the compilation process, including loop unrolling, overlapping execution of different iterations, and parallel scheduling instructions, making full use of hardware resources. Since there are some potentially parallelizable program segments in the FFT program, this embodiment of the invention optimizes the soft pipelining technology to allocate independent computational tasks to independent computing units for parallel execution, and to shorten the execution time of computational tasks by loop unrolling and overlapping execution of different loop iterations.

[0046] The FFT processing system includes a pipeline control module 1 and a soft-pipelined FFT calculation module 2, which is connected to the pipeline control module 1. The pipeline control module 1 can determine pipeline control instructions based on the number of FFT points. These pipeline control instructions include multiple timing-based butterfly operation instructions. In other words, the pipeline control module 1 can determine the pipeline control instructions based on the number of FFT points, and these instructions can be used to control the calculation process of the soft-pipelined FFT calculation module 2.

[0047] It is understandable that the FFT point count refers to the number of FFT points that the soft-pipelined FFT calculation module 2 can support. This number is equal to the sequence length of the input data for the soft-pipelined FFT calculation module. The input data can be the data to be calculated using FFT, and can include sequences with a preset transform length, such as x(n), where the preset transform length is N. Therefore, the FFT point count is equal to the preset transform length.

[0048] Since the soft pipelined FFT calculation module 2 needs to perform multiple loops of butterfly operations in chronological order, the pipeline control instructions can include multiple time-series butterfly operation instructions. These multiple butterfly operation instructions can be represented as hfft0, hfft1, hfft2, etc. The number of butterfly operation instructions is determined by the number of FFT points and is not specifically limited here.

[0049] Each butterfly operation instruction includes multiple cycles, and the number of cycles in each butterfly operation instruction is related to the preset transformation length. For example, if N is a power of 2, then each butterfly operation instruction can include 4 cycles; if N is a power of 4, then each butterfly operation instruction can include 10 cycles. No specific limitation is made here.

[0050] The soft-flow FFT calculation module 2 can receive input data and rotation factors. The input data can come from memory, and the rotation factors refer to the weights required when performing FFT calculations on the input data, which can also come from memory.

[0051] It is understandable that, since it is inevitable to cache the intermediate results obtained during the FFT calculation process, the soft pipeline FFT calculation module 2 in this embodiment of the invention has the function of accessing various registers or storage units.

[0052] The DFT of the input data x(n) is:

[0053]

[0054] in, Let x(n) be the rotation factor.

[0055] Decompose X(k) into even arrays X based on the parity of k. even (k) and odd number X odd (k), respectively:

[0056]

[0057]

[0058] Therefore, the N-point DFT can be divided into two N / 2-point DFTs:

[0059]

[0060]

[0061] X even (k) is denoted as a complex number P, where the real part of P is P r The imaginary part is P. i ; X odd (k) is denoted as a complex number Q, where the real part of Q is Q'. r The imaginary part is Q. i ;Will Let W be the denoted W, and let W' be the real part of W. r The imaginary part is W i ; can be done as follows Figure 2 The process shown performs a radix-2 butterfly operation on P and Q to obtain P′ and Q′ respectively, where the real part of P′ is P. r ′, where the imaginary part is P i Q′, the real part of Q′ is Q′ r ′, where the imaginary part is Q. i ′。 And there is:

[0062] P′=P+QW

[0063] Q′=P-QW

[0064] P r ′=P r +(Q r W r -Q i W i )

[0065] Q r ′=P r -(Q r W r -Q i W i )

[0066] P i ′=P i +(Q r W i +Q i W r )

[0067] Q i ′=P i -(Q r W i +Q i W r )

[0068] Therefore, when performing the butterfly operation corresponding to each butterfly operation instruction, each butterfly operation can include one multiplication and two additions, as well as micro-operations such as data reading. Each micro-operation can occupy one cycle of the butterfly operation instruction, or multiple micro-operations can occupy one cycle.

[0069] Therefore, in this embodiment of the invention, the potential parallelism of the butterfly operation corresponding to each butterfly operation instruction can be analyzed, that is, it can be determined which micro-operations in the butterfly operation corresponding to a butterfly operation instruction can be processed in parallel with the micro-operations in the butterfly operation corresponding to other butterfly operation instructions.

[0070] Furthermore, based on the parallelizability of the butterfly operations obtained from the analysis, the butterfly operation corresponding to each butterfly operation instruction is broken down into multiple micro-operations within each butterfly operation instruction, based on the cycle count. Here, the number of micro-operations within a butterfly operation is the same as the number of cycles of the corresponding butterfly operation instruction.

[0071] Taking an input data sequence of powers of 4 with a preset transformation length as an example, each butterfly operation instruction contains 10 cycles. Figure 3 This is a pipeline diagram of the FFT loop body when the butterfly operation corresponding to each butterfly operation instruction is not split. Figure 3 Only four butterfly operation instructions are shown: hfft0, hfft1, hfft2, and hfft3. The butterfly operation corresponding to each butterfly operation instruction is completed in 10 cycles, and there is no parallel execution between the butterfly operation instructions.

[0072] Figure 4 A pipeline diagram of the FFT loop body after decomposing the butterfly operation corresponding to each butterfly operation instruction. Figure 4 Only six butterfly operation instructions are shown: hfft0, hfft1, hfft2, hfft3, hfft4, hfft5, and hfft6. The butterfly operation corresponding to each butterfly operation instruction is completed in 10 cycles, and two adjacent butterfly operation instructions are executed in parallel starting from the third cycle.

[0073] Because the parallelism of butterfly operations is considered, when performing butterfly operations on the input data and twitch factor, the FFT calculation result is obtained by selectively executing the micro-operations corresponding to each butterfly operation instruction in parallel. Figure 3 and Figure 4A comparison shows that executing three butterfly operation instructions sequentially originally required 30 cycles, while considering the parallelism of butterfly operations, executing six butterfly operation instructions only requires 22 cycles. This significantly reduces the time spent on FFT calculations and improves FFT efficiency. Furthermore, the FFT processing system provided in this embodiment, as a hardware structure for parallel execution of butterfly operation instructions, significantly reduces FFT processing power consumption, thereby significantly reducing the hardware overhead of FFT processing.

[0074] The FFT processing system provided in this embodiment of the invention is implemented based on soft pipelining technology, including: a pipeline control module and a soft pipelining FFT calculation module, the soft pipelining FFT calculation module being connected to the pipeline control module; the pipeline control module can determine pipeline control instructions based on the number of FFT points, the pipeline control instructions including multiple timing-sequential butterfly operation instructions; the soft pipelining FFT calculation module can receive input data and a twitch factor, and based on the parallelism of the butterfly operation operations corresponding to the multiple butterfly operation instructions, execute the micro-operations corresponding to the multiple butterfly operation instructions on the input data and the twitch factor to obtain the FFT calculation result. This FFT processing system can not only greatly shorten the time consumed by FFT calculation and improve FFT calculation efficiency, but also, as a hardware structure for parallel execution of butterfly operation instructions, significantly reduce the power consumption of FFT processing, thus significantly reducing the hardware overhead of FFT processing.

[0075] Based on the above embodiments, the FFT processing system provided in this embodiment of the invention includes a soft pipeline FFT calculation module comprising a first-level butterfly operation unit that is time-decimated.

[0076] The first-level butterfly operation unit is used to receive the input data, and according to the parallelism, to perform micro-operations corresponding to four cycles in each butterfly operation instruction on the input data and the rotation factor to obtain the first-level butterfly operation result, and to determine the FFT calculation result based on the first-level butterfly operation result.

[0077] Specifically, in this embodiment of the invention, the soft pipeline FFT calculation module may include a first-level butterfly operation unit that is time-decimated. This first-level butterfly operation unit can receive input data and, based on parallelizability, perform micro-operations corresponding to the four cycles in each butterfly operation instruction on the input data and the twitch factor to obtain the first-level butterfly operation result.

[0078] Since the first-level butterfly operation unit can handle the micro-operations of four cycles in the butterfly operation instruction, the FFT processing system at this time is suitable for the case where the input data is a sequence of powers of 2 with a preset transform length.

[0079] The first-level butterfly operation unit includes two input ports, two output ports, and a four-cycle computation unit. One input port is used to input the real part P of the even array P obtained from the DFT decomposition of x(n) in the first cycle. r The real part Q of the odd array Q r Another input port is used for the imaginary part P of the even array P obtained by the DFT decomposition of the second-period input x(n). i The imaginary part Q of the odd array Q i The two output ports are used to output different parts of the first-stage butterfly operation result in a sequential manner.

[0080] The four-cycle computation unit is used to perform various micro-operations on the input data and the twiddle factor. The four-cycle computation unit may include a multiplication unit and an addition unit.

[0081] The operation flow of the first-level butterfly arithmetic unit is as follows: Figure 5 As shown.

[0082] In the first cycle, P r P i Read register BF1 from the input port and read the rotation factor W simultaneously. r and W i .

[0083] In the second cycle, Q r Q i BF2 is read from the input port, and the rotation factor W is read simultaneously. r Q r Q i The result Q is fed into the multiplication unit for multiplication, and then the multiplication result Q is... r W r Q i W r Store it in BF2, and store P in BF1. r and P i Store in BF2.

[0084] In the third cycle, Q in BF2 r W r Q i W r With P r P i The data is fed into the addition unit for addition and subtraction operations, and the result P is returned. r +Q r W r P r -Q r W r P i -Q i W r P i +Qi W r Store it in BF3, and store Q in BF2. r Q i With W i The data is fed into the multiplication unit for multiplication, and Q is... r W i Q i W i Store in BF3.

[0085] In the fourth cycle, P in BF3 is... r +Q r W r P r -Q r W r P i -Q i W r P i +Q i W r With Q r W i Q i W i The input is fed into the addition unit for addition and subtraction operations, and the result P is obtained. r +Q r W r -Q i W i P r -Q r W r +Q i W i P i -Q i W r -Q r W i P i +Q i W r +Q r W i That is, P r ′、Q r ′、P i ′、Q i Store the results in BF4. This completes the first-level butterfly calculation.

[0086] After obtaining the first-level butterfly operation result through the first-level butterfly operation unit, the final FFT calculation result can be determined through the first-level butterfly operation result. For example, the first-level butterfly operation result can be directly used as the FFT calculation result, i.e., P′ and Q′.

[0087] In this embodiment of the invention, the soft pipelined FFT calculation module of the FFT processing system includes a first-level butterfly operation unit that is time-decimated. This unit can perform FFT processing on sequences with a preset transform length of 2 powers, thereby shortening the time consumed by FFT calculation, improving FFT calculation efficiency, and reducing the power consumption and hardware overhead of the FFT processing system.

[0088] Based on the above embodiments, the FFT processing system provided in this embodiment of the invention further includes a bit reversal processing unit and a second-level butterfly operation unit that performs time-decimation in the FFT calculation module; the first-level butterfly operation unit, the bit reversal processing unit, and the second-level butterfly operation unit are connected in sequence.

[0089] The bit reversal processing unit is used to perform bit reversal processing on the first-level butterfly operation result to obtain the bit reversal processing result.

[0090] The second-level butterfly operation unit is used to receive the bit reversal processing result, and according to the parallelism, to perform micro-operations corresponding to six cycles in each butterfly operation instruction on the bit reversal processing result and the rotation factor to obtain the second-level butterfly operation result, and to determine the FFT calculation result based on the second-level butterfly operation result.

[0091] Specifically, in this embodiment of the invention, the soft pipelined FFT calculation module includes not only a first-level butterfly operation unit, but also a bit-reversal processing unit and a time-decimated second-level butterfly operation unit. The first-level butterfly operation unit, the bit-reversal processing unit, and the second-level butterfly operation unit are connected sequentially. The first-level butterfly operation result obtained by the first-level butterfly operation unit is bit-reversed by the bit-reversal processing unit and then subjected to six cycles of micro-operations by the second-level butterfly operation unit.

[0092] In other words, the soft-pipeline FFT calculation module, which combines the first-level butterfly operation unit, the bit reversal processing unit, and the second-level butterfly operation unit, can handle 10 cycles of micro-operations in the butterfly operation instructions. Therefore, the FFT processing system at this time is suitable for the case where the input data is a sequence of powers of 4 with a preset transformation length.

[0093] The second-level butterfly operation unit includes two input ports, two output ports, and a six-cycle calculation unit. One input port is used to input the real part Q of the first-level butterfly operation result in the first cycle. 0r And the imaginary part Q 0i And in the third period, the real part P of a data P0 in the sequence corresponding to the input data is input. 0r and the imaginary part P 0i The other input port is used to input the real part Q of the result of the second first-level butterfly operation in the first cycle.1r And the imaginary part Q 1i And in the third period, input the real part P of another data P1 in the sequence corresponding to the input data. 1r and the imaginary part P 1i The two output ports are used to output different parts of the second-stage butterfly operation result in a sequential manner.

[0094] The six-cycle computation unit is used to perform various micro-operations on the input data and the rotation factor. The six-cycle computation unit may include a multiplication unit and an addition unit.

[0095] The operation flow of the second-level butterfly arithmetic unit is as follows: Figure 6 As shown.

[0096] In the first cycle, Q 0r Q 0i Q 1r Q 1i Read register BF1 from the input port and read the rotation factor W simultaneously. 0r W 0i and Q 0r Q 0i respectively with W 0r W 0i Multiply and convert the result Q. 0r W 0r Q 0i W 0i Store in register BF1.

[0097] In the second cycle, Q in BF1 0r W 0r Q 0i W 0i The result is Q, which is fed into the addition unit for subtraction. 0r W 0r -Q 0i W 0i And store it in BF2, and transfer Q from BF1. 0i Q 0r With W 0r W 0i The result Q is fed into the multiplication unit for multiplication and the result is then passed to the multiplication unit. 0i W 0r and Q 0r W 0i Store it in register BF2, and set Q 1r Q 1i Store in register BF2.

[0098] In the third cycle, the P input to the port will be... 0r Q in BF2 0r W 0r -Q 0i W0i The data is fed into the addition unit for addition and subtraction operations, and the result P is calculated. 0r +Q 0r W 0r -Q 0i W 0i and P 0r -(Q 0r W 0r -Q 0i W 0i The data is stored in register BF3, and the data in BF3 at this time is output as the first and second data in the second-level butterfly calculation result.

[0099] Q in BF2 0i W 0r and Q 0r W 0i The result Q is sent to the addition unit for addition operation and then processed. 0i W 0r +Q 0r W 0i Store in BF3, and it will be linked with Q. 1r Q 1i Store in register BF3, and then connect BF2 with Q. 1r Q 1i respectively with W 1r W 1i Multiply and convert the result Q. 1r W 1r and Q 1i W 1i Store it in BF3, and input P to the port. 0i Store in register BF3, and set the port input P 1r P 1i Save to BF3.

[0100] In the fourth cycle, Q stored in BF3 is... 0r W 0i +Q 0i W 0r And P in BF3 0i The result is P, which is fed into the addition unit for addition and subtraction operations. 0i +Q 0r W 0i +Q 0i W 0r and P 0i -(Q 0r W 0i +Q 0i W 0r Store the data in BF4, and output the data in BF4 as the third and fourth data in the second-level butterfly calculation result.

[0101] Q in BF3 1i Q 1r With W 1r W 1i The result Q is fed into the multiplication unit for multiplication and the result is then passed to the multiplication unit. 1i W 1r and Q 1r W 1i Store it in BF4, and store Q from BF3. 1r W 1r and Q 1i W 1i The result Q is fed into the addition unit for subtraction and then processed. 1r W 1r -Q 1i W 1i Store in BF4, and store P in BF3. 1r P 1i Save to BF4.

[0102] In the fifth cycle, Q in BF4 1r W 1r -Q 1i W 1i And P in BF4 1r The data is fed into the addition unit for addition and subtraction operations, and the result P is returned. 1r +Q 1r W 1r -Q 1i W 1i and P 1r -(Q 1r W 1r -Q 1i W 1i Store the data in BF5, and output the data in BF5 as the fifth and sixth data in the second-level butterfly calculation result.

[0103] Q in BF4 1r W 1r and Q 1r W 1i The result Q is sent to the addition unit for addition operation and then processed. 1r W 1r +Q 1r W 1i Store in BF5, and store P in BF4. 1i Save to BF5;

[0104] In the sixth cycle, Q in BF5 is... 1i W 1r +Q 1r W 1i And P in BF4 1i The data is fed into the addition unit for addition and subtraction operations, and the result P is returned. 1i+Q 1r W 1r +Q 1r W 1i and P 1i -(Q 1r W 1r +Q 1r W 1i The data is stored in BF6, and then the data in BF6 at this point is output as the seventh and eighth data in the second-level butterfly calculation result. Thus, the complete second-level butterfly calculation result is obtained.

[0105] In this embodiment of the invention, the soft pipelined FFT calculation module of the FFT processing system includes a first-level butterfly operation unit with time decimation, a bit reversal processing unit, and a second-level butterfly operation unit with time decimation. It can perform FFT processing on sequences with a preset transform length of 4 exponents, which can shorten the time consumed by FFT calculation, improve FFT calculation efficiency, and reduce the power consumption and hardware overhead of the FFT processing system.

[0106] Based on the above embodiments, the FFT processing system provided in this embodiment of the invention further includes a selector, which is connected to the first-level butterfly operation unit, the second-level butterfly operation unit and the pipeline control module respectively;

[0107] The pipeline control command also includes a selection command determined based on the preset transformation length;

[0108] The selector is used to select either the first-level butterfly operation result or the second-level butterfly operation result as the FFT calculation result based on the selection instruction.

[0109] Specifically, in the embodiments of the present invention, such as Figure 7 As shown, in the case where the soft pipelined FFT calculation module 2 includes a time-decimated first-level butterfly operation unit 21, a bit-reversal processing unit 22, and a time-decimated second-level butterfly operation unit 23, it may also include a selector 24. This selector 24 can be connected to the first-level butterfly operation unit 21, the second-level butterfly operation unit 22, and the pipeline control module 1, respectively. The pipeline control instructions also include a selection instruction determined based on a preset transform length. This selection instruction is used to control the selector. Through this selection instruction, the selector can be controlled to choose either the first-level butterfly operation result or the second-level butterfly operation result as the FFT calculation result output.

[0110] After receiving a selection instruction, the selector can choose either the result of the first-level butterfly operation or the result of the second-level butterfly operation as the FFT calculation result for output.

[0111] In this embodiment of the invention, the soft-pipelined FFT computation module of the FFT processing system includes a first-level butterfly operation unit with time decimation, a bit reversal processing unit, and a second-level butterfly operation unit with time decimation. Combined with a selector, and controlled by the pipeline control module, the selector can perform FFT processing on sequences with a preset transform length of a power of 2, as well as sequences with a preset transform length of a power of 4. This not only shortens the time consumed by FFT computation, improves FFT computation efficiency, reduces the power consumption and hardware overhead of the FFT processing system, but also expands the application scope of the FFT processing system.

[0112] Based on the above embodiments, in the FFT processing system provided in this embodiment of the invention, both the first-level butterfly operation unit 21 and the second-level butterfly operation unit 22 can perform butterfly operations using the radix-2 complex FFT algorithm.

[0113] like Figure 8 As shown, based on the above embodiments, the FFT processing system provided in this embodiment of the invention further includes a rotation factor module 3, which is connected to the soft-flow FFT calculation module 2; the rotation factor module 3 is used to store the rotation factor.

[0114] Specifically, in this embodiment of the invention, the FFT processing system may further include a rotation factor module, which stores the rotation factors required for FFT calculation of the input data. During the calculation process, when a rotation factor is needed, a read request can be sent to the rotation factor module to retrieve the corresponding rotation factor.

[0115] like Figure 8 As shown, based on the above embodiments, the FFT processing system provided in this embodiment of the invention further includes an output buffer module 4, which enables the storage and output of FFT operation results.

[0116] The output buffer module 4 can be connected to the pipeline control module 1. The pipeline control instructions can include output buffer instructions. Specifically, the output buffer module can be used to store and output the FFT operation results according to the output buffer instructions.

[0117] like Figure 9 As shown, based on the above embodiments, this embodiment of the invention also provides a processing method based on the FFT processing system provided in the above embodiments, including:

[0118] S1, Determine the input data;

[0119] S2, input the input data into the FFT processing system to obtain the FFT calculation result corresponding to the input data output by the FFT processing system.

[0120] Specifically, the processing method provided in this embodiment of the invention is executed by an FFT processing device, which can be a DSP processor or configured within a DSP processor, and is not specifically limited here.

[0121] First, step S1 can be executed to determine the input data. This input data can come from memory, and there are no specific limitations here.

[0122] Then, step S2 is executed, where the input data is input into the FFT processing system. The pipeline control module in the FFT processing system determines the pipeline control instructions based on the number of FFT points. The soft pipeline FFT calculation module then performs micro-operations corresponding to multiple butterfly operation instructions on the input data and twiddle factor according to the parallelism of the butterfly operation operations corresponding to multiple butterfly operation instructions in the pipeline control instructions, and obtains the FFT calculation results.

[0123] The processing method provided in this embodiment of the invention first determines the input data; then, the input data is input to the FFT processing system to obtain the FFT calculation result corresponding to the input data output by the FFT processing system. This processing method can not only greatly shorten the time spent on FFT calculation and improve the efficiency of FFT calculation, but also reduce the hardware power consumption of FFT processing, thus greatly reducing the hardware overhead of FFT processing.

[0124] In existing technologies, FFT calculations often employ a "general-purpose core + accelerator" approach. This approach introduces an additional high-speed bus between the master and slave ends of the processor to enable the accelerator to access on-chip memory, increasing hardware resources and memory access power consumption. Therefore, based on the above embodiments, this invention also provides a DSP processor, including the FFT processing system provided in the above embodiments. This reduces the computation time and increases the computation efficiency of the DSP processor during FFT calculations, while also reducing the hardware power consumption of the DSP processor.

[0125] Based on the above embodiments, the DSP processor provided in this embodiment of the invention further includes: a processing unit and a storage unit. The processing unit is connected to the pipeline control module and can be used to control the pipeline control module. The storage unit is connected to the soft pipeline FFT calculation module and can be used to store input data and provide FFT calculation objects to the soft pipeline FFT calculation module.

[0126] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0127] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An FFT processing system, characterized in that, Based on soft pipeline technology, it includes: a pipeline control module and a soft pipeline FFT calculation module, wherein the soft pipeline FFT calculation module is connected to the pipeline control module; The pipeline control module is used to determine pipeline control instructions based on the number of FFT points. The pipeline control instructions include multiple timing butterfly operation instructions. The number of butterfly operation instructions is determined by the number of FFT points. The soft-flow FFT calculation module is used to receive input data and a twitch factor, and, based on the parallelizability of the butterfly operations corresponding to the multiple butterfly operation instructions, execute the micro-operations corresponding to the multiple butterfly operation instructions on the input data and the twitch factor to obtain the FFT calculation result; the parallelizability refers to the micro-operations that can be processed in parallel with the butterfly operation corresponding to one butterfly operation instruction and the butterfly operation corresponding to other butterfly operation instructions. The input data includes a sequence with a preset transform length, which is equal to the number of FFT points; the micro-operations corresponding to the multiple butterfly operation instructions are obtained by periodically splitting the butterfly operation corresponding to the multiple butterfly operation instructions.

2. The FFT processing system according to claim 1, characterized in that, The soft-flow FFT calculation module includes a first-level butterfly operation unit that extracts data by time. The first-level butterfly operation unit is used to receive the input data, and according to the parallelism, to perform micro-operations corresponding to four cycles in each butterfly operation instruction on the input data and the rotation factor to obtain the first-level butterfly operation result, and to determine the FFT calculation result based on the first-level butterfly operation result.

3. The FFT processing system according to claim 2, characterized in that, The soft pipelined FFT calculation module also includes a bit reversal processing unit and a second-level butterfly operation unit that performs time-decimation; the first-level butterfly operation unit, the bit reversal processing unit, and the second-level butterfly operation unit are connected in sequence. The bit reversal processing unit is used to perform bit reversal processing on the first-level butterfly operation result to obtain the bit reversal processing result. The second-level butterfly operation unit is used to receive the bit reversal processing result, and according to the parallelism, to perform micro-operations corresponding to six cycles in each butterfly operation instruction on the bit reversal processing result and the rotation factor to obtain the second-level butterfly operation result, and to determine the FFT calculation result based on the second-level butterfly operation result.

4. The FFT processing system according to claim 3, characterized in that, It also includes a selector, which is connected to the first-level butterfly operation unit, the second-level butterfly operation unit and the pipeline control module respectively; The pipeline control command also includes a selection command determined based on the preset transformation length; The selector is used to select either the first-level butterfly operation result or the second-level butterfly operation result as the FFT calculation result based on the selection instruction.

5. The FFT processing system according to claim 3, characterized in that, Both the first-level butterfly operation unit and the second-level butterfly operation unit perform butterfly operations based on the radix-2 complex FFT algorithm.

6. The FFT processing system according to any one of claims 1-5, characterized in that, It also includes a rotation factor module, which is connected to the soft flow FFT calculation module; The rotation factor module is used to store the rotation factor.

7. The FFT processing system according to any one of claims 1-5, characterized in that, It also includes an output buffer module for storing and outputting the FFT calculation results.

8. A processing method based on the FFT processing system as described in any one of claims 1-7, characterized in that, include: Determine the input data; The input data is input into the FFT processing system to obtain the FFT calculation result corresponding to the input data output by the FFT processing system.

9. A DSP processor, characterized in that, Includes the FFT processing system as described in any one of claims 1-7.

10. The DSP processor according to claim 9, characterized in that, Also includes: The system includes a processing unit and a storage unit, wherein the processing unit is connected to the pipeline control module and the storage unit is connected to the soft pipeline FFT calculation module. The storage unit is used to store the input data.

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