Semiconductor memory device

Abstract

An embodiment of the present application provides a semiconductor memory device that operates at high speed. The semiconductor memory device of an embodiment includes a first pad that receives a first signal; a second pad that receives a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and capable of storing user data read from the first memory cell array; and a control circuit capable of performing an operation that targets the first memory cell array. The first memory cell array includes a plurality of first memory strings. Each of the plurality of first memory strings includes a plurality of first memory cell transistors. In addition, the semiconductor memory device acquires a set of instructions that indicate an operation via the first pad in a first mode. In addition, the semiconductor memory device acquires a set of instructions that indicate an operation via the second pad in a second mode.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-57290 (filed on March 30, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a memory cell array including a plurality of memory cells; and peripheral circuitry connected to the memory cell array, which outputs user data according to an input of an instruction set including instruction data and address data. Summary of the Invention

[0005] One embodiment of the present invention provides a high-speed semiconductor memory device.

[0006] One embodiment of a semiconductor memory device includes: a first pad for receiving a first signal; a second pad for receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and capable of storing user data read from the first memory cell array; and control circuitry capable of performing operations targeting the first memory cell array. The first memory cell array includes a plurality of first memory strings. Each of the plurality of first memory strings includes a plurality of first memory cell transistors. Furthermore, in a first mode, the semiconductor memory device obtains an instruction set indicating an operation via the first pad. Furthermore, in a second mode, the semiconductor memory device obtains an instruction set indicating an operation via the second pad. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0008] Figure 2 This is a schematic side view showing an example of the configuration of the memory system 10.

[0009] Figure 3 This is a schematic top view showing an example of the configuration of the memory system 10.

[0010] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0011] Figure 5 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0012] Figure 6 This is a schematic 3D diagram showing a partial structure of a memory die (MD).

[0013] Figure 7 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0014] Figure 8 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0015] Figure 9 It is a schematic diagram used to illustrate the action mode MODEa.

[0016] Figure 10 It is a schematic diagram used to illustrate the action mode MODEb.

[0017] Figure 11 It is a truth table used to describe the action mode MODEa.

[0018] Figure 12 It is a truth table used to describe the action mode MODEb.

[0019] Figure 13 It is a truth table used to describe the action mode MODEb.

[0020] Figure 14 It is a schematic waveform diagram used to illustrate the action mode MODEa.

[0021] Figure 15 It is a schematic waveform diagram used to illustrate the action mode MODEb.

[0022] Figure 16 It is a schematic timing diagram used to illustrate the action mode MODEa.

[0023] Figure 17 It is a schematic timing diagram used to illustrate the action mode MODEa.

[0024] Figure 18 It is a schematic timing diagram used to illustrate the action mode MODEb.

[0025] Figure 19 It is a schematic timing diagram used to illustrate the action mode MODEb.

[0026] Figure 20 This is a schematic circuit diagram showing a partial configuration example of a memory die (MD).

[0027] Figure 21 It is a schematic waveform diagram used to illustrate the operation method of the memory die MD.

[0028] Figure 22This is a schematic circuit diagram showing a partial configuration example of a memory die (MD).

[0029] Figure 23 This is a schematic circuit diagram showing a partial configuration example of a memory die (MD).

[0030] Figure 24 This is a schematic block diagram showing the configuration of the memory die MD2 in the second embodiment.

[0031] Figure 25 This is a schematic circuit diagram showing a partial configuration of the memory die MD2.

[0032] Figure 26 It is a truth table used to describe the action mode MODEc.

[0033] Figure 27 It is a truth table used to describe the action mode MODEc.

[0034] Figure 28 It is a schematic waveform diagram used to illustrate the operation of the memory die MD2.

[0035] Figure 29 It is a schematic waveform diagram used to illustrate the operation of the memory die MD2.

[0036] Figure 30 This is a schematic circuit diagram showing a partial configuration example of the memory die MD2.

[0037] Figure 31 This is a schematic block diagram showing the configuration of the memory die MD3 in the third embodiment.

[0038] Figure 32 It is a schematic waveform diagram used to illustrate the operation of the MD3 memory die.

[0039] Figure 33 This is a schematic block diagram showing the configuration of the memory die MD4 in the fourth embodiment.

[0040] Figure 34 This is a schematic block diagram representing the structure of the MD4 memory die.

[0041] Figure 35 It is a truth table used to describe the action mode MODEd.

[0042] Figure 36 It is a schematic waveform diagram used to illustrate the operation of the MD4 memory die.

[0043] Figure 37 It is a schematic waveform diagram used to illustrate the operation of the MD4 memory die.

[0044] Figure 38It is a schematic waveform diagram used to illustrate the operation of the MD4 memory die.

[0045] Figure 39 This is a schematic waveform diagram used to illustrate the operation of a memory die in another embodiment. Detailed Implementation

[0046] The semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention.

[0047] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to a memory die (memory chip), and sometimes to a memory system that includes a controller die, such as a memory card or SSD (Solid State Drive). Moreover, it sometimes refers to a device including a host, such as a smartphone, tablet, or personal computer.

[0048] Furthermore, in this specification, when the first component is described as being "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in an OFF state, the first transistor is still "electrically connected" to the third transistor.

[0049] Additionally, in this specification, when it is stated that the first component is "connected" between the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected via the first and third components.

[0050] Furthermore, in this specification, when it is stated that a circuit or the like "makes" two wirings "conduct", it means, for example, that the circuit or the like includes a transistor or the like, and that the transistor or the like is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0051] [First Implementation]

[0052] [Memory System 10]

[0053] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0054] The memory system 10 performs reading, writing, erasing, and the like of user data in accordance with signals transmitted from the host 20. The memory system 10 is, for example, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory dies MD that store user data, and a controller die CD connected to the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc., and performs processes such as logical address and physical address translation, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0055] Figure 2 is a schematic side view illustrating a configuration example of the memory system 10 of the present embodiment. Figure 3 is a schematic top view illustrating the configuration example of the present embodiment. For convenience of description, Figure 2 and Figure 3 a part of the configuration is omitted in the drawings.

[0056] As shown in Figure 2 , the memory system 10 of the present embodiment includes a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided in an end region in the Y direction on the upper surface of the mounting substrate MSB, and the other region is bonded to the lower surface of the memory die MD via an adhesive or the like. Pad electrodes P are provided in an end region in the Y direction on the upper surface of the memory die MD, and the other region is bonded to the lower surface of another memory die MD or the controller die CD via an adhesive or the like. Pad electrodes P are provided in an end region in the Y direction on the upper surface of the controller die CD.

[0057] As shown in Figure 3 , the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD each include a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory dies MD, and the controller die CD are connected to one another via bonding wires B, respectively.

[0058] Furthermore, Figure 2 and Figure 3 the illustrated configurations are merely examples, and specific configurations can be appropriately adjusted. For example, in Figure 2 and Figure 3In the illustrated example, a controller die CD is stacked on a plurality of memory dies MD, and these components are connected by bonding wires B. In this configuration, the plurality of memory dies MD and the controller die CD are contained in a single package. However, the controller die CD may be contained in a different package from the memory dies MD. Further, the plurality of memory dies MD and the controller die CD may be connected to each other via through electrodes or the like instead of the bonding wires B.

[0059] [Configuration of Memory Die MD]

[0060] Figure 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 5 is a schematic circuit diagram showing a partial configuration of the memory die MD. Figure 6 is a schematic perspective view showing a partial configuration of the memory die MD. Figure 7 and Figure 8 are schematic circuit diagrams showing a partial configuration of the memory die MD. For convenience of description, Figures 4-8 a part of the configuration is omitted in the drawings.

[0061] Furthermore, Figure 4 a plurality of control terminals and the like are illustrated in the drawings. The plurality of control terminals may be represented as control terminals corresponding to high-active signals (positive logic signals), as control terminals corresponding to low-active signals (negative logic signals), or as control terminals corresponding to both high-active signals and low-active signals. Figure 4 in the drawings, the symbols of the control terminals corresponding to low-active signals include an overline (overbar). In the present specification, the symbols of the control terminals corresponding to low-active signals include a slash (" / "). Moreover, Figure 4 the description above is an example, and specific aspects can be appropriately adjusted. For example, part or all of the high-active signals can be made into low-active signals, or part or all of the low-active signals can be made into high-active signals.

[0062] Further, in Figure 4 the drawings, arrows indicating the input / output directions are illustrated beside the plurality of control terminals shown. Figure 4 in the drawings, a control terminal marked with an arrow pointing from left to right can be used to input data or other signals from the controller die CD to the memory die MD. Figure 4 in the drawings, a control terminal marked with an arrow pointing from right to left can be used to output data or other signals from the memory die MD to the controller die CD. Figure 4 in the drawings, a control terminal marked with a bidirectional arrow pointing left and right can be used to input data or other signals from the controller die CD to the memory die MD, and to output data or other signals from the memory die MD to the controller die CD.

[0063] like Figure 4 As shown, the memory die MD includes: memory cell arrays MCA0 and MCA1 for storing user data; and peripheral circuitry PC connected to memory cell arrays MCA0 and MCA1. Furthermore, in the following description, memory cell arrays MCA0 and MCA1 are sometimes referred to as memory cell array MCA. Additionally, memory cell arrays MCA0 and MCA1 are sometimes referred to as planar arrays PLN0 and PLN1.

[0064] [Composition of a Memory Cell Array (MCA)]

[0065] like Figure 5 As shown, the memory cell array MCA has multiple memory blocks BLK. Each of these memory blocks BLK has multiple string components SU. Each of these string components SU has multiple memory strings MS. One end of each of these memory strings MS is connected to the peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0066] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), a source-side selection transistor (STS), and a source-side selection transistor (STSb). Hereinafter, the drain-side selection transistor (STD), the source-side selection transistor (STS), and the source-side selection transistor (STSb) are sometimes simply referred to as selection transistors (STD, STS, STSb).

[0067] A memory cell (MC) is a field-effect transistor (FET) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. A memory cell (MC) stores one or more bits of user data. Furthermore, the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS) are connected to word lines (WL). These word lines (WL) are collectively connected to all memory strings (MS) within a memory block (BLK).

[0068] Select transistors (STD, STS, STSb) are field-effect transistors (FETs) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS, SGSb) are connected to the gate electrodes of the select transistors (STD, STS, STSb). The drain-side select gate line SGD corresponds to a string assembly SU and is commonly connected to all memory strings MS within a single string assembly SU. The source-side select gate line SGS is commonly connected to all memory strings MS within a memory block BLK. The source-side select gate line SGSb is commonly connected to all memory strings MS within a memory block BLK.

[0069] For example, Figure 6 As shown, the memory cell array MCA is disposed above the semiconductor substrate 100. Furthermore, Figure 6 In the example, between the semiconductor substrate 100 and the memory cell array MCA, there are multiple transistors Tr that constitute the peripheral circuit PC.

[0070] The memory cell array (MCA) has multiple memory blocks (BLKs) arranged in the Y direction. In addition, an inter-block insulating layer (ST) such as silicon oxide (SiO2) is disposed between two adjacent memory blocks (BLKs) in the Y direction.

[0071] For example, Figure 6 As shown, the memory block BLK includes: a plurality of conductive layers 110 arranged in the Z direction; a plurality of semiconductor pillars 120 extending in the Z direction; and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0072] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0073] Additionally, two or more of the bottommost conductive layers 110 among the multiple conductive layers 110 serve as source-side selected gate lines SGS, SGSb ( Figure 5 The gate electrodes of the multiple source-side selection transistors STS and STSb connected to the source-side selection gate lines SGS and SGSb function as such. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0074] Additionally, the plurality of conductive layers 110 located above the plurality of conductive layers 110 serve as word lines WL ( Figure 5 ), and multiple memory cells MC connected to the word line WL ( Figure 5 The gate electrode of the ) functions. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0075] Additionally, one or more conductive layers 110 located above the plurality of conductive layers 110 serve as drain-side selected gate lines SGD and a plurality of drain-side selected transistors STD connected to the drain-side selected gate lines SGD. Figure 5 The gate electrode of the conductive layer 110 functions. The width of the multiple conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110.

[0076] Below the conductive layer 110, a semiconductor layer 112 is provided. The semiconductor layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the semiconductor layer 112 and the conductive layer 110.

[0077] Semiconductor layer 112 serves as the source line SL ( Figure 5 To perform its function. The source line SL is, for example, commonly set in all memory blocks BLK contained within the memory cell array MCA.

[0078] For example, Figure 6 As shown, the semiconductor pillars 120 are arranged in a specific pattern in the X and Y directions. The semiconductor pillars 120 serve as a memory string (MS). Figure 5 The multiple memory cells MC and the channel regions of the selection transistors (STD, STS, STSb) contained within the semiconductor pillar 120 function as semiconductor layers, such as polycrystalline silicon (Si). Figure 6 As shown, the semiconductor pillar 120 has a generally bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central part. In addition, the outer peripheral surfaces of the semiconductor pillar 120 are surrounded by conductive layers 110, which face each other.

[0079] At the upper end of the semiconductor pillar 120, there is an impurity region 121 containing N-type impurities such as phosphorus (P). The impurity region 121 is connected to the bit line BL via contact Ch and contact Cb.

[0080] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 may include, for example, a tunnel insulating film, a charge storage film, and a barrier insulating film deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the barrier insulating film may be insulating films such as silicon oxide (SiO2). The charge storage film may be a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film, the charge storage film, and the barrier insulating film have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0081] In addition, the gate insulating film 130 may also have a floating gate, such as polysilicon containing N-type or P-type impurities.

[0082] Multiple contacts CC are provided at the ends of the multiple conductive layers 110 in the X direction. The multiple conductive layers 110 are connected to the peripheral circuit PC via these multiple contacts CC. Figure 6 As shown, these multiple contacts CC extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contacts CC may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0083] [Construction of the peripheral circuit PC]

[0084] For example, Figure 4 As shown, the peripheral circuit PC includes line decoders RD0 and RD1, and sense amplifiers SA0 and SA1, which are respectively connected to the memory cell arrays MCA0 and MCA1. Additionally, the peripheral circuit PC includes a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC includes input / output control circuits (I / O), a logic circuit CTR, an address register ADR, an instruction register CMR, a status register STR, and a data output timing adjustment unit TCT. In the following description, line decoders RD0 and RD1 are sometimes referred to as line decoders RD, and sense amplifiers SA0 and SA1 are sometimes referred to as sense amplifiers SA.

[0085] [The structure of the line decoder RD]

[0086] For example, Figure 5 As shown, the line decoder RD( Figure 4 It includes: an address decoder 22, which adds address data (Add( Figure 4 The address decoder 22 performs decoding; the block selection circuit 23 and the voltage selection circuit 24 transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0087] Address decoder 22 has multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22, for example, refers sequentially to address register ADR based on control signals from sequencer SQC. Figure 4 The row address RA is decoded, and the specific block select transistor 35 and voltage select transistor 37 corresponding to the row address RA are turned on, while other block select transistors 35 and voltage select transistors 37 are turned off. For example, the voltage of a specific block select line BLKSEL and voltage select line 33 is set to "H", and the voltage of other lines is set to "L". Furthermore, when using P-channel transistors instead of N-channel transistors, the opposite voltage is applied to these lines.

[0088] Furthermore, in the illustrated example, the address decoder 22 has one block select line BLKSEL for each memory block BLK. However, this configuration can be modified appropriately. For example, one block select line BLKSEL can also be provided for two or more memory blocks BLK.

[0089] The block select circuit 23 includes multiple block select sections 34 corresponding to memory blocks BLK. Each of these block select sections 34 includes multiple block select transistors 35 corresponding to word lines WL and select gate lines (SGD, SGS, SGSb). The block select transistors 35 are, for example, field-effect transistors. The drain electrodes of the block select transistors 35 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb). The source electrodes are electrically connected to the voltage supply line 31 via wiring CG and the voltage selection circuit 24. The gate electrodes are all connected to the corresponding block select line BLKSEL.

[0090] In addition, the block selection circuit 23 includes a plurality of transistors (not shown). These transistors are field-effect transistors connected between the select gate lines (SGD, SGS, SGSb) and the voltage supply lines supplied with ground voltage VSS. These transistors supply ground voltage VSS to the select gate lines (SGD, SGS, SGSb) contained in the non-selected memory block BLK. Furthermore, the plurality of word lines WL contained in the non-selected memory block BLK are in a floating state.

[0091] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS, SGSb). Each of these voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS, SGSb) via wiring CG and block select circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0092] [Composition of the Sensing Amplifier SA]

[0093] Sensing amplifiers SA0, SA1 ( Figure 4 Each of the two modules has a sense amplifier module (SAM0, SAM1) and a high-speed cache memory (CM0, CM1, data register). The high-speed cache memory (CM0, CM1) has latch circuits (XDL0, XDL1).

[0094] In addition, in the following description, the sense amplifier modules SAM0 and SAM1 are sometimes referred to as sense amplifier modules SAM, the cache memory CM0 and CM1 are referred to as cache memory CM, and the latch circuits XDL0 and XDL1 are referred to as latch circuits XDL.

[0095] The sense amplifier module (SAM) includes, for example, sense circuits corresponding to multiple bit lines (BL) and multiple latch circuits connected to the sense circuits.

[0096] The cache memory CM has multiple latch circuits XDL. These multiple latch circuits XDL are connected to latch circuits within the sense amplifier module SAM. The latch circuits XDL, for example, store user data Dat written to or read from the memory unit MC.

[0097] For example, Figure 7 As shown, the cache memory CM is connected to the column decoder COLD. The column decoder COLD corresponds to the address register ADR ( Figure 4 The column address CA stored in the memory is decoded, and the latch circuit XDL corresponding to the column address CA is selected.

[0098] Furthermore, the user data Dat contained in these multiple latch circuits XDL is sequentially transmitted to the latch circuits within the sense amplifier module SAM during write operations. Additionally, the user data Dat contained in the latch circuits within the sense amplifier module SAM is sequentially transmitted to the latch circuits XDL during read operations. Furthermore, the user data Dat contained in the latch circuits XDL is sequentially transmitted to the input / output control circuit I / O via the column decoder COLD and the multiplexer MPX during the data output operations described later.

[0099] [Construction of the voltage generation circuit VG]

[0100] For example, Figure 5 As shown, the voltage generation circuit VG( Figure 4 The voltage generation circuit VG is connected to multiple voltage supply lines 31. It includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits are respectively connected to the supplied power supply voltage VCC and the ground voltage VSS. Figure 4 The voltage supply lines. These voltage supply lines are connected, for example, to the reference. Figure 2 , Figure 3The pad electrode P is described. The voltage generation circuit VG, for example, generates various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS, SGSb) during read, write, and erase operations for the memory cell array MCA, based on control signals from the sequencer SQC, and simultaneously outputs these voltages to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 can be appropriately adjusted according to the control signals from the sequencer SQC.

[0101] [Structure of Sequencer SQC]

[0102] Sequencer SQC ( Figure 4 Based on the instruction data Cmd stored in the instruction register CMR, internal control signals are output to the row decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG. Additionally, the sequencer SQC appropriately outputs the status data Stt, representing the state of the memory die MD, to the status register STR.

[0103] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY is in the "L" state during operations that supply voltage to the memory cell array MCA, such as read, write, and erase operations; otherwise, it is in the "H" state. Furthermore, even when performing operations that do not supply voltage to the memory cell array MCA, such as data output or status read operations described later, the terminal RY / / BY will not be in the "L" state. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is essentially prohibited. Conversely, during the period when the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. Furthermore, the terminal RY / / BY is, for example, referenced... Figure 2 , Figure 3 The pad electrode P described herein is implemented.

[0104] In addition, the sequencer SQC has a feature register FR. The feature register FR is a register that stores the value representing the action of any of the action modes MODEa and MODEb described later.

[0105] [Structure of the Address Register (ADR)]

[0106] like Figure 4 As shown, the address register ADR is connected to the input / output control circuit (I / O) and stores the address data Add input from the I / O circuit. The address register ADR may have multiple 8-bit register columns. These register columns, for example, store the address data Add corresponding to the internal operation being performed, such as read, write, or erase operations.

[0107] In addition, the address data Add, for example, includes the column address CA ( Figure 4 ) and row address RA ( Figure 4 The row address RA, for example, contains: a specific outgoing memory block BLK (). Figure 5 The block address of the specific output string element (SU) and the page address of the word line (WL), the plane address of the specific output memory cell array (MCA) (plane), and the chip address of the specific output memory die (MD).

[0108] [Structure of the Instruction Register (CMR)]

[0109] The instruction register (CMR) is connected to the input / output control circuit (I / O) and stores the instruction data (Cmd) input from the I / O. The instruction register CMR typically has at least one set of 8-bit register columns. When instruction data (Cmd) needs to be stored in the instruction register CMR, a control signal is sent to the sequencer (SQC).

[0110] [The structure of the status register STR]

[0111] The status register STR is connected to the input / output control circuit (I / O) and stores the status data Stt of the output to the I / O circuit. The status register STR may have multiple 8-bit register columns. These register columns, for example, store the status data Stt related to the internal operation being performed, such as read, write, or erase operations. Additionally, the register columns may store the ready / busy information of the memory cell arrays MCA0 and MCA1.

[0112] [Structure of the Data Output Timing Adjustment Unit (TCT)]

[0113] The data output timing adjustment unit (TCT) is connected to the bus line DB between the cache memories CM0 and CM1 and the input / output control circuit (I / O). For example, when continuously performing data output operations (described later) on the cache memories CM0 and CM1, the TCT adjusts the start time of the data output operation for the cache memory CM1 so that the data output operation for the cache memory CM1 begins without any downtime after the data output operation for the cache memory CM0 is completed.

[0114] [Composition of Input / Output Control Circuit (I / O)]

[0115] Input / output control circuit I / O ( Figure 4 It has data signal input / output terminals DQ0~DQ7, data strobe signal input / output terminals DQS, / DQS, shift register, and buffer circuit.

[0116] Data signal input / output terminals DQ0 to DQ7, and data strobe signal input / output terminals DQS and / DQS, each for example, refer to... Figure 2 , Figure 3 The pad electrode P described herein is implemented. Data input via data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or instruction register CMR according to the internal control signal from the logic circuit CTR. Similarly, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0117] Signals input via data strobe input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used when data is input via data input / output terminals DQ0 to DQ7. Data input via data input / output terminals DQ0 to DQ7 is captured into a shift register within the input / output control circuit I / O at the points when the voltage of data strobe input / output terminal DQS rises (input signal switching) and the voltage of data strobe input / output terminal / DQS falls (input signal switching), and at the points when the voltage of data strobe input / output terminal DQS falls (input signal switching) and the voltage of data strobe input / output terminal / DQS rises (input signal switching).

[0118] For example, Figure 8 As shown, data signal input / output terminals DQ0 to DQ7 and data strobe signal input / output terminals DQS and / DQS are respectively connected to input circuit 201 and output circuit 202. Input circuit 201 is, for example, a receiver such as a comparator. Output circuit 202 is, for example, a driver such as an OCD (Off-Chip Driver) circuit.

[0119] [Construction of the CTR logic circuit]

[0120] Logic circuit CTR ( Figure 4 It has multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and logic circuits connected to these external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, / WP, and outputs internal control signals to the input / output control circuit (I / O) according to the external control signals.

[0121] For example, Figure 8As shown, the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP are each connected to the input circuit 201. Furthermore, the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP are each connected, for example, via reference... Figure 2 , Figure 3 The pad electrode P described herein is implemented.

[0122] Signals input via the external control terminal / CE (e.g., chip enable signal) are used when selecting the memory die MD. When the external control terminal / CE is input with "L", the memory die MD is in a state where it can input / output user data Dat, instruction data Cmd, and address data Add (hereinafter sometimes simply referred to as "data"). When the external control terminal / CE is input with "H", the memory die MD is in a state where it cannot input / output data. Furthermore, as... Figure 8 As shown, the external control terminal / CE is connected to the input circuit 201.

[0123] Signals input via the external control terminal CLE (e.g., the instruction latch enable signal) are utilized when the instruction register CMR is used. The function of the external control terminal CLE will be described below.

[0124] Signals input via the external control terminal ALE (e.g., the address latch enable signal) are utilized when the address register ADR is used. The function of the external control terminal ALE will be described below.

[0125] Signals input via the external control terminal / WE (e.g., write enable signal) are utilized during data input from the controller die CD to the memory die MD. The function of the external control terminal / WE will be described below.

[0126] Signals input via external control terminals / RE and RE (e.g., read enable signal and its complementary signal) are utilized during data output via data signal input / output terminals DQ0 to DQ7. Data output from data signal input / output terminals DQ0 to DQ7 switches at the falling edge (input signal switching) and rising edge (input signal switching) of the voltage at external control terminal / RE, and at the falling edge (input signal switching) of the voltage at external control terminal / RE.

[0127] Signals input via external control terminals / WP (e.g., write protection signals) are used for input restrictions such as limiting user data Dat from the controller die CD to the memory die MD.

[0128] [Motion Mode MODEa and Action Mode MODEb]

[0129] The semiconductor memory device of this embodiment can perform operations in operation mode MODEa and operation mode MODEb. Hereinafter, refer to... Figures 9-19 The descriptions of action modes MODEa and MODEb are provided.

[0130] [Function of external terminals in each mode]

[0131] Figure 9 This is a schematic diagram used to illustrate the function of the signal input / output terminals and external control terminals in the MODEa operating mode. Figure 10 This is a schematic diagram illustrating the function of the signal input / output terminals and external control terminals in operating mode MODEb. Furthermore, in the following description, data signal input / output terminals DQ0 to DQ7 may sometimes be referred to as data signal input / output terminals DQ<7:0>.

[0132] In Action Mode MODEa, for example... Figure 9 As shown, in addition to using the data signal input / output terminals DQ<7:0> for the input and output of user data Dat, they are also used for the input of instruction data Cmd and address data Add.

[0133] On the other hand, in action mode MODEb, for example... Figure 10 As shown, the data signal input / output terminals DQ<7:0> are used for the input / output of user data Dat, but not for the input of instruction data Cmd and address data Add. In operation mode MODEb, the external control terminals CLE and ALE are used for the input of instruction data Cmd and address data Add.

[0134] [The function of external terminals in MODEa mode]

[0135] Figure 11 This is a truth table used to explain the function of external terminals in the MODEa operating mode. Furthermore, Figure 11 In this code, "Z" indicates that either "H" or "L" can be input. "X" indicates that the input signal is fixed at either "H" or "L". "Input" indicates the case of data input. "Output" indicates the case of data output.

[0136] When the instruction data Cmd is input in the operation mode MODEa, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" according to each bit of the 8-bit instruction data Cmd. When "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H".

[0137] When "H" or "L" is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is stored as instruction data Cmd in the buffer memory within the input / output control circuit I / O, and is then transferred to the instruction register CMR. Figure 4 ).

[0138] Additionally, when the address data Add is input, the controller die CD sets the voltage of the data signal input / output terminal DQ<7:0> to "H" or "L" according to each bit of the 8-bit data constituting the address data Add. When "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H".

[0139] When "L" or "H" is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is stored as address data Add in the buffer memory within the input / output control circuit I / O and then transferred to the address register ADR. Figure 4 ).

[0140] Additionally, when user data Dat is input, the controller die CD, for example, sets the voltage of the data signal input / output terminals DQ<7:0> to "H" or "L" according to each bit of the 8-bit data constituting user data Dat. With "L" input to the external control terminal CLE and "L" input to the external control terminal ALE, the input signal (trigger) of the data strobe signal input / output terminals DQS and / DQS is switched.

[0141] When "L" is input to the external control terminals CLE and ALE, the data input via the data signal input / output terminals DQ<7:0> is stored as user data Dat in the buffer memory within the input / output control circuit I / O, and then transmitted to the high-speed cache memory CM via the bus DB. Figure 4 ).

[0142] Additionally, when outputting user data Dat or status data Stt, the controller die CD switches (triggers) the input signals of external control terminals / RE and RE, for example. Simultaneously, 8 bits of the output user data Dat or status data Stt are output to the data signal input / output terminals DQ0 to DQ7. Furthermore, the output signals of the data strobe signal input / output terminals DQS and / DQS are switched.

[0143] Additionally, when the memory die MD is set to standby mode, the controller die CD inputs "H" to the external control terminal / CE, for example.

[0144] Additionally, when the memory die MD is in a bus idle state, the controller die CD inputs "H" to the external control terminal / WE, for example.

[0145] [Function of external terminals under MODEb action mode]

[0146] Figure 12 and Figure 13 This is a truth table used to explain the function of the external terminals in the MODEb operating mode. Furthermore, Figure 12 and Figure 13 In this code, "Z" indicates that either "H" or "L" can be input. "X" indicates that the input signal is fixed at either "H" or "L". "Input" indicates data input. "Output" indicates data output.

[0147] As described above, in operation mode MODEb, the external control terminals CLE and ALE are used for inputting command data and address data. See below for further details. Figure 15 As described above, when inputting instruction data Cmd or address data Add in operation mode MODEb, the controller die CD inputs a signal to the memory die MD indicating whether the next input data is instruction data Cmd or address data Add. Hereinafter, this signal will be referred to as the input / output data selection signal.

[0148] Figure 12 This shows the period during which the input / output data selection signal is input (MSel). Figure 15 The function of the external control terminals. Figure 13 This shows the period S_In after the input / output data selection signal is input. Figure 15 The function of the external control terminals.

[0149] During the MSel period, when the input / output data selection signal for inputting instruction data Cmd is input, the controller die CD, for example, when the external control terminal CLE is input with "H" and the external control terminal ALE is input with "L", will cause the external control terminal / WE to change from "L" to "H".

[0150] During the MSel period, if "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the data input during the S_In period immediately following the MSel period is stored as instruction data Cmd in the buffer memory within the input / output control circuit I / O and is transferred to the instruction register CMR. Figure 4 ).

[0151] Additionally, during MSel, when the input / output data selection signal intended for inputting address data Add is input, the controller die CD, for example, with "L" input to external control terminal CLE and "H" input to external control terminal ALE, will raise the external control terminal / WE from "L" to "H".

[0152] During the MSel period, if "L" is input to the external control terminal CLE and "H" is input to the external control terminal ALE, the data input during the S_In period following MSel is stored as address data Add in the buffer memory within the input / output control circuit I / O and is transferred to the address register ADR. Figure 4 ).

[0153] During the input of instruction data Cmd or address data Add in S_In, the controller die CD sets the voltage of the external control terminals CLE and ALE to "H" or "L" based on each bit of the 2-bit data constituting instruction data Cmd or address data Add, thereby raising the voltage of the external control terminal / WE from "L" to "H".

[0154] Furthermore, when user data Dat is input in operation mode MODEb, the controller die CD sets the voltage of the data signal input / output terminals DQ<7:0> to "H" or "L" based on each bit of the 8-bit data constituting user data Dat. With "H" or "L" input to the external control terminals / RE and RE, the controller switches the input signals of the data strobe signal input / output terminals DQS and / DQS. This operation can be performed during both MSel and S_In.

[0155] In operation mode MODEb, the data input via the data signal input / output terminals DQ<7:0> is stored as user data Dat in the buffer memory within the input / output control circuit I / O, and then transmitted to the high-speed buffer memory CM via the bus DB.

[0156] Additionally, when outputting user data Dat or status data Stt, the controller die CD switches the input signals of external control terminals / RE and RE, for example. Simultaneously, 8 bits of the output user data Dat or status data Stt are output to data signal input / output terminals DQ0 to DQ7. Furthermore, the output signals of data strobe signal input / output terminals DQS and / DQS are switched. This operation can be performed during both MSel and S_In periods.

[0157] Additionally, when the memory die MD is in standby mode, the controller die CD inputs "H" to the external control terminal / CE, for example.

[0158] Additionally, when the memory die MD is in a bus idle state, the controller die CD inputs "H" to the external control terminal / WE, for example.

[0159] [Examples of signal input and output in each mode]

[0160] Figure 14 and Figure 15 This is a schematic waveform diagram used to illustrate the operation of the memory die MD in the first embodiment.

[0161] Figure 14 The waveform is shown when the command data Cmd and address data Add are entered in the action mode MODEa. Figure 14 In the example shown, at time t101, the controller die CD inputs instruction data Cmd to the memory die MD. Additionally, at time t102, the controller die CD inputs address data Add to the memory die MD. Furthermore, in the illustrated example, at times t102 to t103, 8 bits of data constituting the address data Add are input, but the number of cycles may be less or more than 5. Also, at time t103, the controller die CD inputs instruction data Cmd to the memory die MD. Finally, at time t104, read operations begin, and the voltage at terminals RY / / BY drops from "H" to "L".

[0162] Figure 15 The waveform is shown when the command data Cmd and address data Add are input in the action mode MODEb. Figure 15In the example, the external control terminal / WE is input with "L" and "H" at a roughly fixed pace. Furthermore, the period from the first drop to the second drop of the input signal to the external control terminal / WE at a specific point in time is denoted as the period MSel. Additionally, the period from the end of the period MSel to the subsequent four drops of the input signal to the external control terminal / WE is denoted as the period S_In.

[0163] Figure 15 In the example, during the period from time t201 to t202, MSel, the controller die CD inputs the input / output data selection signal of the specified instruction data Cmd to the memory die MD.

[0164] Additionally, during the period S_In from time point t202 to t203, the controller die CD inputs instruction data Cmd to the memory die MD.

[0165] Here, Figure 15 In the example, during S_In, the controller die C inputs 2 bits of the 8-bit instruction data Cmd into the memory die MD in 4 cycles. For example, the 8-bit instruction data Cmd is set to bits "7" to "0". First, in the data input of the first cycle, corresponding to bits "7" and "6", with the voltage of the external control terminals CLE and ALE set to "H" or "L", the external control terminal / WE is raised from "L" to "H". The same applies to the data input of the second to fourth cycles. Corresponding to bits "5", "4", "3", "2", and "1", "0", with the voltage of the external control terminals CLE and ALE set to "H" or "L" respectively, the external control terminal / WE is raised from "L" to "H".

[0166] Additionally, during the period from time t203 to t204, MSel, the controller die CD inputs the input / output data selection signal to the memory die MD to specify the address data Add.

[0167] Additionally, during the period S_In from time point t204 to t205, the controller die CD inputs address data Add to the memory die MD.

[0168] Here, Figure 15 In the example, during S_In, the controller die CD will input 2 bits of the 8-bit data that constitutes the address data Add into the memory die MD in 4 cycles.

[0169] Furthermore, although the illustration is omitted, the same applies at time points t205 to t206, where each input consists of 2 bits forming the address data Add.

[0170] Additionally, during the period MSel from time point t206 to t207, the input / output data selection signal for inputting the specified instruction data Cmd is the same as during time points t201 to t202.

[0171] Additionally, during the period from time t207 to t208, S_In, the controller die CD inputs instruction data Cmd to the memory die MD. Also, at time t208, read operations begin, and the voltage at terminal RY / / BY drops from "H" to "L".

[0172] [action]

[0173] Next, the operation of the memory die MD will be explained.

[0174] The memory die (MD) is configured to perform a read operation. The read operation involves reading user data (Dat) from the memory cell array (MCA) via the sense amplifier module (SAM) and transferring the read user data (Dat) to the latch circuit (XDL). During the read operation, the user data (Dat) read from the memory cell array (MCA) is transmitted to the latch circuit (XDL) via the bit line (BL) and the sense amplifier module (SAM).

[0175] Furthermore, the memory die MD is configured to perform a data output operation. The data output operation is the action of outputting the user data Dat contained in the latch circuit XDL to the controller die CD. In the data output operation, the user data Dat contained in the latch circuit XDL is referenced... Figure 7 The described column decoder COLD, multiplexer MPX, bus wiring DB, and input / output control circuit I / O output to the controller die CD.

[0176] Furthermore, the memory die MD is configured to perform status reads. A status read is the operation of outputting the status data Stt contained in the status register STR to the controller die CD. During a status read, the status data Stt contained in the status register STR is output to the controller die CD via the input / output control circuit I / O or the logic circuit CTR.

[0177] [Reading and data output actions under MODEa]

[0178] Figure 16 This is a schematic timing diagram illustrating the execution of read and data output actions under the MODEa action mode. Figure 16 In the example, the memory die MD is set to the action mode MODEa.

[0179] Figure 16In this example, firstly, instruction data "00h", address data "Add", and instruction data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. Instruction data "00h" is instruction data Cmd input at the beginning of the instruction set indicating the read operation. Instruction data "30h" is instruction data Cmd input at the end of the instruction set indicating the read operation.

[0180] With the input of instruction data "00h", address data Add, and instruction data "30h", the read operation begins, and the voltage at terminal RY / / BY drops from "H" to "L". Meanwhile, user data Dat is transferred to the latch circuit XDL. At the end of the read operation, the voltage at terminal RY / / BY rises from "L" to "H".

[0181] Next, the instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. Instruction data "05h" is the instruction data Cmd input at the beginning of the instruction set indicating data output action. Instruction data "E0h" is the instruction data Cmd input at the end of the instruction set indicating data output action.

[0182] With the input of instruction data "05h", address data Add, and instruction data "E0h", after a specific standby time, the controller die CD switches (triggers) the input signals of external control terminals / RE and RE. This initiates the data output operation, outputting user data Dat via the data signal input / output terminal DQ.

[0183] Figure 17 This is a schematic timing diagram illustrating other scenarios when performing read and data output actions in MODEa mode. Figure 17 In the example, the memory die MD is set to the action mode MODEa.

[0184] Figure 17 In this example, firstly, instruction data "00h", address data Add, and instruction data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this instruction set contains the plane PLN0, which is the object of the read operation. Figure 4 The information is used as the plane address.

[0185] With the input of instruction data "00h", address data Add and instruction data "30h", the reading operation of plane PLN0 begins, and the user data Dat is transmitted to latch circuit XDL0.

[0186] Next, the instruction data "00h", address data Add, and instruction data "30h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this instruction set contains the plane PLN1, which is the object of the read operation. Figure 4 The information is used as the plane address.

[0187] With the input of instruction data "00h", address data Add and instruction data "30h", the read operation for plane PLN1 begins, and user data Dat is transmitted to latch circuit XDL1.

[0188] Next, input the command data "70h" via the data signal input / output terminals DQ<7:0>. The command data "70h" is the command data indicating the status read. With the input of the command data "70h", the status is read, and the status data Stt is output via the data signal input / output terminals DQ<7:0>.

[0189] Next, the instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this instruction set contains the plane PLN0, which is the object of the data output action. Figure 4 The information is used as the plane address.

[0190] With the input of instruction data "05h", address data Add, and instruction data "E0h", after a specific standby time, the controller die CD switches (triggers) the input signals of external control terminals / RE and RE. This initiates data output to the plane PLN0, outputting user data "DataOut" via data signal input / output terminals DQ<7:0>.

[0191] After the data output action for plane PLN0 is completed, the command data "70h" is input via the data signal input / output terminal DQ<7:0>. With the input of the command data "70h", the status is read again, and the status data Stt is output via the data signal input / output terminal DQ<7:0>.

[0192] Next, similar to the data output operation for PLN0, the instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via the data signal input / output terminals DQ<7:0>. The address data Add included in this instruction set contains the plane PLN1 (which is the target of the data output operation). Figure 4 The information is used as the plane address.

[0193] After a specific period of time, the controller die CD switches (triggers) the input signals of the external control terminals / RE and RE. This initiates the data output operation for the plane PLN1, outputting user data "DataOut" via the data signal input / output terminals DQ<7:0>.

[0194] [Reading and data output actions under Action Mode MODEb]

[0195] Figure 18 This is a schematic timing diagram illustrating the situation when reading and data output actions are performed in action mode MODEb. Figure 18 In the example, the memory die MD is set to the action mode MODEb.

[0196] Figure 18 In the example, firstly, an instruction set containing the instruction data "00h" is input via the external control terminals CLE and ALE. Next, an instruction set containing the instruction data "05h" is input via the external control terminals CLE and ALE. Furthermore, in operation mode MODEb, data input / output via the data signal input / output terminals DQ<7:0> and data input / output via the external control terminals CLE and ALE can be performed at independent time points. For example, Figure 18 In the example, these instruction sets are input during the execution of the data output action (during the period when the input signal of the external control terminal / RE is triggered).

[0197] Figure 19 This is a schematic timing diagram illustrating other scenarios when performing read and data output actions in action mode MODEb. Figure 19 In the example, the memory die MD is set to the action mode MODEb.

[0198] Figure 19 In this example, firstly, instruction data "00h", address data Add, and instruction data "30h" are sequentially input via external control terminals CLE and ALE. The address data Add included in this instruction set contains the plane PLN0 (which is the object of the read operation). Figure 4 The information is used as the plane address.

[0199] Next, the instruction data "00h", address data Add, and instruction data "30h" are sequentially input via the external control terminals CLE and ALE. The address data Add included in this instruction set contains the plane PLN1, which is the object of the read operation. Figure 4 The information is used as the plane address.

[0200] Next, input the command data "70h" via the external control terminals CLE and ALE. With the input of the command data "70h", the status is read and the status data Stt is output via the data signal input / output terminals DQ<7:0>.

[0201] Next, the instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via the external control terminals CLE and ALE. The address data Add includes the plane PLN0, which is the object of the data output action. Figure 4 The information is used as the plane address.

[0202] After a specific standby time, the data output operation for plane PLN0 begins, and user data "DataOut" is output via data signal input / output terminals DQ<7:0>.

[0203] in addition, Figure 19 In the example, during the data output operation for plane PLN0, the command data "70h" is input via the external control terminals CLE and ALE. With the input of the command data "70h", a status read is performed. After the data output operation for plane PLN0 is completed, the status data Stt is output via the data signal input / output terminals DQ<7:0>.

[0204] Next, the instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via the external control terminals CLE and ALE. The address data Add includes the plane PLN1, which is the object of the data output action. Figure 4 The address of the plane is used as the plane address.

[0205] Here, in action mode MODEb, unlike action mode MODEa, the data output timing adjustment unit TCT (…) Figure 4 Adjust the start time of the data output operation for plane PLN1. After the data output operation for plane PLN0 is completed, the data output operation for plane PLN1 is started according to the internal signal issued by the data output timing adjustment unit TCT, and the user data "DataOut" is output through the data signal input / output terminals DQ<7:0>.

[0206] [Effect]

[0207] The semiconductor memory device of this embodiment can operate in Operation Mode MODEb. In Operation Mode MODEb, as described above, while performing data output operations via the data signal input / output terminals DQ<7:0>, instruction data Cmd and address data Add can also be input via the external control terminals CLE and ALE. Therefore, the time required to input the instruction set to the memory die MD can be significantly reduced. This enables high-speed operation of the semiconductor memory device.

[0208] [Circuit applicable to the memory die MD of the first embodiment]

[0209] In the memory die MD of the first embodiment, the functions of the data signal input / output terminals DQ<7:0> and external control terminals CLE, ALE, etc., change depending on which of the operating modes MODEa or MODEb is selected. This function can be achieved, for example, by utilizing... Figure 20 , Figure 22 and Figure 23 The circuit shown is implemented as described. Figure 20 , Figure 22 and Figure 23 This is a schematic circuit diagram showing a partial configuration example of a memory die (MD). Figure 21 It is used to explain Figure 20 The circuit shown is illustrated with a schematic waveform diagram illustrating its operation.

[0210] Figure 20 The diagram shows the data signal input / output terminals DQ<7:0>, external control terminals CLE, ALE, / WE, and the circuit section 200 connected to them.

[0211] The circuit section 200 includes, for example, a latch circuit 210, multiplexers 220 and 230, and a deserializer 300.

[0212] The latch circuit 210 is a latch circuit contained in the instruction register CMR or the address register ADR. Figure 20 The illustration shows a latch circuit 210 corresponding to the instruction data "05h". In the illustrated example, the latch circuit 210 stores one bit of data corresponding to the input instruction data Cmd. The data input terminals of the latch circuit 210 are connected to the output terminals DINh<7:0>, CLEh, and ALEh of the multiplexer 220 via logic circuits, and the clock input terminal is connected to the output terminal / WEh' of the multiplexer 230.

[0213] Input the selection signal SerialCA to the respective selection control terminals of multiplexers 220 and 230. The selection signal SerialCA is in the "0" state when operation mode MODEa is selected, and in the "1" state when operation mode MODEb is selected.

[0214] The multiplexer 220 has 10 output terminals: DINh<7:0>, CLEh, and ALEh. Eight of these output terminals, DINh<7:0>, correspond to the data constituting instruction data Cmd or address data Add. The remaining two output terminals, CLEh and ALEh, correspond to the input signals of the external control terminals CLE and ALE.

[0215] Additionally, the multiplexer 220 has 10 input terminals selected when the selection signal SerialCA is in the "0" state, and 10 input terminals selected when the selection signal SerialCA is in the "1" state. Eight of the ten input terminals corresponding to the "0" state are connected to the data signal input / output terminals DQ<7:0>. The remaining two are connected to the external control terminals CLE and ALE. The ten input terminals corresponding to the "1" state are connected to the output terminals of the deserializer 300.

[0216] Multiplexer 230 has one output terminal / WEh'. Additionally, multiplexer 230 has one input terminal / WEh that is selected when the selection signal SerialCA is in the "1" state, and one input terminal that is selected when the selection signal SerialCA is in the "0" state. The input terminal / WEh corresponding to the "1" state is connected to the output terminal of deserializer 300. The input terminal corresponding to the "0" state is connected to the external control terminal / WE.

[0217] The deserializer 300 has 10 output terminals connected to the multiplexer 220. The deserializer 300 converts 2-bit data input to external control terminals CLE and ALE over 4 cycles into 8-bit data, adding an additional 2-bit data indicating whether the 8-bit data is instruction data (Cmd) or address data (Add), resulting in 10-bit data. Furthermore, the deserializer 300 outputs the 10-bit data to the multiplexer 220 via the 10 output terminals. The 10-bit data can be switched, for example, at the start of the MSel period.

[0218] Additionally, the deserializer 300 has one output terminal connected to the multiplexer 230. During the period from the input of the first cycle of the five cycles of data input from the external control terminal / WE to the input of the second cycle (between MSel), the deserializer 300 outputs "L" to the input terminal / WEh of the multiplexer 230. During the remaining periods (between S_In), it outputs "H" to the input terminal / WEh of the multiplexer 230.

[0219] In operating mode MODEa, the 8-bit data input via the data signal input / output terminals DQ<7:0> is input to the logic circuit via the output terminals DINh<7:0> of multiplexer 220. Additionally, the enable signal input via the external control terminals CLE and ALEh is input to the logic circuit via the output terminals CLEh and ALEh of multiplexer 220. In the illustrated example, the 8-bit data input via the data signal input / output terminals DQ<7:0> is the instruction data "05h", and when the input signals of the external control terminals CLE and ALE are "H" and "L", the output signal of the logic circuit becomes "H". Otherwise, the output signal of the logic circuit becomes "L".

[0220] Additionally, in operating mode MODEa, the signal input from the external control terminal / WE is output from the output terminal / WEh' of the multiplexer 230 and input to the clock input terminal of the latch circuit 210.

[0221] In operation mode MODEb, the deserializer 300 converts the 2-bit × 4-cycle data input via external control terminals CLE and ALE, along with the enable signal input via external control terminal / WE, into an 8-bit data signal and an enable signal, and inputs them to the input terminals of multiplexer 220. These data and signals are then input to the logic circuit via the output terminals DINh<7:0>, CLEh, and ALEh of multiplexer 220. In the illustrated example, when MSel inputs "H, L" from external control terminals CLE and ALE, and when S_In inputs instruction data "05h" from external control terminals CLE and ALE, the logic circuit's output signal becomes "H". Otherwise, the logic circuit's output signal becomes "L".

[0222] Additionally, in operation mode MODEb, the signal input to the input terminal / WEh of the multiplexer 230 is output from the output terminal / WEh' of the multiplexer 230 and input to the clock input terminal of the latch circuit 210.

[0223] Figure 22 and Figure 23 This is a schematic circuit diagram showing a partial configuration of the deserializer 300. The deserializer 300 includes, for example: Figure 22 The circuit section 310 shown, and as shown Figure 23 The circuit section 320 shown.

[0224] The circuit section 310 includes five D flip-flops 311 and one D latch circuit 312. The output terminal of the first D flip-flop 311 is connected to the data input terminal of the second D flip-flop 311. Similarly, the output terminals of the second to fourth D flip-flops 311 are connected to the data input terminals of the third to fifth D flip-flops 311. The output terminal of the fifth D flip-flop 311 is connected to the data input terminal of the D latch circuit 312. The output terminal of the D latch circuit 312 is connected to the data input terminal of the first D flip-flop 311. Furthermore, the clock input terminals of these five D flip-flops 311 and the one D latch circuit 312 are connected to the external control terminal / WE.

[0225] Additionally, the circuit section 310 includes five D latch circuits 313 and five AND circuits 314. The data input terminals of the five D latch circuits 313 are respectively connected to the output terminals of the five D flip-flops 311. Furthermore, an inverted signal from the external control terminal / WE is input to the clock input terminals of the five D latch circuits 313. One input terminal of each of the five AND circuits 314 is connected to the output terminal of the five D latch circuits 313. The other input terminal of each of the five AND circuits 314 is connected to the external control terminal / WE. Furthermore, Figure 22 In this example, four of the output terminals of the five AND circuits 314 are designated as output terminals WE1 to WE4. The remaining output terminal is connected to the multiplexer 230. Figure 20 ) input terminal / WEh.

[0226] Here, the initial values ​​of the data stored in the five D flip-flops 311 are set to 0, and the initial values ​​of the data stored in the D latch circuit 312 are set to 1. In this case, when the external control terminal / WE is input with "L" and "H" at approximately a fixed pace, with the input of the external control terminal / WE in the first cycle, the signal of output terminal WE1 becomes "H", and the signals of output terminals WE2, WE3, and WE4 become "L". Furthermore, with the input of the second cycle, the signal of output terminal WE2 becomes "H", and the signals of output terminals WE1, WE3, and WE4 become "L". Furthermore, with the input of the third cycle, the signal of output terminal WE3 becomes "H", and the signals of output terminals WE1, WE2, and WE4 become "L". Furthermore, with the input of the fourth cycle, the signal of output terminal WE4 becomes "H", and the signals of output terminals WE1, WE2, and WE3 become "L".

[0227] The circuit unit 320 includes two each of D latch circuits 321 to D latch circuits 324. The data input terminal of one of the D latch circuits 321 to 324 is connected to the external control terminal CLE. The data input terminal of the other of the D latch circuits 321 to 324 is connected to the external control terminal ALE. In addition, the clock input terminals of the two D latch circuits 321 are connected to the output terminal WE1 of the AND circuit 314. Similarly, the clock input terminals of the D latch circuits 322, 323, and 324 are connected to the output terminals WE2, WE3, and WE4 of the AND circuit 314, respectively.

[0228] Data of the external control terminals CLE and ALE in the first cycle is stored in the two D latch circuits 321. Data of the external control terminals CLE and ALE in the second cycle is stored in the two D latch circuits 322. Data of the external control terminals CLE and ALE in the third cycle is stored in the two D latch circuits 323. Data of the external control terminals CLE and ALE in the fourth cycle is stored in the two D latch circuits 324.

[0229] [Second Embodiment]

[0230] Next, referring to Figure 24 and Figure 25 , the configuration of the semiconductor memory device of the second embodiment will be described. Figure 24 is a schematic block diagram showing the configuration of the memory die MD2 of the second embodiment. Figure 25 is a schematic circuit diagram showing a partial configuration of the memory die MD2. For convenience of description, Figure 24 and Figure 25 a part of the configuration is omitted in.

[0231] As shown in Figure 24 and Figure 25 , the semiconductor memory device of the present embodiment is basically configured the same as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment can output status data Stt via the external control terminals CLE and ALE. As shown in Figure 25 , the external control terminals CLE and ALE of the second embodiment are connected to the input circuit 201 and the output circuit 202.

[0232] In addition, the semiconductor memory device of the present embodiment can operate in an operation mode MODEc in addition to being operable in the operation modes MODEa and MODEb.

[0233] Figure 26 and Figure 27 are truth tables for explaining the roles of the external terminals in the operation mode MODEc. Figure 26This illustrates the function of the external control terminals within MSel during the period. Figure 27 This illustrates the function of the external control terminals within S_In and S_Out during the period.

[0234] The actions of memory die MD2 under action mode MODEc are basically the same as those of memory die MD under action mode MODEb.

[0235] However, in the MODEc operating mode, not only can the address data Add and instruction data Cmd be input via the external control terminals CLE and ALE, but the status data Stt can also be output via the external control terminals CLE and ALE.

[0236] like Figure 26 As shown, during the operation mode MODEc, when MSel is input, and the input / output data selection signal intended to output status data Stt is input, the controller die CD, for example, in the state of inputting "L" to the external control terminal CLE and inputting "L" to the external control terminal ALE, causes the external control terminal / WE to rise from "L" to "H".

[0237] In addition, such as Figure 27 As shown, during the operation mode MODEc, when S_Out is active and the status data Stt is output, the controller die CD, for example, causes the input signal of the external control terminal / WE to decrease. Simultaneously, the output circuit 202 outputs two bits of the status data Stt from the external control terminals CLE and ALE to the controller die CD.

[0238] Figure 28 This is a schematic waveform diagram used to illustrate the operation of the memory die MD2 in the second embodiment. Figure 28 The waveform is shown when the command data Cmd and address data Add are input in the action mode MODEc.

[0239] Figure 28 In the example, the external control terminal / WE is input with "L" and "H" at a roughly fixed pace. Furthermore, the period from the first drop to the second drop of the input signal at a specific point in time is denoted as the period MSel. Additionally, the period from the end of the MSel drop in the input signal at the external control terminal / WE until the input signal drops four times is denoted as either period S_In or period S_Out.

[0240] In operation mode MODEc, when the controller die CD inputs an input / output data selection signal to the memory die MD2 during period MSel, specifying instruction data Cmd or address data Add, the subsequent period becomes period S_In. Conversely, when the controller die CD inputs an input / output data selection signal to the memory die MD2 during period MSel, indicating the output of status data Stt, the subsequent period becomes period S_Out.

[0241] During this period, the status data Stt output by S_Out can be, for example, the same 8-bit data as the status data Stt output when performing status reading in action mode MODEa or action mode MODEb. In this case, the status data Stt can be output in 4 cycles, 2 bits each time.

[0242] Figure 29 This is a schematic timing diagram illustrating the situation when reading and data output actions are performed in action mode MODEc. Figure 29 In this example, the memory die MD2 is set to the action mode MODEc.

[0243] Figure 29 The illustrated actions are basically the same as the reference. Figure 19 The actions described are the same. However, Figure 29 In the example, during the status read operation, "L, L" is input to the external control terminals CLE and ALE. Furthermore, the status data Stt is not output from the data signal input / output terminals DQ<7:0>, but rather from the external control terminals CLE and ALE. Additionally, during the data output operation for plane PLN0, status reads and the output of status data Stt are performed, and then the input of the instruction set intended to execute the data output operation for plane PLN1 begins.

[0244] In addition, the output circuit 202 is connected to the external control terminals CLE and ALE. Figure 25 These output circuits 202 are driven in operating mode MODEc. They may not be driven in operating modes MODEa and MODEb.

[0245] [Circuit applicable to the memory die MD2 in the second embodiment]

[0246] For the memory die MD2 in the second embodiment, when the operation mode MODEc is selected, the 8-bit status data Stt is converted into 2-bit × 4-cycle data and then output. This function can be achieved, for example, through... Figure 30 The circuit shown is implemented as described. Figure 30 This is a schematic circuit diagram showing a partial configuration example of the memory die MD2.

[0247] Figure 30 The circuit shown includes a serializer 331 and two switch circuits 332.

[0248] The serializer 331 has 8 first input terminals and 1 second input terminal. One bit of the 8-bit data FDATA<7:0> constituting the 8-bit status data Stt is input to each of the first input terminals. The second input terminal receives an input from the external control terminal / WE. The serializer 331 converts the 8-bit data FDATA<7:0> into 2-bit data FDATA2<1:0> according to the input from the external control terminal / WE, and sequentially outputs the 2-bit data over 4 cycles.

[0249] The two switch circuits 332 are provided corresponding to the external control terminals CLE and ALE respectively. The output terminal of the switch circuit 332 is connected to the external control terminal CLE or the external control terminal ALE. The input terminal of the switch circuit 332 is connected to the output terminal of the serializer 331. The switch circuit 332 outputs an input signal according to the input of the gate signal S332. The gate signal S332 is, for example, in a period where the external control terminal / WE is in the "L" state, during S_Out( Figure 28 ) in the first cycle, when "L, L" is input to the external control terminals CLE and ALE during MSel, the operation mode MODEc is selected, and the memory die MD2 is selected, the gate signal becomes "H" state.

[0250] [Third Embodiment]

[0251] Next, refer to Figure 31 to describe the configuration of the semiconductor memory device according to the third embodiment. Figure 31 is a schematic block diagram showing the configuration of the memory die MD3 according to the third embodiment. For convenience of description, Figure 31 a part of the configuration is omitted in the drawing.

[0252] As shown in Figure 31 , the semiconductor memory device of this embodiment is basically configured the same as the semiconductor memory device of the second embodiment. However, as shown in Figure 31 , the input / output control circuit I / O of this embodiment includes a compression and expansion circuit C10. The compression and expansion circuit C10 extracts necessary information from the status data Stt in the status register STR and outputs the extracted information.

[0253] In the third embodiment, the status data Stt output during S_Out in the operation mode MODEc is different from the status data Stt output when status reading is performed in the operation mode MODEa or the operation mode MODEb.

[0254] For example, in this embodiment, the status data Stt output during the period S_Out is, for example, as shown in Figure 32 As shown, the status data Stt can be 2-bit data representing the ready / busy status of the two planes PLN0 and PLN1 contained in the selected memory die MD3. Alternatively, for example, if the memory die MD3 contains four or more planes PLN, the status data Stt can be multi-bit data representing the ready / busy status of multiple planes PLN contained in the memory die MD3. In this case, the status data Stt can be output in multiple cycles, each time with 2 bits.

[0255] Additionally, in this embodiment, the status data Stt output in S_Out during the period can be, for example, multi-bit data representing the ready / busy status of all memory die MD3s controlled by the controller die CD. For example, Figure 2 and Figure 3 As illustrated, when multiple pad electrodes P of eight memory dies MD3 are interconnected via bonding wires B, and the eight memory dies MD3 are controlled by a controller die CD, the status data Stt can, for example, be an 8-bit data representing the ready / busy status of these eight memory dies MD3. In this case, the status data Stt of each memory die MD3 can be output in 2 bits each time in 4 cycles, according to the order corresponding to the chip address. More specifically, for example, in the first cycle, the first memory die MD3 outputs the ready / busy status from the external control terminal CLE, while the second memory die MD3 outputs the ready / busy status from the external control terminal ALE. Similarly, in the second cycle, the third memory die MD3 outputs the ready / busy status from the external control terminal CLE, while the fourth memory die MD3 outputs the ready / busy status from the external control terminal ALE. In cycle 3, the fifth memory die MD3 outputs a ready / busy status from the external control terminal CLE, while the sixth memory die MD3 outputs a ready / busy status from the external control terminal ALE. In cycle 4, the seventh memory die MD3 outputs a ready / busy status from the external control terminal CLE, while the eighth memory die MD3 outputs a ready / busy status from the external control terminal ALE. Additionally, in this case, each memory die MD3 sets the external control terminals ALE and / or CLE that have not output status data Stt to a state where they do not accept signals from the outside.

[0256] [Fourth Implementation]

[0257] Next, refer to Figure 33 and Figure 34 The configuration of the semiconductor memory device according to the fourth embodiment will be described. Figure 33 and Figure 34 This is a schematic block diagram illustrating the configuration of the memory die MD4 according to the fourth embodiment. For ease of explanation, Figure 33and Figure 34 a part of the configuration is omitted.

[0258] As shown in Figure 33 , the semiconductor memory device of the present embodiment is basically configured the same as the semiconductor memory device of any one of the first to third embodiments.

[0259] However, as shown in Figure 33 , the logic circuit CTR of the fourth embodiment includes an internal address switching circuit C20. For example, as shown in Figure 34 , in response to the input of the trigger signal TGR1 or the trigger signal TGR2, the internal address switching circuit C20 transmits the address data Add stored in the region RADR1 in the address register ADR to the region RADR2 in the address register ADR. In addition, the region RADR2 may be, for example, a region that stores address data Add corresponding to data input and output via the data signal input / output terminal DQ<7:0>. Further, the region RADR1 may be, for example, a region that stores address data Add corresponding to data input and output via the external control terminals CLE and ALE.

[0260] In addition, the semiconductor memory device of the present embodiment can perform operations not only in the operation modes MODEa, MODEb, and MODEc, but also in the operation mode MODEd.

[0261] For example, as shown in Figure 2 and Figure 3 , a plurality of pad electrodes P of the plurality of memory dies MD may be connected to each other via bonding wires B, respectively. For example, while a data output operation is being performed on one of the plurality of memory dies MD4 in which the pad electrodes P are connected to each other in this manner, an instruction set may be input to another memory die MD4. In this case, if the address data is reflected at the time point when the input of the instruction set is completed, there is a concern that the address data will be switched during the execution of the data output operation, and the user data Dat cannot be appropriately output.

[0262] Therefore, in the semiconductor memory device of the fourth embodiment, the controller die CD detects that the data output operation is completed, and inputs the trigger signals TGR1 and TGR2 to the memory die MD4.

[0263] Figure 35 is a truth table for explaining the function of the external terminals in the operation mode MODEd. Figure 35 shows the functions of the external control terminals in the period MSel.

[0264] The operation of the memory die MD4 in the operation mode MODEd is basically configured the same as the operation of the memory dies MD2 and MD3 in the operation mode MODEc.

[0265] However, in MODEd mode, trigger signals TGR1 and TGR2 can be input during MSel.

[0266] When the input trigger signal TGR1 is received, the controller die CD, for example, when the external control terminal / WE is input with "H" to the external control terminals CLE and ALE, will change from "L" to "H".

[0267] When the input trigger signal TGR2 is received, the controller die CD, for example, when the input to the external control terminal / WE is "H", causes the external control terminal / CE to drop from "H" to "L".

[0268] Figure 36 and Figure 37 This is a schematic timing diagram illustrating the situation when a data output action is performed in the MODEd mode. Figure 36 and Figure 37 In this example, the memory die MD4 is set to the MODEd operating mode.

[0269] Figure 36 and Figure 37 In this example, firstly, instruction data "78h" and address data Add are input via external control terminals CLE and ALE. Instruction data "78h" is instruction data indicating a status read. The address data Add contained in this instruction set includes information about the memory die MD4 (LUN0) to which the data output action is performed, serving as the chip address. With the input of instruction data "78h", a status read is performed, and status data Stt is output via external control terminals CLE and ALE.

[0270] Next, instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via external control terminals CLE and ALE. The address data Add contains information about the memory die MD4 (LUN0) that is the target of the data output action, serving as the chip address.

[0271] After a specific standby time, the controller die CD switches (triggers) the input signals of the external control terminals / RE and RE. This initiates the data output operation for the memory die MD4 (LUN0), outputting user data "DataOut" via the data signal input / output terminals DQ<7:0>.

[0272] in addition, Figure 36In the example, during the data output operation on the memory die MD4 (LUN0), the instruction data "78h" and address data Add are input via the external control terminals CLE and ALE. The address data Add contains information about the memory die MD4 (LUN1) to which the data output operation is performed, serving as the chip address. With the input of instruction data "78h", the execution status is read, and status data Stt is output via the external control terminals CLE and ALE.

[0273] Next, instruction data "05h", address data Add, and instruction data "E0h" are sequentially input via external control terminals CLE and ALE. The address data Add includes the address of the memory die MD4 (LUN1), which is the target of the data output operation, and serves as the chip address. This data input also occurs during the data output operation of the memory die MD4 (LUN0), that is, during the period when the controller die CD switches (triggers) the input signals of the external control terminals / RE and RE. Here, when the multiple pad electrodes P of the memory dies MD4 (LUN0) and MD4 (LUN1) are interconnected via bonding wires B as described above, the external control terminals / RE and RE are also connected. Therefore, during the data output operation of the memory die MD4 (LUN0), when the input signals of the external control terminals / RE and RE of the memory die MD4 (LUN0) are switched (triggered), the input signals of the external control terminals / RE and RE of the memory die MD4 (LUN1) are also switched (triggered). However, as... Figure 34 As shown, in the fourth embodiment, the internal address switching circuit C20 of the logic circuit CTR will not transfer the address data Add stored in area RADR1 of the address register ADR to area RADR2 of the address register ADR unless there is an input of trigger signal TGR1 or trigger signal TGR2. Therefore, even if instruction data "05h", address data Add and instruction data "E0h" are sequentially input via external control terminals CLE and ALE, the memory die MD4 (LUN1) will not output user data from the data signal input / output terminals DQ<7:0> unless there is an input of trigger signal TGR1 or trigger signal TGR2. Therefore, it is possible to avoid simultaneous output of user data from the data signal input / output terminals DQ<7:0> of the memory die MD4 (LUN0) and the data signal input / output terminals DQ<7:0> of the memory die MD4 (LUN1).

[0274] Next, after the data output operation to the memory die MD4 (LUN0) is completed, either of the trigger signals TGR1 or TGR2 is input. Then, the controller die CD switches (triggers) the input signals of the external control terminals / RE and RE. Thus, the data output operation to the memory die MD4 (LUN1) begins, and the user data "DataOut" is output via the data signal input / output terminals DQ<7:0>.

[0275] Furthermore, in the fourth embodiment, state reading can be performed using various methods. For example, in the fourth embodiment, state reading can be performed using the same method as the memory die in any of the first to third embodiments. Additionally, in the fourth embodiment, as... Figure 38 As shown, data S00, S01, S10, S11, S20, S21, S30, and S31 can also be output through status reading. These data S00, S01, S10, S11, S20, S21, S30, and S31 can also represent the ready / busy state of plane PLN0 of the first memory die MD4, the ready / busy state of plane PLN1 of the first memory die MD4, the ready / busy state of plane PLN0 of the second memory die MD4, the ready / busy state of plane PLN1 of the second memory die MD4, the ready / busy state of plane PLN0 of the third memory die MD4, the ready / busy state of plane PLN1 of the third memory die MD4, the ready / busy state of plane PLN0 of the fourth memory die MD4, and the ready / busy state of plane PLN1 of the fourth memory die MD4, respectively.

[0276] [Another implementation method]

[0277] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the above description is only illustrative and the specific configuration and operation can be appropriately adjusted.

[0278] For example, the components and actions described above can also be appropriately combined and used. For example... Figure 39 As illustrated, it is possible to select operating mode MODEa to operate the memory die, select operating mode MODEc to operate the memory die, and then select operating mode MODEa again to operate the memory die. Alternatively, for example, immediately after power-on, the operating mode of the memory die can be set to MODEa, and the operating mode can be switched according to input from the instruction set, etc.

[0279] Additionally, in the above description, under operating modes MODEb, MODEc, and MODEd, 2-bit data input and output are performed using the external control terminals CLE and ALE. However, this method is only illustrative, and the specific method can be adjusted accordingly. For example, under operating modes MODEb, MODEc, and MODEd, other terminals can also be used (for example, refer to...). Figure 4 External control terminals (such as WP, etc.) as described above can be used for input / output of 3 or more bits of data. Alternatively, one or two terminals, including external control terminals CLE and ALE, can be selected for input / output of 1 or 2 bits of data.

[0280] [other]

[0281] Several embodiments of the present invention have been described. These embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and their equivalents.

[0282] [Explanation of Symbols]

[0283] MC storage unit

[0284] MCA storage cell array

[0285] PC peripheral circuits

[0286] ADR Address Register

[0287] CMR instruction register.

Claims

1. A semiconductor memory device comprising: The first solder pad receives the first signal; The second solder pad receives the second signal; The first memory cell array has a plurality of first memory strings, each of which has a plurality of first memory cell transistors; A first sensing amplifier is connected to the first memory cell array; The first data register, connected to the first sensing amplifier, is capable of storing data read from the first memory cell array; The control circuit is capable of performing actions targeting the first memory cell array; A first receiver and a first driver are connected to the first pad; and The second receiver and the second driver are connected to the second pad; In the first mode, a set of instructions instructing the action is obtained via the first solder pad; In the second mode, the instruction set indicating the action is obtained via the second pad; In the first mode, the first receiver, the first driver, and the second receiver are driven, and the driving of the second driver is stopped. In the second mode, the first receiver, the first driver, the second receiver, and the second driver are driven.

2. The semiconductor memory device according to claim 1, wherein... Equipped with a third solder pad for receiving the third signal. The first solder pad is provided in multiple forms. In the first mode, the instruction set indicating the action is obtained via a plurality of the first solder pads. In the second mode, the instruction set indicating the action is obtained via the second pad and the third pad.

3. The semiconductor memory device according to claim 2, wherein... The instruction set includes instruction data and address data. In the first mode, When the second signal input to the second pad is at the first level, and, When the third signal input to the third pad is a second level different from the first level, The first signal input to the first solder pad is obtained as the instruction data. When the second signal input to the second pad is the second level, and, When the third signal input to the third pad is the first level, The first signal input to the first pad is obtained as the address data.

4. The semiconductor memory device according to claim 1, wherein... Equipped with a fourth solder pad for receiving the fourth signal. In the first mode, synchronously with the fourth signal, the instruction set indicating the action is obtained via the first pad. In the second mode, the instruction set indicating the action is obtained synchronously with the fourth signal via the second pad.

5. The semiconductor memory device according to claim 2, comprising: The third receiver and the third driver are connected to the third pad; In the first mode, the third receiver is then driven, and the driving of the third driver is stopped. In the second mode, the third receiver and the third driver are then driven.

6. The semiconductor memory device according to claim 1, wherein... It has an instruction register that can store data input from the first pad and the second pad. The second pad is connected to the instruction register via a deserializer.

7. The semiconductor memory device according to claim 2, wherein... It has an instruction register that can store data input from the first pad, the second pad, and the third pad. The second and third pads are connected to the instruction register via a deserializer.

8. The semiconductor memory device according to claim 1, wherein... After the power is turned on, it is set to the first mode. The input of the instruction set is set to the second mode according to the instruction set.

9. The semiconductor memory device according to claim 1, wherein The control circuit is capable of performing: The read operation involves reading data from the first storage cell array and storing it in the first data register; and The data output action outputs the data stored in the first data register.

10. The semiconductor memory device according to claim 1, comprising: The second memory cell array has multiple second memory strings, each of which has multiple second memory cell transistors; A second sensing amplifier is connected to the second memory cell array; and The second data register, connected to the second sensing amplifier, is capable of storing data read from the second memory cell array; In the second mode, During the process of outputting the data stored in the first data register from the first pad, The instruction set that accepts the instruction to output the data stored in the second data register.

11. The semiconductor memory device according to claim 1, wherein... The fifth pad has a function to receive the fifth signal. In the second mode, After accepting the instruction set that outputs the data stored in the first data register, and After executing the output start action, Data is output from the first pad in response to the fifth signal input to the fifth pad being triggered. After accepting the instruction set that outputs the data stored in the first data register, and Before executing the output start action, Even if the fifth signal input to the fifth pad is triggered, no data will be output from the first pad.

12. The semiconductor memory device according to claim 11, wherein... The sixth pad has a function to receive the sixth signal. During the output start operation in the second mode, the sixth signal is triggered to the sixth pad input.

13. The semiconductor memory device according to claim 1, wherein... It is equipped with a status register, which stores status data indicating the operating status of the first memory cell array. In the first mode, the status data is transmitted via the first solder pad. In the third mode, the status data is transmitted via the second pad.

14. A semiconductor memory device comprising: First solder pad, sending the 7th signal; The second solder pad sends the eighth signal; The first memory cell array has a plurality of first memory strings, each of which has a plurality of first memory cell transistors; A first sensing amplifier is connected to the first memory cell array; The first data register, connected to the first sensing amplifier, is capable of storing data read from the first memory cell array; The control circuit is capable of performing actions targeting the first memory cell array; The status register stores status data representing the operational status of the first storage unit array; A first receiver and a first driver are connected to the first pad; and The second receiver and the second driver are connected to the second pad; In the first mode, the status data is transmitted via the first solder pad. In the third mode, the status data is transmitted via the second solder pad; In the first mode, the first receiver, the first driver, and the second receiver are driven, and the driving of the second driver is stopped. In the third mode, the first receiver, the first driver, the second receiver, and the second driver are driven.

15. The semiconductor memory device according to claim 14, wherein The third pad is equipped with a 9th signal. The first solder pad is provided in multiple forms. In the first mode, the status data is transmitted via multiple of the first solder pads. In the third mode, the status data is transmitted via the second and third pads.

16. The semiconductor memory device of claim 15, wherein The second solder pad receives the second signal. The third pad receives the third signal. In the first mode, When the second signal input to the second pad is at the first level, and, When the third signal input to the third pad is the first level, The status data is output from the first pad as the seventh signal.

17. The semiconductor memory device according to claim 14, wherein Equipped with a fourth solder pad for receiving the fourth signal. In the first mode, the status data is transmitted synchronously with the fourth signal via the first pad. In the third mode, the status data is transmitted via the second pad in sync with the fourth signal.

18. The semiconductor memory device of claim 14, wherein the second pad is connected to the status register via a serializer.

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