Ceramic electronic component, circuit substrate structure, and method of manufacturing ceramic electronic component

Abstract

A ceramic electronic component includes a main body, a first external electrode, and a second external electrode. The main body includes a dielectric, at least one first internal electrode, and at least one second internal electrode stacked on the first internal electrode by a dielectric interposed between the first internal electrode and the second internal electrode. The main body has a top surface, a bottom surface, a pair of side surfaces, a first end surface, and a second end surface, so that the main body has a substantially cuboid shape. The first internal electrode is exposed on the first end surface. The second internal electrode is exposed on the second end surface. The side surfaces of the main body are concavely curved in a longitudinal direction, so that a width at a longitudinal central portion of the main body is smaller than a width at the end surfaces. The first external electrode is formed on the first end surface and electrically connected to the first internal electrode. The second external electrode is formed on the second end surface and electrically connected to the second internal electrode.

Description

Technical Field

[0001] This invention relates to ceramic electronic components, circuit board structures, and methods for manufacturing ceramic electronic components. Background Technology

[0002] As electronic devices become smaller and more complex, there is a need for smaller multilayer ceramic capacitors with higher capacitance. To manufacture these capacitors, one approach is to thin the ceramic dielectric layer and increase the number of ceramic dielectric layers and internal electrode layers. However, this method can lead to delamination, resulting in a deterioration in the characteristics and reliability of the multilayer ceramic capacitor.

[0003] Patent document 1 discloses a multilayer ceramic capacitor in which the capacitor body has sides that are concavely curved along the height direction and has a residual compressive stress of 250 MPa or higher.

[0004] Patent document 2 discloses a chip-type electronic component in which at least one surface in the stacking direction of the ceramic body is a first curved surface that is convexly curved, wherein the absolute value of the coefficient of thermal expansion in the stacking direction of the ceramic body is greater than 5%, and wherein the radius of curvature of the first curved surface is 5.2 mm or less.

[0005] Patent Document 1: JP-A-2007-123835

[0006] Patent Document 2: JP-A-2012-015543

[0007] Patent Document 3: JP-A-2015-65284 Summary of the Invention

[0008] However, in the configurations disclosed in Patent Documents 1 and 2, the residual stress around the internal electrodes of the charge storage stack is large. As a result, when an external impact or electrical load is applied to the multilayer ceramic capacitor, cracks may appear in the multilayer ceramic capacitor, leading to a decrease in insulation resistance and reliability.

[0009] Therefore, the object of the present invention is to provide a ceramic electronic component that can reduce the thickness of the dielectric layer while suppressing the deterioration of reliability; to provide a circuit board structure having the ceramic electronic component; and to provide a method for manufacturing the ceramic electronic component.

[0010] According to one aspect of the present invention, a ceramic electronic component is provided, comprising: a substrate including a dielectric, at least one first internal electrode, and at least one second internal electrode stacked on the first internal electrode via a dielectric disposed between the first and second internal electrodes, the substrate having a top surface, a bottom surface, a pair of side surfaces, a first end surface, and a second end surface, such that the substrate has a generally cuboid shape, the side surfaces of the substrate being concavely curved in a longitudinal direction such that the width at the longitudinal central portion of the substrate is less than the width at the end surface; a first external electrode formed on the first end surface and electrically connected to the first internal electrode; and a second external electrode formed on the second end surface and electrically connected to the second internal electrode.

[0011] The sides of the body can be concavely curved along the height direction, and each side can have a radius of curvature along the height direction, which can be minimum in the longitudinal central part and can increase as it goes towards the end face.

[0012] The base body can satisfy 0 < (W3 - W1) / W3 ≤ 0.15%, where W1 is the width at the longitudinal central portion at the center of the base body in the height direction, and W3 is the width at the end face at the center of the base body in the height direction.

[0013] The base body can satisfy 0.04% < (W3-W1) / W3 ≤ 0.12%.

[0014] The top and bottom surfaces of the substrate can be curved in a convex manner along the longitudinal direction, so that the thickness of the central part of the substrate in the longitudinal direction can be greater than the thickness at the end face.

[0015] The top and bottom surfaces of the substrate can be curved outwards along the width direction, so that the thickness of the central part of the substrate in the lateral direction can be greater than the thickness of the two sides in the lateral direction.

[0016] The body can satisfy 3.5%≤[(W2-W1) / W2] / [(T1-T2) / T2]≤29.3%, where W1 is the width of the longitudinal central portion at the center of the height direction of the body, W2 is the width at the upper and / or lower edge of the longitudinal central portion of the body, T1 is the thickness at the longitudinal central portion at the center of the width direction of the body, and T2 is the thickness at the longitudinal central portion on both sides of the body.

[0017] The base body can satisfy 5.4%≤[(W2-W1) / W2] / [(T1-T2) / T2]≤20.3%.

[0018] The ceramic electronic component may also include a sealing resin layer covering the top surface of the substrate, the top surface of each of the first and second external electrodes, the upper portion of the side surface of the substrate, and the upper portion of the side surface of each of the first and second external electrodes.

[0019] Ceramic electronic components may have a length ranging from 0.25 mm to 0.4 mm, a width ranging from 0.125 mm to 0.2 mm, and a height ranging from 0.125 mm to 0.2 mm.

[0020] The dielectric between the first internal electrode and the second internal electrode can have a thickness ranging from 0.2 micrometers to 0.5 micrometers.

[0021] The average crystal grain size of the dielectric material can range from 80 nanometers to 200 nanometers.

[0022] The thickness of the first internal electrode and the second internal electrode can be in the range of 0.2 micrometers to 0.8 micrometers.

[0023] The capacitance of ceramic electronic components can range from 10 to 1000 μF.

[0024] The main component of the materials used for the first and second external electrodes may be Ni.

[0025] According to another aspect of the present invention, a circuit board structure is provided, comprising: a circuit board; and a ceramic electronic component mounted on the circuit board, which is connected to the circuit board via solder layers attached to first and second external electrodes, each of the solder layers wetting an end face of the first or second external electrode.

[0026] According to another aspect of the invention, a method for manufacturing a ceramic electronic component is provided, the method comprising forming a body comprising a dielectric, internal electrodes, and a capping layer, having a top surface, a bottom surface, a pair of side surfaces, and a pair of end surfaces, such that the body has a generally cuboid shape, each of the internal electrodes being exposed on one of the end surfaces, the capping layer forming the top and bottom surfaces, the capping layer being made of a material having a shrinkage temperature higher than that of the internal electrode material; sintering the body; forming a base layer for external electrodes located at longitudinal ends of the body, the base layer for each of the external electrodes covering the top surface, bottom surface, side surfaces, and corresponding end surfaces of the body; and forming plating layers on the base layers respectively.

[0027] The shrinkage temperature Ta (degrees Celsius) of the internal electrode material and the shrinkage temperature Tx (degrees Celsius) of the covering layer material can satisfy 1.20≤Tx / Ta≤1.85.

[0028] The shrinkage temperature Ta (degrees Celsius) of the internal electrode material and the shrinkage temperature Tx (degrees Celsius) of the covering layer material can satisfy 1.30≤Tx / Ta≤1.60.

[0029] The shrinkage temperature Ta (degrees Celsius) of the internal electrode material and the shrinkage temperature Tx (degrees Celsius) of the covering layer material can satisfy 1.30≤Tx / Ta≤1.40.

[0030] According to various aspects of the present invention, the thickness of the dielectric layer can be reduced while limiting the degradation of reliability. Attached Figure Description

[0031] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to a first embodiment of the present invention.

[0032] Figure 2A It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from line B1-B2.

[0033] Figure 2B It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from line B3-B4.

[0034] Figure 3 It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from the C1-C2 line.

[0035] Figure 4 It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from line A1-A2 in the figure.

[0036] Figure 5 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to the first embodiment.

[0037] Figures 6A to 6I This is a cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the first embodiment.

[0038] Figure 7 It is a graph showing the relationship between temperature and deformation of each material in the multilayer ceramic capacitor according to the first embodiment during heating.

[0039] Figure 8A Is with Figure 2A A cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present invention, taken in the same manner.

[0040] Figure 8B Is with Figure 2B A cross-sectional view of the multilayer ceramic capacitor according to the second embodiment, taken in the same manner.

[0041] Figure 8C Is with Figure 4 A cross-sectional view of the multilayer ceramic capacitor according to the second embodiment, taken in the same manner.

[0042] Figure 9 This is a cross-sectional view showing a construction according to a third embodiment of the present invention, wherein a multilayer ceramic capacitor is mounted on a circuit board.

[0043] Figure 10 This is a perspective view showing a ceramic electronic component according to a fourth embodiment of the present invention.

[0044] Figure 11 This is a table showing the relationship between the size, crack initiation, and durability of different samples of the multilayer ceramic capacitor according to the first embodiment.

[0045] Figure 12 This is a table showing the relationship between the size, crack initiation, and durability of different samples of the multilayer ceramic capacitor according to the first embodiment. Detailed Implementation

[0046] Embodiments of the invention will now be described with reference to the accompanying drawings. The following embodiments are not intended to limit the invention. Combinations of all features described in each embodiment are not absolutely necessary for the invention. The configuration of each embodiment can be modified and / or changed according to the design, specifications, and various conditions (usage conditions, usage environment, etc.) of the device and apparatus to which the invention is applied. The scope of the invention is defined by the appended claims and is not limited to the following embodiments. Furthermore, for easier understanding of the parts, components, and elements, the parts, components, and elements shown in the drawings used in conjunction with the following description may differ in structure, proportion, and shape from the actual parts, components, and elements.

[0047] First Embodiment

[0048] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to a first embodiment of the present invention. Figure 2A It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from line B1-B2. Figure 2B It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from line B3-B4. Figure 3 It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from the C1-C2 line. Figure 4 It is along Figure 1 The cross-sectional view of the multilayer ceramic capacitor taken from line A1-A2 in the figure.

[0049] like Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figure 4As shown, the multilayer ceramic capacitor 1A includes an element body 2 and external electrodes 6A and 6B. The element body 2 has a stacked body 2A, a lower cover layer 5A, and an upper cover layer 5B. The stacked body 2A has an internal electrode layer 3A, other internal electrode layers 3B, and a dielectric layer 4 sandwiched between adjacent internal electrode layers 3A and 3B.

[0050] exist Figure 2A , Figure 2B and Figure 3 In the middle, the boundary between the lower cover layer 5A and the laminate 2A, and the boundary between the upper cover layer 5B and the laminate 2A are indicated by dashed lines, but the sintered boundary, which will be described later, cannot be determined.

[0051] The lower surface of the laminate 2A is covered by a lower capping layer 5A, and the upper surface of the laminate 2A is covered by an upper capping layer 5B. The internal electrode layers 3A and 3B are stacked alternately with a dielectric layer 4 sandwiched between them. Although additionally, Figure 1 , Figure 2A , Figure 2B and Figure 3 An example is shown in which a total of 7 internal electrode layers 3A and 3B are stacked, but there is no limit to the number of internal electrode layers 3A and 3B stacked.

[0052] In the following description, the direction perpendicular to the end faces MA and MB of the substrate 2 can be called the longitudinal direction DL of the substrate 2, the direction perpendicular to the longitudinal direction DL and parallel to the internal electrode layers 3A and 3B can be called the width direction DW of the substrate 2, and the direction perpendicular to the longitudinal direction DL and the width direction DW can be called the stacking direction (height direction) DH of the substrate 2.

[0053] Internal electrode layers 3A and 3B are stacked in the height direction DH, with dielectric layer 4 inserted between them. The left end face MA is opposite to the right end face MB in the longitudinal direction DL.

[0054] The multilayer ceramic capacitor 1A is mounted on a circuit board and is used for purposes including eliminating noise applied to a semiconductor chip mounted on the circuit board.

[0055] The pair of opposing surfaces of the substrate 2, which are approximately parallel to the circuit board, can be referred to as the top surface TS and the bottom surface BS. Additionally, the pair of opposing surfaces of the substrate 2, which are approximately perpendicular to the circuit board and do not expose the internal electrode layers 3A and 3B, can be referred to as a pair of side surfaces SA and SB. The width direction DW passes approximately perpendicularly through the side surfaces SA and SB of the substrate 2.

[0056] In this manual, terms such as "top surface," "bottom surface," "side surface," "height," "thickness," and "width" are used for ease of understanding and are not intended to restrict the orientation of the multilayer ceramic capacitor 1A when mounted on a circuit board.

[0057] like Figure 4 As shown, the sides SA and SB of the body 2 are concavely curved along the longitudinal direction DL, such that the body 2 has a central portion C1 in the longitudinal direction DL, the width W1 of which is smaller than the width W3 at the end faces MA and MB. This means that at least any part of the central portion C1 in the longitudinal direction DL is the narrowest compared to other portions in the longitudinal direction DL, where the widths are compared at the same height level.

[0058] In the illustrated embodiment, the spacing (width of the body 2) between the sides SA and SB of the body 2 gradually decreases from the end faces MA and MB toward points Q1 and Q1' of the sides SA and SB in the central portion C1. Each side may be about Figure 4 The center line Ce1 of the shown body 2 is symmetrical. The center line Ce1 is located at the center of the body 2 in the longitudinal direction DL and passes through it along the width direction DW.

[0059] The vertical central portion C1 is defined, for example, as the middle part of the body 2 in the vertical direction DL when the body 2 is divided into (2N+1) equal parts, where N is a positive integer. For example, when the body 2 is divided into three equal parts in the vertical direction DL, the vertical central portion C1 is defined as the middle part of the body 2 in the vertical direction DL.

[0060] like Figure 2A and Figure 2B As shown, the sides SA and SB of the substrate 2 are concavely curved along the height direction DH, such that the substrate 2 has central portions CA3 and CB3 in the height direction DH, the width of the central portions CA3 and CB3 being smaller than the width of the other portions. Each side can be about Figure 2A and 2B The center lines Ce2 and Ce3 of the shown body 2 are symmetrical. These center lines Ce2 and Ce3 are located at the center of body 2 in the height direction DH and pass through it along the width direction DW.

[0061] from Figure 2A and Figure 2B The comparison is understandable. The radius of curvature of each side of DH along the height direction is the smallest at the longitudinal central part C1 and can gradually increase as it moves toward the longitudinal end of the body 2. Figure 4 Points Q1 and Q1' mentioned above are the points with the smallest radius of curvature on each side of the height direction DH and located within the central portion C1. The concave curvature shape of the side can also be related to... Figure 4 The shown body 2 is axially symmetric along its centerline Ce1.

[0062] like Figure 2B As shown, the width W1 at the central portion C1 of body 2 is precisely defined as the width at the longitudinal central portion C1 at the center of the height direction DH. Figure 2A As shown, the width W3 at the end faces MA and MB of body 2 is precisely defined as the width at the end faces MA and MB at the center in the height direction DH.

[0063] As will be described below, it is preferred that 0 < (W3-W1) / W3 ≤ 0.15%, and more preferably 0.04% < (W3-W1) / W3 ≤ 0.12%.

[0064] like Figure 3 As shown, the top surface TS and bottom surface BS of body 2 are curved protrudingly along the longitudinal direction DL, such that body 2 has a central portion C2 in the longitudinal direction DL, where the thickness (height) T1 of the central portion C2 is greater than the thickness (height) T3 of the end surfaces MA and MB. This means that at least any part of the central portion C2 in the longitudinal direction DL is the thickest compared to other portions in the longitudinal direction DL, where the thickness is compared in the same vertical plane.

[0065] In the illustrated embodiment, the gap between the top surface TS and the bottom surface BS of the substrate 2 (the thickness of the substrate 2) gradually increases from the end surfaces MA and MB toward the longitudinal center.

[0066] The vertical central portion C2 is defined, for example, as the middle part of the body 2 in the vertical direction DL when the body 2 is divided into (2N+1) equal parts, where N is a positive integer. For example, when the body 2 is divided into three equal parts in the vertical direction DL, the vertical central portion C2 is defined as the middle part of the body 2 in the vertical direction DL. The central portion C2 may or may not coincide with the central portion C1.

[0067] As can be seen from the above, body 2 has a top surface TS and a bottom surface BS that are convexly curved along the longitudinal direction DL, and a central portion C2 that is thicker than the end surfaces MA and MB. Each of the top and bottom surfaces can be about Figure 3 The center line Ce4 of the shown body 2 is symmetrical. The center line Ce4 is located at the center of the body 2 in the longitudinal direction DL and passes through it in the height direction DH.

[0068] exist Figure 3 In the cross-section shown, the thickest part of body 2 is located in the central part C2.

[0069] exist Figure 2A and 2BIn the cross-section of body 2 parallel to end faces MA and MB, the central portion in the height direction DH at the end of the longitudinal direction DL of body 2 is called the central portion CA3, and the central portion in the height direction DH at the center of the longitudinal direction DL of body 2 is called the central portion CB3. Furthermore, in the cross-section of body 2 parallel to end faces MA and MB, the central portion in the width direction DW at the end of the longitudinal direction DL of body 2 is called the central portion CA4, and the central portion in the width direction DW at the center of the longitudinal direction DL of body 2 is called the central portion CB4.

[0070] Because the sides SA and SB of body 2 are concavely curved along the longitudinal direction DL (because the width W1 at the longitudinal central portion of body 2 is less than the width W3 at the longitudinal ends), the width at the height-direction central portion CB3 at the longitudinal center of body 2 is less than the width at the height-direction central portion CA3 at the longitudinal ends of body 2. This means that at least any portion of the central portion CB3 in the height direction DH of the longitudinal central portion is the narrowest compared to other portions in the longitudinal direction DL, where the width is compared at the same height level (e.g., at the middle level of the height).

[0071] The central portion CB3 in the height direction is defined, for example, as the middle part of the body 2 in the height direction DH when the body 2 is divided into (2N+1) equal parts, where N is a positive integer. For example, when the body 2 is divided into three equal parts in the height direction DH, the central portion CB3 in the height direction is defined as the middle part of the body 2 in the height direction DH.

[0072] Because the top surface TS and bottom surface BS of body 2 convexly curve along the longitudinal direction DL (because the thickness T1 at the longitudinal central portion of body 2 is greater than the thickness T3 at the longitudinal ends), the thickness at the transverse central portion CB4 at the longitudinal center of body 2 is greater than the thickness at the transverse central portion CA4 at the longitudinal ends of body 2. This means that at least any portion of the central portion CB3 in the width direction DW of the longitudinal central portion is the thickest compared to other portions in the longitudinal direction DL, where the thickness is compared at the same transverse location (e.g., at the middle in the width direction DW).

[0073] The horizontal central portion CB4 is defined, for example, as the middle part of the body 2 in the width direction DW when the body 2 is divided into (2N+1) equal parts, where N is a positive integer. For example, when the body 2 is divided into three equal parts in the width direction DW, the vertical central portion CB3 is defined as the middle part of the body 2 in the width direction DW.

[0074] like Figure 2A and2B As shown, body 2 has a top surface TS and a bottom surface BS that are curved protrudingly along the width direction DW, and has transverse central portions CA4 and CB4 that are thicker than the transverse sides of body 2. Each of the top and bottom surfaces can be about Figure 2A and 2B The center lines Ce5 and Ce6 of the shown body 2 are axially symmetrical. These center lines Ce5 and Ce6 are located at the center of body 2 in the width direction DW and pass through it along the height direction DH.

[0075] from Figure 2A and 2B The comparison is understandable. The radius of curvature of each of the top and bottom surfaces of DW along the width direction is smallest at the longitudinal central portion C1 or C2 and can gradually increase as it moves toward the longitudinal end of the body 2. Figure 4 Points Q1 and Q1' mentioned above are the points with the smallest radius of curvature on each of the top and bottom surfaces of the DW along the width direction and located within the central portion C1 or C2. The convex curved shape of the top and bottom surfaces can also be related to... Figure 4 The shown body 2 is axially symmetric along its centerline Ce1.

[0076] like Figure 2B As shown, the thickness T1 at the longitudinal central portion C1 or C2 of body 2 is precisely defined as the thickness at the central portion CB4 in the width direction DW of the cross section at the longitudinal central portion C1 or C2 of body 2. The thickness of body 2 at the transverse side in the width direction DW of the cross section at the longitudinal central portion C1 or C2 of body 2 is called thickness T2. The width W1 at the longitudinal central portion C1 or C2 of body 2 is precisely defined as the width at the central portion CB3 in the height direction DH of the cross section at the longitudinal central portion C1 or C2 of body 2. The width at the upper and lower edges in the height direction DH of the cross section at the longitudinal central portion C1 or C2 of body 2 is called width W2.

[0077] Preferably, 3.5% ≤ [(W2-W1) / W2] / [(T1-T2) / T2] ≤ 29.3%, and more preferably 5.4% ≤ [(W2-W1) / W2] / [(T1-T2) / T2] ≤ 20.3%. In the inequality, W2 can be the width at the upper and lower edges of the cross-section at the longitudinal central portion C1 or C2 of the substrate 2, or it can be the width at the upper or lower edge of the cross-section at the longitudinal central portion C1 or C2 of the substrate 2.

[0078] Figure 2A , Figure 2B , Figure 3 and Figure 4 The outline of the shown body 2 can be observed by following along Figure 2A , Figure 2B , Figure 3 and Figure 4 The cutting plane obtained by sectioning the cross-section is confirmed by polishing the cutting plane. The aforementioned dimensions of the substrate 2 can also be confirmed by measuring on the cutting plane.

[0079] External electrodes 6A and 6B are located at both ends of the substrate 2, such that they are spaced apart from each other in the longitudinal direction DL. External electrodes 6A and 6B continuously cover the top surface TS, bottom surface BS, side surfaces SA and SB, and the corresponding end surfaces MA or MB of the substrate 2.

[0080] like Figure 3 As shown, in the longitudinal direction DL, internal electrode layers 3A and 3B are alternately arranged at different positions in the laminate 2A. Internal electrode layer 3A may be closer to the left end face MA of the substrate 2 than internal electrode layer 3B, while internal electrode layer 3B may be closer to the right end face MB of the substrate 2 than internal electrode layer 3A.

[0081] The left end of the inner electrode layer 3A is exposed at the left end of the dielectric layer 4 in the left end face MA and is connected to the outer electrode 6A. The right end of the inner electrode layer 3B is exposed at the right end of the dielectric layer 4 in the right end face MB and is connected to the outer electrode 6B.

[0082] On the other hand, such as Figure 4 As shown, in the width direction DW, the sides of the inner electrode layers 3A and 3B are covered by a dielectric material forming the dielectric layer 4. In the width direction DW, the two sides of the inner electrode layer 3A can be aligned with the two sides of the inner electrode layer 3B.

[0083] Therefore, the substrate 2 has a side edge 10 made of a dielectric material and covering the internal electrode layers 3A and 3B in the width direction DW. The substrate 2 may be chamfered along each ridge of the substrate 2.

[0084] The thickness of the internal electrode layers 3A and 3B can range from 0.2 micrometers to 0.8 micrometers.

[0085] The main components of the materials for the internal electrode layers 3A and 3B can be metals, such as Cu (copper), Fe (iron), Zn (zinc), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), or W (tungsten), or alloys containing at least one of the above metals. The main components of the materials for the internal electrode layers 3A and 3B are preferably Ni or Cu.

[0086] The thickness of dielectric layer 4 can range from 0.2 micrometers to 0.5 micrometers. The average crystal grain size of the dielectric contained in dielectric layer 4 can range from 80 nanometers to 200 nanometers.

[0087] The main component of the dielectric layer 4 can be, for example, a ceramic material with a perovskite structure. It can contain 50% or more of the main component. The ceramic material of the dielectric layer 4 can be, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, barium calcium zirconate titanate, or titanium oxide.

[0088] The main components of the materials of the lower cover layer 5A and the upper cover layer 5B can be, for example, ceramic materials. The main components of the ceramic materials of the lower cover layer 5A and the upper cover layer 5B can be the same as the main components of the ceramic material of the dielectric layer 4.

[0089] The convex curved shapes of the top surface TS and bottom surface BS of the substrate 2 and the concave curved shapes of the sides SA and SB of the substrate 2 can be obtained by the distribution of internal stress applied in the substrate 2, which is due to the laminate 2A during the sintering process of the substrate 2 as described below (see Figure 2A and Figure 3 This is caused by the difference between the shrinkage temperature of the substrate 2 and the shrinkage temperatures of the covering layers 5A and 5B. As this difference increases, the internal stress applied to the substrate 2 also increases, resulting in an increase in the curvature of both the convex and concave shapes.

[0090] To change the shrinkage temperature of capping layers 5A and 5B, the grain size of the dielectric (ceramic) material contained in capping layers 5A and 5B can be changed, the amount of glass phase additives (e.g., Si) in the material of capping layers 5A and 5B can be changed, and the amount of binder mixed into the material of capping layers 5A and 5B can be changed.

[0091] The main components of the materials for the external electrodes 6A and 6B can be metals, such as Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or alloys containing at least one of the aforementioned metals. Considering the electrical connection with the internal electrodes 3A and 3B, the main component of the materials for the external electrodes 6A and 6B is preferably Ni.

[0092] like Figure 6I As shown, each of the external electrodes 6A and 6B has a base layer 7 formed on the substrate 2 as a conductive layer and a plating layer 9 formed on the base layer 7.

[0093] The base layers 7 of the external electrodes 6A and 6B are located at opposite ends of the substrate 2, such that the base layers 7 of the external electrodes 6A and 6B are spaced apart from each other in the longitudinal direction DL. The base layer 7 of each of the external electrodes 6A and 6B continuously covers the top surface TS, bottom surface BS, side surfaces SA and SB of the substrate 2, as well as the corresponding end surface MA or MB.

[0094] The conductive material used for the substrate 7 can be a metal, such as Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy containing at least one metal. The substrate 7 may also include co-material particles dispersed within the metal. Here, the term "particles" refers not only to individual small particles but also to a mass formed by the combination of multiple small particles after a sintering process described later. The island-like dispersion of the co-material in the substrate 7 reduces the difference in the coefficients of thermal expansion between the substrate 2 and the substrate 7, thereby alleviating the thermal stress applied to the substrate 7. The co-material is, for example, a ceramic composition that is the main component of the material of the dielectric layer 4. The substrate 7 may also contain a glass component. The glass component in the substrate 7 can densify the substrate 7. The glass component can be, for example, oxides of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), B (boron), etc.

[0095] The base layer 7 is preferably formed from a sintered body of a conductive paste containing metal. This allows the base layer 7 to be thickened while ensuring adhesion between the substrate 2 and the base layer 7, thereby ensuring the strength of the external electrodes 6A and 6B and the conductivity between the base layer 7 and the internal electrode layers 3A and 3B.

[0096] Each of the external electrodes 6A and 6B has a plating layer 9 that continuously covers the corresponding substrate layer 7. The plating layer 9 is electrically connected to the internal electrode layer 3A or 3B through the corresponding substrate layer 7. Furthermore, the plating layer 9 of each of the external electrodes 6A and 6B is electrically connected to an electrode on the circuit board via solder.

[0097] The material of coating 9 can be a metal, such as Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, Sn, etc., or an alloy containing at least one of the above metals. Coating 9 can be a single layer of a single metal composition or multiple layers of different metal compositions.

[0098] Each of the external electrodes 6A and 6B may have a plating layer 9, for example, a three-layer structure consisting of a Cu plating layer formed on the base layer 7, a Ni plating layer formed on the Cu plating layer, and a Sn plating layer formed on the Ni plating layer. The Cu plating layer can improve the adhesion between the plating layer 9 and the base layer 7, while the Ni plating layer can improve the heat resistance of the external electrodes 6A and 6B during soldering. The Sn plating layer can improve the wettability of the solder to the plating layer 9.

[0099] In an embodiment, such as Figure 4 As shown, because the sides SA and SB of the base body 2 are concavely curved along the longitudinal direction DL, in the laminate 2A (see... Figure 2A and 2BIn particular, in the region RE (by) near the boundary between the lower cover layer 5A and the laminate 2A and the boundary between the upper cover layer 5B and the laminate 2A. Figure 2A and 2B The dashed lines in the diagram indicate that the local residual stress present in the laminate 2A can be mitigated. Therefore, the capping layers 5A and 5B are difficult to separate from the laminate 2A, which prevents the rupture of the substrate 2, the deterioration of the mechanical strength of the substrate 2, the deterioration of the insulation resistance, and the deterioration of reliability. The separation of the capping layers 5A and 5B from the laminate 2A is called peeling.

[0100] Furthermore, by adjusting the grain size of the dielectric (ceramic) material contained in the capping layers 5A and 5B, the amount of glass phase additives and / or binders contained in the capping layers 5A and 5B, it is possible to obtain the convex curved shape of the top surface TS and bottom surface BS of the substrate 2, as well as the concave curved shape of the sides SA and SB of the substrate 2. This eliminates the need for further processing of the sintered substrate 2 to obtain the convex and concave curved shapes, thereby suppressing the increase in cost of the substrate 2.

[0101] The external dimensions of the multilayer ceramic capacitor 1A are preferably within the range of JIS "0201" (length = 0.25mm, width = 0.125mm, height = 0.125mm) to JIS "3225" (length = 3.2mm, width = 2.5mm, height = 2.5mm). More preferably, the external dimensions are within the range of JIS "0201" to "0402" (length = 0.4mm, width = 0.2mm, height = 0.2mm). It should be noted that the above dimensions are design values, and the actual product dimensions may include dimensional tolerances. When the external dimensions of the multilayer ceramic capacitor 1A are within the range of "0201" to "0402", the multilayer ceramic capacitor 1A can be miniaturized and have a large capacitance.

[0102] The capacitance of the multilayer ceramic capacitor 1A is preferably in the range of 10μF to 1000μF. More preferably, the capacitance of the multilayer ceramic capacitor 1A is in the range of 470μF to 1000μF. When the capacitance of the multilayer ceramic capacitor 1A is in the range of 470μF to 1000μF, the multilayer ceramic capacitor 1A can be made smaller and can be used as a smoothing capacitor in power supply circuits, and ripple current can be effectively reduced.

[0103] Figure 5 This is a flowchart illustrating an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. Figures 6A to 6I This is a cross-sectional view illustrating an exemplary method of manufacturing a multilayer ceramic capacitor according to the first embodiment. For ease of explanation, Figures 6C to 6IOnly three internal electrode layers 3A and three internal electrode layers 3B are shown, which are alternately stacked with a dielectric layer 4 inserted therebetween.

[0104] exist Figure 5 In step S1 (mixing step), organic binders and organic solvents, acting as dispersants and molding aids, are added to the dielectric material powder, and then pulverized and mixed to prepare a slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may include one or more additives. One or more additives may be, for example, oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), Y (yttrium), Sm (samarium), Eu (europium), Gd (cadmium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium), or Si, or glass. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0105] Next, in Figure 5 In step S2 (slurry coating step), such as Figure 6A As shown, green sheet 24 is manufactured. Specifically, a slurry containing ceramic powder is coated onto a sheet-like carrier film and dried to manufacture green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The coating of the slurry can be performed, for example, by blade coating, die coating, gravure coating, etc. Step S2 is repeated to prepare multiple green sheets 24.

[0106] Next, in Figure 5 In step S3 (electrode printing step), such as Figure 6B As shown, a conductive paste (which will become the internal electrode layer) is applied in a predetermined pattern to each of the green sheets 24 prepared in step S1. Figure 2B The internal electrode layer 3A or 3B shown will be placed on the green sheet to form an internal electrode pattern 23 on the green sheet 24. In step S3, multiple internal electrode patterns 23 can be formed on each single green sheet 24 such that the internal electrode patterns 23 are separated from each other in the longitudinal direction of the green sheet 24.

[0107] The conductive paste used for the inner electrode layers includes metal powders that serve as materials for the inner electrode layers 3A and 3B. For example, if the metal used as materials for the inner electrode layers 3A and 3B is Ni, then the conductive paste used for the inner electrode layers includes Ni powder. The conductive paste used for the inner electrode layers also includes binders, solvents, and (if necessary) additives. The conductive paste used for the inner electrode layers may include a ceramic material as a co-material, the main components of which have the same composition as the main components of the material of the dielectric layer 4.

[0108] The conductive paste for the internal electrode layer can be applied using screen printing, inkjet printing, or gravure printing. Therefore, step S3 can be referred to as the electrode printing step. In this manner, a plurality of green sheets 24 having internal electrode patterns 23 thereon are prepared.

[0109] Next, in Figure 5 In step S4 (cascaded step), as follows Figure 6C As shown, a green sheet 24 with an internal electrode pattern 23 and green sheets 25A and 25B without an internal electrode pattern 23 are stacked in a predetermined order to form a green sheet block 30. The green sheets 25A and 25B without an internal electrode pattern 23 are used as outer layers (lower cover layer 5A and upper cover layer 5B).

[0110] The green sheet 24 having internal electrode patterns 23A or 23B is divided into two groups: a green sheet 24 having internal electrode pattern 23A (which will form internal electrode layer 3A) and a green sheet 24 having internal electrode pattern 23B (which will form internal electrode layer 3B). The green sheets 24 having internal electrode pattern 23A and the green sheets 24 having internal electrode pattern 23B are stacked alternately in the stacking direction, such that the internal electrode pattern 23A on the green sheet 24 and the internal electrode pattern 23B on the next or adjacent green sheet 24 alternate in the longitudinal direction of the green sheet 24.

[0111] In addition, three types of portions are defined in the green wafer block 30. Specifically, the green wafer block 30 includes portions in which only the internal electrode patterns 23A are stacked in the stacking direction, portions in which the internal electrode patterns 23A and 23B are stacked alternately in the stacking direction, and portions in which only the internal electrode patterns 23B are stacked in the stacking direction.

[0112] The green sheets 25A and 25B used for the lower cover layer 5A and the upper cover layer 5B are thicker than the green sheet 24 on which the internal electrode pattern 23 is formed.

[0113] As described above, in order to change the shrinkage temperature of capping layers 5A and 5B, the crystal grain size of the dielectric (ceramic) material contained in capping layers 5A and 5B can be changed, the amount of glass phase additive (e.g., Si) in the material of capping layers 5A and 5B can be changed, and the amount of binder mixed into the material of capping layers 5A and 5B can be changed.

[0114] If the average crystal grain size of the dielectric powder contained in green sheets 25A and 25B is greater than the average crystal grain size of the dielectric powder contained in green sheet 24, the shrinkage temperature of the cover layers 5A and 5B can be adjusted to be higher than the shrinkage temperature of the laminate 2A during sintering.

[0115] If the amount of glass phase additive in the dielectric powder contained in green sheets 25A and 25B is increased, the shrinkage temperature of the capping layers 5A and 5B can be adjusted to be lower during sintering.

[0116] Increasing the amount of binder in the dielectric powder contained in green sheets 25A and 25B increases the distance between the dielectric particles in green sheets 25A and 25B before sintering, thus slowing down the solid solution of the dielectric particles during sintering. This causes the shrinkage temperature of the capping layers 5A and 5B to be higher than that of the laminate 2A during sintering.

[0117] Next, in Figure 5 In step S5 (pressure bonding step), as follows: Figure 6D As shown, it will be Figure 5 The laminated block 30 obtained in step S4 is pressed so that the green sheets 24, 25A and 25B are bonded by pressure. The pressing of the laminated block 30 can be performed, for example, by hydrostatic pressing of the laminated block 30, which can be surrounded by a resin film.

[0118] exist Figure 5 In step S6 (cutting step), as follows Figure 6E As shown, the pressed laminate 30 is cut such that the laminate 30 is divided into multiple bodies, each body having a cuboid shape. Each body has six surfaces. The cutting of the laminate 30 is performed on portions of the internal electrode pattern 23A that are stacked in the stacking direction and portions of the internal electrode pattern 23B that are stacked in the stacking direction, as indicated by the multiple vertical dashed lines 27. The cutting of the laminate 30 can be performed by, for example, blade cutting or similar methods.

[0119] exist Figure 6F The resulting base body 2' is shown in magnified form. (e.g.) Figure 6F As shown, in each substrate 2', internal electrode layers 3A and 3B are alternately stacked with a dielectric layer 4 sandwiched between them. Internal electrode layer 3A is exposed at one end face MA of each substrate 2', and internal electrode layer 3B is exposed at the other end face MB of each substrate 2'.

[0120] The lower cover layer 5A and the upper cover layer 5B are formed in each body 2'.

[0121] Next, in Figure 5 In step S7 (adhesive removal step), the adhesive is removed from the... Figure 5 The adhesive contained in each substrate 2' separated in step S6. The adhesive is removed, for example, by heating the substrate 2' in a N2 atmosphere at about 350 degrees Celsius.

[0122] Next, in Figure 5In step S8 (the step of applying the paste for the base layer), as follows: Figure 6G As shown, a conductive paste 7' for the substrate (bottom layer) 7 is applied to the two end faces MA and MB of each substrate 2 from which the adhesive was removed in step S7, and is also applied to the remaining four faces (top, bottom, and side) of the substrate 2 adjacent to the respective end faces MA and MB. For example, the conductive paste 7' for the substrate layer can be applied using an impregnation method. The conductive paste 7' is then dried.

[0123] The base layer 7 used for the conductive paste 7' contains metal powder or filler, which serves as the conductive material of the base layer 7. For example, when the metal used as the conductive material of the base layer 7 is Ni, the conductive paste 7' used for the base layer contains Ni powder or filler. The conductive paste 7' used for the base layer also contains, for example, a ceramic component as a co-material, which is a major component of the material of the dielectric layer 4. For example, oxide ceramic particles mainly composed of barium titanate (e.g., with a D50 particle size of 0.1 micrometer to 4 micrometers) are mixed as a co-material in the conductive paste 7' used for the base layer. The conductive paste 7' used for the base layer also contains binders and solvents.

[0124] However, after sintering the base material 2 (step S9), a conductive paste 7' for the substrate layer can also be applied and sintered. In this case, the conductive paste 7' can be sintered in a N2 atmosphere at, for example, 780 degrees Celsius for ten to thirty minutes.

[0125] Next, in Figure 5 In step S9 (sintering step), as follows Figure 6H As shown, the substrate 2, to which the conductive paste for the base layer 7 is coated in step S8, undergoes a sintering process, such that the internal electrode layers 3A and 3B are integrated with the dielectric layer 4 of each substrate 2, and the base layer 7 is integrated with the substrate 2. The sintering of the substrate 2 and the conductive paste 7' is carried out, for example, in a sintering furnace at a temperature range of 1000 degrees Celsius to 1400 degrees Celsius for ten minutes to two hours.

[0126] If base metals such as Ni or Cu are used as materials for the inner electrode layers 3A and 3B, the sintering process can be carried out in a sintering furnace while the interior of the sintering furnace is kept in a reducing atmosphere to prevent oxidation of the inner electrode layers 3A and 3B.

[0127] As described above, during the sintering step, due to the difference between the shrinkage temperature of the laminate 2A and the shrinkage temperature of the covering layers 5A and 5B, the internal stress varies depending on the position in the substrate 2, thereby forming the convex curved shape of the top surface TS and bottom surface BS of the substrate 2 and the concave curved shape of the sides SA and SB of the substrate 2.

[0128] During the sintering step, some oxide components in the dielectric material of the substrate 2 can be reduced, allowing for a re-oxidation step after sintering. The re-oxidation step can be carried out in a N2 atmosphere at a temperature range from 600 degrees Celsius to 1000 degrees Celsius.

[0129] Next, in Figure 5 In step S10 (the step of forming the coating), as follows: Figure 6I As shown, coating 9 is formed on substrate 7. When forming coating 9, for example, Cu coating, Ni coating and Sn coating can be formed sequentially. The coating can be formed by housing the substrate 2 on which substrate 7 is formed in a barrel and immersing it in the plating solution inside the barrel, and rotating the barrel and applying electricity.

[0130] Figure 7 This illustrates the relationship between the temperature and deformation of the material of the multilayer ceramic capacitor 1A according to the first embodiment when the temperature rises. Figure 7 This was obtained through thermomechanical analysis (TMA) of the material of the multilayer ceramic capacitor 1A.

[0131] In this figure, curve M1 corresponds to the thermal shrinkage behavior of the materials of the inner electrode layers 3A and 3B in the laminate 2A, while curves M2 to M4 correspond to the thermal shrinkage behavior of the different materials of the capping layers 5A and 5B.

[0132] As shown in each curve, the shrinkage rate increases significantly with increasing temperature. The temperature at which shrinkage begins can be considered the shrinkage initiation temperature, and the temperature at which shrinkage ends can be considered the shrinkage termination temperature.

[0133] The temperature at which the shrinkage rate is greatest relative to temperature change (the temperature at which the slope angle of the curve is greatest) can be called the shrinkage temperature. For curve M1, the shrinkage temperature of the materials of the inner electrode layers 3A and 3B is Ta (degrees Celsius). For curve M3, the shrinkage temperature of the materials of the capping layers 5A and 5B is Tx (degrees Celsius).

[0134] Because the shrinkage temperatures of the capping layers 5A and 5B are higher than those of the inner electrode layers 3A and 3B, the inner electrode layers 3A and 3B begin to shrink before the capping layers 5A and 5B begin to shrink. Since the shrinkage of the inner electrode layers 3A and 3B mainly occurs in the width direction (DW), therefore... Figure 2A and 2B As shown, the sides SA and SB of the substrate 2 are deformed into a concave bend along the height direction DH, which significantly compresses the interior of the laminate 2A. The compressive stress causes the top surface TS and bottom surface BS of the substrate 2 to bulge outward along the width direction DW to release the compressive stress itself.

[0135] If the shrinkage temperatures of the capping layers 5A and 5B are significantly higher than those of the inner electrode layers 3A and 3B, the inner electrode layers 3A and 3B will shrink earlier than the deformation of the capping layers 5A and 5B, and the stress in the laminate 2A will increase. As a result, the concave and convex curvatures of the outer surface of the substrate 2 will increase.

[0136] However, if the stress in the substrate 2 is too high, the durability of the substrate 2 against mechanical and / or electrical fatigue will decrease, and the reliability of the multilayer ceramic capacitor 1A will deteriorate.

[0137] On the other hand, if the shrinkage temperature of the capping layers 5A and 5B is too close to the shrinkage temperature of the inner electrode layers 3A and 3B, peeling is likely to occur between the laminate 2A and the capping layers 5A and 5B.

[0138] To confirm the occurrence and reliability of delamination in different samples of the multilayer ceramic capacitor 1A, the inventors conducted experiments. Table 1 shows the shrinkage temperature Ta (degrees Celsius) of the materials of the internal electrode layers 3A and 3B and the shrinkage temperature Tx (degrees Celsius) of the materials of the capping layers 5A and 5B for each sample. The samples had various Ta values ​​and various Tx values. The shrinkage temperatures Ta and Tx were obtained by TMA.

[0139] The conditions in the TMA are as follows: the heating rate is 10 degrees Celsius / minute, and the atmosphere is a mixture of nitrogen (99%) and hydrogen (1%).

[0140] The reliability of the sample is confirmed by testing its durability (HALT (Highly Accelerated Life Test)).

[0141] Table 1

[0142] Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 Sample 6 Sample 7 Sample 8 Sample 9 Ta (°C) 650 720 760 850 900 800 800 650 900 Tx (°C) 1200 1200 1095 1150 1150 1100 1050 1220 1050 Tx / Ta 1.85 1.67 1.44 1.35 1.28 1.38 1.31 1.88 1.17

[0143] In sample 1, delamination occurred after the sintering process, but it remained at a problem-free level. Post-production durability tests showed good results.

[0144] In sample 2, delamination occurred after the sintering process, but it remained at a problem-free level. Post-production durability tests showed good results.

[0145] In sample 3, almost no delamination occurred after the sintering process. Post-production durability tests showed good results.

[0146] In sample 4, no delamination occurred after the sintering process. Post-production durability tests showed good results.

[0147] In sample 5, almost no delamination occurred after the sintering process. Post-production durability tests showed good results.

[0148] In sample 6, no delamination occurred after the sintering process. Post-production durability tests showed good results.

[0149] In sample 7, no delamination occurred after the sintering process. Post-production durability tests showed good results.

[0150] In sample 8, problematic peeling occurred after the sintering process. Post-production durability testing showed inadequate results.

[0151] In sample 9, problematic delamination occurred after the sintering process. Post-production durability tests showed good results.

[0152] Based on the above experimental results, the preferred ratio is 1.20 ≤ Tx / Ta ≤ 1.85, more preferably 1.30 ≤ Tx / Ta ≤ 1.60, and even more preferably 1.30 ≤ Tx / Ta ≤ 1.40.

[0153] As mentioned above, such as Figure 4 As shown, the sides SA and SB of body 2 are concavely curved along the longitudinal direction DL. Figure 3 As shown, the top surface TS and bottom surface BS of body 2 are curved protrudingly along the longitudinal direction DL. Figure 2A and 2B As shown, the sides SA and SB are concave along the height direction DH, while the top surface TS and bottom surface BS are convex along the width direction DW.

[0154] The preferred shapes of the top surface TS, bottom surface BS, side surface SA and SB of the base body 2 can be obtained by adjusting at least one of the following: (i) the grain size of the dielectric (ceramic) material contained in the capping layers 5A and 5B, (ii) the amount of glass phase additive in the material of the capping layers 5A and 5B, and (iii) the amount of binder mixed into the dielectric powder contained in the capping layers 5A and 5B.

[0155] (i) If the grain size of the dielectric material contained in the capping layers 5A and 5B is increased, the shrinkage initiation temperature of the capping layers 5A and 5B during sintering can be increased, thereby increasing the amount of concave curvature of the longitudinally concave sides SA and SB (see Figure 4 ).

[0156] (ii) If the amount of glass phase additive added to the dielectric material powder contained in the capping layers 5A and 5B is increased, the shrinkage initiation temperature and shrinkage temperature of the capping layers 5A and 5B during sintering can be reduced, thereby reducing the amount of concave curvature of the longitudinally concave sides SA and SB (see) Figure 4 ).

[0157] (iii) If the amount of binder mixed into the dielectric powder contained in the capping layers 5A and 5B is increased, the shrinkage initiation temperature of the capping layers 5A and 5B during sintering can be increased, thereby increasing the amount of concave curvature of the longitudinally concave sides SA and SB (see Figure 4 ), and can increase the amount of convex curvature of the top surface TS and bottom surface BS, which are convexly curved along the longitudinal direction DL (see Figure 3 ).

[0158] Second Embodiment

[0159] Figure 8A Is with Figure 2A A cross-sectional view of the multilayer ceramic capacitor 1B according to the second embodiment of the present invention, taken in the same manner. Figure 8B Is with Figure 2B A cross-sectional view of the multilayer ceramic capacitor 1B according to the second embodiment, taken in the same manner. Figure 8C Is with Figure 4 A cross-sectional view of the multilayer ceramic capacitor 1B according to the second embodiment, taken in the same manner.

[0160] like Figures 8A to 8C As shown, in addition to the body 2 and external electrodes 6A and 6B, the multilayer ceramic capacitor 1B also has a sealing resin layer 8. Except for the sealing resin layer 8, the multilayer ceramic capacitor 1B is the same as the multilayer ceramic capacitor 1A.

[0161] The sealing resin layer 8 covers the top surface TS of the substrate 2, the top surface of each of the external electrodes 6A and 6B, the upper part of the side surfaces SA and SB of the substrate 2, and the upper part of the side surfaces of each of the external electrodes 6A and 6B. Except for the bottom surfaces of the external electrodes 6A and 6B that are electrically connected to the electrodes on the circuit board, the sealing resin layer 8 may also cover the entire multilayer ceramic capacitor 1B.

[0162] The resin layer 8 can be formed from thermoplastic resin, thermosetting resin, or UV-curable resin. The material of the resin layer 8 can be applied by spraying or dipping.

[0163] By coating the substrate 2 and external electrodes 6A and 6B with resin layer 8, moisture can be prevented from entering the charge storage area within the substrate 2, and shock resistance can be improved, thereby enhancing the reliability of the multilayer ceramic capacitor 1B. Furthermore, when mounting the multilayer ceramic capacitor 1B onto the circuit board using solder that connects the external electrodes 6A and 6B to electrodes on the circuit board, the sealing resin layer 8 prevents solder from wetting the top surface of each of the external electrodes 6A and 6B. This prevents the height of the multilayer ceramic capacitor 1B from increasing after mounting onto the substrate.

[0164] like Figure 8A and 8BAs shown, the sides SA and SB of the substrate 2 are concavely curved along the height direction DH. This prevents resin before curing from dripping down the sides SA and SB. Furthermore, the sealing resin layer 8 at the center of each of the sides SA and SB in the height direction of the substrate 2 can be thickened to prevent moisture from penetrating the charge accumulation area within the substrate 2. Therefore, the reliability of the multilayer ceramic capacitor 1B can be ensured.

[0165] Third Embodiment

[0166] Figure 9 This is a cross-sectional view showing the construction of a multilayer ceramic capacitor mounted on a circuit board according to a third embodiment of the present invention.

[0167] like Figure 9 As shown, pad electrodes 12A and 12B are formed on the circuit board 11. The circuit board 11 can be a printed circuit board or a semiconductor board made of, for example, Si. The multilayer ceramic capacitor 1A is connected to the pad electrodes 12A and 12B via solder layers 13A and 13B attached to the plating layers 9 of the external electrodes 6A and 6B, respectively.

[0168] Each of solder layers 13A and 13B wets to the end face of the corresponding external electrode 6A or 6B. If the height of the multilayer ceramic capacitor 1A is small, each of solder layers 13A and 13B may wet to the top face of the corresponding external electrode 6A or 6B.

[0169] However, because the top surface TS of the substrate 2 is curved protrudingly along the longitudinal direction DL, the heights of the external electrodes 6A and 6B gradually decrease towards the end faces MA and MB of the substrate 2. Therefore, even if the solder layers 13A and 13B wet to the top surfaces of the external electrodes 6A and 6B, the solder layers 13A and 13B cannot reach the top surface TS of the substrate 2. As a result, the height of the multilayer ceramic capacitor 1A is prevented from increasing during installation.

[0170] Fourth embodiment

[0171] Figure 10 This is a perspective view showing a ceramic electronic component according to a fourth embodiment of the present invention. Figure 10 The example shown is a chip inductor used as a ceramic electronic component.

[0172] The chip inductor 61 includes a body 62 and two external electrodes 66A and 66B. The body 62 includes a coil pattern 63 and a magnetic material 64, the coil pattern 63 including two terminal segments 63A and 63B formed at its two ends.

[0173] The portion of the coil pattern 63, including terminal segments 63A and 63B, is formed as a thin plate, and the entire coil pattern 63 is formed as a spiral.

[0174] Magnetic material 64 is used as a dielectric to insulate the internal electrode layer formed by the coil pattern 63.

[0175] A lower cover layer 65A, similar to the lower cover layer 5A, is disposed at the bottom of the body 62, and an upper cover layer 65B, similar to the upper cover layer 5B, is disposed at the top of the body 62.

[0176] The shrinkage temperature of the cover layers 65A and 65B is higher than that of the coil pattern 63.

[0177] The shape of base body 62 can be approximately a cuboid.

[0178] However, the sides SA and SB of the body 62 are concavely curved along the longitudinal direction DL, so that the body 62 has a longitudinal central portion with a width smaller than that of the longitudinal ends.

[0179] The top surface TS and bottom surface BS of the body 62 are curved protrudingly along the longitudinal direction DL, so that the body 62 has a longitudinal central portion with a thickness greater than that of the longitudinal ends.

[0180] The sides SA and SB of the body 62 are also concavely curved along the height direction DH, so that the body 62 has a central portion in the height direction with a width smaller than that at the ends in the height direction. The radius of curvature of each side along the height direction DH is smallest at the central portion in the longitudinal direction and gradually increases towards the longitudinal ends of the body 62 (similar to...). Figure 2A and 2B (The above comparison).

[0181] The top surface TS and bottom surface BS of the body 62 are curved protrudingly along the width direction DW, giving the body 62 a transverse central portion with a thickness greater than that of the two transverse sides. The radius of curvature of each of the top and bottom surfaces along the width direction DW is smallest at the longitudinal central portion and gradually increases towards the longitudinal ends of the body 62 (similar to the above). Figure 2A and 2B (Comparison).

[0182] The coil pattern 63 is embedded in the magnetic material 64. However, terminal segment 63A is exposed from the magnetic material 64 on one end face MA of the body 62 and connected to the external electrode 66A, while terminal segment 63B is exposed from the magnetic material 64 on the other end face MB of the body 62 and connected to the external electrode 66B.

[0183] The coil pattern 63 and terminal segments 63A and 63B can be made of, for example, metals such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or alloys containing at least one of these metals. The magnetic material 64 is, for example, ferrite.

[0184] External electrodes 66A and 66B are located on opposite sides of the substrate 62, such that they are spaced apart from each other in the longitudinal direction DL. Each of the external electrodes 66A and 66B extends continuously from the corresponding end face MA or MB of the substrate 62 to the side, top, and bottom surfaces of the substrate 62.

[0185] experiment

[0186] To confirm the crack initiation and durability of different samples of the multilayer ceramic capacitor 1A, the inventors conducted experiments.

[0187] Figure 11 and Figure 12 The relationship between the size, crack initiation, and durability (HALT results) of different samples of multilayer ceramic capacitors according to the first embodiment is shown.

[0188] Figure 11 The sample corresponds to JIS "3225", wherein the material of dielectric layer 4 is barium titanate, and the thickness of each dielectric layer 4 between inner electrode layers 3A and 3B is 1.5 micrometers. The material of inner electrode layers 3A and 3B is nickel, and the thickness of each of inner electrode layers 3A and 3B is 1.0 micrometer. The total number of inner electrode layers 3A and 3B is 200.

[0189] Figure 12 The sample corresponds to JIS standard "1608" (length = 1.6 mm, width = 0.8 mm, height = 0.8 mm), wherein the dielectric layer 4 is made of barium titanate, and the thickness of each dielectric layer 4 between the inner electrode layers 3A and 3B is 0.8 micrometers. The inner electrode layers 3A and 3B are made of nickel, and the thickness of each of the inner electrode layers 3A and 3B is 0.6 micrometers. The total number of inner electrode layers 3A and 3B is 200.

[0190] The samples used in the experiment had various sizes (W1, W2, W3, T1, T2, and T3). Furthermore, the samples satisfied 1.20 ≤ Tx / Ta ≤ 1.85.

[0191] Figure 11 and Figure 12 The “HALT results” indicate the lifetime at which 50% of the samples broke during HALT.

[0192] Based on the occurrence of cracks and the results of HALT, the samples were divided into good quality and poor quality.

[0193] Samples A to I and L to T are good, while samples J, K, U and V are poor.

[0194] As the concave curvature of the sides SA and SB of body 2 increases in the width direction DW, the aforementioned ratio [(W2-W1) / W2] / [(T1-T2) / T2] increases (see...). Figure 2B This is because the difference between widths W2 and W1 increases. Additionally, as the concave curvature along the longitudinal direction DL on the sides SA and SB of body 2 increases, the aforementioned ratio (W3-W1) / W3 increases (see...). Figure 2A This is because the difference between widths W3 and W1 increases.

[0195] As the concave curvature in the width direction DW on the sides SA and SB of the substrate 2 increases, and as the concave curvature in the longitudinal direction DL on the sides SA and SB of the substrate 2 increases, crack generation can be reduced and the lifespan of the multilayer ceramic capacitor 1A can be extended, thereby ensuring the reliability of the multilayer ceramic capacitor 1A.

[0196] However, if the concave curvature in the width direction DW on the sides SA and SB of the substrate 2 is too large, the durability of the multilayer ceramic capacitor 1A will decrease. Therefore, it is preferable that 3.5% ≤ [(W2-W1) / W2] / [(T1-T2) / T2] ≤ 29.3%, and more preferably 5.4% ≤ [(W2-W1) / W2] / [(T1-T2) / T2] ≤ 20.3%.

[0197] Furthermore, if the concave curvature in the width direction DW on the sides SA and SB of the substrate 2 is too large, the durability of the multilayer ceramic capacitor 1A will decrease. Therefore, it is preferable that 0 < (W3-W1) / W3 ≤ 0.15%, and more preferably 0.04% < (W3-W1) / W3 ≤ 0.12%.

[0198] In the above embodiments, multilayer ceramic capacitors and surface-mount inductors are used as examples of ceramic electronic components. However, the ceramic electronic components according to the present invention can be surface-mount resistors or sensor chips. In the above embodiments, each of the ceramic electronic components includes two external electrodes, but the ceramic electronic components can include three or more external electrodes.

[0199] It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from its spirit or scope. Therefore, the present invention is intended to cover modifications and variations falling within the scope of the appended claims and their equivalents. Specifically, it is clearly understood that any part or all of any two or more embodiments described above and their modifications may be combined and considered within the scope of the present invention.

Claims

1. A ceramic electronic component, comprising: A substrate, the substrate including a dielectric, at least one first internal electrode and at least one second internal electrode, the second internal electrode being stacked on the first internal electrode by the dielectric being inserted between the first internal electrode and the second internal electrode, the substrate having a top surface, a bottom surface, a pair of side surfaces, a first end face and a second end face, thereby the substrate having a generally cuboid shape, the side surfaces of the substrate being concavely curved in the longitudinal direction such that the width at the longitudinal central portion of the substrate is smaller than the width at the end face; A first external electrode is formed on the first end face and electrically connected to the first internal electrode; and A second external electrode is formed on the second end face and electrically connected to the second internal electrode.

2. The ceramic electronic component according to claim 1, wherein, The sides of the body are concavely curved along the height direction, each of the sides having a radius of curvature along the height direction, the radius of curvature being minimum at the longitudinal central portion and increasing towards the end face.

3. The ceramic electronic component according to claim 1 or 2, wherein, The base body satisfies 0 < (W3 - W1) / W3 ≤ 0.15%, where W1 is the width at the longitudinal central portion at the center of the base body in the height direction, and W3 is the width at the end face at the center of the base body in the height direction.

4. The ceramic electronic component according to claim 3, wherein, The base body satisfies 0.04% < (W3-W1) / W3 ≤ 0.12%.

5. The ceramic electronic component according to any one of claims 1-2, wherein, The top and bottom surfaces of the substrate are curved in the longitudinal direction, such that the thickness of the central longitudinal portion of the substrate is greater than the thickness at the end face.

6. The ceramic electronic component according to any one of claims 1-2, wherein, The top and bottom surfaces of the substrate are curved in the width direction, such that the thickness of the central portion of the substrate is greater than the thickness at the two sides.

7. The ceramic electronic component according to claim 6, wherein, The base body satisfies 3.5% ≤ [(W2-W1) / W2] / [(T1-T2) / T2] ≤ 29.3%, where W1 is the width of the longitudinal central portion at the center of the height direction of the base body, W2 is the width at the upper edge and / or lower edge of the longitudinal central portion of the base body, T1 is the thickness of the longitudinal central portion at the center of the width direction of the base body, and T2 is the thickness of the longitudinal central portion at both lateral sides of the base body.

8. The ceramic electronic component according to claim 7, wherein, The base body satisfies 5.4%≤[(W2-W1) / W2] / [(T1-T2) / T2]≤20.3%.

9. The ceramic electronic component according to any one of claims 1-2, further comprising a sealing resin layer covering the top surface of the substrate, the top surface of each of the first external electrode and the second external electrode, the upper portion of the side surface of the substrate, and the upper portion of the side surface of each of the first external electrode and the second external electrode.

10. The ceramic electronic component according to any one of claims 1-2, having a length in the range of 0.25 mm to 0.4 mm, a width in the range of 0.125 mm to 0.2 mm, and a height in the range of 0.125 mm to 0.2 mm.

11. The ceramic electronic component according to any one of claims 1-2, wherein, The thickness of the dielectric between the first internal electrode and the second internal electrode is in the range of 0.2 micrometers to 0.5 micrometers.

12. The ceramic electronic component according to any one of claims 1-2, wherein, The average crystal grain size of the dielectric of the substrate is in the range of 80 nanometers to 200 nanometers.

13. The ceramic electronic component according to any one of claims 1-2, wherein, The thickness of the first internal electrode and the second internal electrode is in the range of 0.2 micrometers to 0.8 micrometers.

14. The ceramic electronic component according to any one of claims 1-2, having a capacitance in the range of 10 μF to 1000 μF.

15. The ceramic electronic component according to any one of claims 1-2, wherein, The main component of the materials used for the first and second external electrodes is Ni.

16. A circuit board structure, comprising: Circuit board; and A ceramic electronic component according to any one of claims 1-15 is mounted on the circuit board, the ceramic electronic component being connected to the circuit board via solder layers attached to the first external electrode and the second external electrode, each of the solder layers wetting the end face of the first external electrode or the second external electrode.

17. A method for manufacturing a ceramic electronic component, the method comprising: A body is formed comprising a dielectric, internal electrodes, and a capping layer. The body has a top surface, a bottom surface, a pair of side surfaces, and a pair of end surfaces, thereby giving the body a generally cuboid shape. Each of the internal electrodes is exposed on one of the end surfaces. The capping layer forms the top and bottom surfaces and is made of a material whose shrinkage temperature is higher than that of the material of the internal electrodes. Sintering the base body; A base layer is formed for external electrodes located at the longitudinal ends of the substrate, wherein the base layer for each of the external electrodes covers the top surface, bottom surface, side surface, and corresponding end face of the substrate; and Each coating is formed on the substrate layer.

18. The method according to claim 17, wherein, The shrinkage temperature Ta (degrees Celsius) of the material of the internal electrode and the shrinkage temperature Tx (degrees Celsius) of the material of the covering layer satisfy 1.20≤Tx / Ta≤1.

85.

19. The method according to claim 18, wherein, The shrinkage temperature Ta (degrees Celsius) of the material of the internal electrode and the shrinkage temperature Tx (degrees Celsius) of the material of the covering layer satisfy 1.30≤Tx / Ta≤1.

60.

20. The method according to claim 19, wherein, The shrinkage temperature Ta (degrees Celsius) of the material of the internal electrode and the shrinkage temperature Tx (degrees Celsius) of the material of the covering layer satisfy 1.30≤Tx / Ta≤1.40.

Images