Dielectric layer on a semiconductor device and method of forming the same

Abstract

The present disclosure relates to dielectric layers on semiconductor devices and methods of forming the same. A method of forming a semiconductor device includes forming a first layer on a semiconductor fin, forming a mask on the first layer, the mask being thicker at a top of the semiconductor fin than along sidewalls of the semiconductor fin, thinning the first layer along the sidewalls of the semiconductor fin using the mask, forming a second layer on the semiconductor fin, the second layer covering the mask and the first layer, forming a dummy gate layer on the semiconductor fin, and patterning the dummy gate layer to expose a top surface of the semiconductor fin.

Description

Technical Field

[0001] This disclosure relates to a dielectric layer on a semiconductor device and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a semiconductor fin and an isolation region adjacent to the semiconductor fin; forming a first layer on the semiconductor fin; forming a mask on the first layer, the mask being thicker at the top of the semiconductor fin than along the sidewalls of the semiconductor fin; thinning the first layer along the sidewalls of the semiconductor fin using the mask, the thinning of the first layer removing a portion of the mask; forming a second layer on the semiconductor fin, the second layer covering the remaining portion of the mask and the remaining portion of the first layer; forming a dummy gate layer on the semiconductor fin; and patterning the dummy gate layer, wherein the patterning of the dummy gate layer exposes the top surface of the semiconductor fin.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: depositing a first dielectric layer on a first semiconductor fin and a second semiconductor fin using plasma-enhanced atomic layer deposition, wherein the first semiconductor fin is in a first region of a die and the second semiconductor fin is in a second region of the die; forming a mask layer on the first dielectric layer, wherein the mask layer covers the top surface of a portion of the first dielectric layer on the first semiconductor fin and the second semiconductor fin, the thickness of the mask layer tapering along the upper portion of a sidewall of the first dielectric layer; removing an exposed portion of the first dielectric layer; depositing a second dielectric layer on the mask layer and the remaining portion of the first dielectric layer on the first semiconductor fin and the second semiconductor fin; removing a first portion of the second dielectric layer, a first portion of the mask layer, and a first portion of the first dielectric layer on the first semiconductor fin, wherein a second portion of the first dielectric layer, a second portion of the mask layer, and a second portion of the second dielectric layer remain on the second semiconductor fin; and forming a first gate electrode on the first semiconductor fin and forming a second gate electrode on a second portion of the second dielectric layer.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being in a first region of a die and the second semiconductor fin being in a second region of the die; a first gate dielectric on the first semiconductor fin, the first gate dielectric substantially contacting the top surface of the first semiconductor fin; a first dielectric layer on the second semiconductor fin; a second dielectric layer on the first dielectric layer, the second dielectric layer comprising carbon; a third dielectric layer on the second dielectric layer; a second gate dielectric on the third dielectric layer; a first gate electrode on the first gate dielectric; and a second gate electrode on the second gate dielectric. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a FinFET is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E , Figure 21F , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 24A , Figure 24B , Figure 24C and Figure 24D This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of embodiments of the present invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0012] According to some embodiments, a dielectric layer is formed on the fin before forming the dummy gate on the semiconductor feature (e.g., fin). The dielectric layer includes a mask layer that allows for the formation of a dielectric material with a greater thickness on the top of the fin than on the sidewalls of the fin. The dielectric layer can reduce fin loss on the top surface of the fin during subsequent patterning processes of the dummy gate, which can improve device performance by reducing contact resistance. The process for forming the dielectric layer can be integrated with and followed by an oxide deposition process, which is low-cost and enables high wafer rates per hour.

[0013] Figure 1 An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 60 extending from a substrate 50 (e.g., a semiconductor substrate). An isolation region 70 is disposed on the substrate 50, and the fin 60 protrudes from and between adjacent isolation regions 70. Although the isolation regions 70 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may be used to refer to a semiconductor substrate only or a semiconductor substrate including the isolation regions. Furthermore, although the fin 60 is shown as being a single continuous material with the substrate 50, the fin 60 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 60 refers to the portion extending between adjacent isolation regions 70.

[0014] The gate dielectric layer 110 is along the sidewall of the fin 60 and above the top surface of the fin 60, and the gate electrode 112 is above the gate dielectric layer 110. The source / drain region 102 is disposed on the opposite side of the fin 60 relative to the gate dielectric layer 110 and the gate electrode 112. Figure 1Reference cross sections used in subsequent figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 112 and in a direction perpendicular to, for example, the current direction between the source / drain regions 102 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 60, and in the direction of current flow between, for example, the source / drain regions 102 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0015] Some embodiments discussed herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs), nanostructured field-effect transistors (NSFETs) (e.g., nanosheets, nanowires, gate-all-around, etc.), etc.

[0016] Figures 2 to 23B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 It shows Figure 1 The reference cross section AA shown in the figure includes multiple fins / FinFETs. Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 20C , Figure 21A , Figure 21D , Figure 22A , Figure 22C , Figure 23A , Figure 23C , Figure 24A and Figure 24C Along Figure 1 The reference section AA shown is illustrated, and Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 20D , Figure 21B , Figure 21C , Figure 21E , Figure 21F , Figure 22B , Figure 22D , Figure 23B , Figure 23D , Figure 24B and Figure 24D Along Figure 1 The diagram shows a similar cross-section BB, except for multiple fins / FinFETs. Figure 17C and Figure 17D Along Figure 1 The reference cross section C / DC / D shown is illustrated, in addition to multiple fins / FinFETs.

[0017] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0018] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, or an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, or a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P.

[0019] Suitable wells (not shown) can be formed in substrate 50. In the illustrated embodiment, a p-type well is formed in an n-type region 50N, and an n-type well is formed in a p-type region 50P. The wells are formed by implanting p-type and / or n-type impurities into n-type regions 50N and p-type regions 50P. After implantation into n-type regions 50N and p-type regions 50P, annealing can be performed to activate the implanted p-type and / or n-type impurities.

[0020] In embodiments with different well types, photoresist or other masks (not shown) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed on the n-type region 50N of the substrate 50. The photoresist is patterned to expose the p-type region 50P of the substrate 50, such as a PMOS region. The photoresist can be formed using a spin coating technique, and the photoresist can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N, such as an NMOS region. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 (For example, in about 10) 17 cm -3 Peace Treaty 10 18 cm -3 (between). After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0021] After implantation into the p-type region 50P, a photoresist is formed on top of the p-type region 50P of the substrate 50. The photoresist is patterned to expose the n-type region 50N of the substrate 50, such as an NMOS region. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P, such as a PMOS region. The p-type impurities can be boron, BF2, indium, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 (For example, in about 10) 17 cm -3 Peace Treaty 10 18 cm -3 (between). After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0022] A first semiconductor region 52 is formed on the substrate 50. The first semiconductor region 52 is a semiconductor material such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc. In some embodiments, the first semiconductor region 52 is silicon. The first semiconductor region 52 is epitaxially grown on the substrate 50. As discussed further below, the first semiconductor region 52 will be patterned to form fins in the n-type region 50N.

[0023] exist Figure 3 In this process, a second semiconductor region 54 is formed on the substrate 50. The second semiconductor region 54 is a semiconductor material such as silicon-germanium (e.g., Si). x Ge 1-x The second semiconductor region 54 is silicon-germanium. The second semiconductor region 54 is epitaxially grown on the substrate 50. As an example, materials that can be used to form a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc. In some embodiments, the second semiconductor region 54 is silicon-germanium. The second semiconductor region 54 is epitaxially grown on the substrate 50. As an example of forming the second semiconductor region 54, an opening can be formed in the first semiconductor region 52 above the p-type region 50P of the substrate. This opening can be formed using a photoresist as an etching mask through one or more etching processes. The etching process can include wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, etc., and can be anisotropic. The second semiconductor region is then epitaxially grown on the substrate 50 in the opening.

[0024] Silicon and silicon-germanium have different lattice constants. Thus, the second semiconductor region 54 and the substrate 50 have mismatched lattice constants. The lattice constant mismatch depends on the germanium concentration in the second semiconductor region 54, with higher germanium concentrations resulting in larger lattice constant mismatches. This lattice constant mismatch induces compressive strain in the second semiconductor region 54, which can increase the carrier mobility of the second semiconductor region 54, thereby improving the channel region mobility of the subsequently formed p-type device. The channel region formed in the second semiconductor region 54 can be a partially or fully strained channel region.

[0025] In some embodiments, the first semiconductor region 52 and the second semiconductor region 54 are in-situ doped during growth to have suitable doped regions (e.g., wells). The doped regions of the first semiconductor region 52 and the second semiconductor region 54 may have the same doping type as the doped regions of the underlying substrate 50. The doped regions of the first semiconductor region 52 and the second semiconductor region 54 may have the same doping concentration as the doped regions of the underlying substrate 50, or they may have different doping concentrations. In some embodiments, doping of the first semiconductor region 52 and the second semiconductor region 54 may avoid implantation in the substrate 50, although in-situ doping and implantation doping may be used together.

[0026] exist Figure 4 In the design, trench 56 is formed in a first semiconductor region 52 and a second semiconductor region 54 (and optionally a substrate 50). Trench 56 can be formed using a photoresist as an etching mask through one or more etching processes. The etching processes (one or more) can include wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, and can be anisotropic. Trench 56 may extend partially into the first semiconductor region 52 and the second semiconductor region 54, or may extend through the semiconductor regions and into the substrate 50. The portions of the first semiconductor region 52 and the second semiconductor region 54 (and optionally the substrate 50) retained between the trench 56 are referred to as fins 60. Each fin 60 includes a lower portion 62 and an upper portion 64. The lower portion 62 includes lower portions 62N and 62P, wherein the lower portion 62N includes the remaining portion of the n-type region 50N of the substrate 50, and the lower portion 62P includes the remaining portion of the p-type region 50P of the substrate 50. The upper portion 64 includes upper portions 64N and 64P, wherein upper portion 64N includes the remaining portion of the first semiconductor region 52, and upper portion 64P includes the remaining portion of the second semiconductor region 54. The fin 60 is formed with a first width W1. In some embodiments, the first width W1 is in the range of 5 nm to 15 nm. This fin width allows the fin to maintain sufficient thickness after subsequent etching processes (described below).

[0027] The fin can be patterned using any suitable method. For example, the fin 60 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on the fin 60.

[0028] exist Figure 5 In this embodiment, an insulating material 68 is formed on the substrate 50 and between adjacent fins 60. The insulating material 68 may be formed such that excess portions of the insulating material 68 cover the fins 60. The insulating material 68 may be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD) based material deposition in a remote plasma system, followed by post-curing to convert it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 68 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. Although the insulating material 68 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fins 60. Subsequently, a filler material, such as those discussed above, may be formed on the liner.

[0029] exist Figure 6In this process, insulating material 68 is recessed to form shallow trench isolation (STI) regions 70. Insulating material 68 is recessed such that the upper portion 64 of fin 60 protrudes between adjacent STI regions 70. The insulating material 68 can be recessed by performing a planarization process followed by an acceptable etching process. In some embodiments, the planarization process includes chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc. The planarization process exposes fin 60. After the planarization process, the top surfaces of fin 60 and insulating material 68 are flush. The STI regions 70 can then be recessed using an acceptable etching process (e.g., a process selective for the material of insulating material 68). For example, it can be removed using a chemical oxide using a hydrogen source (e.g., ammonia) and a fluorine source (e.g., nitrogen trifluoride), or using a chemical oxide using dilute hydrofluoric acid (dHF). The top surface of the STI region 70 can be formed as flat, raised, and / or recessed by the etching process. The exposed portion of fin 60 has a first height H1. In some embodiments, the first height H1 is in the range of 40 nm to 60 nm.

[0030] In the illustrated embodiment, the top surface of the STI region 70 is flush with the top surface of the lower portion 62 of the fin 60, thus fully exposing the upper portion 64 of the fin 60. In some embodiments, the top surface of the STI region 70 is configured to be higher than the top surface of the lower portion 62 of the fin 60, thus partially exposing the upper portion 64 of the fin 60. In some embodiments, the top surface of the STI region 70 is configured to be lower than the top surface of the lower portion 62 of the fin 60, thus fully exposing the upper portion 64 of the fin 60 and partially exposing the lower portion 62 of the fin 60.

[0031] In some embodiments, a protective cap (not shown) is formed on the exposed portion of the fin 60. Germanium is more prone to oxidation than silicon, and therefore the upper 64P of the fin 60, which may include germanium, faces a greater risk of oxidation. Forming a protective cap can help avoid / reduce oxidation during subsequent processing. The protective cap can be a semiconductor material such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. In some embodiments, the protective cap is silicon and is epitaxially grown on the exposed portion of the fin 60.

[0032] Figures 7 to 10 A dummy dielectric layer 80 is shown formed on a fin 60 according to some embodiments. The dummy dielectric layer 80 includes dielectric sublayers, and the thickness of the dielectric material formed on the top of the fin 60 is greater than the thickness of the dielectric material formed on the sidewalls of the fin 60 (see below). Figure 10 The subsequent removal process of the dummy gate formed on fin 60 (see below) Figure 12A and Figure 12BDuring this process, a greater thickness at the top of the dummy dielectric layer 80 can reduce fin losses on the top surface of the fin 60 without increasing the thickness of the dielectric sublayer 80A on the sidewalls of the fin 60. This increase could cause undesirable merging of subsequent portions of the dummy dielectric layer 80 on adjacent fins 60 and / or dummy gate layers between adjacent fins 60 (see below). Figures 11A-11B Undesirable gaps in the subsequent formation of the part.

[0033] exist Figure 7 In this configuration, a first dielectric sublayer 80A is formed over the upper portion 64 of the fin 60 and the exposed portion of the STI region 70. The first dielectric sublayer 80A may comprise most of the subsequently formed dummy dielectric layer 80 on the top surface of the fin 60. The first dielectric sublayer 80A may comprise one or more oxide (e.g., silicon oxide) and / or nitride (e.g., silicon nitride) layers and may be formed by suitable processes such as CVD, PECVD, PVD, ALD, and PEALD. In some embodiments, the first dielectric sublayer 80A comprises silicon oxide and is formed by PEALD, wherein the plasma generation power is in the range of 15W to 200W. In some embodiments, the first dielectric sublayer 80A is formed on... to The first thickness T1 within the range is advantageous for subsequent patterning processes of the dummy gate (see below). Figures 12A-13B Reduce fin losses during this period. The first dielectric sublayer 80A is formed to be smaller than... The thickness of the dummy gate may cause undesirable fin losses during subsequent patterning processes. The first dielectric sublayer 80A is formed to be greater than... The thickness may cause undesirable merging of subsequently formed portions of the dummy dielectric layer 80 on adjacent fins 60 and / or dummy gate layers between adjacent fins 60 (see below). Figures 11A-11B Undesirable gaps in the subsequent formation of the part.

[0034] After the first dielectric sublayer 80A is formed, it can be subjected to plasma treatment (e.g., O2 plasma treatment). Plasma treatment can further oxidize the material of the first dielectric sublayer 80A, which can reduce fin losses during subsequent patterning processes of the dummy gate. Plasma treatment can be performed using plasma generation power in the range of 400W to 600W.

[0035] exist Figure 8 In the process, a mask sublayer 80B is formed on the top surface of the first dielectric sublayer 80A above the fin 60. The mask sublayer 80B is then used in subsequent etch-back processes (see below). Figure 9During this period, a portion of the first dielectric sublayer 80A is protected. A mask sublayer 80B is formed to cover the top surface of the portion of the first dielectric sublayer 80A above the fin 60. In some embodiments, the mask sublayer 80B exposes the top surface of the portion of the first dielectric sublayer 80A on the STI region 70. In some embodiments, a sidewall portion of the mask sublayer 80B extends along the upper portion of the sidewall of the first dielectric sublayer 80A. The thickness of the sidewall portion of the mask sublayer 80B may taper along the upper portion of the sidewall of the first dielectric sublayer 80A. For example, in situations such as... Figure 8 In the illustrated embodiments, the bottom of the sidewalls of the first dielectric sublayer 80A can be exposed, and the thickness of the mask sublayer 80B can be tapered, wherein the thickness increases as the mask sublayer 80B extends further away from the substrate 50. In some embodiments where the first dielectric sublayer 80A comprises, for example, silicon oxide, the mask sublayer 80B can comprise carbon and / or nitrogen and can be formed using suitable processes such as CVD, PECVD, PVD, ALD, PEALD, etc. In these embodiments, such as where the first dielectric sublayer 80A comprises silicon oxide and the mask sublayer 80B comprises nitrides, carbides, etc., the mask sublayer 80B has a lower etch rate than the first dielectric sublayer 80A, thereby acting as an etch mask in subsequent etch-back processes to allow etching of uncovered portions of the first dielectric sublayer 80A (e.g., on the sidewalls of the fin 60) while protecting the top of the first dielectric sublayer 80A. For example, in some embodiments, the mask sublayer 80B is silicon nitride, silicon carbonitride, silicon carbonitride, or a combination thereof, and is formed using bis(diethylamino)silane (BDEAS), SiH3-N(CH-(CH3)2)2, or a combination thereof as a precursor.

[0036] In some embodiments, the mask sublayer 80B is formed using a suitable process such as ALD, which has relatively high pressure, short purge time, and short plasma treatment time. The higher pressure, shorter purge time, and shorter plasma treatment time can result in less adsorption of the precursor on the sidewalls of the first dielectric sublayer 80A and more adsorption on the top surface of the first dielectric sublayer 80A. This can result in the mask sublayer 80B having more material on the top surface of the first dielectric sublayer 80A than on the sidewalls of the first dielectric sublayer 80A; for example, the thickness of the mask sublayer 80B can be tapered, with the thickness increasing as the mask sublayer 80B extends further away from the substrate 50. In some embodiments, the ALD process utilizes multiple deposition cycles of alternating precursor gases. For example, the ALD process can be cyclic deposition, including a first cycle using, for example, a first precursor such as bis(diethylamino)silane (BDEAS), followed by a second cycle using a second precursor such as SiH3-N(CH-(CH3)2)2. In some embodiments, silicon and oxygen deposited in the first cycle can react with silicon, carbon, and nitrogen deposited in the second cycle to form a material comprising silicon, oxygen, carbon, and nitrogen. Alternating first and second cycles can be repeated until the mask sublayer reaches a desired thickness, for example, silicon carbonitride. The mask sublayer 80B can be formed using a plasma generation power in the range of 15W to 150W. The mask sublayer 80B can be formed under a pressure in the range of 1500 torr to 3500 torr. The mask sublayer 80B can be formed when the purge time for each cycle of the ALD is in the range of 0.05s to 0.25s and the plasma treatment time for each cycle of the ALD is in the range of 0.05s to 0.25s.

[0037] In some embodiments, the mask sublayer 80B is formed to have a dielectric layer 80A on the top surface of the first dielectric sublayer 80A above the fin 60. to The second thickness T2 within the range is beneficial for maintaining sufficient thickness of the mask sublayer 80B to protect the top of the first dielectric sublayer 80A after subsequent etch-back processes. The mask sublayer 80B is formed to be less than... The thickness may be disadvantageous because it does not provide sufficient thickness to protect the top of the first dielectric sublayer 80A. Forming the mask sublayer 80B to be larger than... The thickness may be disadvantageous because it can cause undesirable merging of subsequent portions of the dummy dielectric layer 80 on adjacent fins 60 and / or dummy gate layers between adjacent fins 60 (see below). Figures 11A-11B Undesirable gaps in the subsequent formation of the part.

[0038] exist Figure 9 In this process, patterning, such as an etch-back process, is performed to remove portions of the first dielectric sublayer 80A and mask sublayer 80B on the sidewalls of the fin 60. By removing the sidewall portions of the first dielectric sublayer 80A and mask sublayer 80B, the etch-back process can increase the process window for subsequent processes (e.g., dummy gate layer formation between fins 60) by increasing the distance between adjacent structures (e.g., between adjacent fins). By increasing the distance, undesirable merging of subsequent formation portions of the dummy dielectric layer 80 on adjacent fins and / or dummy gate layers between adjacent fins 60 are reduced (see below). Figures 11A-11B The possibility of unwanted voids in the subsequently formed portion of the fin. Mask sublayer 80B serves as an etch stop layer to protect the top of the first dielectric sublayer 80A on the top surface of the fin 60 from the etch-back process. The etch-back process can be a cyclic etching process including wet etching, dry etching, or a combination thereof. In some embodiments, the etch-back process includes wet etching using dilute hydrofluoric acid, hydrochloric acid, or a combination thereof as an etchant. In some embodiments, the etch-back process includes dry etching using NH3, HF, or a combination thereof as an etchant. The etch-back process can stop when the sidewall portion of the first dielectric sublayer 80A has been removed, exposing the sidewalls of the upper portion 64 of the fin 60.

[0039] After the etch-back process, the top of the first dielectric sublayer 80A remains on the top surface of the fin 60, covered by the remainder of the mask sublayer 80B. In some embodiments, the remainder of the mask sublayer 80B has... to The third thickness T3 within the range facilitates the removal of the sidewall portions of the first dielectric sublayer 80A and mask sublayer 80B by the etch-back process. The remaining portion of the mask sublayer 80B has a thickness less than [missing information]. This could cause etching of the first dielectric sublayer 80A, potentially resulting in undesirable subsequent fin loss. The remaining portion of the mask sublayer 80B has a thickness greater than [missing information]. This could leave a portion of the sidewall of the first dielectric sublayer 80A on the fin 60, which would reduce the process window for subsequent processes such as dummy gate formation.

[0040] exist Figure 10 In this process, a second dielectric sublayer 80C is formed over the upper portion 64 of the fin 60 and the exposed portion of the STI region 70, covering the remaining portions of the first dielectric sublayer 80A and the mask sublayer 80B. The remaining portions of the first dielectric sublayer 80A and the mask sublayer 80B, together with the second dielectric sublayer 80C, form a dummy dielectric layer 80, wherein the thickness of the dielectric material formed over the top of the fin 60 is greater than the thickness of the dielectric material formed over the sidewalls of the fin 60. This allows for subsequent removal processes of the dummy gate formed over the fin 60 (see below). Figure 12A and Figure 12B During this period, fin loss on the top surface of fin 60 is reduced. In some embodiments, the second dielectric sublayer 80C is composed of a first dielectric sublayer 80A (see above) Figure 7 Similar materials are formed using similar methods. Note that, for illustrative purposes only, the second dielectric sublayer 80C is shown as covering the STI region 70. In some embodiments, the second dielectric sublayer 80C covers only the fin 60.

[0041] In some embodiments, the second dielectric sublayer 80C is formed to have a dielectric layer on the sidewalls of the fin 60 and on the top surface of the fin 60. to The fourth thickness T4 within the range is advantageous for subsequent patterning processes of the dummy gate (see below). Figures 12A-13B Reduce fin losses during this period. Form the second dielectric sublayer 80C to be smaller than... The thickness of the dummy gate may cause undesirable fin losses during subsequent patterning processes. The second dielectric sublayer 80C is formed to be greater than... The thickness may cause undesirable merging of portions of the second dielectric sublayer 80C on adjacent fins 60 and / or undesirable voids in portions of the subsequently formed dummy gate layer between adjacent fins 60 (see below). Figures 11A-11B ).

[0042] In some embodiments, the dummy dielectric layer 80 has a measurement between the top surface of the fin 60 and the top surface of the dummy dielectric layer 80 above the fin 60. to The fifth thickness T5 within the range is advantageous for subsequent patterning processes of the dummy gate (see below). Figures 12A-13B Reduce fin losses during this period. The fifth thickness T5 of the dummy dielectric layer 80 is less than... This may cause undesirable fin losses during subsequent patterning processes of the dummy gate. The fifth thickness T5 of the dummy dielectric layer 80 is greater than... This may reduce the process window for subsequent processes (e.g., dummy gate formation).

[0043] In some embodiments, the ratio of the fifth thickness T5 to the fourth thickness T4 is in the range of 2:1 to 5:1, which can help reduce fin loss on the top surface of the fin 60 while increasing the process window for subsequent processes (e.g., dummy gate formation). A ratio of the fifth thickness T5 to the fourth thickness T4 less than 2:1 may cause undesirable fin loss on the top surface of the fin 60 or reduce the process window for subsequent processes (e.g., dummy gate formation). A ratio of the fifth thickness T5 to the fourth thickness T4 greater than 5:1 may affect the subsequent removal process of the dummy dielectric layer 80 (see below). Figures 20A-20B During this period, it causes undesirable fin loss on the sidewall of fin 60.

[0044] exist Figure 11A and Figure 11B In this process, a dummy gate layer 82 is formed over a dummy dielectric layer 80, and a mask layer 84 is formed over the dummy gate layer 82. The dummy gate layer 82 may be deposited over the dummy dielectric layer 80 and then planarized (e.g., by CMP). The mask layer 84 may be deposited over the dummy gate layer 82. The dummy gate layer 82 may be a conductive or semiconductor material and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 82 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 82 may be made of other materials with high etch selectivity relative to the etching of isolation regions (e.g., STI region 70 and / or dummy dielectric layer 80). The mask layer 84 may include, for example, one or more layers of silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 82 and a single mask layer 84 are formed across the n-type region 50N and the p-type region 50P.

[0045] Figures 12A to 23B Various additional steps are shown in the manufacturing of the embodiment device. Although Figures 12A to 23B Features in p-type region 50P are shown; however, it should be understood that the illustrated structure is applicable to both n-type region 50N and p-type region 50P. The differences in structure between n-type region 50N and p-type region 50P (if any) are described in the accompanying text to each figure.

[0046] exist Figure 12A and Figure 12B In this process, acceptable photolithography and etching techniques can be used to process mask layer 84 (see above). Figures 11A-11BThe pattern is then patterned to form a mask 94. The pattern of the mask 94 can then be transferred to the dummy gate layer 82 to form dummy gates 92. The dummy gates 92 cover the corresponding channel regions 58 of the fin 60. The pattern of the mask 94 can be used to separate each dummy gate 92 from the adjacent dummy gate entity. The dummy gates 92 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 60.

[0047] exist Figure 13A and Figure 13B In this process, the patterns of mask 94 and dummy gate 92 are transferred to dummy dielectric layer 80 using an acceptable etching technique to form dummy gate dielectric layer 90. In some embodiments, dummy gate dielectric layer 90 is formed by an etching process including wet etching, dry etching, or a combination thereof. In some embodiments, the etching process includes wet etching using dilute hydrofluoric acid, hydrochloric acid, or a combination thereof as etchants. In some embodiments, the etching process includes dry etching using NH3, HF, or a combination thereof as etchants. In some embodiments where the corresponding materials of the first dielectric sublayer 80A, mask sublayer 80B, and second dielectric sublayer 80C have different etching selectivity, the etching process may include a first etchant (e.g., O2, HBr, etc.) selected for etching the material of the first dielectric sublayer 80A, a second etchant (e.g., O2, HBr, etc.) selected for etching the material of the mask sublayer 80B, and a third etchant (e.g., O2, HBr, etc.) selected for etching the material of the second dielectric sublayer 80C. In some embodiments, the material of the first dielectric sublayer 80A is the same as the material of the second dielectric sublayer 80C, and the first etchant is the same as the third etchant.

[0048] Due to the virtual dielectric layer 80 with a thickness of T5 (see above) Figure 10 The upper portion 64 of the fin 60 is covered and can be etched with a distance D1, where the distance D1 is in the range of 1 nm to 2 nm. The fin loss at distance D1 on the upper portion 64 of the fin 60 can be less than the corresponding fin loss that occurs when the thickness of the dummy dielectric layer 80 above the upper portion 64 of the fin 60 is small. This can improve device performance by reducing contact resistance.

[0049] exist Figure 14A and Figure 14BIn this embodiment, a gate sealing spacer 96 is formed on the exposed surfaces of the dummy gate 92, mask 94, dummy gate dielectric layer 90, and / or fin 60. The gate sealing spacer 96 can be formed by thermal oxidation or deposition (followed by anisotropic etching). In the illustrated embodiment, the gate sealing spacer 96 is formed by thermal oxidation of the sidewall portions of the dummy gate 92, mask 94, dummy gate dielectric layer 90, and fin 60. The gate sealing spacer 96 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0050] exist Figure 15A and Figure 15B In this process, implantation is performed for the lightly doped source / drain (LDD) region 98. In embodiments with different device types, the process is similar to that described above. Figure 2 The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 60 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have a doping density of approximately 10. 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair injection damage and reactivate the injected impurities.

[0051] exist Figure 16A and Figure 16B In this process, a gate spacer 100 is formed on the gate sealing spacer 96 along the sidewalls of the dummy gate 92 and the mask 94. The gate spacer 100 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 100 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. The gate spacer 100 extends above the upper portion 64 of the fin 60.

[0052] It should be noted that the above disclosure provides a general description of the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, steps can be taken in different sequences (e.g., the gate seal spacer 96 may not be etched before forming the gate spacer 100, resulting in an "L-shaped" gate seal spacer), spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device can be formed before forming the gate seal spacer 96, while the LDD region for a p-type device can be formed after forming the gate seal spacer 96.

[0053] exist Figure 17A and Figure 17B In the fin 60, an epitaxial source / drain region 102 is formed. The epitaxial source / drain region 102 is formed in the fin 60 such that each dummy gate 92 is disposed between adjacent pairs of the corresponding epitaxial source / drain region 102. In some embodiments, the epitaxial source / drain region 102 may extend into the fin 60 and may also penetrate the fin 60. In some embodiments, the gate spacer 100 is used to separate the epitaxial source / drain region 102 from the dummy gate 92 and the dummy gate dielectric layer 90 by an appropriate lateral distance such that the epitaxial source / drain region 102 does not short-circuit the gate of the subsequently formed FinFET. The material of the epitaxial source / drain region 102 can be selected to apply stress in the corresponding channel region 58, thereby improving performance.

[0054] The epitaxial source / drain region 102 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region) and etching the source / drain region of the fin 60 in the p-type region 50P to form a recess in the fin 60. The epitaxial source / drain region 102 in the p-type region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 102 can include, for example, any acceptable material suitable for a p-type FinFET. For example, if the fin 60 is silicon-germanium, the epitaxial source / drain region 102 in the p-type region 50P can include a material to which tensile strain is applied in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin-silicon, etc. The epitaxial source / drain region 102 in the p-type region 50P can have a surface protruding from the corresponding surface of the fin 60 and can have facets.

[0055] The epitaxial source / drain region 102 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region) and etching the source / drain region of the fin 60 in the n-type region 50N to form a recess in the fin 60. The epitaxial source / drain region 102 in the n-type region 50N is then epitaxially grown in the recess. The epitaxial source / drain region 102 can include, for example, any acceptable material suitable for FinFETs. For example, if the fin 60 is silicon, the epitaxial source / drain region 102 in the n-type region 50N can include a material for applying compressive strain in the channel region 58, such as silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 102 in the n-type region 50N can have a surface protruding from the corresponding surface of the fin 60 and can have a facet.

[0056] The epitaxial source / drain regions 102 and / or fins 60 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be approximately 10. 19 cm -3 To about 10 21 cm -3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 102 can be doped in situ during growth.

[0057] As a result of the epitaxial process used to form the epitaxial source / drain regions 102 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 102 has small facets that extend laterally outward beyond the sidewalls of the fin 60. In some embodiments, these small facets cause adjacent source / drain regions 102 of the same FinFET to merge, such as... Figure 17C As shown. In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 102 remain separated, as shown. Figure 17D As shown. In Figure 17C and Figure 17D In the illustrated embodiment, gate spacer 100 is formed to cover the portion of the sidewall of fin 60 extending above STI region 70, thereby preventing epitaxial growth. In some other embodiments, the spacer etching for forming gate spacer 100 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of STI region 70.

[0058] exist Figure 18A and Figure 18B In the middle, the first interlayer dielectric (ILD) 106 is deposited on Figure 17A and Figure 17BThe structure shown is above the first ILD 106. The first ILD 106 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 104 is disposed between the first ILD 106 and the epitaxial source / drain region 102, mask 94, and gate spacer 100. The CESL 104 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., with an etch rate lower than that of the material of the overlying first ILD 106.

[0059] exist Figure 19A and Figure 19B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 106 flush with the dummy gate 92 or mask 94 (see above). Figures 15A-15B The top surfaces of the dummy gate 92, gate seal spacer 96, gate spacer 100, and first ILD 106 are flush with each other. The planarization process also removes the mask 94 on the dummy gate 92, as well as portions of the gate seal spacer 96 and gate spacer 100 along the sidewalls of the mask 94. After the planarization process, the top surfaces of the dummy gate 92, gate seal spacer 96, gate spacer 100, and first ILD 106 are flush. Therefore, the top surface of the dummy gate 92 is exposed through the first ILD 106. In some embodiments, the mask 94 may be retained, in which case the planarization process flushes the top surface of the first ILD 106 with the top surface of the mask 94.

[0060] Figures 20A to 24D Various additional steps are shown when fabricating the embodiment device in a first region 500 (e.g., core logic region) and a second region 600 (e.g., input / output region) of the die. Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A and Figure 24B The first region 500 is shown, and Figure 20C , Figure 20D , Figure 21D , Figure 21E , Figure 21F , Figure 22C , Figure 22D , Figure 23C , Figure 23D , Figure 24C and Figure 24D The second region 600 is shown.

[0061] exist Figures 20A to 20D In one or more etching steps, the dummy gate 92 and mask 94 (if present) are removed to form a recess 108. A portion of the dummy gate dielectric layer 90 within the recess 108 may also be removed. In some embodiments, only the dummy gate 92 is removed, and the dummy gate dielectric layer 90 remains and is exposed by the recess 108. In some embodiments, the dummy gate dielectric layer 90 is removed from the recess 108 in a first region 500 of the die (e.g., a core logic region) and remains in the recess 108 in a second region 600 of the die (e.g., an input / output region). In some embodiments, the dummy gate 92 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 92 and barely etch the first ILD 106 or gate spacer 100. Each recess 108 exposes and / or overlays the channel region 58 of the corresponding fin 60. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 102. During removal, the dummy gate dielectric layer 90 can be used as an etch stop layer when the dummy gate 92 is etched. After the dummy gate 92 is removed, the dummy gate dielectric layer 90 can then be removed in the first region 500 (e.g., Figures 20A-20B (as shown), and can be retained in the second region 600 (as shown) Figures 20C-20D (As shown). When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0062] exist Figure 21A , Figure 21B , Figure 21D and Figure 21E In this process, a gate dielectric layer 110 and a gate electrode 112 are formed to replace the gate. Figure 21C It shows Figure 21B A detailed view of area 12, and Figure 21F It shows Figure 21E A detailed view of region 14. A gate dielectric layer 110, comprising one or more layers, is deposited in the recess 108. In some embodiments, in the first region 500, the gate dielectric layer 110 is deposited on the top surface and sidewalls of the fin 60 and on the sidewalls of the gate sealing spacer 96 / gate spacer 100 (e.g., Figures 21A-21B As shown), and in the second region 600, the gate dielectric layer 110 is deposited on the top surface and sidewalls of the dummy gate dielectric layer 90 and on the sidewalls of the gate sealing spacer 96 / gate spacer 100 (as shown). Figures 21D-21E(As shown). The gate dielectric layer 110 may also be formed on the top surface of the first ILD 106. In some embodiments, the gate dielectric layer 110 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 110 in the first region 500 includes a silicon oxide interface layer formed by thermal oxidation or chemical oxidation and an overlying high-k dielectric material (e.g., metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof) (e.g. Figures 21A-21B As shown), and the gate dielectric layer 110 in the second region 600 includes a high-k dielectric material (such as...). Figures 21D-21E (As shown). The gate dielectric layer 110 may include a dielectric layer with a k value greater than about 7.0. The method for forming the gate dielectric layer 110 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0063] Gate electrode 112 is correspondingly deposited on gate dielectric layer 110 and fills the remaining portion of recess 108. Gate electrode 112 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although Figure 21B and Figure 21E A single-layer gate electrode 112 is shown, but the gate electrode 112 may include any number of liner layers 112A, any number of work function tuning layers 112B, and filler material 112C (such as...). Figure 21C and Figure 21F (As shown). After filling the recess 108, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 110 and gate electrode 112 above the top surface of the ILD 106. The remaining material from the gate dielectric layer 110 and gate electrode 112 thus forms the replacement gate of the resulting FinFET. The gate electrode 112 and gate dielectric layer 110 can be collectively referred to as the “gate stack”. The gate and gate stack can extend along the sidewalls of the channel region 58 of the fin 60.

[0064] The formation of the gate dielectric layer 110 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 110 in each region is formed of the same material, and the formation of the gate electrode 112 can occur simultaneously, such that the gate electrode 112 in each region is formed of the same material. In some embodiments, the gate dielectric layer 110 in each region can be formed by different processes, such that the gate dielectric layer 110 can be made of different materials, and / or the gate electrode 112 in each region can be formed by different processes, such that the gate electrode 112 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0065] exist Figures 22A to 22D In this configuration, a gate mask 114 is formed on a gate stack (including a gate dielectric layer 110 and a corresponding gate electrode 112), and the gate mask may be disposed between opposing portions of the gate spacers 100. In some embodiments, forming the gate mask 114 includes recessing the gate stack to form a recess directly above the gate stack and between opposing portions of the gate spacers 100. The gate mask 114, comprising one or more layers of dielectric material (e.g., nitride, silicon oxynitride, etc.), fills the recess, and then a planarization process is performed to remove excess dielectric material extending over the first ILD 106. The gate mask 114 is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain flush with the top surface of the first ILD 106.

[0066] For example Figures 22A to 22D As shown, the second ILD 116 is deposited on top of the first ILD 106. In some embodiments, the second ILD 116 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 116 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and can be deposited by any suitable method such as CVD and PECVD. The gate contact 118 is subsequently formed (see below). Figures 23A to 23D It penetrates the second ILD 116 and the gate mask 114 (if present) to contact the top surface of the recessed gate electrode 112.

[0067] exist Figures 23A to 23DIn some embodiments, a gate contact 118 and a source / drain contact 120 are formed in the p-type region 50P through a second ILD 116 and a first ILD 106. An opening for the source / drain contact 120 is formed through the first ILD 106 and the second ILD 116, and an opening for the gate contact 118 is formed through the second ILD 116 and a gate mask 114 (if present). Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown), such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 116. The remaining liner and conductive material form the source / drain contact 120 and the gate contact 118 in the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 102 and the source / drain contact 120. The source / drain contact 120 is physically and electrically coupled to the epitaxial source / drain region 102, and the gate contact 118 is physically and electrically coupled to the gate electrode 112. The source / drain contact 120 and the gate contact 118 can be formed using different processes or the same process. Although each of the source / drain contact 120 and the gate contact 118 is shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 120 and the gate contact 118 can be formed in different cross-sections, which avoids short circuits in the contacts.

[0068] Figures 24A to 24D The diagram shows a gate contact 118 and a source / drain contact 120 formed through a second ILD 116 and a first ILD 106 in an n-type region 50N, according to some embodiments. Figures 24A to 24D The structure shown can be derived from Figure 11A and Figure 11B The structure shown is formed in the n-type region 50N using a similar method to that used to form the structure in the p-type region 50P (as per [reference]). Figures 12A-23D (As described).

[0069] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, all-gate-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning alternating stacks of channel and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to the embodiments described above. After the dummy gate stack is removed, the sacrificial layer may be partially or completely removed in the channel region. Replacement gate structures are formed in a manner similar to the embodiments described above, and the replacement gate structures may partially or completely fill the openings left by removing the sacrificial layer, and may partially or completely surround the channel layer in the channel region of the NSFET device. ILDs and contacts to the replacement gate structures and source / drain regions can be formed in a manner similar to the embodiments described above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0070] The embodiments offer advantages. A dielectric layer, including a mask layer, is formed on the semiconductor fin before forming the dummy gate. The mask layer allows for the formation of a dielectric material with a greater thickness on the top surface of the fin than on the sidewalls. This greater thickness of the dielectric layer on the top surface of the fin can improve device performance during subsequent patterning processes for the dummy gate. Because the process for forming the dielectric layer can be integrated with and followed by a standard oxide deposition process, the process for forming the dielectric layer is low-cost and can achieve high wafer rates per hour.

[0071] According to an embodiment, a method of forming a semiconductor device includes: forming a semiconductor fin and an isolation region adjacent to the semiconductor fin; forming a first layer on the semiconductor fin; forming a mask on the first layer, the mask being thicker at the top of the semiconductor fin than along the sidewalls of the semiconductor fin; thinning the first layer along the sidewalls of the semiconductor fin using the mask, the thinning of the first layer removing a portion of the mask; forming a second layer on the semiconductor fin, the second layer covering the remaining portion of the mask and the remaining portion of the first layer; forming a dummy gate layer on the semiconductor fin; and patterning the dummy gate layer, wherein the patterning of the dummy gate layer exposes the top surface of the semiconductor fin. In an embodiment, forming the first layer includes: forming the first layer on the isolation region, wherein thinning the first layer removes a first portion of the first layer on the isolation region, and wherein thinning the first layer also removes a second portion of the first layer on the sidewalls of the semiconductor fin. In an embodiment, before thinning the first layer, the mask has been prepared in… arrive The first thickness within the range. In an embodiment, after thinning the first layer, the mask has... arrive A second thickness within the range. In an embodiment, the second layer is formed with a thickness of... arrive Within the range. In an embodiment, after the second layer is formed, the first layer, the mask, and the second layer have [a certain range]. arrive The combined thickness is within a certain range. In an embodiment, after forming the second layer, the ratio of the combined thickness of the first layer, mask, and second layer to the thickness of the second layer is in the range of 2:1 to 5:1. In an embodiment, the dummy gate layer is patterned to etch the upper portion of the semiconductor fin to a distance of less than 2 nm. In an embodiment, forming the first layer includes performing plasma-enhanced atomic layer deposition of silicon oxide. In an embodiment, the method further includes performing O2 plasma treatment on the first layer.

[0072] According to another embodiment, a method of forming a semiconductor device includes: depositing a first dielectric layer on a first semiconductor fin and a second semiconductor fin using plasma-enhanced atomic layer deposition (PEALD), wherein the first semiconductor fin is in a first region of a die and the second semiconductor fin is in a second region of a die; forming a mask layer on the first dielectric layer, wherein the mask layer covers the top surface of a portion of the first dielectric layer on the first and second semiconductor fins, and the thickness of the mask layer tapers along the upper portion of a sidewall of the first dielectric layer; removing an exposed portion of the first dielectric layer; depositing a second dielectric layer on the mask layer and the remaining portion of the first dielectric layer on the first and second semiconductor fins; removing a first portion of the second dielectric layer, a first portion of the mask layer, and a first portion of the first dielectric layer on the first semiconductor fins, wherein a second portion of the first dielectric layer, a second portion of the mask layer, and a second portion of the second dielectric layer remain on the second semiconductor fins; and forming a first gate electrode on the first semiconductor fins and a second gate electrode on the second portion of the second dielectric layer. In an embodiment, forming the mask layer includes using bis(diethylamino)silane (BDEAS) or SiH3-N(CH-(CH3)2)2 as a precursor. In an embodiment, forming the mask layer includes atomic layer deposition using plasma generation power in the range of 15W to 150W. In an embodiment, forming the mask layer is performed at a pressure in the range of 1500 torr to 3500 torr. In an embodiment, forming the mask layer includes a purge time in the range of 0.5s to 0.25s. In an embodiment, forming the mask layer includes a plasma treatment time in the range of 0.5s to 0.25s.

[0073] According to another embodiment, a semiconductor device includes: a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being in a first region of a die and the second semiconductor fin being in a second region of the die; a first gate dielectric on the first semiconductor fin, the first gate dielectric substantially contacting the top surface of the first semiconductor fin; a first dielectric layer on the second semiconductor fin; a second dielectric layer on the first dielectric layer, the second dielectric layer comprising carbon; a third dielectric layer on the second dielectric layer; a second gate dielectric on the third dielectric layer; a first gate electrode on the first gate dielectric; and a second gate electrode on the second gate dielectric. In an embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer have a dielectric material on the top surface of the second semiconductor fin. arrive The combined thickness is within the range. In an embodiment, the third dielectric layer has a thickness within the range of the second semiconductor fin's sidewall. arrive The thickness is within the specified range. In an embodiment, the second dielectric layer is silicon nitride, silicon carbonitride, or silicon carbonitride.

[0074] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0075] Example 1 is a method of forming a semiconductor device, the method comprising: forming a semiconductor fin and an isolation region adjacent to the semiconductor fin; forming a first layer on the semiconductor fin; forming a mask on the first layer, the mask being thicker at the top of the semiconductor fin than along the sidewalls of the semiconductor fin; thinning the first layer along the sidewalls of the semiconductor fin using the mask, the thinning of the first layer removing a portion of the mask; forming a second layer on the semiconductor fin, the second layer covering the remaining portion of the mask and the remaining portion of the first layer; forming a dummy gate layer on the semiconductor fin; and patterning the dummy gate layer, wherein the patterning of the dummy gate layer exposes the top surface of the semiconductor fin.

[0076] Example 2 is the method of Example 1, wherein forming the first layer includes: forming the first layer on the isolation region, wherein thinning the first layer removes a first portion of the first layer on the isolation region, and wherein thinning the first layer further removes a second portion of the first layer on the sidewall of the semiconductor fin.

[0077] Example 3 is the method described in Example 1, wherein, before thinning the first layer, the mask has in arrive The first thickness within the range.

[0078] Example 4 is the method described in Example 1, wherein, after thinning the first layer, the mask has in arrive The second thickness within the range.

[0079] Example 5 is the method described in Example 1, wherein the second layer is formed to have a thickness of arrive Within the range.

[0080] Example 6 is the method described in Example 1, wherein, after the second layer is formed, the first layer, the mask, and the second layer have in arrive The combined thickness within the range.

[0081] Example 7 is the method described in Example 1, wherein, after the second layer is formed, the ratio of the combined thickness of the first layer, the mask, and the second layer to the thickness of the second layer is in the range of 2:1 to 5:1.

[0082] Example 8 is the method described in Example 1, wherein the dummy gate layer is patterned to etch the upper part of the semiconductor fin at a distance of less than 2 nm.

[0083] Example 9 is the method of Example 1, wherein forming the first layer includes performing plasma-enhanced atomic layer deposition of silicon oxide.

[0084] Example 10 is the method of Example 1, further comprising: performing O2 plasma treatment on the first layer.

[0085] Example 11 is a method of forming a semiconductor device, the method comprising: depositing a first dielectric layer over a first semiconductor fin and a second semiconductor fin using plasma-enhanced atomic layer deposition, wherein the first semiconductor fin is in a first region of a die and the second semiconductor fin is in a second region of the die; forming a mask layer over the first dielectric layer, wherein the mask layer covers the top surface of a portion of the first dielectric layer over the first and second semiconductor fins, the thickness of the mask layer tapering along the upper portion of a sidewall of the first dielectric layer; removing an exposed portion of the first dielectric layer; depositing a second dielectric layer over the mask layer and the remaining portion of the first dielectric layer over the first and second semiconductor fins; removing a first portion of the second dielectric layer, a first portion of the mask layer, and a first portion of the first dielectric layer over the first semiconductor fin, wherein a second portion of the first dielectric layer, a second portion of the mask layer, and a second portion of the second dielectric layer remain on the second semiconductor fin; and forming a first gate electrode over the first semiconductor fin and a second gate electrode over a second portion of the second dielectric layer.

[0086] Example 12 is the method described in Example 11, wherein forming the mask layer includes using bis(diethylamino)silane (BDEAS) or SiH3-N(CH-(CH3)2)2 as a precursor.

[0087] Example 13 is the method of Example 11, wherein forming the mask layer includes: atomic layer deposition using plasma generation power in the range of 15W to 150W.

[0088] Example 14 is the method described in Example 11, wherein the formation of the mask layer is performed under a pressure in the range of 1500 torr to 3500 torr.

[0089] Example 15 is the method of Example 11, wherein forming the mask layer includes a purge time in the range of 0.5 s to 0.25 s.

[0090] Example 16 is the method of Example 11, wherein forming the mask layer includes a plasma processing time in the range of 0.5 s to 0.25 s.

[0091] Example 17 is a semiconductor device comprising: a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being in a first region of a die and the second semiconductor fin being in a second region of the die; a first gate dielectric on the first semiconductor fin, the first gate dielectric body contacting a top surface of the first semiconductor fin; a first dielectric layer on the second semiconductor fin; a second dielectric layer on the first dielectric layer, the second dielectric layer comprising carbon; a third dielectric layer on the second dielectric layer; a second gate dielectric on the third dielectric layer; a first gate electrode on the first gate dielectric; and a second gate electrode on the second gate dielectric.

[0092] Example 18 is the semiconductor device described in Example 17, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer have a dielectric layer on the top surface of the second semiconductor fin. arrive The combined thickness within the range.

[0093] Example 19 is the semiconductor device described in Example 17, wherein the third dielectric layer has a [missing information - likely referring to a specific feature or characteristic] on the sidewall of the second semiconductor fin. arrive The thickness is within the range.

[0094] Example 20 is the semiconductor device described in Example 17, wherein the second dielectric layer is silicon nitride, silicon carbonitride, or silicon carbonitride.

Claims

1. A method for forming a semiconductor device, the method comprising: Forming a semiconductor fin and an isolation region adjacent to the semiconductor fin; A first layer is formed on the semiconductor fin; A mask is formed on the first layer, the mask being thicker on top of the semiconductor fin than along the sidewalls of the semiconductor fin; The first layer is thinned along the sidewall of the semiconductor fin using the mask, and the thinning of the first layer removes a portion of the mask; A second layer is formed on the semiconductor fin, the second layer covering the remainder of the mask and the remainder of the first layer; A dummy gate layer is formed on the semiconductor fin; as well as The dummy gate layer is patterned, wherein the patterning of the dummy gate layer exposes the top surface of the semiconductor fin.

2. The method according to claim 1, wherein, Forming the first layer includes: forming the first layer on the isolation region, wherein thinning the first layer removes a first portion of the first layer on the isolation region, and wherein thinning the first layer also removes a second portion of the first layer on the sidewall of the semiconductor fin.

3. The method according to claim 1, wherein, Before thinning the first layer, the mask has a first thickness in the range of 5 Å to 10 Å.

4. The method according to claim 1, wherein, After thinning the first layer, the mask has a second thickness in the range of 2 Å to 5 Å.

5. The method according to claim 1, wherein, The second layer is formed to have a thickness in the range of 15 Å to 35 Å.

6. The method according to claim 1, wherein, After the second layer is formed, the first layer, the mask, and the second layer have a combined thickness in the range of 45 Å to 65 Å.

7. The method according to claim 1, wherein, After the second layer is formed, the ratio of the combined thickness of the first layer, the mask, and the second layer to the thickness of the second layer is in the range of 2:1 to 5:

1.

8. The method according to claim 1, wherein, The dummy gate layer is patterned to etch the upper part of the semiconductor fin at a distance of less than 2 nm.

9. The method according to claim 1, wherein, Forming the first layer includes performing plasma-enhanced atomic layer deposition of silicon oxide.

10. The method according to claim 1, further comprising: O2 plasma treatment is performed on the first layer.

11. A method of forming a semiconductor device, the method comprising: A first dielectric layer is deposited on a first semiconductor fin and a second semiconductor fin using plasma-enhanced atomic layer deposition, wherein the first semiconductor fin is in a first region of the die and the second semiconductor fin is in a second region of the die; A mask layer is formed on the first dielectric layer, wherein the mask layer covers the top surface of the portion of the first dielectric layer above the first semiconductor fin and the second semiconductor fin, and the thickness of the mask layer tapers along the upper part of the sidewall of the first dielectric layer; Remove the exposed portion of the first dielectric layer; A second dielectric layer is deposited over the mask layer and the remaining portion of the first dielectric layer over the first semiconductor fin and the second semiconductor fin; Remove a first portion of the second dielectric layer, a first portion of the mask layer, and a first portion of the first dielectric layer on the first semiconductor fin, wherein a second portion of the first dielectric layer, a second portion of the mask layer, and a second portion of the second dielectric layer remain on the second semiconductor fin; and A first gate electrode is formed on the first semiconductor fin, and a second gate electrode is formed on a second portion of the second dielectric layer.

12. The method according to claim 11, wherein, Forming the mask layer includes using bis(diethylamino)silane (BDEAS) or SiH3-N(CH-(CH3)2)2 as a precursor.

13. The method according to claim 11, wherein, Forming the mask layer includes atomic layer deposition using plasma generation power in the range of 15 W to 150 W.

14. The method according to claim 11, wherein, The formation of the mask layer is performed under pressure ranging from 1500 torr to 3500 torr.

15. The method according to claim 11, wherein, The formation of the mask layer includes a purging time in the range of 0.5 s to 0.25 s.

16. The method according to claim 11, wherein, The formation of the mask layer includes a plasma processing time in the range of 0.5 s to 0.25 s.

17. A semiconductor device, comprising: A first semiconductor fin and a second semiconductor fin, wherein the first semiconductor fin is in a first region of the die and the second semiconductor fin is in a second region of the die; A first gate dielectric on the first semiconductor fin, the first gate dielectric physically contacting the top surface of the first semiconductor fin; A first dielectric layer on the second semiconductor fin; A second dielectric layer on the first dielectric layer, the second dielectric layer comprising carbon; A third dielectric layer on the second dielectric layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer have a combined thickness in the range of 45 Å to 65 Å above the top surface of the second semiconductor fin, and wherein the third dielectric layer directly covers the sidewall of the second semiconductor fin and has a thickness in the range of 15 Å to 35 Å on the sidewall of the second semiconductor fin; The second gate dielectric on the third dielectric layer; The first gate electrode on the first gate dielectric; and The second gate electrode on the second gate dielectric The first dielectric layer, the second dielectric layer, and the third dielectric layer are formed before the dummy gate is formed on the second semiconductor fin.

18. The semiconductor device according to claim 17, wherein, The second dielectric layer is silicon carbonitride or silicon carbonitride.

19. The semiconductor device according to claim 17, wherein, The ratio of the combined thickness to the thickness of the third dielectric layer is in the range of 2:1 to 5:1.

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