Memory device including control gate having tungsten structure

Abstract

The present disclosure relates to memory devices including control gates having tungsten structures. Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separate from the first dielectric material; a string of memory cells including a pillar extending through the first dielectric material and the second dielectric material, the pillar including a portion between the first dielectric material and the second dielectric material; an additional dielectric material contacting the portion of the pillar; a conductive material contacting the additional dielectric material; and a tungsten structure including a tungsten portion contacting the conductive material, wherein a majority of the tungsten portion is beta-phase tungsten.

Description

Technical Field

[0001] The embodiments described herein relate to memory devices with a structure including a control gate for the memory device. Background Technology

[0002] Memory devices are widely used in computers and many other electronic projects. Memory devices typically have a large number of memory cells for storing information (e.g., data) and control gates for controlling access to the memory cells during operation of the memory device. The resistance of the control gates can affect some aspects of the memory device's operation. The resistance of the control gates can be based on the structure of the control gates. In some conventional memory devices, constructing the control gates to achieve a balance or optimal combination of device operation and control gate resistance can present challenges. Summary of the Invention

[0003] This disclosure relates to an apparatus comprising: a first dielectric material; a second dielectric material separate from the first dielectric material; a memory cell string including posts extending through the first dielectric material and the second dielectric material, the posts including portions between the first dielectric material and the second dielectric material; an additional dielectric material contacting the portions of the posts; a conductive material contacting the additional dielectric material; and a tungsten structure including a tungsten portion contacting the conductive material, wherein a majority of the tungsten portion is β-phase tungsten.

[0004] Another aspect of this disclosure relates to an apparatus comprising: a first dielectric material; a second dielectric material separate from the first dielectric material; a memory cell string including posts extending through the first dielectric material and the second dielectric material, the posts including additional dielectric material between the first dielectric material and the second dielectric material; a conductive material contacting the additional dielectric material; and a tungsten structure including a tungsten portion contacting the conductive material, wherein a majority of the tungsten portion is β-phase tungsten.

[0005] Another aspect of this disclosure relates to an apparatus comprising: a first dielectric material; a second dielectric material separate from the first dielectric material; a memory cell string including posts extending through the first dielectric material and the second dielectric material, the posts including portions between the first dielectric material and the second dielectric material; an additional dielectric material contacting the portions of the posts, the additional dielectric material having a dielectric constant greater than that of silicon dioxide; a conductive material contacting the additional dielectric material, the conductive material containing titanium; and a tungsten structure including a tungsten portion contacting the conductive material, wherein a majority of the tungsten portion is β-phase tungsten.

[0006] Another aspect of this disclosure relates to an apparatus comprising: a control gate of a memory cell string, the control gate being interleaved with a dielectric material, the control gate comprising a control gate located between a first dielectric material and a second dielectric material of the dielectric material; a post of the memory cell string extending through the control gate and the dielectric material, the post comprising a portion between the first dielectric material and the second dielectric material; an additional dielectric material formed on the portion of the post, the first dielectric material, and the second dielectric material of the dielectric material, the dielectric constant of the additional dielectric material being at least equal to the dielectric constant of aluminum oxide; a conductive material formed on the additional dielectric material, the conductive material comprising titanium; and a tungsten structure comprising a tungsten portion contacting the conductive material, wherein a majority of the tungsten portion is β-phase tungsten.

[0007] Another aspect of this disclosure relates to a method comprising: forming a first dielectric material interleaved with a second dielectric material; forming a memory cell string including posts formed through the first dielectric material and the second dielectric material; removing a portion of the first dielectric material from a location occupied by the first dielectric material to expose a portion of the posts at one of the locations; forming an additional dielectric material on the portion of the posts; forming a conductive material on the additional dielectric material; and forming a tungsten structure such that the tungsten structure includes a portion of tungsten in contact with the conductive material, wherein a majority of the portion of tungsten is β-phase tungsten.

[0008] Another aspect of this disclosure relates to a method comprising: forming a first dielectric material interleaved with a second dielectric material; forming a memory cell string including posts formed through the first dielectric material and the second dielectric material; removing a portion of the first dielectric material from a location occupied by the first dielectric material to expose a portion of the posts at one of the locations; forming an additional dielectric material on the portion of the posts, the additional dielectric material having a dielectric constant at least equal to that of aluminum oxide; forming a conductive material on the additional dielectric material; forming a silicon material on the conductive material; converting the silicon material into an initial tungsten material; and forming an additional tungsten material on the initial tungsten material. Attached Figure Description

[0009] Figure 1 A block diagram of a device in the form of a memory device according to some embodiments described herein is shown.

[0010] Figure 2 This diagram shows a general schematic representation of a portion of a memory device comprising a memory array having a string of memory cells and associated selection circuitry, according to some embodiments described herein.

[0011] Figure 3 Some embodiments according to the description herein are shown. Figure 2 A detailed schematic diagram of the memory device.

[0012] Figure 4A This illustration shows a memory cell string comprising posts having control gates extending through two blocks of memory cells, and a dielectric structure between the two blocks, according to some embodiments described herein. Figure 3 A side view (e.g., cross-section) of the structure of a portion of a memory device.

[0013] Figure 4B Some embodiments according to the description herein are shown. Figure 4A A cross-section (e.g., top view) of a portion of the guide pillars and a portion of the control gate of the memory device.

[0014] Figure 4C The relative positions of the blocks, dielectric structure, post links of the memory cell string, and data lines of the memory device are shown according to some embodiments described herein. Figure 4A A top view of a portion of the memory device.

[0015] Figure 5 A block BLK0 comprising a memory array, a step region, a dielectric structure, and a memory device is shown according to some embodiments described herein. Figure 4A A top view of the memory device.

[0016] Figure 6A and Figures 6B to 17A and Figure 17B Different views of elements during the process of forming a memory device are shown according to some embodiments described herein. Detailed Implementation

[0017] The technology described herein relates to control gates of memory devices. Control gates can be used to control access to corresponding memory cells in a string of memory cells to the memory device. Each of the control gates may contain a tungsten structure. The tungsten structure may have relatively low resistance to improve the operation of the memory device. References are provided below. Figures 1 to 16B This paper further discusses the improvements and benefits of the technology described in this paper.

[0018] Figure 1A block diagram of a device in the form of a memory device 100 according to some embodiments described herein is shown. The memory device 100 may include a memory array (or multiple memory arrays) 101 containing memory cells 102 arranged in blocks (blocks of memory cells), such as blocks BLK0 and BLK1. Each of blocks BLK0 and BLK1 may contain its own sub-blocks, such as sub-blocks SB0 and SB1. In the physical structure of the memory device 100, the memory cells 102 may be arranged vertically (e.g., above each other) above a substrate (e.g., a semiconductor substrate) of the memory device 100. Figure 1 A memory device 100 is shown as an example, having two blocks BLK0 and BLK1, and two sub-blocks in each of the blocks. The memory device 100 may have more than two blocks and more than two sub-blocks in each of the blocks.

[0019] like Figure 1 As shown, memory device 100 may include access lines (which may include word lines) 150 and data lines (which may include bit lines) 170. Access lines 150 may carry signals (e.g., word line signals) WL0 to WLm. Data lines 170 may carry signals (e.g., bit line signals) BL0 to BLn. Memory device 100 may use access lines 150 to selectively access memory cells 102 of blocks BLK0 and BLK1, and may use data lines 170 to selectively exchange information (e.g., data) with memory cells 102 of blocks BLK0 and BLK1. Block BLK0 may have access lines (e.g., word lines) that are electrically separate from the access lines (e.g., word lines) of block BLK1. Sub-blocks of the same block may share access lines (e.g., may share word lines) and may be controlled by the same access lines. For example, sub-blocks SB0 and SB1 of block BLK0 may share a group of access lines associated with block BLK0, and sub-blocks SB0 and SB1 of block BLK1 may share another group of access lines associated with block BLK1.

[0020] Memory device 100 may include an address register 107 to receive address information (e.g., address signals) ADDR on lines (e.g., address lines) 103. Memory device 100 may include row access circuitry 108 and column access circuitry 109 capable of decoding the address information from address register 107. Based on the decoded address information, memory device 100 may determine which memory cells 102 of which sub-blocks of blocks BLK0 and BLK1 will be accessed during memory operations. Memory device 100 may perform read operations to read (e.g., sense) information (e.g., previously stored information) from memory cells 102 of blocks BLK0 and BLK1, or perform write (e.g., programming) operations to store (e.g., program) information in memory cells 102 of blocks BLK0 and BLK1. Memory device 100 may use data lines 170 associated with signals BL0 to BLn to provide information to be stored in memory cells 102 or to obtain information read (e.g., sensed) from memory cells 102. The memory device 100 can also perform an erase operation to erase some or all of the information from the memory cells 102 of blocks BLK0 and BLK1.

[0021] Memory device 100 may include a control unit 118 configured to control memory operations of memory device 100 based on control signals on line 104. Examples of control signals on line 104 include one or more clock signals and other signals (e.g., chip enable signal CE#, write enable signal WE#) to indicate which operation (e.g., read, write, or erase) memory device 100 may perform. Other devices external to memory device 100 (e.g., memory controller or processor) may control the values ​​of the control signals on line 104. Specific values ​​of combinations of signals on line 104 may generate commands (e.g., read, write, or erase commands) that cause memory device 100 to perform corresponding memory operations (e.g., read, write, or erase operations).

[0022] Memory device 100 may include a sensing and buffering circuitry system 120, which may include components such as a sense amplifier and page buffer circuitry (e.g., a data latch). The sensing and buffering circuitry system 120 may respond to signals BL_SEL0 to BL_SELn from column access circuitry 109. The sensing and buffering circuitry system 120 may be configured to determine (e.g., by sensing) the value of information read from memory cells 102 of blocks BLK0 and BLK1 (e.g., during a read operation) and provide the value of the information to line (e.g., a global data line) 175. The sensing and buffering circuitry system 120 may also be configured to use signals on line 175 to determine the value of information to be stored (e.g., programmed) in memory cells 102 of blocks BLK0 and BLK1 (e.g., during a write operation) based on the value of the signals on line 175 (e.g., voltage values) (e.g., during a write operation).

[0023] Memory device 100 may include an input / output (I / O) circuitry 117 to exchange information between memory cells 102 of blocks BLK0 and BLK1 and lines (e.g., I / O lines) 105. Signals DQ0 to DQN on line 105 may represent information read from or stored in memory cells 102 of blocks BLK0 and BLK1. Line 105 may contain nodes within memory device 100 or pins (or solder balls) that may reside on the package of memory device 100. Other devices outside memory device 100 (e.g., memory controllers or processors) may communicate with memory device 100 via lines 103, 104, and 105.

[0024] The memory device 100 may receive a supply voltage, including a supply voltage Vcc and a supply voltage Vss. The supply voltage Vss may operate at ground potential (e.g., having a value of approximately zero volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an AC-DC converter circuit.

[0025] Each of the memory cells 102 is programmable to store information representing the value of at most one bit (e.g., a single bit) or the value of multiple bits, such as two, three, four, or another number of bits. For example, each of the memory cells 102 is programmable to store information representing the binary value "0" or "1" of a single bit. A single bit / cell is sometimes referred to as a single-level cell. In another instance, each of the memory cells 102 is programmable to store information representing the value of multiple bits, such as one of the four possible values ​​of two bits "00", "01", "10", and "11", one of the eight possible values ​​of three bits "000", "001", "010", "011", "100", "101", "110", and "111", or one of other values ​​of another number of multiple bits (e.g., more than three bits per memory cell). A cell with the ability to store multiple bits is sometimes referred to as a multi-level cell (or multi-state cell).

[0026] Memory device 100 may include a non-volatile memory device, and memory cell 102 may include a non-volatile memory cell, such that memory cell 102 can retain information stored thereon when power supply (e.g., voltage Vcc, Vss, or both) is disconnected from memory device 100. For example, memory device 100 may be a flash memory device, such as NAND flash memory (e.g., 3D NAND), or a NOR flash memory device, or another memory device, such as a variable resistance memory device (e.g., a phase-change memory device or a resistive random access memory (RAM) device).

[0027] Those skilled in the art will recognize that the memory device 100 may include other components, some of which are not included in the present invention. Figure 1 The examples and embodiments described herein are shown in the figures to avoid confusion. At least a portion of the memory device 100 may include a structure and be configured as described below. Figures 2 to 16B The structure and operation of any of the described memory devices are similar or identical.

[0028] Figure 2 This diagram shows a general schematic representation of a portion of a memory device 200 comprising a memory array 201 having memory cell strings and associated selection circuitry, according to some embodiments described herein. The memory device 200 may correspond to... Figure 1 The memory device 100. For example, the memory array 201 may be formed. Figure 1 Part of the memory array 101.

[0029] like Figure 2As shown, memory device 200 may include blocks (blocks of memory cells) BLK0 and BLK1. The two boxes are shown as examples. Memory device 200 may include a number of blocks (e.g., up to thousands or more). In the physical structure of memory device 200, one block may be arranged (e.g., formed) adjacent to another block, such that each block may have neighboring blocks. Adjacent blocks are blocks positioned adjacent to (e.g., neighboring) each other. For example, in the physical structure of memory device 200, blocks BLK0 and BLK1 may be adjacent blocks.

[0030] Each of blocks BLK0 and BLK1 in memory device 200 may contain (e.g., may be divided into) sub-blocks. For example, each of blocks BLK0 and BLK1 may contain sub-blocks SB0 and SB1. Blocks BLK0 and BLK1 may contain the same number of sub-blocks. Figure 2 The diagram shows an instance where each of blocks BLK0 and BLK1 may contain two sub-blocks (e.g., SB0 and SB1). However, each of blocks BLK0 and BLK1 may have more than two blocks (e.g., four sub-blocks SB0, SB1, SB2, and SB3 or more than four sub-blocks).

[0031] like Figure 2 As shown, each sub-block (e.g., SB0 or ​​SB1) has its own memory cell string, and each of the memory cell strings can be associated with (e.g., coupled to) a corresponding selection circuit. For example, sub-block SB0 of block BLK0 has memory cell strings 231a, 232a, and 233a and corresponding associated selection circuits (e.g., drain selection circuits) 241a, 242a, and 243a, as well as corresponding selection circuits (e.g., source selection circuits) 241'a, 242'a, and 243'a. In another example, sub-block SB1 of block BLK0 has memory cell strings 234a, 235a, and 236a and corresponding associated selection circuits (e.g., drain selection circuits) 244a, 245a, and 246a, as well as corresponding selection circuits (e.g., source selection circuits) 244'a, 245'a, and 246'a.

[0032] Similarly, sub-block SB0 of block BLK1 has memory cell strings 231b, 232b, and 233b and corresponding associated selection circuits (e.g., drain selection circuits) 241b, 242b, and 243b, as well as corresponding selection circuits (e.g., source selection circuits) 241'b, 242'b, and 243'b. Sub-block SB1 of block BLK1 has memory cell strings 234b, 235b, and 236b and corresponding associated selection circuits (e.g., drain selection circuits) 244b, 245b, and 246b, as well as corresponding selection circuits (e.g., source selection circuits) 244'b, 245'b, and 246'b. Sub-blocks of blocks (e.g., blocks BLK0 and BLK1) of memory device 200 may have the same number of memory cell strings and associated selection circuits.

[0033] Figure 2 An example of three memory cell strings and their associated circuitry in a sub-block (e.g., sub-block SB0) is shown. The number of memory cell strings and their associated selection circuitry in each sub-block of blocks BLK0 and BLK1 can vary. Each memory cell string in memory device 200 may contain memory cells connected in series (in... Figure 3 and Figure 4A (as shown in the details) and guide posts (e.g., Figure 4A (The guide post 450 in the middle), wherein the serially connected memory cells can be positioned along the corresponding portion of the guide post (e.g., vertically positioned).

[0034] like Figure 2 As shown, the memory device 200 may include corresponding carrier signals BL0 to BL1. N Data cable 2700 to 270 N Data cable 2700 to 270 N Each of them can be configured as a conductive line that may contain conductive material (e.g., conductive doped polysilicon, metal or other conductive material).

[0035] The memory cell strings of blocks BLK0 and BLK1 can share data lines 2700 to 270. NInformation (in signal form) carried in a memory cell of the memory device 200 (e.g., a selected memory cell in block BLK0 or BLK1) is read from or to be stored therein. For example, memory cell strings 231a and 234a (of block BLK0), and 231b and 234b (of block BLK1) may share data line 2700. Memory cell strings 232a and 235a (of block BLK0), and 232b and 235b (of block BLK1) may share data line 2701. Memory cell strings 233a and 236a (of block BLK0), and 233b and 236b (of block BLK1) may share data line 2702.

[0036] Memory device 200 may include a source (e.g., source line, source plate, or source region) 290 that can carry a signal (e.g., a source line signal) SRC. Source 290 may be configured as a conductive line or conductive plate (e.g., a conductive region) of memory device 200. Source 290 may be a common source (e.g., a common source plate or common source region) of blocks BLK0 and BLK1. Alternatively, each of blocks BLK0 and BLK1 may have its own source similar to source 290. Source 290 may be coupled to a ground connection of memory device 200.

[0037] Memory device 200 may include control gates (e.g., word lines) 2200, 2210, 2220, and 2230 in block BLK0, which may be portions of conductive paths (e.g., access lines) 2560 of memory device 200 (which may correspond to...). Figure 1 The memory device 200 may include control gates (e.g., word lines) 2201, 2211, 2221, and 2231 in block BLK1, which may be portions of other conductive paths (e.g., access lines) 2561 of the memory device 200 (which may correspond to...). Figure 1 (A portion of the access line 150 of the memory device 100). Control gates 2200, 2210, 2220, and 2230 are electrically decoupled from each other. Control gates 2201, 2211, 2221, and 2231 are electrically decoupled from each other. Control gates 2200, 2210, 2220, and 2230 are electrically decoupled from control gates 2201, 2211, 2221, and 2231. Therefore, blocks BLK0 and BLK1 can be accessed individually (e.g., one at a time). For example, block BLK0 can be accessed simultaneously using control gates 2200, 2210, 2220, and 2230, and block BLK1 can be accessed at another time using control gates 2201, 2211, 2221, and 2231.

[0038] The memory device 200 may have the same number of control gates in blocks of the memory device 200 (e.g., blocks BLK0 and BLK1). Figure 2 In one example, memory device 200 has four control gates in each of blocks BLK0 and BLK1. Figure 2 A memory device 200 comprising four control gates in blocks BLK0 and BLK1 is shown as an example. The number of control gates in blocks (e.g., blocks BLK0 and BLK1) of the memory device 200 may be different from four. For example, each of blocks BLK0 and BLK1 may contain hundreds of control gates.

[0039] Each of the control gates 2200, 2210, 2220, and 2230 may be a portion of a structure (e.g., a layer) of conductive material located in a layer of the memory device 200. The control gates 2200, 2210, 2220, and 2230 may carry corresponding signals (e.g., word line signals) WL00, WL10, WL20, and WL30. The memory device 200 may use signals WL00, WL10, WL20, and WL30 to selectively control access to memory cells of block BLK0 during operations (e.g., read, write, or erase operations). For example, during a read operation, the memory device 200 may use signals WL00, WL10, WL20, and WL30 to control access to selected memory cells of block BLK0 to read (e.g., sense) information (e.g., previously stored information) from the memory cells of block BLK0. In another instance, during a write operation, the memory device 200 may use signals WL00, WL10, WL20 and WL30 to control access to selected memory cells of block BLK0 to store information in the selected memory cells of block BLK0.

[0040] Each of the control gates 2201, 2211, 2221, and 2231 may be a portion of a structure (e.g., a layer) of conductive material located in a layer of the memory device 200. The control gates 2201, 2211, 2221, and 2231 may carry corresponding signals (e.g., word line signals) WL01, WL11, WL21, and WL31. The memory device 200 may use the signals WL01, WL11, WL21, and WL31 to selectively control access to memory cells of block BLK1 during operations (e.g., read, write, or erase operations). For example, during a read operation, the memory device 200 may use the signals WL01, WL11, WL21, and WL31 to control access to selected memory cells of block BLK1 to read (e.g., sense) information (e.g., previously stored information) from the memory cells of block BLK1. In another instance, during a write operation, the memory device 200 may use signals WL01, WL11, WL21 and WL31 to control access to selected memory cells of block BLK1 to store information in the selected memory cells of block BLK1.

[0041] like Figure 2 As shown, in sub-block SB0 of block BLK0, memory device 200 includes a select line (e.g., a drain select line) 2800 that can be shared by select circuits 241a, 242a, and 243a. In sub-block SB1 of block BLK0, memory device 200 includes a select line (e.g., a drain select line) 2801 that can be shared by select circuits 244a, 245a, and 246a. Block BLK0 may include a select line (e.g., a source select line) 284 that can be shared by select circuits 241'a, 242'a, 243'a, 244'a, 245'a, and 246'a.

[0042] In sub-block SB0 of block BLK1, memory device 200 includes a select line (e.g., drain select line) 2800 that can be shared by select circuits 241b, 242b, and 243b. The select line 2800 of block BLK0 is electrically isolated from the select line 2800 of block BLK1. In sub-block SB1 of block BLK1, memory device 200 includes a select line (e.g., drain select line) 2801 that can be shared by select circuits 244b, 245b, and 246b. The select line 2801 of block BLK0 is electrically isolated from the select line 2801 of block BLK1. Block BLK1 may include a select line (e.g., source select line) 284 that can be shared by select circuits 241'b, 242'b, 243'b, 244'b, 245'b, and 246'b.

[0043] For simplicity, Figure 2The same markings are shown for select lines 2800 and 2801 in blocks BLK0 and BLK1. However, select lines 2800 and 2801 in block BLK0 are electrically disconnected from select lines 2800 and 2801 in block BLK1, respectively.

[0044] Figure 2 An example is shown in which the memory device 200 includes a single drain select line (e.g., select line 2800 or 2801) associated with a drain select circuit (e.g., select circuits 241a, 242a, or 243a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include multiple drain select lines associated with drain select circuits.

[0045] Figure 2 An example is shown in which the memory device 200 includes a source select line (e.g., select line 284) associated with a source select circuit (e.g., select circuits 241'a, 242'a, or 243'a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include more than one source select line associated with a source select circuit.

[0046] Each of the drain select circuits in memory device 200 may include a drain select gate (e.g., a transistor) coupled between a respective data line and a respective memory cell string. The drain select gate may be controlled (e.g., turned on or off) by the drain select line based on the voltage of a signal provided to the drain select line.

[0047] Each of the source selection circuits in memory device 200 may include a select gate coupled between source 290 and the corresponding memory cell string. Figure 3 (As shown). The source-select gate can be controlled by the source-select line (e.g., turned on or off) based on the voltage of the signal provided to the source-select line.

[0048] exist Figure 2 In the memory device 200, each of the memory cell strings has memory cells arranged in a string (e.g., coupled in series with each other). Figure 3 (As shown) to store information. During operation of the memory device 200 (e.g., read, write, or erase operation), the memory cell string can be individually selected to access memory cells in the selected memory cell string in order to store information in or read information from the selected memory cell string. One or two selection circuits (drain selection circuit and source selection circuit) associated with the selected memory cell string may be activated depending on which operation the memory device 200 performs on the selected memory cell string (e.g., by turning on the selection gate (e.g., transistor) in the selection circuit (or selection circuit)).

[0049] Activating a specific selection circuit within the selection circuitry of the memory device 200 during operation may include providing (e.g., applying) a voltage of a certain value to a selection line associated with the specific selection circuit. When a specific drain selection circuit of the memory device 200 is activated, it may electrically connect (e.g., form a current path from) selected memory cells associated with the specific selection circuit to the corresponding data lines (e.g., data lines 2700 to 2700). N (One of them). When a particular source selection circuit is activated, it can electrically connect (e.g., form a current path from) a selected memory cell associated with the particular selection circuit to the source 290.

[0050] Figure 3 Some embodiments according to the description herein are shown. Figure 2 A detailed schematic diagram of the memory device 200. For simplicity, in Figure 3 Only marked in Chinese Figure 2 Some of the memory cells in the memory device 200 and some of the selection circuitry. Figure 3 The directions X, Y, and Z in the diagram may be related to the physical orientation (e.g., dimension) of the structure of the memory device 200. For example, the Z direction may be perpendicular to the substrate of the memory device 200 (e.g., ...). Figure 4A The orientation of the substrate 499 shown (e.g., the vertical direction relative to the substrate). The Z direction is perpendicular to the X and Y directions (e.g., the Z direction is perpendicular to the XY plane of the memory device 200).

[0051] like Figure 3 As shown, each select line can carry an associated select signal. For example, in sub-block SB0 of block BLK0, select line (e.g., drain select line) 2800 can carry an associated signal (e.g., drain select gate signal) SGD00. In sub-block SB1 of block BLK0, select line (e.g., drain select line) 2801 can carry an associated signal SGD01. Sub-blocks SB0 and SB1 of block BLK0 can share select line 284 and the associated signal of block BLK0 (e.g., source select gate signal) SGS0.

[0052] In sub-block SB0 of block BLK1, the select line (e.g., drain select line) 2800 may carry the associated signal SGD00. In sub-block SB1 of block BLK1, the select line (e.g., drain select line) 2801 may carry the associated signal SGD01. Sub-blocks SB0 and SB1 of block BLK1 may share select line 284 and the associated signal of block BLK1 (e.g., source select-gate signal) SGS1.

[0053] like Figure 3As shown, the memory device 200 may include: memory cells 210, 211, 212, and 213; a select gate (e.g., a drain-select gate or a transistor) 260; and a select gate (e.g., a source-select gate) 264, which may be relative to the structure of the memory device 200. Figure 4A (As shown) are arranged in a three-dimensional (3D) form in, for example, the X, Y and Z directions (e.g., dimensions).

[0054] exist Figure 3 In the memory device 200, each of the memory cell strings (e.g., memory cell strings 231a, 232a, 233a, 234a, 231b and 234b) may contain one of memory cells 210, one of memory cells 211, one of memory cells 212 and one of memory cells 213. Figure 3 Examples of four memory cells 210, 211, 212, and 213 in each memory cell string are shown. The number of memory cells in each memory cell string can vary.

[0055] like Figure 3 As shown, each of the selection circuits (e.g., drain selection circuits) 241a, 242a, 243a, 244a, 241b and 244b may include a selection gate 260. Figure 3 An example is shown in which the memory device 200 includes one drain select gate (e.g., select gate 260) in each drain select circuit. However, the memory device 200 may include multiple drain select gates in each drain select circuit, depending on the number of drain select lines associated with each drain select circuit. The number of drain select gates in each drain select circuit may be equal to the number of drain select lines associated with each drain select circuit.

[0056] Each selection circuit (e.g., a source selection circuit) 241'a, 242'a, 243'a, 244'a, 241'b, and 244'b may include a selection gate 264. Figure 3 An example is shown in which the memory device 200 includes one source select gate (e.g., select gate 264) in each source select circuit. However, the memory device 200 may include multiple source select gates in each source select circuit, depending on the number of source select lines associated with each source select circuit. The number of source select gates in each source select circuit (e.g., Figure 3 One of the examples) can be equal to the number of source select lines associated with each source select circuit (e.g., Figure 3 (One of the examples).

[0057] Each of the gates 260 and 264 can operate as a transistor. For example, the gate 260 of the selection circuit 241a can operate as a field-effect transistor (FET), such as a metal-oxide-semiconductor FET (MOSFET). An example of this MOSFET includes an n-channel MOS (NMOS) transistor.

[0058] like Figure 3 As shown, the selection lines shared between specific selection circuits can be shared by the corresponding selection gates of those specific selection circuits. For example, the selection line 2800 of sub-block SB0 of block BLK0 can be shared by the selection gates 260 of selection circuits 241a, 242a, and 243a of sub-block SB0 of block BLK0. In another example, the selection line 284 of sub-block SB0 of block BLK0 can be shared by the selection gates 264 of selection circuits 241'a, 242'a, and 243'a of sub-block SB0 of block BLK0.

[0059] The select line (e.g., select line 2800 of sub-block SB0 of block BLK0) may carry a signal (e.g., signal SGD00), but it is not used as a switch (e.g., transistor). The select gate (e.g., select gate 260 of select circuit 241a of sub-block SB0 of block BLK0) may receive a signal (e.g., signal SGD00) from the corresponding select line (e.g., select line 2800 of sub-block SB0 of block BLK0) and may be used as a switch (e.g., transistor).

[0060] In the physical structure of memory device 200, the select line (e.g., select line 2800 of sub-block SB0 of block BLK0) may be a structure (e.g., a layer of conductive material) located in a single level of memory device 200. The conductive material may include metals, doped polysilicon, or other conductive materials.

[0061] In the physical structure of the memory device 200, the selection gate (e.g., the selection gate 260 of the selection circuit 241a of the sub-block SB0 of block BLK0) may include (or be formed by) the following: a portion of the conductive material of the corresponding selection line (e.g., the selection line 2800 of the sub-block SB0 of block BLK0), a portion of the channel material (e.g., a polysilicon channel), and a portion of the dielectric material (e.g., the gate oxide similar to that of a transistor (e.g., a FET)) between the portion of the conductive material and the portion of the channel material.

[0062] Figure 4AThe diagram illustrates control gates 2200, 2210, 2220, and 2230 for block BLK0, control gates 2201, 2211, 2221, and 2231 for block BLK1, post (memory cell post) 450 in the respective blocks BLK0 and BLK1, and dielectric structure 451 between blocks BLK0 and BLK1, according to some embodiments described herein. Figure 3 A side view (e.g., cross-section) of a portion of the structure of the memory device 200. Figure 4B and Figure 4C (The following text is in) Figure 4A (The following description shows more views of the memory device 200.) Figure 4B Show along Figure 4A The line 4B-4B cuts a cross-section of the control gate 2230 and a portion of the adjacent post 450 of the memory device 200. Figure 4C The diagram shows the relative positions of the blocks (e.g., blocks BLK0 and BLK1), dielectric structure 451, post 450, and data lines 2700, 2701, 2702, and 2703. Figure 4A A top view of the memory device 200. The following description refers to... Figure 4A .

[0063] Figure 4A The structure of the memory device 200 in the middle corresponds to Figure 3 This is a partial schematic diagram of the memory device 200 shown. For simplicity, from... Figure 4A The structure of part of the memory device 200 shown is omitted. Figure 3 Some components of the memory device 200.

[0064] For simplicity, cross-sectional lines (e.g., section lines) are omitted from some or all of the elements shown in the drawings described herein. Some elements of memory device 200 (and other memory devices described herein) may be omitted from specific drawings to avoid confusion with the view or description of the elements (or elements) being depicted in a particular drawing. Furthermore, the dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not scaled.

[0065] like Figure 4AAs shown, the memory device 200 may include a substrate 499 on which memory cells 210, 211, 212, and 213 of memory cell strings 231a, 234a, 231b, and 234b of corresponding sub-blocks SB0 and SB1 of blocks BLK0 and BLK1 may be formed (e.g., formed vertically in the z-direction relative to the source 290 and the substrate 499). A dielectric structure 451 electrically separates blocks BLK0 from blocks BLK1. The dielectric structure 451 may have a depth (e.g., height) in the z-direction. The depth of the dielectric structure 451 may be the distance (e.g., vertical distance) between the source 290 and the data lines (e.g., data lines 2700 or 2701).

[0066] like Figure 4A As shown, the memory device 200 may include different layers 409 to 414 relative to the Z direction. Layers 409 to 414 are internal device layers between the substrate 499 and the data line 2700.

[0067] The substrate 499 of the memory device 200 may comprise a single-crystal (also referred to as a single-crystal) semiconductor material. For example, the substrate 499 may comprise single-crystal silicon (also referred to as single-crystal silicon). The single-crystal semiconductor material of the substrate 499 may contain impurities, such that the substrate 499 may have a specific conductivity type (e.g., n-type or p-type).

[0068] like Figure 4A As shown, the memory device 200 may include a circuit system 495 located (e.g., formed on) a substrate 499. At least a portion of the circuit system 495 (e.g., the entire circuit system 495 or only a portion of the circuit system 495) may be located in a portion of the substrate 499 below (e.g., directly below) the memory cell strings 231a, 234a, 231b, and 234b. The circuit system 495 may include circuit elements (e.g., transistors T1 and T2 and other transistors (not shown)) coupled to other circuit elements outside the substrate 499. For example, data line 2700 ( Figure 4A The control gates 2200, 2210, 2220, 2230 of block BLK0 and the control gates 2201, 2211, 2221, and 2231 of block BLK1 can be coupled to circuit elements of memory device 200. Circuit system 495 may include decoder circuitry, drive circuitry, buffers, sense amplifiers, charge pumps, and other circuitry of memory device 200. Transistors T1 and T2 (and other transistors, not shown) of circuit system 495 may be (e.g., may be represented) part of such decoder circuitry, drive circuitry, buffers, sense amplifiers, charge pumps, and other circuitry of memory device 200.

[0069] The source 290 may contain conductive material (or material (e.g., different layers of material)) and may have a length extending in the X direction. Figure 4A An example is shown in which the source 290 may be formed on a portion of the substrate 499 (e.g., by depositing a conductive material on the substrate 499). Alternatively, the source 290 may be formed in or on a portion of the substrate 499 (e.g., by doping a portion of the substrate 499).

[0070] like Figure 4A As shown, the select lines (e.g., drain select lines) 2800 and 2801 for each of blocks BLK0 and BLK1 may be located in layer 414. The select lines (e.g., source select lines) 284 for each of blocks BLK0 and BLK1 may be located in the same layer (e.g., layer 409) between substrate 499 and memory cell strings 231a, 234a, 231b, and 234b. The memory cells of the corresponding memory cell strings (memory cell strings 231a, 234a, 231b, and 234b) may be located in different layers from layers 410 to 413.

[0071] like Figure 4A As shown, the memory device 200 may include a conductive structure 275 coupled between a corresponding post 450 and a data line 2700.

[0072] like Figure 4A As shown, a select line (e.g., 2800) may be a structure (e.g., a layer) of conductive material (e.g., a conductive material or a layer of material (e.g., a sheet)) located in a single layer of memory device 200. As described above, the select line may carry a signal (e.g., signal SGD00), but it does not function as a switch (e.g., a transistor). A select gate (e.g., 260) may include a portion of the corresponding select line (e.g., a portion of the conductive material sheet forming the corresponding select line) and additional structures to perform a function (e.g., the function of a transistor). For example, in... Figure 4A In the block BLK0, the selection gate 260 of the sub-block SB0 may include a portion of the selection line 2800 of the sub-block SB0 of the block BLK0 and a portion of the post 450 of the selection line 2800 of the adjacent sub-block SB0 of the block BLK0.

[0073] like Figure 4AAs shown, memory cells 210, 211, 212, and 213 of memory cell strings 231a, 234a, 231b, and 234b can be located in layers 410, 411, 412, and 413, respectively. Control gates 2200, 2210, 2220, and 2230 of block BLK0 (associated with memory cells 210, 211, 212, and 213, respectively) can be located in layers 410, 411, 412, and 413 adjacent to the corresponding portions (e.g., sidewalls) 450W of the pillar 450 in block BLK0, respectively. The control gates 2201, 2211, 2221, and 2231 of block BLK1 (associated with memory cells 210, 211, 212, and 213, respectively) may be located in layers 410, 411, 412, and 413 adjacent to the corresponding portions (e.g., sidewalls) 450W of the pillar 450 in block BLK1. Figure 4A As shown, control gates 2200, 2210, 2220 and 2230 can be located on the same level as control gates 2201, 2211, 2221 and 2231 respectively.

[0074] The memory device 200 may include dielectric material (e.g., dielectric material layers) 221 interleaved (in the Z direction) with control gates 2200, 2210, 2220, and 2230 of block BLK0 and control gates 2201, 2211, 2221, and 2231 of block BLK1 between different layers of the memory device 200 (e.g., layers interleaved with layers 409 to 413). The dielectric material 221 may comprise silicon dioxide. For simplicity, Figure 4A Dielectric material (e.g., silicon dioxide) located between other components of the memory device 200 is omitted.

[0075] like Figure 4A As shown, the memory device 200 may include guide posts (memory cell guide posts) 450 in corresponding sub-blocks SB0 and SB1 of blocks BLK0 and BLK1. Each guide post 450 may be part of a corresponding memory cell string. Each guide post 450 may have an outwardly extending length (e.g., extending vertically in the Z direction).

[0076] like Figure 4A As shown, memory cells 210, 211, 212 and 213 and control gates 2200, 2210, 2220, 2230, 2201, 2211, 2221 and 2231 may be positioned along corresponding portions (e.g., segments) of the post 450 in the Z direction (e.g., one level (e.g., layer) stacked on top of another level in the Z direction).

[0077] Memory device 200 may include a structure 430 and a dielectric material 405, which may be part of a respective post of a post 450 and extend continuously along the length of the respective post. The dielectric material 405 may comprise silicon dioxide. The structure 430 may be electrically coupled to a source 290 and a corresponding data line (e.g., data line 2700). The structure 430 of the respective post 450 is adjacent to (e.g., in contact with) a portion of the corresponding control gate. For example, the structure 430 of the post 450 in block BLK0 is adjacent to (e.g., in contact with) the control gates 2200, 2210, 2220, and 2230 of block BLK0.

[0078] like Figure 4A As shown, structure 430 may include portions 401, 402, 403, and 404. Each of the memory cells 210, 211, 212, and 213 of the memory cell string may include a portion of each of portions 401, 402, 403, and 404 located adjacent to a control gate (one of control gates 2200, 2210, 2220 and 2230, 2201, 2211, 2221, and 2231). For example, memory cell 213 of memory cell string 231a may include portions of structure 430 (portions 401, 402, 403, and 404) adjacent to control gate 2230. In another example, memory cell 212 of memory cell string 231a may include portions of structure 430 (portions 401, 402, 403, and 404) adjacent to control gate 2220.

[0079] Structure 430 may include a conductive structure (e.g., portion 404) that may be part of a conductive path (e.g., a post-channel structure) to conduct current between data line 2700 and source 290. Structure 430 may be a portion of an ONOS (SiO2, Si3N4, SiO2, Si) structure. For example, portion 401 may include SiO2 and may be combined with a portion adjacent to the control gate to form a charge-blocking material (or multiple charge-blocking materials) capable of blocking charge tunneling. Portion 402 may include a charge storage element (e.g., a charge storage portion, a charge storage material (or multiple charge storage materials), such as Si3N4) that provides charge storage functionality (e.g., charge trapping) to represent the value of information stored in memory cells 210, 211, 212, or 213. Portion 403 may include a dielectric, such as one or more tunneling dielectric materials (e.g., SiO2) capable of allowing the tunneling of charges (e.g., electrons). Section 404 may comprise polysilicon (e.g., doped or undoped polysilicon) and may be a channel structure (e.g., a pillar channel) capable of conducting current during operation of the memory device 200. For example, section 403 may allow electrons to tunnel from section 404 to section 402 during a write operation and allow electrons to tunnel from section 402 to section 404 during an erase operation of the memory device 200. Furthermore, section 403 may allow holes to tunnel from section 404 to section 402, thereby compensating for the recombination of trapped electrons during the erase operation of the memory device 200.

[0080] In an alternative arrangement, structure 430 may be a portion of a SONOS (Si, SiO2, Si3N4, SiO2, Si) structure. In another alternative arrangement, structure 430 may be a portion of a floating gate structure (e.g., portion 402 may be polysilicon). Figure 4A Showing a specific shape (e.g., Figure 4A The structure 430 is an example of the shape shown. However, the structure 430 may have different shapes.

[0081] Figure 4B This illustrates a portion of a control gate 2230 and an adjacent post 450 at memory cell 213 of memory cell string 231a, according to some embodiments described herein. Figure 4A The cross-section of a portion of the memory device 200 is shown in line 4B-4B. Other control gates and posts of the memory cell string of the memory device 200 have... Figure 4B Similar or identical structures as shown.

[0082] like Figure 4BAs shown, the control gate 2230 may comprise a combination of materials (e.g., materials that may be formed therefrom), the materials comprising dielectric material 452 (e.g., a high-k dielectric material), material (e.g., a titanium-containing material) 455, material 453 (e.g., a metal (e.g., tungsten)) and material 454 (e.g., a metal (e.g., tungsten)).

[0083] Material 454 is accessible (e.g., directly coupled to) material 453. Material 453 is accessible (e.g., directly coupled to) material 455. Material 455 is accessible (e.g., directly coupled to) dielectric material 452. Dielectric material 452 is accessible (e.g., directly coupled to) portion 450W of post 450.

[0084] Part 450W may include a portion of part 401 of post 450 (e.g., silicon dioxide). Although dielectric material 452 (e.g., high-k dielectric material) is described herein as a portion of control gate 2230, dielectric material 452 may be a portion of post 450 (rather than control gate 2230). For example, dielectric material 452 (e.g., high-k dielectric material) may be a portion of control gate 2230 such that dielectric material 452 is formed after post 450 is formed. In another example, dielectric material 452 (e.g., high-k dielectric material) may be a portion of post 450 such that dielectric material 452 is formed as a portion of post 450 (e.g., formed during the formation of post 450).

[0085] Dielectric material 452 may have a thickness ranging from 2 nanometers (nm) to 5 nm (in the X direction). Alternatively, dielectric material 452 may have a thickness greater than 5 nm. Material 453 may have a thickness ranging from 2 nm to 5 nm (in the X direction). Material 455 may have a thickness ranging from 2 nm to 5 nm (in the X direction). Alternatively, material 455 may have a thickness greater than 5 nm. For comparative purposes, dielectric material 221 ( Figure 4A The thickness (in the Z direction) of the dielectric material 455 can be in the range of 20 nm to 30 nm. Therefore, as an example, the thickness of the dielectric material 455 can be one-tenth (0.1) or about one-tenth of the thickness of the dielectric material 221.

[0086] Dielectric material 452 may comprise a high-k (or hi-k) dielectric material or a combination of high-k dielectric materials. A high-k dielectric material is a dielectric material having a dielectric constant greater than that of silicon dioxide. Dielectric material 452 may be configured (e.g., arranged) to protect (e.g., safeguard) the dielectric material (e.g., silicon dioxide) of portion 401 of post 450 from certain processes (e.g., etching processes) during processes forming the memory device 200, such as processes forming portions of control gate 2230 and other control gate portions of the memory device 200. Dielectric material 452 may also be configured (e.g., arranged) to prevent charge tunneling from post 450 (e.g., from portion 402 of post 450 (e.g., charge storage portion)) to other portions of control gate 2230 (e.g., material 453 or 454, or both).

[0087] For example, dielectric material 452 may comprise aluminum oxide (AlOx). In another example, dielectric material 452 may comprise titanium silicon nitride (TiSiN). In yet another example, dielectric material 452 may contain hafnium. Examples of hafnium-containing dielectric material 452 include hafnium dioxide (HfOx) and hafnium silicate (HfSiOx).

[0088] The dielectric material 452 listed in this document is an example. However, other dielectric materials (e.g., other high-k dielectric materials) may be used. For example, other dielectric materials with a dielectric constant greater than that of aluminum oxide may be used.

[0089] Furthermore, for the control gate 2230 and other control gates of the memory device 200, using some high-k dielectric material for dielectric material 452 can provide more benefits than using other high-k dielectric materials for dielectric material 452. For example, compared to a memory device 200 using aluminum oxide (AlOx) for dielectric material 452, using a hafnium-containing dielectric material (e.g., HfOx, HfSiOx, or other hafnium-based dielectric materials) for dielectric material 452 can produce a memory device 200 with a relatively wide program / erase window (P / E window).

[0090] Material 455 may comprise a conductive material. Material 455 may be configured (e.g., arranged) to improve the work function of memory cell operation for memory device 200. Alternatively or additionally, material 455 may also be configured to assist the bonding and nucleation of dielectric material 452 with materials 453, 454, or both. Material 455 may contain titanium, nitrogen, or both. For example, material 455 may comprise titanium silicon nitride (TiSiN). In another example, material 455 may comprise titanium nitride (TiN).

[0091] like Figure 4BAs shown, material 455 may have a continuous structure, allowing it to be fully formed (e.g., fully coated) onto dielectric material 452. For example, material 455 may be a relatively thin layer (e.g., 2 nm to 5 nm, or alternatively greater than 5 nm) of TiSiN (or, alternatively, TiN) conformally to dielectric material 452 (e.g., conformally to the sidewalls of dielectric material 452). Alternatively, material 455 may have a discontinuous structure, allowing it to be less completely conformally to dielectric material 452 (e.g., the sidewalls of dielectric material 452 may not be fully coated).

[0092] Material 453 may contain a conductive material. For example, material 453 may contain tungsten (W). Material 454 may contain a conductive material. For example, material 454 may contain tungsten (W). Although both materials 453 and 454 may contain tungsten, materials 453 and 454 may contain tungsten in different forms (e.g., β phase and α phase). For example, the majority (e.g., greater than 50% by volume) of the tungsten in material 453 may be β phase tungsten (β-W), and the majority (e.g., greater than 50% by volume) of the tungsten in material 454 may be α phase tungsten (α-W).

[0093] The grain size of the α-phase tungsten in material 454 is larger than that of the β-phase tungsten in material 453. When discussing the grain size of the α-phase tungsten material, those skilled in the art will recognize that the grains will generally be irregularly shaped. Therefore, the grain size discussed herein relates to the maximum (i.e., longest) dimension through an individual grain; and the discussion herein addresses this maximum dimension as "at least" an identified reference value to distinguish smaller grains whose maximum dimension is less than the identified reference value.

[0094] In some instances, most of the tungsten in material 454 ( Figure 4B The maximum size of the material 454 is 50 nm (or about 50 nm) or larger, some examples of which contain grains with a maximum size of at least 80 nm (or at least about 80 nm), and in some examples, include grains with a maximum size of at least 100 nm (or at least about 100 nm). In some examples, tungsten in material 454 having grains with a maximum size greater than about 50 nm may form at least about 50% or more of material 454. In other examples, tungsten in material 454 having grains with a maximum size of 50 nm may provide beneficial electrical properties if it is present in only about 40% of material 454. The term "about" as used herein means a difference of ±10% including the structure or properties to account for variations in manufacturing processes, measurement techniques, etc.

[0095] Therefore, materials 453 and 454 can form tungsten structures that exhibit different properties (e.g., characteristics) in different portions of the tungsten structure of the control gate 2230. For example, portions of the tungsten structure formed by material 453 can exhibit the properties (e.g., characteristics) of β-phase tungsten, and portions of the tungsten structure formed by material 454 can exhibit the properties (e.g., characteristics) of α-phase tungsten. The resistivity of material (e.g., β-phase tungsten) 453 is substantially higher than that of material (e.g., α-phase tungsten) 454 (e.g., in some embodiments, the resistivity is about 3 to 10 times that of α-phase tungsten).

[0096] In some instances, compared to the α-phase tungsten of a conventional control gate without β-phase tungsten, control gate 2230 ( Figure 4A The resistance of material 454 can be relatively low (e.g., for a one-dimensional structure with a width of about 20 nm in the Z direction and a length of 65-100 nm in another dimension, the resistance is about 2-4 Ω / sq) (e.g., for a similar structure, the resistance of the α-phase tungsten of a conventional control gate may be greater than 5 Ω / sq).

[0097] Therefore, material 453 may have a different crystal structure (e.g., β-phase tungsten crystal structure) than the crystal structure of material 454 (e.g., the crystal structure of α-phase tungsten). The crystal structures of materials 453 and 454 can be observed (e.g., detected) using orientation and phase mapping in transmission electron microscopy (TEM) or other techniques.

[0098] In another instance, material 453 may have an X-ray diffraction (XRD) signature that is different from that of material 454 (e.g., the XRD signature of α-phase tungsten). An X-ray diffractometer (or other equipment) may be used to measure the XRD signatures of materials 453 and 454.

[0099] Since materials 453 and 454 may contain tungsten (e.g., β-phase tungsten and α-phase tungsten, respectively), materials 453 and 454 can form tungsten structures (or structures of tungsten materials) and can be referred to as tungsten materials. Therefore, as described herein, Figure 4B The tungsten structure (or tungsten material) of the control gate 2230 shown may include a portion of the β-phase tungsten (from material 453) that contacts (e.g., touches) the dielectric material 452, and a portion of the α-phase tungsten (from material 454) that contacts (e.g., connects) the β-phase tungsten.

[0100] In alternative structures for the control gate 2230 (and other control gates) of the memory device 200, material 455 (e.g., not formed in the control gates and other control gates) can be excluded from the control gate 2230 and the other control gates of the memory device 200. Therefore, in such alternative structures, material 453 (e.g., β-phase tungsten) can contact (e.g., can be directly coupled to) dielectric material (e.g., high-K dielectric material) 452. However, compared to a structure with a control gate 2230 without material 455, a structure with material 455 in the control gate 2230 (e.g., β-phase tungsten) can still benefit from the alternative structure. Figure 4B As shown, the operation of memory device 200 can be improved. For example, including material 455 (e.g., TiSiN or TiN) in the control gate 2230 (and other control gates) of memory device 200 can make memory device 200 have a relatively wider program erase window compared to memory device 200 without material 455 in the control gate 2230 (and other control gates).

[0101] Figure 4C The diagram shows the relative positions of the blocks (e.g., blocks BLK0 and BLK1), dielectric structure 451, post 450 of the memory cell string, and data lines 2700, 2701, 2702, and 2703. Figure 4A A top view of the memory device 200. For simplicity, this is not a full view. Figure 4C All memory cell strings (including the corresponding guide post 450) are marked. Figure 4C Some components of the memory device 200 are in Figures 2 to 4A Not shown, it includes data line 2703 (and associated signal BL3) and a string of memory cells coupled to data line 2703.

[0102] like Figure 4C As shown, dielectric structure 451 may include materials 451L and 451P formed in the slit (unlabeled) between blocks BLK0 and BLK1. Material 451L may contain a dielectric material (e.g., silicon dioxide). Material 451P may contain polysilicon.

[0103] Data lines 2700, 2701, 2702, and 2703 may be located above (in the Z direction) and extend across the blocks of memory device 200 (in the X direction) of the memory device 200 (e.g., blocks BLK0 and BLK1). Each of data lines 2700, 2701, 2702, and 2703 may be electrically coupled to a corresponding post 450 of blocks BLK0 and BLK1. Figure 4A A portion of the memory device 200 along line 4A-4A is shown.

[0104] Figure 5Some embodiments according to the description herein are shown. Figure 4A A top view of a memory device 200 in the XY direction, the memory device 200 including a memory array 201, regions (e.g., stepped regions) 545, dielectric structures 451, and blocks BLK0 and BLK1 to BLKi. For simplicity, Figure 5 Omitted Figure 4A Some elements of the memory device 200 (e.g., associated posts 450 of the memory cell strings and memory array 201). Furthermore, Figure 5 Labels for similar or identical elements within blocks (e.g., blocks BLK0, BLK1, and BLKi) are omitted, and descriptions of these elements are not repeated.

[0105] like Figure 5 As shown, blocks BLK0 and BLK1 to BLKi of the memory device 200 can be positioned side-by-side in the X direction. Figure 5 As shown, neighboring blocks can be electrically separated from each other by a dielectric structure 451 between neighboring blocks. Each dielectric structure 451 may have a length in the Y direction, a width in the X direction, and a depth (e.g., a height) in the Z direction (as shown). Figure 4A (As shown). Data cable 2700 to 270 N It can have a corresponding length that spans blocks BLK0 to BLKi in the X direction.

[0106] Region 545 (e.g., a stepped region) of memory device 200 may be a region where conductive contacts 565 are formed to electrically couple the control gate of a corresponding block to a corresponding conductive path (e.g., conductive paths 2560 and 2561) of memory device 200. Each of conductive paths 2560 and 2561 may contain a conductive line (e.g., a metal wire).

[0107] like Figure 5 As shown, the control gates 2200, 2210, 2220, and 2230 of block BLK0 can be coupled to the corresponding conductive path 2560 through the corresponding conductive contact 565 at region 545 of block BLK0. The control gates 2201, 2211, 2221, and 2231 of block BLK1 can be coupled to the corresponding conductive path 2561 through the conductive contact 565 at region 545 of block BLK1.

[0108] Figures 2 to 5 The memory device 200 shown may use part or all of its structure with reference to the following. Figure 6A and Figures 6B to 16A and Figure 16B The process described is related to the process of formation.

[0109] Figure 6A and Figures 6B to 17A and Figure 17BDifferent views of elements during the process of forming memory device 600 according to some embodiments described herein are shown. Figure 6A The image shows a side view (e.g., cross-section) of the device 600 in the X direction after dielectric material (dielectric material layer) 621 and dielectric material (dielectric material layer) 622 are alternatively formed on substrate 699. Substrate 699 is similar to (e.g., may correspond to) substrate 499 of memory device 200. Figure 4A Dielectric materials 621 and 622 can be formed sequentially on substrate 699 in an alternating manner, one material after another, so that dielectric material 621 can be interleaved with dielectric material 622.

[0110] Figure 6B Show along Figure 6A A top view of a portion of the memory device 200 (e.g., in the XY plane) taken by lines 6B-6B. Figure 6A The side view (in the XZ direction) of the memory device 600 shown is along... Figure 6B The line (e.g., the cross-sectional line) is cut off at 6A-6A.

[0111] like Figure 6A As shown, the process of forming the memory device 600 may include forming a material 690 on a substrate 699. The material 690 may be formed in a manner similar to... Figure 4A The source of source 290 (e.g., associated with signal SRC).

[0112] Those skilled in the art will readily recognize that the references in this article... Figure 6A and Figures 6B to 17A and Figure 17B The process for forming the memory device 600 described herein may be included Figure 6A Additional elements (not shown) are formed in portions 691 and 692 (shown in dashed lines) of the memory device 200. For example, the additional elements in portion 691 may include selection circuits similar to selection circuits (e.g., source selection circuits) 241'a, 244'a, 241'b, and 244'b, as well as selection circuits in the memory device 200. Figure 2 , Figure 3 and Figure 4A Other components of ) . In another example, additional components in part 692 may include selection circuits similar to selection circuits (e.g., drain selection circuits) 241a, 244a, 241b and 244b, and memory device 200 ( Figure 2 , Figure 3 and Figure 4A Other elements of ). For simplicity and without obscuring the embodiments described herein, the description of the formation of such additional elements in parts 691 and 692 is omitted from the description herein.

[0113] In the following description, different views of the memory device 600 in subsequent processes are based on Figure 6A and Figure 6B The view of the memory device 600 and following Figure 6A and Figure 6B The same arrangement of views (e.g., side view and top view). For example, Figure 7A Show along Figure 7B A side view of a portion of the memory device 600 taken by lines (e.g., cross-sectional lines) 7A-7A. Figure 7B Show along Figure 7A The line 7B-7B cut Figure 7A A top view of a portion of the memory device 600. For simplicity, the following description omits repeated specific views (e.g., side views and top views) and specific cross-sectional lines of portions of the memory device 600 from one process to the next.

[0114] In the description herein, elements given the same numerical designation are considered similar or identical elements. For example, guide post 450 ( Figure 4A ) and guide post 450' Figure 8A ) are similar or identical elements. In another example, control gates 2200, 2210, 2220 and 2230 ( Figure 4A ) and control gates 220'0, 221'0, 222'0 and 223'0 ( Figure 16A ) are similar or identical elements. In another example, control gates 2201, 2211, 2221 and 2231 ( Figure 4A ) and control gates 220'1, 221'1, 222'1 and 223'1 ( Figure 16A () are similar or identical components. Therefore, for simplicity, detailed descriptions of similar or identical components may not be repeated.

[0115] Figure 7A and Figure 7B Different views of the memory device 600 are shown after an opening (e.g., a hole) 750 is formed through dielectric materials 621 and 622. Forming the opening 750 may include removing (e.g., etching) a portion of the dielectric materials 621 and 622 at the location of the opening 750.

[0116] Figure 8A and Figure 8B Different views of the memory device 600 are shown after the formation of the guide post 450'. The formation of the guide post 450' may include forming a structure 430' and a dielectric material 405' within a corresponding opening 750. The guide post 450' is similar to (e.g., may correspond to) Figure 4A The guide post 450. The structure 430' and the dielectric material 405' are respectively similar to (e.g., may correspond to) Figure 4AThe structure is 430 and the dielectric material is 405. (And...) Figure 4A The structure is similar to 430. Figure 8A Structure 430' in the middle can be formed Figure 8A A portion of the memory cells in the corresponding memory cell string of the memory device 600 (e.g., with Figure 4A (Similar to memory cells 210, 211, 212, and 213). Figure 8A and Figure 8B The corresponding pins 450' of the memory device 600 shown, for strings 234'a, 231'b, and 234'b, are respectively similar to (for example, may correspond to) Figure 4A and Figure 4C The memory cell strings 231a, 234b, and 234b of the memory device 200 have a guide post 450. For simplicity, Figure 8B The structure 430' of each guide post 450' is shown in dashed lines.

[0117] exist Figure 8A In this context, the dielectric material 622 layer (e.g., a layer) (or alternatively, two adjacent layers comprising the dielectric material 621 layer and the dielectric material 622 layer) may be referred to as layers of the memory device 200. Figure 8A As shown, the layers of the memory device 800 may be located (e.g., stacked) on top of each other in the Z direction on the substrate 699, such that two adjacent layers may be separated from each other by the respective levels (e.g., layers) of the dielectric material (e.g., silicon dioxide) 621. Figure 8A An example of a specific number of levels (e.g., four levels) is shown. However, the memory device 200 may contain up to (or more than) hundreds of levels.

[0118] Figure 9A and Figure 9B The image shows a memory device 600 after a slit (e.g., opening, groove, or cut) 951 has been formed. The slit 951 may be formed horizontally to extend through dielectric materials 621 and 622. The slit 951 may include sidewalls 951A and 951B opposite each other in the X direction. Figure 9A As shown, sidewalls 915A and 915B are vertical sidewalls that may contain corresponding portions of dielectric materials 621 and 622 exposed at slit 951.

[0119] Slit 951 can be configured to divide (e.g., separate) the elements of memory device 600 (e.g., respective memory cell strings and other elements) into portions that can be part of respective blocks (e.g., blocks BLK0 and BLK1) of memory device 600. For example, slit 951 can separate dielectric materials 621 and 622 into corresponding portions within blocks BLK0 and BLK1. In another example, slit 951 can separate the posts 450' of respective memory cell strings of memory device 600 into corresponding portions within blocks BLK0 and BLK1. Figure 9A and Figure 9B As shown, the post 450' of memory cell string 234'a can be part of block BLK0. The posts 450' of memory cell strings 231'b and 234'b can be part of block BLK1.

[0120] The following description (and) Figure 10A and Figures 10B to 17A and Figure 17B The associated process involves removing layers of dielectric material (e.g., silicon nitride) 622 and then replacing the layers with the material of the corresponding layers to form a control gate in the corresponding layer of the memory device 600.

[0121] Figure 10A and Figure 10B The memory device 600 is shown after the dielectric material 622 has been removed (e.g., dug out) from position 1022. Figure 10A Position 1022 in the middle is by Figure 9A The dielectric material 622 occupies the voids (empty spaces). In subsequent processes, material can be formed in position 1022 to form the corresponding control gate of the memory device 600. For example... Figure 10A As shown, each guide post 450 may include a portion 450'W exposed at the corresponding location 1022. Each portion 450'W may be part of the vertical sidewall of the corresponding guide post 450. Figure 10A As shown, each portion 450'W can extend in the Z direction between two adjacent dielectric material 621 layers that are also exposed at the corresponding location 1022.

[0122] Figure 11A and Figure 11B The image shows a memory device 600 after the dielectric material 1152 has been formed. The dielectric material 1152 may be similar to... Figure 4A The dielectric material 452 of the memory device 200 may be the same as or similar to that of the dielectric material. For example, the dielectric material 1152 may comprise a high-k dielectric material (e.g., AlOx, TiSiN, HfSiOx, HfOx, or other high-k dielectric materials). The dielectric material 1152 may have a thickness in the range of 2 nm to 5 nm. Alternatively, the dielectric material 1152 may have a thickness greater than 5 nm.

[0123] like Figure 11A As shown, dielectric material 1152 can be a relatively thin layer (e.g., a film) that can be coated (e.g., conformally to) portions of post 450' (e.g., sidewalls) 450'W and portions of dielectric material 621 exposed at location 1022. Dielectric material 1152 can also be formed on portions of dielectric material 621 exposed at slit 951 (e.g., vertical sidewalls, not labeled).

[0124] Figure 12A and Figure 12B A memory device 600 is shown after the dielectric material 1255 has been formed. Material 1255 may be formed directly on (e.g., coated) dielectric material 1152 such that material 1255 is conformal to material 1152. Material 1255 may have a thickness in the range of 2 nm to 5 nm. Alternatively, material 1155 may have a thickness greater than 5 nm.

[0125] Material 1255 is similar to (for example, may correspond to) the reference above. Figure 4B The described memory device 200 is made of material 455. Therefore, material 1255 may contain titanium (a titanium-containing material). For example, material 1255 may contain titanium silicon nitride (TiSiN). In another example, material 1255 may contain titanium nitride (TiN).

[0126] and Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B The following processes, associated with the description, describe different portions of the tungsten structure forming the respective control gate in the corresponding layers of the memory device 600. These processes include forming the tungsten structure by means of processes that facilitate coverage of desired steps, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Figure 13A and Figure 13B An example of material 1353 (e.g., a silicon-containing material). Then, material 1353 (e.g., a silicon-containing material) is converted... Figure 14A and Figure 14B Material 1453 (e.g., tungsten seed material mainly composed of β-phase tungsten). As described below, material 1353 (e.g., Figure 13A and Figure 13B The silicon-containing material in the process will preferably include tungsten seed material present in the conversion (e.g., Figure 14A and Figure 14B The dopant in material 1453 is selected to suppress the formation of dopants on material 1453 (e.g., tungsten seed material, which is mainly β-phase tungsten). Figure 15A and Figure 15BNucleation in material 1554 (e.g., subsequently deposited tungsten-filled material, which is mainly α-phase tungsten).

[0127] Figure 13A and Figure 13B A memory device 600 is shown after the formation of dielectric material 1353. Material 1353 may be formed directly on (e.g., coated) dielectric material 1255 such that material 1353 is conformal to material 1255. As discussed above, material 1353 is a silicon-containing material. Material 1353 may contain silicon (e.g., polycrystalline silicon) and suitable dopants. For example, the dopants may be any one or more of chlorine, arsenic, and phosphorus. The dopants in material (e.g., silicon-containing material) 1353 are selected to promote the formation of dielectric material 1353. Figure 14A and Figure 14B The material (e.g., tungsten seed material) 1453 described below forms a β-phase tungsten that is the main component.

[0128] In some instances, Figure 13A and Figure 13B Material 1353 (a silicon-containing material) can be deposited in such a manner that dopant is also deposited within material 1353. In other instances, silicon can be deposited first, followed by doping with a dopant. Atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes can be used to deposit material 1353 (with or without dopant). As those skilled in the art will know, CVD deposition can be performed as a single-stage deposition or a multi-stage deposition (similar to ALD deposition).

[0129] In material 1353 ( Figure 13A and Figure 13B In a process for depositing doped materials, CVD deposition of doped silicon can be performed by providing multiple precursors, at least one of which contains a dopant. For example, CVD deposition of chlorine-doped silicon can be performed using a precursor containing disilane (Si₂H₆) and dichlorosilane (H₂Cl₂Si). In some instances, the precursors can be alternated by a limited number of cycles (e.g., five or fewer cycles, and in some cases only two cycles). As example process conditions for such CVD or ALD deposition, deposition can be performed in a temperature range of 300 to 500 degrees Celsius and a pressure range of 1 n Torr to 10 Torr. In some instances, the precursor can be supplied in an amount of chlorine dopant ranging from 0.001% to 10%. In some instances, a dopant concentration in the range of about 0.05% to about 2% is satisfactory; a doping concentration in the range of 0.1% to about 0.5% is generally suitable; for example, in some embodiments, about 0.02% (or about ~1E20 atoms / cm²) is suitable. 3 That might be appropriate.

[0130] In many instances, doped silicon can be deposited, making material 1353 ( Figure 13A and Figure 13B It can be formed to a thickness of 2nm to 5nm. As discussed above, dopants are selected in material 1353 to promote [the formation of...]. Figure 14A and Figure 14B β-phase tungsten is formed in the material (e.g., tungsten seed material) 1453 as described below.

[0131] Material 1353 was formed by first depositing silicon and then doping it. Figure 13A and Figure 13B In the process, silicon can be deposited using a disilane precursor (Si₂H₆). In other instances, as an alternative, the precursor may comprise silane (SiH₄) or possibly other silicon-containing precursors. In many instances, silicon thicknesses ranging from 2 nm to 5 nm can be deposited. Subsequently, the deposited silicon can be doped with suitable dopants, for example, any one or more of chlorine, arsenic, and phosphorus. The doping level of chlorine has been discussed above. In some instances, for example, arsenic and phosphorus can be doped at doping levels within the aforementioned chlorine doping range.

[0132] In many applications, material 1353 ( Figure 13A and Figure 13B The thickness of the silicon deposited in the material is limited to the thickness discussed above (e.g., 2 nm to 5 nm) because the silicon in material 1353 will be reduced to β-phase tungsten (containing... Figure 14A and Figure 14B In material 1453, as described below). It is desired that β-phase tungsten be used to reduce the subsequent deposition of α-phase tungsten (included in...). Figure 15A and Figure 15B Nucleation occurs in material 1554 (as described below). However, the resistivity of the β-phase tungsten is higher than that of the α-phase tungsten (e.g., in some embodiments, the resistivity is about 3 to 10 times that of the α-phase tungsten). Therefore, the volume ratio of α-phase tungsten (in material 1554) to β-phase tungsten (in material 1453) is relatively high, resulting in a lower resistivity of the tungsten structure. Therefore, it is advantageous to minimize the size of the β-phase tungsten in the tungsten seed material (in material 1453) (considering competitive factors such as process complexity and cost) while maintaining the nucleation suppression performance of the tungsten seed material.

[0133] Material 1453, whose majority composition is β-phase tungsten, facilitated the formation of subsequently formed material 1454 on material 1453 (material whose majority composition is β-phase tungsten). Figure 14A and Figure 14B As described below, relatively large-grained α-phase tungsten is formed, which constitutes the majority of the structure. As discussed above, relatively large-grained α-phase tungsten can reduce the resistance of the tungsten structure of the control gate of the memory device, thereby reducing the resistance of the control gate.

[0134] Figure 14A and Figure 14B The image shows a memory device 600 after the formation of a material (e.g., a tungsten seed material) 1453. As discussed above, material 1453 can be formed by converting material (e.g., a silicon-containing material) 1353 into material (e.g., β-phase tungsten) 1453. Figure 14A and Figure 14B In the middle, since material 1453 can be made from material 1353 ( Figure 13A and Figure 13B ) is formed, and material 1353 can be directly formed on dielectric material 1255 (can be in contact with said dielectric material 1255), therefore material 1453 ( Figure 14A and Figure 14B It can also be formed directly on material 1255 (which can be in contact with the dielectric material 1255).

[0135] As described above, when using material 1453 Figure 15A and Figure 15B When the material 1554 (e.g., the subsequent tungsten-filled material) is in action, the material 1453 containing the dopant material (mainly having β-phase tungsten seed material) is configured to suppress nucleation, and thus promote the formation of the 1554 material dominated by α-phase tungsten (i.e., volume greater than 50%), and further promote the formation of relatively large grains of α-phase tungsten in the 1554 material. While not wishing to be bound by theory, it appears that the suppression of nucleation of β-phase tungsten (in material 1453) leads to sparse nucleation of α-phase tungsten (in material 1554) on the β-phase tungsten, thus allowing the α-phase grains (in material 1554) to “bloom” to a larger size compared to grains obtained by conventional deposition processes.

[0136] Material 1453 ( Figure 14A and Figure 14B ) can be achieved by applying material 1353 under appropriate conditions. Figure 13A and Figure 13B Exposure to tungsten hexafluoride (WF6) typically works in the presence of hydrogen (H2). For example, for materials (e.g., silicon-containing materials) 1353 with a thickness of 2 nm to 5 nm, exposure to WF6 for about 20 to 30 seconds at a WF6 to H2 ratio of .0001 to 100.0 is satisfactory. This process condition can be implemented to make material 1353 ( Figure 13A and Figure 13B In this material, virtually all silicon is reduced to material 1453. Figure 14A and Figure 14B ) in tungsten.

[0137] Figure 15A and Figure 15B A memory device 600 is shown after forming a material (e.g., tungsten-filled material) 1554. Material 1554 may be formed on material 1453 and may occupy (e.g., fill) the remaining voids at positions 1022 and slit 951. Material 1554 may be formed by an ALD process or a CVD process. For example, forming material 1554 may involve forming tungsten on material 1453 until the tungsten (material 1554) fills the voids at positions 1022 and slit 951. Alternatively, forming material 1554 may involve depositing additional tungsten (material 1554) on the initial tungsten of material 1453 until the tungsten (material 1554) fills the voids at positions 1022 and slit 951.

[0138] The CVD process for forming (e.g., depositing) material (e.g., tungsten-filled material) 1554 can use tungsten hexafluoride (WF6); and can be operated at temperatures of 200-500°C or more specifically between about 375°C and 425°C or about 395°C. The CVD process can use a high-power, long-range plasma of about 4-40 kW for about 10-100 seconds. The chamber pressure for batch CVD deposition of tungsten to increase the tungsten grain size of material 1554 can be in the range of, for example, about 30 Torr and about 50 Torr, such as 40 Torr, but higher or lower pressures can also be used.

[0139] The CVD process used to form (e.g., deposit) a material (e.g., tungsten-filled material) 1554 may alternatively include various processes, such as diborane (B2H6)-based nucleation and / or silane (SiH4)-based nucleation. In such examples, the CVD process may comprise bulk deposition or pulsed nucleation. A diborane (B2H6) nucleation cycle in a CVD deposition process comprises diborane (B2H6) immersion, tungsten fluoride (WF6) incorporation, and then a B2H6 / WF6 pulse. This nucleation cycle may be repeated in the range of 1 to 20 times or more specifically between 1 and 4 times. A silane (SiH4)-based nucleation cycle in a CVD tungsten process comprises silane (SiH4) immersion, tungsten fluoride (WF6) incorporation, and then a SiH4 / WF6 pulse. This nucleation cycle may be repeated in the range of 1 to 20 times or more specifically between 3 and 5 times. In some instances, the nucleation temperature range for diborane or silane can be between approximately 250°C and 350°C, and the chamber temperature and pressure ranges are the same as described above.

[0140] Therefore, with Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B The associated processes can be included Figure 13A and Figure 13B Forming material 1353 (e.g., silicon-containing material); converting material 1353 into Figure 14A and Figure 14B Material 1453 (e.g., β-phase tungsten seed material (initial tungsten material)) is formed in the material 1453; then material 1554 (e.g., α-phase tungsten filler material (additional tungsten material)) is formed on the material 1453.

[0141] Material 1453 is similar to (for example, may correspond to) the above reference. Figure 4B The memory device 200 described is made of material 453. Therefore, similar to the tungsten structure formed by material 453, material 1453 as described above can form a tungsten structure that exhibits the properties (e.g., characteristics) of β-phase tungsten, wherein the majority (e.g., greater than 50% by volume) of the tungsten in material 1453 is β-phase tungsten.

[0142] Material 1554 is similar to (for example, may correspond to) the reference above. Figure 4B The described memory device 200 uses material 454. Therefore, similar to the tungsten structure formed from material 454, material 1554, as described above, can have a resistance similar to (or the same as) that of material 454 (as described above). Material 1554 also contains tungsten, wherein a majority (e.g., more than 50% by volume) of the tungsten in material 1554 is α-phase tungsten. The grain size of the α-phase tungsten in material 1554 can also be similar to (or the same as) the grain size of the α-phase tungsten in material 454. For example, a majority (e.g., at least 50%) of the tungsten in material 1554 has a maximum size of at least 50 nm (or at least about 50 nm). In another example, a majority (e.g., at least 50%) of the tungsten in material 1554 has a maximum size of at least 80 nm (or at least about 80 nm). In yet another example, a majority (e.g., at least 50%) of the tungsten in material 1554 has a maximum size of at least 100 nm (or at least about 100 nm).

[0143] As referenced above Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15BAs described, a material (e.g., β-phase tungsten) 1453 is formed on a material (e.g., a high-k dielectric material) 1255, and then a material (e.g., α-phase tungsten) 1554 is formed on the material 1453. Since the material 1453 contains β-phase tungsten, the nucleation of the α-phase tungsten (included in the material 1554) on the β-phase tungsten allows for a relatively large grain size (having the relative grain size described above, e.g., at least 50 nm) in the tungsten structure of the control gate of the memory device 600. As an example, the grain size of the material 1554 formed using the material 1453 may be relatively large (e.g., at least twice as large) compared to the grain size of the material 1554 formed using an alternative process. A larger grain size can reduce the relative resistance of the control gate of the memory device 600, thereby improving the operation of the memory device 600 (e.g., read, write, and erase operations).

[0144] Figure 16A and Figure 16B A memory device 600 is shown after the formation of control gates 220'0, 221'0, 222'0, and 223'0 (in block BLK0) and control gates 220'1, 221'1, 222'1, and 223'1 (in block BLK1). The control gates 220'0, 221'0, 222'0, and 223'0 in block BLK0 and the control gates 220'1, 221'1, 222'1, and 223'1 in block BLK1 are respectively similar to (e.g., may correspond to) these gates. Figure 4A The control gates 2200, 2210, 2220 and 2230 in block BLK0 and the control gates 220, 2211, 2221 and 2231 in block BLK1 of the memory device 200.

[0145] The formation of control gates 220'0, 221'0, 222'0, and 223'0 (in block BLK0) and control gates 220'1, 221'1, 222'1, and 223'1 (in block BLK1) may include removing (e.g., by etching or cutting) a portion of material 1554 at slit 951, such that the remaining portions of material 1554 at different levels (e.g., layers) of the memory device 600 are electrically isolated from each other. Figure 16A As shown, control gates 220'0, 221'0, 222'0 and 223'0 (in block BLK0) and control gates 220'1, 221'1, 222'1 and 223'1 (in block BLK1) are the remainder of material 1554 in the corresponding layers of memory device 600.

[0146] Figure 17A and Figure 17B Shown in slit 951 (in Figure 15AThe memory device 600 is formed after the dielectric structure 451' is formed in the slit 951 (referred to as "the reference numeral"). Forming the dielectric structure 451' may include forming a material (e.g., a pad) 451'L in the slit 951 (e.g., on the sidewall of the slit 951), and then forming a material (e.g., polysilicon) 451'P between the materials 451'L. The dielectric structure 451' and the materials 451'L and 451'P are respectively similar to (e.g., may correspond to) those referenced above. Figure 4A and Figure 4C The dielectric structure 451 and materials 451L and 451P of the described memory device 200.

[0147] like Figure 17A As shown, dielectric structure 451' can electrically separate material 1554 into corresponding portions in blocks BLK0 and BLK1, which form corresponding control gates 220'0, 221'0, 222'0 and 223'0 (in block BLK0) and corresponding control gates 220'1, 221'1, 222'1 and 223'1 (in block BLK0).

[0148] refer to Figure 6A and Figures 6B to 17A and Figure 17B The description of forming memory device 600 may include other processes that form the complete memory device (e.g., memory device 600). Such processes are omitted from the above description in order not to obscure the subject matter described herein. Memory device 600 may have similar improvements and advantages to memory device 200 (e.g., lower resistance and better performance).

[0149] The descriptions of devices (e.g., memory devices 100, 200, and 600) and methods (e.g., processes associated with memory devices 600 and 1800) are intended to provide a general understanding of the structure of the various embodiments and are not intended to provide a complete description of all elements and features of devices that may utilize the structures described herein. For example, device as used herein refers to means (e.g., any one of memory devices 100, 200, and 600) or a system (e.g., a computer, cellular phone, or other electronic system) that includes means such as any one of memory devices 100, 200, and 600.

[0150] The above reference Figures 1 to 17BAny of the components described can be implemented in several ways, including through software simulation. Therefore, a portion of any device (e.g., memory devices 100, 200, and 600) or any of the memory devices described above can be characterized herein as a plurality of “modules” (or a single “module”). Such a module may include hardware circuitry, single-processor and / or multi-processor circuitry, memory circuitry, software program modules and objects and / or firmware, and combinations thereof, as required and / or appropriate for a particular implementation of the various embodiments. For example, such a module may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitor-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware for operating or simulating the operation of various potential embodiments.

[0151] Memory devices 100, 200, and 600 may be included in devices (e.g., electronic circuits), such as high-speed computers, communication and signal processing circuits, single-processor or multi-processor modules, single or multiple embedded processors, multi-core processors, message switches, and dedicated modules, including multi-layer and multi-chip modules. These devices may be further included as sub-components within a variety of other devices (e.g., electronic systems) (e.g., televisions, cellular phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, set-top boxes, etc.).

[0152] The above reference Figures 1 to 17B The described embodiments include an apparatus and a method of forming said apparatus. One of the apparatuses includes: a first dielectric material; a second dielectric material separate from the first dielectric material; a string of memory cells including posts extending through the first dielectric material and the second dielectric material, the posts including portions between the first dielectric material and the second dielectric material; an additional dielectric material contacting said portions of the posts; a conductive material contacting the additional dielectric material; and a tungsten structure including a tungsten portion contacting the conductive material, wherein a majority of said tungsten portion is β-phase tungsten. Other embodiments including additional apparatus and methods are described.

[0153] In the detailed description and claims, the terms "on" or "one on" another, used in relation to two or more elements (e.g., materials), imply at least some contact between the elements (e.g., between materials). The term "above" implies that the elements (e.g., materials) are very close together, but may have one or more additional intervening elements (e.g., materials) that make contact possible but not required. Neither "on" nor "above" implies any directionality as used herein unless stated otherwise.

[0154] In the detailed description and claims, the list of items joined by the term "at least one of" can mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A, only B, only C, A and B (excluding C), A and C (excluding B), B and C (excluding A); or all A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0155] In the detailed description and claims, a list of items joined by the term "one of" can mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another instance, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0156] The foregoing description and figures illustrate some embodiments of the subject matter of this invention to enable those skilled in the art to practice these embodiments. Other embodiments may have structural, logical, electrical, technological, and other variations. The examples represent only possible variations. Parts and features of some embodiments may be included in or replace those parts and features of other embodiments. After reading and understanding the foregoing description, those skilled in the art will understand many other embodiments.

Claims

1. An apparatus comprising: First dielectric material; The second dielectric material is separate from the first dielectric material; A memory cell string comprising posts extending through a first dielectric material and a second dielectric material, the posts comprising portions between the first dielectric material and the second dielectric material; The control gate associated with the memory cell string; Additional dielectric material that contacts the portion of the guide post; A conductive material that contacts the additional dielectric material; as well as A tungsten structure comprising a tungsten portion in contact with the conductive material, wherein the tungsten structure is part of the control gate, and wherein more than 50% of the tungsten portion by volume is β-phase tungsten, wherein the tungsten portion is converted from a silicon material comprising silicon and a dopant selected from chlorine, arsenic, and phosphorus, and wherein the tungsten structure comprises an additional tungsten portion in contact with the tungsten portion, and more than 50% of the additional tungsten portion by volume is α-phase tungsten, and wherein more than 50% of the additional tungsten portion by volume has a grain size of at least 80 nanometers.

2. The device of claim 1, wherein at least 50% of the additional tungsten portion has a grain size of at least 100 nanometers.

3. The device of claim 1, wherein the additional dielectric material comprises aluminum oxide.

4. The device according to claim 1, wherein the first dielectric material and the second dielectric material have the same dielectric material.

5. The device according to claim 1, wherein the conductive material contains titanium.

6. The device according to claim 1, wherein the conductive material has a thickness in the range of 2 nanometers to 5 nanometers.

7. The device according to claim 1, wherein the conductive material has a discontinuous structure.

8. An apparatus comprising: First dielectric material; The second dielectric material is separate from the first dielectric material; A memory cell string comprising posts extending through the first dielectric material and the second dielectric material, the posts comprising additional dielectric material between the first dielectric material and the second dielectric material; The control gate associated with the memory cell string; A conductive material that contacts the additional dielectric material; as well as A tungsten structure comprising a tungsten portion in contact with the conductive material, wherein the tungsten structure is part of the control gate, and wherein more than 50% of the tungsten portion by volume is β-phase tungsten, wherein the tungsten portion is converted from a silicon material comprising silicon and a dopant selected from chlorine, arsenic, and phosphorus, and wherein the tungsten structure comprises an additional tungsten portion in contact with the tungsten portion, and more than 50% of the additional tungsten portion by volume is α-phase tungsten, and wherein more than 50% of the additional tungsten portion by volume has a grain size of at least 80 nanometers.

9. The device of claim 8, wherein at least 50% of the additional tungsten portion has a grain size of at least 100 nanometers.

10. The device of claim 8, wherein the additional dielectric material comprises aluminum oxide.

11. The device of claim 8, wherein the first dielectric material and the second dielectric material have the same dielectric material.

12. The device according to claim 8, wherein the conductive material contains titanium.

13. An apparatus comprising: First dielectric material; The second dielectric material is separate from the first dielectric material; A memory cell string comprising posts extending through a first dielectric material and a second dielectric material, the posts comprising portions between the first dielectric material and the second dielectric material; The control gate associated with the memory cell string; An additional dielectric material, which contacts the portion of the post, wherein the dielectric constant of the additional dielectric material is greater than that of silicon dioxide; A conductive material, which contacts the additional dielectric material, the conductive material containing titanium; and A tungsten structure comprising a tungsten portion in contact with the conductive material, wherein the tungsten structure is part of the control gate, and wherein more than 50% of the tungsten portion by volume is β-phase tungsten, wherein the tungsten portion is converted from a silicon material comprising silicon and a dopant selected from chlorine, arsenic, and phosphorus, and wherein the tungsten structure comprises an additional tungsten portion in contact with the tungsten portion, and more than 50% of the additional tungsten portion by volume is α-phase tungsten, and wherein more than 50% of the additional tungsten portion by volume has a grain size of at least 80 nanometers.

14. The device of claim 13, wherein the additional dielectric material comprises aluminum oxide.

15. The device of claim 13, wherein the first dielectric material and the second dielectric material have the same dielectric material.

16. The device of claim 13, wherein the conductive material comprises titanium silicon nitride.

17. The device of claim 13, wherein the conductive material comprises titanium nitride.

18. An apparatus comprising: A control gate for a string of memory cells, the control gate being interleaved with a dielectric material, the control gate comprising a control gate located between a first dielectric material and a second dielectric material of the dielectric material; The memory cell string has a post that extends through the control gate and the dielectric material, the post including a portion between the first dielectric material and the second dielectric material; An additional dielectric material is formed on the portion of the post, the first dielectric material of the dielectric material, and the second dielectric material of the dielectric material, wherein the dielectric constant of the additional dielectric material is at least equal to the dielectric constant of aluminum oxide; A conductive material formed on the additional dielectric material, the conductive material containing titanium; and A tungsten structure comprising a tungsten portion in contact with the conductive material, wherein the tungsten structure is part of the control gate, and wherein more than 50% of the tungsten portion by volume is β-phase tungsten, wherein the tungsten portion is converted from a silicon material comprising silicon and a dopant selected from chlorine, arsenic, and phosphorus, and wherein the tungsten structure comprises an additional tungsten portion in contact with the tungsten portion, and more than 50% of the additional tungsten portion by volume is α-phase tungsten, and wherein more than 50% of the additional tungsten portion by volume has a grain size of at least 80 nanometers.

19. The device of claim 18, wherein the conductive material comprises titanium silicon nitride.

20. The device of claim 18, wherein the conductive material comprises titanium nitride.

21. The device of claim 18, wherein the first dielectric material and the second dielectric material have the same dielectric material.

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