Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present disclosure disclose a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate comprising a plurality of active regions; a bit line structure above the active regions, the bit line structure comprising a plurality of bit lines extending along a first direction and a plurality of contact plugs, the contact plugs electrically connecting the bit lines and the active regions, the first direction being parallel to a surface of the substrate; an isolation structure comprising a first insulating layer, a second insulating layer and a third insulating layer; the first insulating layer comprising a first part and a second part below the first part; the first part covering at least sidewalls of the bit lines, the second part covering at least sidewalls of the contact plugs; the second insulating layer covering a surface of the second part, the third insulating layer covering at least a surface of the first part.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In semiconductor devices, dielectric material is formed between conductive lines (e.g., bit lines). As the feature size of semiconductor devices continues to shrink, the distance between conductive lines gradually decreases, leading to a deterioration in the performance of the semiconductor devices. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0004] Substrate, the substrate comprising a plurality of active regions;

[0005] A bit line structure is located above the active region. The bit line structure includes multiple bit lines extending along a first direction and multiple contact plugs. The contact plugs are electrically connected to the bit lines and the active region. The first direction is parallel to the surface of the substrate.

[0006] An isolation structure includes a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer includes a first portion and a second portion located below the first portion; the first portion at least covers the sidewall of the bit line, the second portion at least covers the sidewall of the contact plug; the second insulating layer covers the surface of the second portion, and the third insulating layer at least covers the surface of the first portion.

[0007] In some embodiments, the dielectric constant of the second portion is greater than that of the first portion, and the dielectric constants of the second insulating layer and the third insulating layer are greater than that of the second portion.

[0008] In some embodiments, the material of the first portion includes silicon oxide, and the material of the second portion includes silicon carbon oxide.

[0009] In some embodiments, the thickness of the first insulating layer is 4 nanometers to 8 nanometers.

[0010] In some embodiments, the material of the second insulating layer may be the same as or different from the material of the third insulating layer.

[0011] In some embodiments, the materials of the second insulating layer and the third insulating layer include any one of silicon nitride, silicon oxide nitride, or silicon carbon nitride.

[0012] In some embodiments, the bit line structure further includes a protective layer covering the surface of the bit line away from the substrate, and the first portion also covers the surface of the protective layer.

[0013] In some embodiments, the bit line includes a first conductive line and a second conductive line, the first conductive line being located above the second conductive line; the contact plug includes a first conductive plug and a second conductive plug, the first conductive plug being located above the second conductive plug, the first conductive plug being electrically connected to the second conductive line, and the second conductive plug being electrically connected to the active region.

[0014] In some embodiments, the material of the first conductive wire includes tungsten or molybdenum, the material of the second conductive wire includes titanium nitride, the material of the first conductive plug includes metal silicide, and the material of the second conductive plug includes polycrystalline silicon.

[0015] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0016] Provides a substrate comprising multiple active regions;

[0017] A bit line structure electrically connected to the active region is formed; wherein the bit line structure includes multiple bit lines extending along a first direction and multiple contact plugs, the contact plugs electrically connecting the bit lines and the active region, and the first direction is parallel to the surface of the substrate;

[0018] An isolation structure is formed covering the bit line structure; wherein the isolation structure includes a first insulating layer, a second insulating layer and a third insulating layer; the first insulating layer includes a first portion and a second portion located below the first portion; the first portion at least covers the sidewall of the bit line, the second portion at least covers the sidewall of the contact plug; the second insulating layer covers the surface of the second portion, and the third insulating layer at least covers the surface of the first portion.

[0019] In some embodiments, the bit line structure forming an electrical connection with the active region includes:

[0020] The substrate is etched to form a plurality of contact holes, the contact holes exposing the active region, and the contact holes are filled to form a conductive contact material layer. The conductive contact material layer has a first surface and a second surface disposed opposite to each other, the first surface being in contact with the active region, and the size of the first surface being smaller than the size of the second surface.

[0021] A conductive material layer is formed covering the substrate and the conductive contact material layer;

[0022] The conductive material layer is etched to form a plurality of grooves extending along the first direction, and the conductive material layer between two adjacent grooves forms the bit line;

[0023] The conductive contact material layer exposed by the groove is etched to form a gap, and the remaining conductive contact material layer forms the contact plug, with the gap located on both sides of the contact plug.

[0024] In some embodiments, forming the isolation structure covering the bit line structure includes:

[0025] A first insulating material layer is formed, which covers the surface of the gap, the sidewalls of the bit line structure, and the surface of the substrate;

[0026] A second insulating material layer is formed, which covers the surface of the first insulating material layer;

[0027] Remove part of the second insulating material layer, leaving only the second insulating material layer located in the gap, to form the second insulating layer;

[0028] A portion of the first insulating material layer is oxidized to form a first portion of the first insulating layer;

[0029] A third insulating material layer is formed, which covers the surface of the second insulating layer and the first portion.

[0030] In some embodiments, the oxidation treatment of a portion of the first insulating material layer includes:

[0031] Oxygen plasma is used to oxidize the top and sidewalls of the bit line structure and the first insulating material layer on the substrate surface.

[0032] In some embodiments, the material of the first insulating material layer includes silicon carbide, and the material of the first portion includes silicon oxide; the materials of the second insulating material layer and the third insulating material layer include any one of silicon nitride, silicon nitride, or silicon carbide.

[0033] In some embodiments, prior to forming the first insulating material layer, the preparation method further includes forming a protective layer that covers the surface of the bit line away from the substrate.

[0034] In this embodiment of the disclosure, by setting an isolation structure, the isolation structure includes a first insulating layer, a second insulating layer and a third insulating layer, and the first insulating layer includes a first part and a second part located below the first part. Since the first part covers the sidewall of the bit line, the second part covers the sidewall of the contact plug, the second insulating layer covers the surface of the second part, and the third insulating layer covers at least the surface of the first part, the dielectric constant of the isolation structure as a whole can be reduced, which is beneficial to reducing the parasitic capacitance between the bit line structures.

[0035] Furthermore, the reduction in parasitic capacitance between bit line structures helps to improve the sensing margin of the semiconductor structure, thereby improving the operational performance of the semiconductor structure. Attached Figure Description

[0036] Figure 1 a This is a circuit connection diagram of a memory according to an exemplary embodiment;

[0037] Figure 1 b This is a cross-sectional view of a memory according to an exemplary embodiment;

[0038] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0039] Figures 3 to 9 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure;

[0040] Figure 10 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0041] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0042] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0043] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0044] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0045] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0046] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0047] Dynamic Random Access Memory (DRAM) consists of multiple memory cells, each of which includes a transistor (T) and a capacitor (C) coupled to the transistor. That is, DRAM has a 1T1C architecture.

[0048] Figure 1 a This is a schematic diagram of the circuit connections of a memory 100 according to an exemplary embodiment. (Refer to...) Figure 1 a As shown, the source or drain of transistor 110 is coupled to bit line (BL) 130, and the drain or source of transistor 110 is coupled to one plate of capacitor 120, the other plate of capacitor 120 is grounded, and the gate of transistor 110 is coupled to word line 140. Applying a voltage to word line 140 controls the on / off state of transistor 110; bit line 130 is used to perform read or write operations on capacitor 120 when transistor 110 is on. Here, bit line 130 and word line 140 are electrically insulated from each other.

[0049] As the size of the memory 100 shrinks and the frequency requirements increase, the capacitance value of the capacitor 120 becomes lower and lower. In order to ensure normal read and write operations of the memory 100, the parasitic capacitance of the bit line 130 needs to be reduced as much as possible to ensure normal sense margin.

[0050] Figure 1 b A cross-sectional view of the memory 100 is shown. An isolation structure 104 covers the sidewalls and top of the bit line 130. The isolation structure 104 comprises a composite film of silicon nitride layer 101, silicon oxide layer 102, and silicon nitride layer 103 (SiN-SiO2-SiN, NON). Due to the high dielectric constant of silicon nitride, the overall dielectric constant of the isolation structure is high, resulting in significant parasitic capacitance between the bit lines 130. This reduces the sensing margin of the memory 100, affecting its normal read and write operations.

[0051] In view of this, the present disclosure provides a semiconductor structure and a method for preparing the same.

[0052] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. (Refer to...) Figure 2 As shown, the method includes at least the following steps:

[0053] S110: Provides a substrate including multiple active regions;

[0054] S120: Forming a bit line structure electrically connected to the active region; wherein the bit line structure includes multiple bit lines extending along a first direction and multiple contact plugs, the contact plugs electrically connecting the bit lines and the active region, and the first direction being parallel to the surface of the substrate.

[0055] S130: An isolation structure is formed to cover the bit line structure; wherein the isolation structure has a first insulating layer, a second insulating layer and a third insulating layer; the first insulating layer includes a first portion and a second portion located below the first portion; the first portion at least covers the sidewall of the bit line, and the second portion at least covers the sidewall of the contact plug; the second insulating layer covers the surface of the second portion, and the third insulating layer at least covers the surface of the first portion.

[0056] In this embodiment of the disclosure, by forming a bit line structure electrically connected to the active region, the bit line structure includes multiple bit lines extending along a first direction and multiple contact plugs, as well as forming an isolation structure covering the bit line structure. Since the isolation structure includes a first insulating layer, a second insulating layer and a third insulating layer, a first portion of the first insulating layer at least covers the sidewalls of the bit lines, a second portion of the first insulating layer at least covers the sidewalls of the contact plugs, the second insulating layer covers the surface of the second portion, and the third insulating layer at least covers the surface of the first portion, the overall dielectric constant of the isolation structure can be reduced, which is beneficial to reducing the parasitic capacitance between the bit line structures.

[0057] Furthermore, the reduction in parasitic capacitance between bit line structures helps to improve the sensing margin of the semiconductor structure, thereby improving the operational performance of the semiconductor structure.

[0058] Figures 3 to 9 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure. The following will be combined with… Figure 2 , Figures 3 to 9 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0059] First, refer to Figure 3 As shown, step S110 is performed: a substrate 201 including multiple active regions 2021 is provided. Multiple active regions 2021 can be formed in the substrate 201 by processes such as thin film deposition, etching and doping.

[0060] Thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. Etching processes include, but are not limited to, dry etching, wet etching, or combinations thereof. Doping processes include, but are not limited to, ion implantation or ion diffusion.

[0061] The substrate 201 may be made of elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0062] The active region 2021 contains doped semiconductor materials, such as doped monocrystalline silicon, doped polycrystalline silicon, or doped amorphous silicon. The dopants in the active region 2021 include P-type dopants or N-type dopants.

[0063] Then, step S120 is performed: forming bit line structure 205 electrically connected to active region 2021.

[0064] In some embodiments, combined with Figure 3 and Figure 4 As shown, step S120 above includes:

[0065] The substrate is etched to form multiple contact holes, the contact holes expose the active region 2021, and the contact holes are filled to form a conductive contact material layer 203'. The conductive contact material layer 203' has a first surface and a second surface disposed opposite to each other. The first surface contacts the active region 2021, and the size of the first surface is smaller than the size of the second surface.

[0066] A conductive material layer is formed covering the substrate 201 and the conductive contact material layer 203';

[0067] A portion of the conductive material layer is etched to form a plurality of grooves 2051 extending along a first direction, and a bit line 204 is formed between two adjacent grooves 2051 in the conductive material layer.

[0068] The conductive contact material layer 203' exposed by the etched groove 2051 forms a gap 2031, and the remaining conductive contact material layer 203' is a contact plug 203, with the gap 2031 located on both sides of the contact plug 203.

[0069] For example, combined Figure 3As shown, the insulating layer covering the active region 2021 is etched to form multiple contact holes. The bottom of the contact holes exposes the active region 2021, and the size of the bottom of the contact hole is smaller than the size of the top of the contact hole. Conductive contact material is deposited into the contact holes to form a conductive contact material layer 203'. The first surface of the conductive contact material layer 203' contacts the active region 2021, and the second surface of the conductive contact material layer 203' is substantially flush with the insulating layer.

[0070] For example, a conductive material layer covering the substrate 201 and the conductive contact material layer 203' is formed by a thin film deposition process. The conductive material layer is etched downward along the z direction to form a plurality of grooves 2051 arranged side by side along the x direction. The conductive material layer between two adjacent grooves 2051 is a bit line 204. Both the grooves 2051 and the bit lines 204 extend along the y direction.

[0071] It should be noted that the first direction, the second direction, and the third direction used in this disclosure refer to the y direction, the x direction, and the z direction, respectively. The first direction and the second direction are both parallel to the surface of the substrate and intersect each other. The third direction is perpendicular to the surface of the substrate, and will not be described again hereafter.

[0072] For example, the conductive contact material layer 203' is etched downward through the groove 2051 to form a gap 2031. The remaining conductive contact material layer 203' serves as a contact plug 203. The gap 2031 is located on both sides of the contact plug 203. The contact plug 203 is located between the active region 2021 and the bit line 204, and contacts both the active region 2021 and the bit line 204. Here, the bit line structure 205 includes the contact plug 203 and the bit line 204.

[0073] In some embodiments, bit line 204 may be a single film layer, such as a tungsten metal layer. In other embodiments, bit line 204 may be a composite film layer. In one specific embodiment, bit line 204 includes a first conductive line and a second conductive line, with the first conductive line located above the second conductive line, i.e., the second conductive line is located between the contact plug 203 and the first conductive line. The material of the first conductive line includes tungsten or molybdenum, and the material of the second conductive line includes titanium nitride. By providing a composite bit line including the first conductive line and the second conductive line, the second conductive line can act as a barrier layer to prevent the diffusion of the material of the first conductive line, avoiding the increase in contact resistance caused by the diffusion of the material of the first conductive line, thereby ensuring the stability of the electrical performance of the composite bit line.

[0074] In some embodiments, the contact plug 203 may be a single film layer, such as a polycrystalline silicon layer. In other embodiments, the contact plug 203 may be a composite film layer. In one specific embodiment, the contact plug 203 includes a first conductive plug and a second conductive plug. The first conductive plug is located above the second conductive plug, that is, the first conductive plug is located between the second conductive plug and the bit line 204. Specifically, the first conductive plug is located between the second conductive plug and the second conductive line. The first conductive plug is electrically connected to the second conductive line, and the second conductive plug is electrically connected to the active region 2021. The material of the first conductive plug includes metal silicides, such as cobalt silicide (CoSi), nickel silicide (NiSi), or titanium silicide (TiSi). The material of the second conductive plug includes semiconductor materials or doped semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon, or doped polycrystalline silicon. By providing a composite contact plug including the first conductive plug and the second conductive plug, the first conductive plug can serve as a connection layer, reducing the contact resistance between the bit line and the second conductive plug.

[0075] Finally, refer to Figures 4 to 9 As shown, step S130 is performed: forming an isolation structure covering the bit line structure 205; wherein, the isolation structure includes a first insulating layer 207, a second insulating layer 208, and a third insulating layer 209; the first insulating layer 207 includes a first portion 207a and a second portion 207b located below the first portion 207a; the first portion 207a at least covers the sidewall of the bit line 204, and the second portion 207b at least covers the sidewall of the contact plug 203; the second insulating layer 208 covers the surface of the second portion 207b, and the third insulating layer 209 at least covers the surface of the first portion 207a.

[0076] In some embodiments, combined with Figures 4 to 8 As shown, step S130 above includes:

[0077] A first insulating material layer 207' is formed, which covers the surface of the gap 2031, the sidewall of the bit line structure 205, and the surface of the substrate 201.

[0078] A second insulating material layer 208' is formed, which covers the surface of the first insulating material layer 207';

[0079] Part of the second insulating material layer 208' is removed, leaving only the second insulating material layer 208' located in the gap, to form the second insulating layer 208;

[0080] A portion of the first insulating material layer 207' is oxidized to form a first portion 207a of the first insulating layer;

[0081] A third insulating material layer 209 is formed, which covers the surface of the second insulating layer 208 and the first portion 207a.

[0082] For example, the first insulating material layer 207' can be sequentially formed by a thin film deposition process (e.g., ...). Figure 5 (as shown) and the second insulating material layer 208' (as shown) Figure 6 (As shown). The first insulating material layer 207' covers the surface of the gap 2031, the sidewall of the bit line structure 205, and the surface of the substrate 201. The material of the first insulating material layer 207' includes silicon carbide, for example, silicon carbon oxide (SiCO). The second insulating material layer 208' covers the first insulating material layer 207'. The material of the second insulating material layer 208' includes any one of silicon nitride, silicon nitride, or silicon carbon nitride.

[0083] For example, a portion of the second insulating material layer 208' can be removed by an etching process to form such a Figure 7 The structure shown. (Refer to...) Figure 7 As shown, the remaining second insulating material layer 208' is located within the gap and is referred to as the second insulating layer 208.

[0084] Exemplarily, after removing a portion of the second insulating material layer 208', the first insulating material layer 207' covering the sidewalls and top of the bit line 204 and the surface of the substrate 201 is exposed. This exposed first insulating material layer 207' is then oxidized to form a structure as shown below. Figure 8 The first portion 207a shown has an unoxidized first insulating material layer 207' located within the gap and between the contact plug 203 and the second insulating layer 208, referred to as the second portion 207b. Here, the second portion 207b and the second insulating layer 208 within the gap protect the contact plug 203 and reduce the probability of oxidation of the contact plug 203. Simultaneously, the second portion 207b within the gap is made of silicon carbide, and the second insulating layer 208 is made of silicon nitride. The isolation layer formed by the second portion 207b and the second insulating layer 208 provides better protection against leakage between the bit line contact plug and the storage node plug compared to an isolation layer formed by conventional silicon dioxide and silicon nitride layers.

[0085] It should be understood that the first insulating layer 207 includes a first portion 207a and a second portion 207b. The material of the first portion 207a includes silicon oxide, for example, silicon oxyoxide. In this example, the dielectric constant of the first portion 207a is less than the dielectric constant of the second portion 207b, and the dielectric constant of the second portion 207b is less than the dielectric constant of the second insulating layer 208. In a specific example, the first portion 207a is silicon oxide with a dielectric constant of 3.9, the second portion 207b is silicon carbide with a dielectric constant of 4.5, and the second insulating layer 208 is silicon nitride with a dielectric constant of 7.9.

[0086] In some embodiments, the oxidation treatment includes any one or a combination of plasma oxidation treatment, thermal oxidation treatment, or wet oxidation treatment.

[0087] In one specific embodiment, the oxidation treatment of a portion of the first insulating material layer 207' includes: oxidizing the first insulating material layer 207' located on the top and sidewalls of the bit line structure, as well as on the substrate surface, using oxygen plasma. It should be noted that using oxygen plasma to oxidize the first insulating material layer 207' can lower the oxidation temperature, which helps to reduce heat consumption.

[0088] For example, a third insulating material layer, denoted as third insulating layer 209, can be formed by a thin film deposition process. Figure 9 As shown, the third insulating layer 209 covers the second insulating layer 208 and the first portion 207a. The material of the third insulating layer 209 includes any one of silicon nitride, silicon oxide nitride, or silicon carbon nitride. In a specific example, the material of the third insulating layer 209 is the same as the material of the second insulating layer 208.

[0089] In this embodiment of the disclosure, by sequentially depositing a first insulating material layer and a second insulating material layer, and then removing part of the second insulating material layer to expose the first insulating material layer covering the sidewalls and top of the bit line, and oxidizing the first insulating material layer, a first part with a dielectric constant lower than that of the first insulating material layer can be formed. This is beneficial to reduce the overall dielectric constant of the isolation structure, thereby reducing the parasitic capacitance between the bit lines.

[0090] Furthermore, the preparation method provided in this embodiment can form a composite isolation structure including a first insulating layer, a second insulating layer, and a third insulating layer, which is beneficial to improving the electrical isolation performance of the isolation structure and reducing the probability of leakage in the semiconductor structure.

[0091] In addition, the second part and the second insulating layer located in the gap can protect the contact plug during the oxidation process, reduce the probability of the contact plug being oxidized, and help ensure the stability of the electrical performance of the contact plug.

[0092] In some embodiments, before forming the first insulating material layer 207', the above preparation method further includes:

[0093] A protective layer 206 is formed, which covers the surface of bit line 204 away from substrate 201.

[0094] For example, a conductive material layer and a protective material layer covering the substrate 201 and the conductive contact material layer 203' can be formed by a thin film deposition process, and the protective material layer and the conductive material layer can be etched downward along the z-direction to form a structure as shown in the figure. Figure 4 The groove 2051 shown has a protective material layer 206 between adjacent grooves 2051. The material of the protective layer 206 includes any one of silicon nitride, silicon oxide nitride, or silicon carbon nitride, for example, silicon nitride. In a specific example, the material of the protective layer 206 is the same as the material of the second insulating layer 208.

[0095] In this embodiment of the disclosure, by forming a protective material layer covering the conductive material layer, the protective material layer can protect the conductive material layer, reduce the damage to the conductive material layer caused by the etching process, and help ensure the electrical performance of the bit line.

[0096] In some embodiments, refer to Figure 3 As shown, substrate 201 further includes a channel region 2023 located between the first active region 2021 and the second active region 2022; the above method further includes:

[0097] A gate dielectric layer and a word line structure are formed within a substrate 201; wherein the gate dielectric layer is located between the word line structure and the channel region 2023, the word line structure extends along a second direction, the second direction is parallel to the surface of the substrate, and the second direction intersects with the first direction;

[0098] A second contact plug coupled to the second active region 2022 is formed on the second active region 2022.

[0099] For example, a first active region 2021 and a second active region 2022 can be formed in a substrate 201 through processes such as thin film deposition, etching, and doping. The second active region 2022 includes a doped semiconductor material, such as doped monocrystalline silicon, doped polycrystalline silicon, or doped amorphous silicon. The dopants in the second active region 2022 include P-type dopants or N-type dopants.

[0100] The first active region 2021 can serve as the source or drain of the transistor, the second active region 2022 can serve as the drain or source of the transistor, and the substrate portion located between the first active region 2021 and the second active region 2022 can serve as the channel region 2023 of the transistor.

[0101] For example, a gate dielectric layer (not shown in the figure) covering the first active region 2021, the second active region 2022 and the channel region 2023 is formed, a gate layer covering the gate dielectric layer is formed, the gate layer can serve as the control gate of the transistor for controlling the transistor to be turned on or off, and a word line (not shown in the figure) extending in a direction parallel to the x-axis is formed. The word line is coupled to the gate layer. Here, the word line structure includes the gate layer and the word line.

[0102] The fabrication process of the second contact plug coupled to the second active region 2022 can be similar to the fabrication process of the contact plug 203 described above, and will not be repeated here.

[0103] In some embodiments, the method further includes: forming a capacitor electrically connected to a second contact plug; wherein the capacitor includes a first plate, an inter-plate dielectric layer and a second plate, and the second contact plug is electrically connected to a second active region 2022 and the first plate.

[0104] For example, a capacitor (not shown in the figure) electrically connected to the second contact plug can be formed through processes such as thin film deposition, photolithography, and etching. The materials of the first and second plates include conductive materials, such as tungsten, platinum, copper, titanium, and aluminum, while the material of the inter-plate dielectric layer can be a dielectric material, such as silicon oxide. The material of the inter-plate dielectric layer can also be a ferroelectric material, such as hafnium oxide or chromium oxide.

[0105] Figure 10 This is a schematic diagram of a semiconductor structure 300 according to an embodiment of the present disclosure. (Refer to...) Figure 10 As shown, the semiconductor structure 300 includes:

[0106] Substrate 301, which includes multiple active regions 3021;

[0107] Bit line structure 305 is located above active region 3021. Bit line structure 305 includes bit line 304 extending along a first direction and a plurality of contact plugs 303. Contact plugs 303 are electrically connected to bit line 304 and active region 3021. The first direction is parallel to the surface of substrate 301.

[0108] The isolation structure 310 includes a first insulating layer 307, a second insulating layer 308, and a third insulating layer 309. The first insulating layer 307 includes a first portion 307a and a second portion 307b located below the first portion 307a. The first portion 307a at least covers the sidewall of the bit line 304, and the second portion 307b at least covers the sidewall of the contact plug 303. The second insulating layer 308 covers the surface of the second portion 307b, and the third insulating layer 309 at least covers the surface of the first portion 307a.

[0109] The substrate 301 may be made of elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0110] The active region 3021 includes doped semiconductor materials, such as doped monocrystalline silicon, doped polycrystalline silicon, or doped amorphous silicon. The dopants in the active region 3021 include P-type dopants or N-type dopants.

[0111] The materials of the contact plug 303 include semiconductor materials or doped semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon or doped polycrystalline silicon, etc.

[0112] Bit line 304 extends along the y-direction. In some embodiments, bit line 304 may be a single film layer, such as a tungsten metal layer. In other embodiments, bit line 304 may also be a composite film layer. In one specific embodiment, bit line 304 includes a first conductive line and a second conductive line, with the first conductive line located above the second conductive line, i.e., the second conductive line is located between the contact plug 303 and the first conductive line. The material of the first conductive line includes tungsten or molybdenum, and the material of the second conductive line includes titanium nitride. By providing a composite bit line including a first conductive line and a second conductive line, the second conductive line can act as a barrier layer to prevent the diffusion of the material of the first conductive line, avoiding the increase in contact resistance caused by the diffusion of the material of the first conductive line, thereby ensuring the stability of the electrical performance of the composite bit line.

[0113] In some embodiments, the contact plug 303 may be a single film layer, such as a polycrystalline silicon layer. In other embodiments, the contact plug 303 may be a composite film layer. In one specific embodiment, the contact plug 303 includes a first conductive plug and a second conductive plug. The first conductive plug is located above the second conductive plug, that is, the first conductive plug is located between the second conductive plug and the bit line 304. Specifically, the first conductive plug is located between the second conductive plug and the second conductive line. The first conductive plug is electrically connected to the second conductive line, and the second conductive plug is electrically connected to the active region 3021. The material of the first conductive plug includes metal silicides, such as cobalt silicide (CoSi), nickel silicide (NiSi), or titanium silicide (TiSi). The material of the second conductive plug includes semiconductor materials or doped semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, doped monocrystalline silicon, or doped polycrystalline silicon. By providing a composite contact plug including the first conductive plug and the second conductive plug, the first conductive plug can serve as a connection layer, reducing the contact resistance between the bit line and the second conductive plug.

[0114] The isolation structure 310 covers the bit line structure 305. Specifically, the isolation structure 310 includes a first insulating layer 307, a second insulating layer 308, and a third insulating layer 309. The first insulating layer 307 includes a first portion 307a and a second portion 307b located below the first portion 307a. The second portion 307b covers the sidewall of the contact plug 303. The second insulating layer 308 covers the surface of the second portion 307b. The first portion 307a covers the sidewall and top of the bit line 304, as well as the surface of the substrate 301. The third insulating layer 309 covers the surface of the first portion 307a and the second insulating layer 308. In one example, the top surface of the second insulating layer 308 is substantially flush with the top surface of the first portion 307a covering the surface of the substrate 301.

[0115] The material of the first part 307a includes silicon oxide, such as silicon oxide; the material of the second part 307b includes silicon carbide, such as silicon carbon oxide (SiCO); and the materials of the second insulating layer 308 and the third insulating layer 309 include any one of silicon nitride, silicon oxide nitride, or silicon carbon nitride, such as silicon nitride. In some embodiments, the materials of the second insulating layer 308 and the third insulating layer 309 are the same; in other embodiments, the materials of the second insulating layer 308 and the third insulating layer 309 are different.

[0116] In this embodiment of the disclosure, by setting an isolation structure, the isolation structure includes a first insulating layer, a second insulating layer and a third insulating layer, and the first insulating layer includes a first part and a second part located below the first part. Since the first part covers the sidewall of the bit line, the second part covers the sidewall of the contact plug, the second insulating layer covers the surface of the second part, and the third insulating layer covers at least the surface of the first part, the dielectric constant of the isolation structure as a whole can be reduced, which is beneficial to reducing the parasitic capacitance between the bit line structures.

[0117] Furthermore, the reduction in parasitic capacitance between bit line structures helps to improve the sensing margin of the semiconductor structure, thereby improving the operational performance of the semiconductor structure.

[0118] In some embodiments, the dielectric constant of the second portion 307b is greater than that of the first portion 307a, and the dielectric constants of the second insulating layer 308 and the third insulating layer 309 are greater than that of the second portion 307b.

[0119] In a specific example, the first part 307a is silicon oxide with a dielectric constant of 3.9, the second part 307b is silicon carbide with a dielectric constant of 4.5, and the second insulating layer 308 and the third insulating layer 309 are silicon nitride with a dielectric constant of 7.9.

[0120] In this embodiment of the disclosure, by setting the dielectric constant of the second part to be greater than that of the first part, that is, the dielectric constant of the first part covering the bit line sidewall and top is less than that of the second part covering the contact plug sidewall, it is beneficial to reduce the parasitic capacitance between bit lines.

[0121] Furthermore, by setting a composite isolation structure including a first insulating layer, a second insulating layer, and a third insulating layer, it is beneficial to improve the electrical isolation performance of the isolation structure and reduce the probability of leakage in the semiconductor structure.

[0122] In some embodiments, the thickness of the first insulating layer 307 ranges from 4 nanometers to 8 nanometers.

[0123] In some embodiments, refer to Figure 10 As shown, the semiconductor structure 300 further includes a protective layer 306, which covers the surface of the bit line 304 away from the substrate 301, and a first portion 307a also covers the surface of the protective layer 306.

[0124] In this embodiment of the disclosure, by providing a protective layer covering the bit lines, the protective layer can protect the bit lines, reduce the damage to the bit lines caused by the manufacturing process, and help ensure the electrical performance of the bit lines.

[0125] In some embodiments, the semiconductor structure 300 further includes:

[0126] Channel region 3023 is located between the first active region 3021 and the second active region 3022;

[0127] The second contact plug is located on the second active region 3022 and is coupled to the second active region 3022;

[0128] The word line structure is located within the substrate 301 and extends along a second direction; wherein the second direction is parallel to the surface of the substrate 301 and intersects with the first direction;

[0129] The character line structure covers the 3023 channel area;

[0130] The gate dielectric layer is located between the word line structure and the channel region 3023.

[0131] The second active region 3022 includes a doped semiconductor material, such as doped monocrystalline silicon, doped polycrystalline silicon, or doped amorphous silicon. The dopants in the second active region 3022 include P-type dopants or N-type dopants.

[0132] The first active region 3021 can be used as the source or drain of the transistor, the second active region 3022 can be used as the drain or source of the transistor, and the substrate portion located between the first active region 3021 and the second active region 3022 can be used as the channel region 3023 of the transistor.

[0133] A gate dielectric layer (not shown in the figure) covers the first active region 3021, the second active region 3022, and the channel region 3023. A gate layer (not shown in the figure) covers the gate dielectric layer. The gate layer can serve as the control gate of the transistor, used to control the transistor's on or off state. A word line (not shown in the figure) extends in a direction parallel to the x-axis and is coupled to the gate layer. Here, the word line structure includes the gate layer and the word line itself.

[0134] In some embodiments, the semiconductor structure 300 further includes:

[0135] The capacitor includes a first plate, an inter-plate dielectric layer, and a second plate; wherein, a second contact plug is electrically connected to the second active region 3022 and the first plate.

[0136] The second contact plug (not shown in the figure) is located between the second active region 3022 and the capacitor (not shown in the figure) for electrically connecting the second active region 3022 and the capacitor. The material of the second contact plug can be the same as the material of the contact plug 303, which will not be described in detail here.

[0137] The materials of the first and second plates can be conductive materials, such as tungsten, platinum, copper, titanium, and aluminum. The material of the dielectric layer between the plates can be a dielectric material, such as silicon oxide. Alternatively, the material of the dielectric layer can be a ferroelectric material, such as hafnium oxide or chromium oxide.

[0138] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a plurality of active regions; A bit line structure is located above the active region. The bit line structure includes multiple bit lines extending along a first direction and multiple contact plugs. The contact plugs are electrically connected to the bit lines and the active region. The first direction is parallel to the surface of the substrate. An isolation structure is provided, comprising a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer comprises a first portion and a second portion located below the first portion; the first portion at least covers the sidewall of the bit line, and the second portion at least covers the sidewall of the contact plug; the second insulating layer covers the surface of the second portion, and the third insulating layer at least covers the surface of the first portion; the dielectric constant of the second portion is greater than the dielectric constant of the first portion, and the dielectric constants of the second insulating layer and the third insulating layer are greater than the dielectric constant of the second portion.

2. The semiconductor structure according to claim 1, characterized in that, The material of the first part includes silicon oxide, and the material of the second part includes silicon carbon oxide.

3. The semiconductor structure according to claim 1, characterized in that, The thickness of the first insulating layer is 4 nanometers to 8 nanometers.

4. The semiconductor structure according to claim 1, characterized in that, The material of the second insulating layer may be the same as or different from the material of the third insulating layer.

5. The semiconductor structure according to claim 4, characterized in that, The materials of the second insulating layer and the third insulating layer include any one of silicon nitride, silicon oxide nitride, or silicon carbon nitride.

6. The semiconductor structure according to claim 1, characterized in that, The bit line structure further includes a protective layer that covers the surface of the bit line away from the substrate, and the first portion also covers the surface of the protective layer.

7. The semiconductor structure according to claim 1, characterized in that, The bit line includes a first conductive line and a second conductive line, with the first conductive line located above the second conductive line; the contact plug includes a first conductive plug and a second conductive plug, with the first conductive plug located above the second conductive plug, the first conductive plug being electrically connected to the second conductive line, and the second conductive plug being electrically connected to the active region.

8. The semiconductor structure according to claim 7, characterized in that, The first conductive wire is made of tungsten or molybdenum, the second conductive wire is made of titanium nitride, the first conductive plug is made of metal silicide, and the second conductive plug is made of polycrystalline silicon.

9. A method for fabricating a semiconductor structure, characterized in that, include: Provides a substrate comprising multiple active regions; A bit line structure electrically connected to the active region is formed; wherein the bit line structure includes multiple bit lines extending along a first direction and multiple contact plugs, the contact plugs electrically connecting the bit lines and the active region, and the first direction is parallel to the surface of the substrate; An isolation structure is formed covering the bit line structure; wherein the isolation structure includes a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer includes a first portion and a second portion located below the first portion; the first portion at least covers the sidewall of the bit line, and the second portion at least covers the sidewall of the contact plug; the second insulating layer covers the surface of the second portion, and the third insulating layer at least covers the surface of the first portion, wherein the dielectric constant of the second portion is greater than the dielectric constant of the first portion, and the dielectric constants of the second insulating layer and the third insulating layer are greater than the dielectric constant of the second portion.

10. The preparation method according to claim 9, characterized in that, The bit line structure that forms an electrical connection with the active region includes: The substrate is etched to form a plurality of contact holes, the contact holes exposing the active region, and the contact holes are filled to form a conductive contact material layer. The conductive contact material layer has a first surface and a second surface disposed opposite to each other, the first surface being in contact with the active region, and the size of the first surface being smaller than the size of the second surface. A conductive material layer is formed covering the substrate and the conductive contact material layer; The conductive material layer is etched to form a plurality of grooves extending along the first direction, and the conductive material layer between two adjacent grooves forms the bit line; The conductive contact material layer exposed by the groove is etched to form a gap, and the remaining conductive contact material layer forms the contact plug, with the gap located on both sides of the contact plug.

11. The preparation method according to claim 10, characterized in that, The isolation structure forming the bit line structure includes: A first insulating material layer is formed, which covers the surface of the gap, the sidewalls of the bit line structure, and the surface of the substrate; A second insulating material layer is formed, which covers the surface of the first insulating material layer; Remove part of the second insulating material layer, leaving only the second insulating material layer located in the gap, to form the second insulating layer; A portion of the first insulating material layer is oxidized to form a first portion of the first insulating layer; A third insulating material layer is formed, which covers the surface of the second insulating layer and the first portion.

12. The preparation method according to claim 11, characterized in that, The oxidation treatment of a portion of the first insulating material layer includes: using oxygen plasma to oxidize the first insulating material layer located on the top and sidewalls of the bit line structure and on the surface of the substrate.

13. The preparation method according to claim 11, characterized in that, The material of the first insulating material layer includes silicon carbide, and the material of the first portion includes silicon oxide; the materials of the second insulating material layer and the third insulating material layer include any one of silicon nitride, silicon nitride, or silicon carbide.

14. The preparation method according to claim 11, characterized in that, Before forming the first insulating material layer, the preparation method further includes: forming a protective layer that covers the surface of the bit line away from the substrate.

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