Electronic device comprising two high electron mobility transistors

Abstract

Embodiments of the present disclosure relate to an electronic device comprising two high electron mobility transistors. The present disclosure relates to an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked one on top of the other. The main transistor and the additional transistor comprise a common drain electrode and respectively a main source electrode and an additional source electrode, arranged so that, when one and the other of these HEMT transistors are in an on state, a conductive path, possibly formed by two conductive layers, is connected in parallel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application FR2103238, filed on March 30, 2021, entitled "Electronic Device Including Two High Electron Mobility Transistors," which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to the field of electronic devices, and more specifically to the field of power electronic devices. More specifically, this disclosure relates to an electronic device having two high electron mobility transistors. Background Technology

[0004] High electron mobility transistors (“HEMTs”), as is well known to those skilled in the art, are now widely used in overclocking and as switches for power electronic converters.

[0005] In this respect, HEMT transistors are typically made of a layer of III-V semiconductor material and more specifically of a layer of III-N semiconductor material. Summary of the Invention

[0006] The device according to this disclosure is arranged to allow for better integration of two high electron mobility transistors.

[0007] The arrangement provided in this disclosure enables the acquisition of a compact device relative to a single high electron mobility transistor, which allows for an increase in the current density that may flow through the device.

[0008] The embodiment includes an electronic device comprising a HEMT transistor called a main transistor and at least one other HEMT transistor called an additional transistor. The main transistor and the additional transistor are respectively disposed in a main stack and an additional stack, with an insulating layer inserted between the main stack and the additional stack. The main stack and the additional stack extend from the insulating layer toward the back side and the front side of the electronic device, respectively, and each includes a barrier layer and a channel layer extending from the insulating layer. When the HEMT transistor of consideration switches from a non-conducting state to a conducting state, the channel layer is capable of forming a conductive layer. The main transistor and the additional transistor respectively include a common drain electrode and a main source electrode and an additional source electrode. The main source electrode and the additional source electrode are arranged such that when one of these HEMT transistors is in a conducting state, conductive paths possibly formed by the two conductive layers are connected in parallel. The switching from one of the non-conducting state and the conducting state to the other of the two states is independently controlled for one of the main transistor and the additional gate electrode, respectively.

[0009] Therefore, according to this disclosure, the density of high electron mobility transistors can be increased without increasing the surface area occupied by the electronic device.

[0010] Furthermore, the parallel arrangement of the conductive layers of the two transistors allows for an increase in the current that may flow through the electronic device, thus paving the way for higher power applications. Therefore, according to this disclosure, the additional transistor can be turned on once the current flowing through the main transistor exceeds a threshold.

[0011] Furthermore, the electronic device according to this disclosure does not require a change in the size of its included high electron mobility transistors.

[0012] Furthermore, the parallel connection of conductive paths enables the limitation of the resistivity Ron of electronic devices.

[0013] According to an embodiment, the drain electrode passes through an insulating layer and extends on either side of the insulating layer to electrically contact the channel layer of one and the other of the main transistor and the auxiliary transistor. In some implementations, the electronic device includes a pad called a drain pad, which is arranged on the back side and enables electrical contact with the drain electrode.

[0014] According to an embodiment, the electrical device includes a pad referred to as a main gate pad and a pad referred to as an additional gate pad, the main gate pad being disposed on the back side and capable of electrically contacting the main gate electrode, and the additional gate pad being disposed on the front side and capable of electrically contacting the additional gate electrode.

[0015] According to an embodiment, the main transistor and the auxiliary transistor are enhancement-mode HEMT transistors, and the main source electrode and the auxiliary source electrode form a single source electrode. In some implementations, the source electrode passes through an insulating layer and extends on either side of the insulating layer to electrically contact the channel layer of one of the main transistor and the auxiliary transistor.

[0016] According to an embodiment, the electronic device includes a pad referred to as a source pad, which is capable of making electrical contact with a source electrode.

[0017] According to an embodiment, the source pad is arranged on the positive side.

[0018] According to an embodiment, the main transistor and the auxiliary transistor are depletion-type HEMT transistors, and each is cascaded with a MOSFET transistor referred to as the main MOSFET transistor and the auxiliary MOSFET transistor, respectively.

[0019] According to an embodiment, the main MOSFET transistor and the auxiliary MOSFET transistor are arranged to independently apply an on-state or a non-on state to the main transistor and the auxiliary transistor, respectively.

[0020] According to an embodiment, the electronic device further includes two pads, referred to as the main source pad and the auxiliary source pad, which are capable of making electrical contact with the main source electrode and the auxiliary source electrode, respectively, and the main source pad and the auxiliary source pad are respectively arranged on the back side and the front side.

[0021] According to the embodiments, the main stack and the additional stack are substantially the same.

[0022] According to an embodiment, the main transistor and the auxiliary transistor have the same threshold voltage.

[0023] According to an embodiment, the main transistor and the auxiliary transistor each have different main threshold voltages and auxiliary threshold voltages.

[0024] According to an embodiment, the two channel layers comprise GaN, and the barrier layer comprises a ternary AlGaN alloy.

[0025] According to an embodiment, the insulating layer includes a dielectric material, which in some implementations is silicon dioxide.

[0026] The implementation of an insulating layer is particularly advantageous because it can effectively insulate the two barrier layers.

[0027] This insulating layer also simplifies the assembly of two high-mobility transistors. In fact, the latter makes it possible to consider assembly via molecular bonding of the two transistors.

[0028] This disclosure also relates to an electronic package, comprising:

[0029] Electronic devices according to this disclosure;

[0030] A device for controlling a main transistor and an auxiliary transistor to switch from one of a non-conducting state and a conducting state to the other of these two states, the controller being configured to turn on the auxiliary transistor once the main transistor itself is in a conducting state and when the current conducting through the main transistor is greater than a threshold. Attached Figure Description

[0031] Other features and advantages of this disclosure will become apparent from the following detailed description relating to the accompanying drawings, wherein:

[0032] Figure 1 This is a simplified representation of a HEMT transistor known in the prior art, specifically showing the HEMT transistor along a cross-section perpendicular to the positive side;

[0033] Figure 2A This is a simplified representation of an electronic device according to a first embodiment of the present disclosure along a cross section;

[0034] Figure 2B It shows that it can be electrically connected. Figure 2AThe representation of the offset positioning of the main gate electrode and the auxiliary gate electrode of the electronic device, including the main gate pad and the auxiliary gate pad;

[0035] Figure 2C This is a representation shown in the front view of the device of the offset positioning of the additional gate pad, which enables it to be positioned relative to... Figure 2A Additional gate electrode electrical connection of electronic devices;

[0036] Figure 3 This is a simplified representation of an electronic device according to a second embodiment of the present disclosure along a cross section;

[0037] Figure 4 This is a functional representation of the package that implements the electronic device according to the first embodiment of the present disclosure;

[0038] Figure 5 This is a simplified representation of the steps for forming an additional transistor in accordance with the terms of this disclosure;

[0039] Figure 6 This is a simplified representation of the steps for forming the main transistor in accordance with the terms of this disclosure;

[0040] Figure 7 This is a simplified representation of the steps involved in forming pads for electrical contact between the source and gate electrodes. Detailed Implementation

[0041] Figure 1 A HEMT transistor 10 is shown. This HEMT transistor 10 is provided with a stack 13, which, from the front side 11 to the back side 12, includes an insulating layer 14, a barrier layer 15, and a channel layer 16 capable of forming a conductive layer 16a in the form of a two-dimensional electron gas layer. In some implementations, the conductive layer 16a extends within the channel layer 16 from an interface 15a formed between the barrier layer 15 and the channel layer 16.

[0042] The III-V semiconductor materials selected for forming the barrier layer 15 and / or the channel layer 16 may include gallium nitride (GaN), aluminum nitride (AlN), and Al x Ga 1-x N x Ternary alloys, gallium arsenide (GaAs), AlGaAs, or InGaAs ternary alloys. For example, barrier layer 15 and channel layer 16 may comprise an AlaGaN compound and GaN, respectively. Insulating layer 14 may comprise a dielectric material, particularly silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0043] The HEMT transistor 10 also includes a source electrode 17 and a drain electrode 18 that are electrically contacted with the conductive layer 16a. More specifically, the source electrode 17 and drain electrode 18 are exposed through the front side 11 and extend through the barrier layer 15 to reach the interface 15a and electrically contact the conductive layer 16a. The source electrode 17 and drain electrode 18 may partially or entirely extend through the conductive layer 16a. The source electrode 17 and drain electrode 18 may comprise a metallic material, such as aluminum, filling trenches formed in the stack 13.

[0044] The HEMT transistor 10 also includes a gate electrode 19 designed to be subjected to a voltage V, which enables control of the state of the conductive layer 16a. Specifically, the transistor is in a conducting state once the potential difference between the gate electrode 19 and the source electrode 17, Vg-Vs, is greater than a threshold voltage Vth representing the characteristics of the HEMT transistor 10. Conversely, the HEMT transistor 10 is in a non-conducting state once Vg-Vs is less than Vth, and thus acts as a turn-off switch.

[0045] Therefore, depending on the value of the threshold voltage Vth, and more specifically, its sign, if the threshold voltage Vth of the HEMT transistor is negative, the HEMT transistor can be in depletion (normally on) mode, or if the threshold voltage Vth of the HEMT transistor is positive, the HEMT transistor can be in enhancement (normally off) mode.

[0046] However, such high electron mobility transistors have an on-resistivity Ron (Ron is the drain / source resistance in the on state), which limits the intensity of the current that may flow through the conductive layer.

[0047] In this respect, the main parameters affecting resistivity Ron are:

[0048] Surface resistance of the channel layer;

[0049] The resistance of the contact area between the conductive layer and the source and drain electrodes;

[0050] The resistivity of the wiring metal in the chip;

[0051] The resistance sensed in the final assembly of a transistor with high electron mobility integrated in the final assembly.

[0052] To overcome this problem, increasing the surface area of ​​high electron mobility transistors (HEMTs) can significantly reduce their resistivity (Ron). However, space constraints for integrating HEMTs prevent such a solution from being foreseen.

[0053] As a variant approach, optimizing the parameters affecting resistivity Ron is conceivable. However, implementing this solution remains complex because it requires both a complete resize of the high electron mobility transistor and an examination of methods for manufacturing the transistor.

[0054] This disclosure provides an apparatus whose arrangement allows for a high integration density of high electron mobility transistors without significantly increasing the space occupied by the apparatus.

[0055] This disclosure also provides a device that allows for effective management of surge current.

[0056] It should be understood that this disclosure is not limited to the described embodiments, and alternative embodiments may be incorporated into this disclosure without departing from its framework.

[0057] Furthermore, it should be understood that the various figures shown in connection with this specification are given for illustrative purposes only and do not limit this disclosure in any way. It should be particularly clear that relative scale or dimensions may be disregarded.

[0058] Throughout the specification, it is acknowledged that layers or interfaces are generally planar and extend along a plane parallel to the (0, x, y) plane of an orthogonal (0, x, y, z) reference system. Furthermore, once referenced along a cross-section, the cross-section is perpendicular to all planes formed by the layers, and in some implementations, perpendicular to the (0, x, y) plane. It should also be understood that once the layer stack is referenced, these layers are stacked along the z-direction of the (0, x, y, z) orthogonal reference system.

[0059] This disclosure includes an electronic device comprising a HEMT transistor, referred to herein as a "main transistor" for illustrative purposes, and at least one other HEMT transistor, referred herein as an "additional transistor" for illustrative purposes.

[0060] The main transistor and the auxiliary transistor are respectively provided with a main stack and an auxiliary stack, and an insulating layer is inserted between the main stack and the auxiliary stack.

[0061] The main stack and the additional stack extend from the insulating layer to the back and front sides of the electronic device, respectively, and each includes a barrier layer and a channel layer starting from the insulating layer.

[0062] For example, once the HEMT under consideration switches from a non-conducting state to a conducting state, a conductive layer can be formed in the channel layer. In some implementations, this conductive layer takes the form of a two-dimensional electron gas and extends in the channel layer from the interface formed between the barrier layer and the channel layer.

[0063] The main transistor and the auxiliary transistor include a common drain electrode and a main source electrode and an auxiliary source electrode, respectively, and are arranged such that when one and the other of the HEMT transistor are in the on state, the conductive paths formed by the two conductive layers may be connected in parallel.

[0064] For one of the main transistor and the other of the auxiliary transistor, the switching from one of the non-conducting state and the on state to the other of the two states is independently controlled via the main gate electrode and the auxiliary gate electrode, respectively.

[0065] This configuration is advantageous in several ways. In fact, the parallelization of the conductive channels of the two transistors allows for an increase in the intensity of the current that may flow through the electronic device without increasing its surface area. In some implementations, when the current flowing through the main transistor exceeds a threshold voltage, an additional transistor can be turned on to form a conductive layer in the main transistor that is connected in parallel with the conductive layer of the additional transistor.

[0066] Furthermore, this parallelization also enables a reduction in the on-state resistivity Ron of electronic devices.

[0067] Figures 2A-2C An example of an electronic device 100 according to a first embodiment of the present disclosure is shown.

[0068] Therefore, the electronic device 100 according to this disclosure includes a high electron mobility transistor (hereinafter referred to as a "HEMT transistor"). In some implementations, the electronic device 100 includes at least one additional transistor 101 and a main transistor 102 separated by an insulating layer 200 from the front side 100a to the back side 100b. In some implementations, the insulating layer 200 includes silicon dioxide or silicon nitride.

[0069] According to this embodiment, the HEMT transistor is in enhancement mode. In other words, this transistor exhibits a positive threshold voltage Vth (the transistor is turned on when the potential difference Vg-VS applied between the gate electrode and the source electrode is greater than Vth).

[0070] The description in this disclosure uses an implementation with a single additional transistor as an illustrative example. However, this aspect is not intended to limit the scope of this disclosure. In some implementations, based on the general knowledge of those skilled in the art and the description herein, implementing multiple additional transistors within the framework of this disclosure will be within the capabilities of those skilled in the art.

[0071] The first transistor 101 and the second transistor 102 each include stacks referred to as a first stack 201 and a second stack 202, respectively. In some implementations, each of these stacks may include a III-V semiconductor material, and in some implementations, a III-N semiconductor material. In some implementations, the III-V semiconductor material may be selected from gallium nitride (GaN), aluminum nitride (AlN), and Al... x Ga 1-x N-ternary alloys, or those selected from gallium arsenide (GaAs) and its compounds (AlGaAs, InGaAs).

[0072] The additional stack 201 and the main stack 202 each include a barrier layer and a channel layer. In some implementations, the additional stack 201 includes an additional barrier layer 201a and an additional channel layer 201b from the insulating layer 200 to the front side 100a. Equivalently, from the insulating layer 200 to the back side 100b, the main stack 202 includes a main barrier layer 202a and a main channel layer 202b.

[0073] As an example and in accordance with this disclosure, the barrier layer may include Al x Ga 1-x N-ternary alloys, while the channel layer may include GaN.

[0074] Furthermore, the barrier layer can have a thickness ranging from 1 nm to 100 nm.

[0075] The channel layer can have a thickness ranging from 10 nm to 2 μm.

[0076] According to the terminology of this disclosure, stack 201 or 202 can form a two-dimensional electron gas layer (2DEG), which forms a conductive layer.

[0077] The conductive layer within the stack extends in the channel layer from the interface formed between the barrier layer and the channel layer of the stack under consideration.

[0078] Therefore, the additional stack 201 includes an additional conductive layer 201c that extends in the additional channel layer 201b from an additional interface formed between the additional barrier layer 201a and the additional channel layer 201b.

[0079] Equivalently, the main stack 202 includes a main conductive layer 202c extending from the main interface formed between the main barrier layer 202a and the main channel layer 202b in the main channel layer 202b.

[0080] Electronic device 100 includes a source electrode 203 and a drain electrode 204 that are electrically in contact with one and the other of an additional conductive layer 201c and a main conductive layer 202c. It should be noted that different types of electrical contacts are known to electrically connect the source electrode 203 and the drain electrode 204 to the conductive layers 201c and 202c: in some implementations, ohmic contacts, tunnel contacts, or Schottky contacts.

[0081] In some implementations, the source electrode 203 and the drain electrode 204 pass through the insulating layer 200 and extend on either side of the insulating layer 200 to make electrical contact with the additional conductive layer 201c and the main conductive layer 220c, respectively.

[0082] The electrical device 100 may include a pad referred to as a source pad 206, which is disposed on the positive side 100a and enables electrical contact with the source electrode 203. In some implementations, the source pad 206 comprises doped silicon.

[0083] Electrical device 100 may include a pad referred to as drain pad 207, which is disposed on the back side 100b and enables electrical contact with drain electrode 204. In some implementations, drain pad 207 may include doped silicon.

[0084] When a HEMT transistor is turned on, the conductive layer of the HEMT transistor is designed to ensure the conduction of current between the source and drain electrodes of the HEMT transistor under consideration.

[0085] The electronic device 100 according to this disclosure also includes two gate electrodes that are different from each other (i.e., electrically insulated from each other). In some implementations, the electronic device 100 includes a main gate electrode 205a and an additional gate electrode 205b.

[0086] The electrical device 100 may include a pad called a main gate pad 208a, which is arranged on the back side and enables electrical contact with the main gate electrode.

[0087] Equivalently, the electrical device 100 may include a pad referred to as an additional gate pad 208b, which is arranged on the positive side and enables electrical contact with the additional gate electrode.

[0088] It should be understood that for each HEMT transistor, the electrical contact between the gate electrode and its associated gate pad is offset to avoid the risk of electrical contact with the conductive layer of the transistor in question. In some implementations, the main gate pad and the additional gate pad are offset from the active region of the electronics. Figure 2B "Offset" refers to the gate pad, which is positioned outside the outline defining one of the two transistors. Figure 2CThis is a representation of device 100 in a front view (along a plane parallel to the (0, x, y) plane). The dashed line defines the active section ZA of the electronic device, in which any contact between the gate electrode and one or the other of the barrier layer and channel layer is avoided.

[0089] Therefore, the main gate electrode 205a is arranged to control the main transistor 102 and, in some implementations, to control the switching from one of the non-conducting and conducting states to the other of the two states.

[0090] Equivalently, the additional gate electrode 205b is arranged to control the additional transistor 101, and in some implementations, to control the switching from one of the non-conducting and conducting states to the other of the two states.

[0091] "On-state" refers to a transistor in which current may flow between the source and drain electrodes. In some implementations, HEMT transistors include a conductive layer, as defined herein, when they are in the on-state.

[0092] "Non-conducting state" means that the transistor behaves as if it is off, so that no current can flow between its source and drain electrodes.

[0093] In some implementations, the HEMT transistor switches from a non-conducting state to a conducting state once the potential difference Vg-Vs between the gate electrode and the source electrode is greater than the threshold voltage Vth of the transistor under consideration.

[0094] Therefore, according to this disclosure, the main transistor 102 and the auxiliary transistor 101 can be controlled independently. In some implementations, the main transistor and the auxiliary transistor can be in the same or different states depending on the voltage applied to their gate electrodes.

[0095] For example, once current is to be conducted through electronic device 100, the switching of the main transistor from a non-conducting state to a conducting state can be controlled first, while the auxiliary transistor remains in a non-conducting state. As long as the current remains below the threshold current value Is, these conducting and non-conducting states of the main transistor and the auxiliary transistor can be maintained respectively.

[0096] The threshold current value Is can be less than or equal to the damage current value Id. The degradation current Id corresponds to a current value exceeding which the main transistor is at risk of being damaged.

[0097] As an example, the value of the threshold current Is can be less than half the value of the damage current Id.

[0098] Therefore, in some implementations, the additional transistor 101 is implemented in a way that enables protection of the main transistor in the event of a surge current.

[0099] As a variant or supplement, an additional transistor 101 can be implemented once the main transistor overcomes the excessively high resistance Ron of the current path through its conductive layer. In some implementations, this effect can occur as the temperature of the electronic device increases.

[0100] As a variant, an additional transistor 101 can be implemented to absorb current peaks that may occur in the main transistor when it switches from a non-conducting state to its conducting state. For this purpose, the switching to the conducting state of the additional transistor, which occurs simultaneously with the switching to the conducting state of the main transistor, can overcome the occurrence of current peaks.

[0101] Figure 3 An electronic device 100 according to an embodiment of the present disclosure is shown. This embodiment has information regarding... Figure 2A-2C Most of the characteristics described.

[0102] According to this second embodiment, the HEMT transistor is in depletion mode or normally-on mode. In other words, this transistor has a threshold voltage Vth less than 0. Therefore, this transistor is turned on when the potential difference applied between the gate electrode and the source electrode is zero.

[0103] According to this second embodiment, the main transistor 102 and the auxiliary transistor no longer share the same source electrode.

[0104] In some implementations, the main transistor 102 includes a source electrode referred to as the main source electrode 203a, which passes through the main stack 202 and is exposed through the back side 100b. In this regard, the electronic device includes a pad referred to as the main source pad 206a, which is disposed on the back side 100b and is capable of establishing an electrical contact with the main source electrode 203a.

[0105] Equivalently, the additional transistor 101 includes a source electrode called an additional source electrode 203b, which passes through the additional stack 201 and is exposed through the positive side 100a. In this respect, the electronic device includes a pad called an additional source pad 206b, which is arranged on the positive side 100b and is capable of establishing an electrical contact with the additional source electrode 203b.

[0106] According to the second embodiment, both the main transistor and the auxiliary transistor are cascaded with the MOSFET transistor.

[0107] In some implementations, the main transistor 102 is cascaded with a MOSFET transistor, referred to as the main MOSFET transistor, via its source. The MOSFET transistor includes a source Sa connected to the main gate electrode 205a, a drain Da connected to the main source electrode 203a, and a gate Ga, which is capable of controlling the switching of the main MOSFET from an on state to an off state or vice versa.

[0108] Equivalently, the additional transistor 101 is cascaded with a MOSFET transistor, referred to as the additional MOSFET transistor, through its source. The MOSFET transistor includes a source Sb connected to the additional gate electrode 205b, a drain Db connected to the additional source electrode 203b, and a gate Gb, which is capable of controlling the switching of the additional MOSFET transistor from an on state to an off state or vice versa.

[0109] Similarly, according to this second embodiment, the source electrodes Sa and Sb are also electrically connected.

[0110] According to the second embodiment, the main gate electrode and the auxiliary gate electrode are controlled by gate Ga and gate Gb, respectively.

[0111] The operation of the electronic device according to the second embodiment is similar to that discussed in the context of the first embodiment.

[0112] Regardless of the conceivable embodiments, the electronic device according to this disclosure can be integrated into an electronic package 1000 in which the controller 600 is provided. Figure 4 In some implementations, the electronic package includes an input E and an output S connected to the source electrode and drain electrode, respectively.

[0113] In some implementations, the controller 600 is configured to control the switching of the main transistor and the auxiliary transistor from one of a non-conducting state and a conducting state to the other of these two states. In some implementations, the controller is connected to the electronic device 100 via connections Ga1 and Ga2, respectively, for applying voltages to the main gate electrode and the auxiliary gate electrode.

[0114] In some implementations, the controller 600 is configured to turn on the additional transistor once the main transistor itself is in the on state and its on current is greater than the threshold Is.

[0115] In some implementations, the controller 600 can be configured to synchronize the main gate electrode and the auxiliary gate electrode to limit current spikes that may occur when switching the two transistors to the on state.

[0116] This disclosure also relates to a method of manufacturing the electronic device 100 described above. The manufacturing method is described only in the context of forming the electronic device 100 according to the first embodiment. Those skilled in the art can adapt the method to be implemented in the context of the second embodiment based on their general knowledge and the concepts discussed below.

[0117] In some implementations, the method includes the step of forming an additional transistor 101. Figure 5 ).

[0118] In some implementations, the formation of this additional transistor 101 includes epitaxially growing an additional stack 201 on a first surface of a first substrate 400 (e.g., a silicon substrate). In some implementations, the epitaxial growth may first include forming an additional channel layer 201b, and then forming an additional barrier layer 201a. In some implementations, the formation of the additional channel layer may occur after the formation of an additional adapter layer (the additional channel layer must be located on top of the additional adapter layer). In some implementations, the additional adapter layer is intended to restrict the formation of dislocations in the additional channel layer.

[0119] After epitaxial growth, a first insulating layer 200a is formed on the additional barrier layer 201a. The first insulating layer includes, for example, silicon dioxide or silicon nitride.

[0120] Then, after the deposition of the insulating layer 200a, a first source electrode 203b, a first drain electrode 204b, and a first gate electrode 205b are formed. In some implementations, the two electrodes 203b and 204b extend from the free surface of the first insulating layer toward or into the additional stack 201.

[0121] The manufacturing method includes the step of forming the main transistor 102. Figure 6 ).

[0122] In some implementations, the formation of this main transistor 102 includes epitaxially growing a main stack 202 on a first surface of a second substrate 500 (e.g., a silicon substrate). In some implementations, the epitaxial growth may first include forming a main channel layer 202b, and then forming a main barrier layer 202a. In some implementations, the formation of the main channel layer may occur after the formation of a main adapter layer (the main channel layer must be located on top of the main adapter layer). In some implementations, the main adapter layer is intended to restrict the formation of dislocations in the main channel layer.

[0123] After epitaxial growth, a second insulating layer 200b is formed on the main barrier layer 202a. The second insulating layer includes, for example, silicon dioxide.

[0124] Then, after depositing the second insulating layer 200b, the second source electrode 203a, the second drain electrode 204a, and the second gate electrode 205a are formed.

[0125] The manufacturing method also includes the step of assembling the additional transistor 101 and the main transistor 102. In this regard, the assembly step is performed by bringing the first insulating layer 200a into contact with the second insulating layer 200b, and aligning the first source electrode 203b and the first drain electrode 204b with the second source electrode 203a and the second drain electrode 204a, respectively.

[0126] In other words, the assembly of the first insulating layer and the second insulating layer forms the insulating layer 200. The assembly of the first source electrode 203b and the second source electrode 203a forms the source electrode 203. The assembly of the first drain electrode 204b and the second drain electrode 204a forms the drain electrode 204. The first gate electrode 205b and the second gate electrode 205a remain independent of each other.

[0127] It should also be noted that this assembly step can be performed in a board-to-board configuration. In some implementations, the method may include a plurality of first transistors formed on a first substrate and a plurality of main transistors formed on a second substrate. The two substrates are then assembled so that each additional transistor is positioned opposite the main transistors.

[0128] As a variant, the assembly may include pick-up and placement steps. In some implementations, each additional transistor may be placed individually on top of each main transistor formed on a second substrate.

[0129] Finally, still as a variant scheme, the main transistor and the auxiliary transistors were separated and then assembled in pairs.

[0130] In the final step, the source and gate pads are formed by thinning and etching the first substrate. Figure 7 ).

[0131] In some implementations, the electronic device according to this disclosure is implemented in a power management / consumption system.

[0132] In some implementations, the management system may include a power storage device and a path for the power consumption. The storage device may be, for example, a battery or accumulator.

[0133] The consumption path can be an electric motor. Therefore, in some implementations, the electronic device 100 according to this disclosure is implemented in an electric vehicle (car, truck, bicycle, train).

[0134] An electronic device can be summarized as including a HEMT transistor called a main transistor and at least one other HEMT transistor called an auxiliary transistor. The main transistor and the auxiliary transistor are respectively provided with a main stack and an auxiliary stack. An insulating layer is inserted between the main stack and the auxiliary stack. The main stack and the auxiliary stack extend from the insulating layer toward the back side and the front side of the electronic device, respectively, and each includes a barrier layer and a channel layer from the insulating layer. When the HEMT transistor under consideration switches from a non-conducting state to a conducting state, the channel layer can form a conductive layer. The main transistor and the auxiliary transistor include a common drain electrode and respectively include a main source electrode and an auxiliary source electrode. The main source electrode and the auxiliary source electrode are arranged such that when one of the HEMT transistors is in a conducting state, conductive paths formed by the two conductive layers can be connected in parallel. The switching from one of the non-conducting state and the conducting state to the other of the two states is controlled independently for one of the main transistor and the auxiliary gate electrode.

[0135] The drain electrode can penetrate the insulating layer and can extend on either side of the insulating layer to electrically contact the channel layer of one of the main transistors and the auxiliary transistors. In some implementations, the electronic device may include pads called drain pads, which are arranged on the back side and enable electrical contact with the drain electrode.

[0136] The electrical device may include a pad referred to as a main gate pad and a pad referred to as an additional gate pad, the main gate pad being disposed on the back side and capable of electrically contacting the main gate electrode, and the additional gate pad being disposed on the front side and capable of electrically contacting the additional gate electrode.

[0137] The main transistor and the auxiliary transistor can be enhancement-mode HEMT transistors, and the main source electrode and the auxiliary source electrode can form a single source electrode. In some implementations, the source electrode passes through an insulating layer and extends on either side of the insulating layer to electrically contact the channel source of one of the main transistor and the auxiliary transistor.

[0138] The electronic device may include pads referred to as source pads, which are capable of making electrical contact with source electrodes.

[0139] The source pads can be placed on the positive side.

[0140] The main transistor and the auxiliary transistor can be depletion-type HEMT transistors, and each can be cascaded with MOSFET transistors referred to as the main MOSFET transistor and the auxiliary MOSFET transistor, respectively.

[0141] The main MOSFET transistor and the additional MOSFET transistor can be arranged to independently apply an on or off state to the main transistor and the additional transistor, respectively.

[0142] The electronic device may also include two pads, referred to as the main source pad and the auxiliary source pad, which are capable of making electrical contact with the main source electrode and the auxiliary source electrode, respectively, and the main source pad and the auxiliary source pad are respectively arranged on the back side and the front side.

[0143] The main stack and the additional stack can be essentially the same.

[0144] The main transistor and the auxiliary transistor can have the same threshold voltage.

[0145] The main transistor and the auxiliary transistor can each have different main threshold voltages and auxiliary threshold voltages.

[0146] The two channel layers may include GaN and the barrier layer may include an AlGaN ternary alloy.

[0147] The insulating layer may include a dielectric material, and in some implementations, the dielectric material is silicon dioxide.

[0148] Electronic packaging can be broadly categorized as including the electronic devices discussed herein; devices for controlling the switching of a main transistor and an auxiliary transistor from one of a non-conducting state and a conducting state to the other of these two states, said control device being configured to turn on the auxiliary transistor once the main transistor itself is in a conducting state and when the current conducting through the main transistor is greater than a threshold.

[0149] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to employ the concepts of various embodiments to provide additional embodiments.

[0150] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents granted by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device comprising: The first high electron mobility transistor, HEMT transistor; as well as At least one second HEMT transistor, The first HEMT transistor includes a first layer stack, and the second HEMT transistor includes a second layer stack. An insulating layer is inserted between the first layer stack and the second layer stack. The first layer stack and the second layer stack extend from the insulating layer toward a first side and a second side of the electronic device, respectively. Each of the first and second layer stacks includes a barrier layer and a channel layer extending from the insulating layer; and The first HEMT transistor includes a first source electrode and a first gate electrode, and the second HEMT transistor includes a second source electrode and a second gate electrode. The first HEMT transistor and the second HEMT transistor include a common drain electrode and are arranged such that when one of the HEMT transistors is in the on state, the conductive paths formed by the two corresponding channel layers are connected in parallel.

2. The apparatus according to claim 1, wherein, The common drain electrode passes through the insulating layer and extends on either side of the insulating layer, contacting both the channel layer of the first HEMT transistor and the channel layer of the second HEMT transistor. The electronic device further includes a drain pad disposed on the first side and in contact with the drain electrode.

3. The apparatus according to claim 1, further comprising: A first gate pad is disposed on the first side and in contact with the first gate electrode; as well as The second gate pad is disposed on the second side and is in contact with the second gate electrode.

4. The apparatus according to claim 1, wherein, The first HEMT transistor and the second HEMT transistor are enhancement-mode HEMT transistors, and The first source electrode and the second source electrode are the same source electrode, which extends through the insulating layer, on either side of the insulating layer, and contacts the channel layer of the first HEMT transistor and the channel layer of the second HEMT transistor.

5. The apparatus according to claim 4 further includes a source pad in contact with the source electrode.

6. The apparatus according to claim 5, wherein, The source pad is arranged on the second side.

7. The apparatus of claim 1, further comprising a first MOSFET transistor and a second MOSFET transistor, in, The first HEMT transistor and the second HEMT transistor are depletion-type HEMT transistors, and are respectively cascaded with the first MOSFET transistor and the second MOSFET transistor.

8. The apparatus according to claim 7, wherein, The first MOSFET transistor and the second MOSFET transistor are configured to independently apply an on state or a non-on state to the first HEMT transistor and the second HEMT transistor, respectively.

9. The apparatus according to claim 1 further includes a first source pad and a second source pad that are in contact with the first source electrode and the second source electrode respectively, the first source pad and the second source pad being disposed on the first side and the second side respectively.

10. The apparatus according to claim 1, wherein, The first stack and the second stack are mirror images of each other.

11. The apparatus according to claim 1, wherein, The first HEMT transistor and the second HEMT transistor have the same threshold voltage.

12. The apparatus according to claim 1, wherein, The first HEMT transistor has a first threshold voltage, and the second HEMT transistor has a second threshold voltage that is different from the first threshold voltage.

13. The apparatus according to claim 1, wherein, The channel layer of the first HEMT transistor and the second HEMT transistor comprises GaN, and the barrier layer of the first HEMT transistor and the second HEMT transistor comprises an AlGaN ternary alloy.

14. The apparatus according to claim 1, wherein, The insulating layer comprises silicon dioxide.

15. An electronic package, comprising: First HEMT transistor; Second HEMT transistor; as well as Control circuit device, The first HEMT transistor includes a first layer stack extending from the insulating layer toward a first direction, and the second HEMT transistor includes a second layer stack extending from the insulating layer toward a second direction opposite to the first direction. Each of the first and second layer stacks includes a barrier layer and a channel layer extending from the insulating layer. Wherein, the first HEMT transistor includes a first source electrode and a first gate electrode, the second HEMT transistor includes a second source electrode and a second gate electrode, and the first HEMT transistor and the second HEMT transistor include a common drain electrode; and The control circuit is configured to control the second HEMT transistor to switch to the on state once the first HEMT transistor is in the on state and the current conducted by the first HEMT transistor is greater than a threshold.

16. The packaging according to claim 15, wherein, The control circuit device controls the first HEMT transistor and the second HEMT transistor to switch individually between a non-conducting state and a conducting state via the first gate electrode and the second gate electrode, respectively.

17. The packaging according to claim 16, wherein, When the first HEMT transistor and the second HEMT transistor are in the ON state, the conductive paths in the channel layers of the first HEMT transistor and the second HEMT transistor are connected in parallel.

18. An electronic device comprising: Insulation layer A first layer stack extends from the insulating layer toward a first direction, the first layer stack including a first barrier layer and a first channel layer; The second layer stack extends from the insulating layer toward a second direction opposite to the first direction, and the second layer stack includes a second barrier layer and a second channel layer; as well as A common drain electrode that is in contact with both the first channel layer and the second channel layer. The first and second stacked layers belong to different HEMT transistors, each having a source electrode and a gate electrode. The HEMT transistor includes a common drain electrode and is arranged such that when one and the other of the HEMT transistor are in the on state, the conductive paths formed by the two corresponding channel layers are connected in parallel.

19. The apparatus of claim 18, comprising: A source electrode extends from the first channel layer toward the insulating layer, and the source electrode is in contact with the first channel layer; as well as The first gate electrode is adjacent to the insulating layer and is located between the source electrode and the common drain electrode.

20. The apparatus of claim 19, wherein, The source electrode is in contact with the second channel layer; The source electrode extends from one side of the first layer stack and terminates before extending over the entire thickness of the second channel layer; and The common drain electrode extends from one side of the second layer stack and terminates before reaching the entire thickness of the first channel layer.

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