Semiconductor devices and their manufacturing methods

Abstract

This invention discloses a semiconductor device and its fabrication method, including a substrate, memory node pads, a support structure, and a capacitor structure. The memory node pads and the support structure are disposed on the substrate, and the support structure includes a first support layer and a second support layer. The capacitor structure is disposed on the substrate and includes multiple capacitors. Each capacitor sequentially includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer. Each bottom electrode layer has two upwardly extending portions, one of which includes a first thickness extending between the memory node pads and the first support layer, and a second thickness extending between the first support layer and the second support layer, wherein the first thickness is greater than the second thickness. This improves the structural reliability of the memory node, thereby optimizing the function and performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] With the trend of miniaturization in various electronic products, the design of semiconductor memory devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage current caused by capacitor structure. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structure.

[0003] Generally, dynamic random access memory (DRAM) with a recessed gate structure consists of a large number of memory cells arranged in an array to store information. Each memory cell can be composed of a transistor assembly and a capacitor assembly connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, leading to increasing difficulties and complexity in related manufacturing processes and designs. Therefore, existing technologies and structures need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0004] One objective of this invention is to provide a semiconductor device in which the bottom electrode layer of the internal memory node has a uniform thickness and a structural feature of being thinner at the top and thicker at the bottom. Therefore, it effectively avoids the formation of seals in the bottom electrode layer and / or capacitor dielectric layer, which could affect the structure and function of the memory node. Furthermore, the uniform thickness of the bottom electrode layer can additionally avoid tip effects, preventing over-discharge and resulting instability. Thus, the semiconductor device can improve the structural reliability of the memory node, thereby optimizing its function and performance.

[0005] To achieve the above objectives, one embodiment of the present invention provides a method for manufacturing a semiconductor device, which expands the openings of the memory node by thinning the bottom electrode layer in the upper half, thereby avoiding the formation of seals during the deposition of the bottom electrode layer and / or capacitor dielectric layer, which would affect the structure and function of the memory node. Thus, even with continuously increasing memory cell density, a memory node that combines structural reliability and device performance can be formed.

[0006] A semiconductor device according to an embodiment of the present invention includes a substrate, memory node pads, a support structure, and a capacitor structure. The memory node pads and the support structure are disposed on the substrate. The support structure includes a first support layer and a second support layer sequentially disposed from bottom to top. The capacitor structure is disposed on the substrate and includes a plurality of capacitors respectively contacting each of the memory node pads. Each capacitor includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer sequentially stacked from bottom to top. Each bottom electrode layer has two portions, one of which includes a first thickness extending between each memory node pad and the first support layer, and a second thickness extending between the first support layer and the second support layer, wherein the first thickness is greater than the second thickness.

[0007] A method for fabricating a semiconductor device according to an embodiment of the present invention includes the following steps. First, a substrate is provided, and a memory node pad and a support structure are formed on the substrate. The support structure includes a first support layer and a second support layer sequentially disposed from bottom to top. Then, a capacitor structure is formed on the substrate. The capacitor structure includes a plurality of capacitors respectively contacting each of the memory node pads. Each capacitor includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer sequentially stacked from bottom to top. Each bottom electrode layer has two parts, one of which includes a first thickness extending between each memory node pad and the first support layer, and a second thickness extending between the first support layer and the second support layer, wherein the first thickness is greater than the second thickness. Attached Figure Description

[0008] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 8 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention is shown, wherein:

[0010] Figure 1 This is a schematic cross-sectional view of the semiconductor device of the present invention after the support layer structure has been formed;

[0011] Figure 2 This is a schematic cross-sectional view of the semiconductor device of the present invention after the electrode material layer has been formed;

[0012] Figure 3 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the first etching process.

[0013] Figure 4 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the second etching process.

[0014] Figure 5 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the third etching process.

[0015] Figure 6 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after a thinning process.

[0016] Figure 7 This is a schematic cross-sectional view of the semiconductor device of the present invention after the first support layer has been completely removed; and

[0017] Figure 8 This is a cross-sectional view of the semiconductor device of the present invention after the capacitor structure has been formed.

[0018] Figures 9 to 10 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention is shown, wherein:

[0019] Figure 9 This is a cross-sectional view of the semiconductor device of the present invention after a thinning process; and

[0020] Figure 10 This is a cross-sectional view of the semiconductor device of the present invention after the capacitor structure has been formed.

[0021] Figure 11 A cross-sectional schematic diagram of a semiconductor device according to a third embodiment of the present invention is shown.

[0022] The reference numerals in the attached figures are explained as follows:

[0023] 100, 300, 500 semiconductor devices

[0024] 101 Insulation Zone

[0025] 110 substrate

[0026] 130 dielectric layer

[0027] 131 Oxide Layer

[0028] 133 Nitride layer

[0029] 135 oxide layer

[0030] 140 Spacer Wall Structure

[0031] 141 First gap wall

[0032] 143 Second spacer wall

[0033] 145 Third spacer wall

[0034] 150 contacts

[0035] 160 bit line

[0036] 160a bit line contact

[0037] 161 Semiconductor Layer

[0038] 163 Barrier Layer

[0039] 165 conductive layer

[0040] 167 cap layer

[0041] 170 dielectric layer

[0042] 180 storage node pads

[0043] 190 Support layer structure

[0044] 191 First Support Material Layer

[0045] 192 Opening

[0046] 193 Second Support Material Layer

[0047] 195 Third Support Material Layer

[0048] 197 Fourth Support Material Layer

[0049] 200 electrode material layer

[0050] 210, 210a Initial bottom electrode layer

[0051] Parts 211 and 213

[0052] 220 mask pattern

[0053] 230, 230a bottom electrode layer

[0054] Parts 231 and 233

[0055] 231a, 233a First segment

[0056] 231b, 233b Second segment

[0057] 231c Third segment

[0058] 232 recess

[0059] 240 capacitor dielectric layer

[0060] 250 top electrode layer

[0061] 260 Capacitor Structure

[0062] 260A capacitor

[0063] 290 Supporting Structure

[0064] 291 First Support Layer

[0065] 293 Second Support Layer

[0066] 330, 330a bottom electrode layer

[0067] Parts 331 and 333

[0068] 331a, 333a First segment

[0069] 331b, 333b Second segment

[0070] 340 capacitor dielectric layer

[0071] 350 top electrode layer

[0072] 360° Capacitor Structure

[0073] 360A capacitor

[0074] 390 Supporting Structure

[0075] 391 First Support Layer

[0076] 393 Second Support Layer

[0077] 490 Supporting Structure

[0078] 491 First Support Layer

[0079] T1 thickness

[0080] T2 First Thickness

[0081] T3 Second Thickness

[0082] T4 Third Thickness

[0083] P1 First Etching Process

[0084] P2 Second Etching Process

[0085] P3 Third Etching Process

[0086] P4 Thinning process Detailed Implementation

[0087] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0088] Please refer to Figures 1 to 9 The illustration shows the steps of a method for manufacturing a semiconductor device 100 according to the first embodiment of the present invention. First, as... Figure 1 As shown, a substrate 110 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate. At least one insulating region 101, such as a shallow trench isolation (STI), is formed within the substrate 110. Multiple active areas (AA, not shown) are defined on the substrate 100. In one embodiment, the insulating region 101 is formed, for example, by first etching multiple trenches (not shown) in the substrate 100, and then filling the trenches with an insulating material (e.g., silicon oxide or silicon oxynitride, etc.), but this is not a limitation.

[0089] Furthermore, a plurality of buried gates (not shown) may be formed within the substrate 110. These buried gates extend parallel to each other along a direction (e.g., the x-direction, not shown) and across the active region, serving as buried word lines (BWLs, not shown) of the semiconductor device 100. A plurality of bit lines 160 and a plurality of contacts 150 may be formed above the substrate 110, extending in another direction perpendicular to the aforementioned direction (e.g., the y-direction, not shown) and arranged alternately. Although the overall extension directions of the active region, the buried gates, and the bit lines 160 are not specifically shown in the accompanying drawings of this embodiment, those skilled in the art will readily understand that, viewed from a top view, the bit lines 160 should be perpendicular to the buried gates and simultaneously cross the active region and the buried gates.

[0090] Specifically, each bit line 160 is formed on the substrate 110 in a spaced manner and includes, but is not limited to, a semiconductor layer (e.g., polysilicon) 161, a barrier layer 163 (e.g., titanium and / or titanium nitride), a conductive layer 165 (e.g., a low-resistivity metal such as tungsten, aluminum, or copper), and a capping layer 167 (e.g., silicon oxide, silicon nitride, or silicon oxynitride). It should be noted that, in principle, all bit lines 160 are formed parallel to each other on the dielectric layer 130 above the substrate 110. The dielectric layer 130 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure, but is not limited to this. Furthermore, each bit line 160 extends and crosses multiple active regions 101. The bit lines 160 crossing each active region 101 extend further into each active region 101 via corresponding bit line contacts (BLCs) 160a formed below them. It should also be noted that the bit line contacts 160a are integrally formed with the semiconductor layer 161 of the bit line 160 and directly contact the underlying substrate 110 (each active region 101). On the other hand, each contact 150 is also formed on the substrate 110 in a spaced manner and further extends into each active region 101. Thus, each contact 150 can serve as a storage node contact (SNC) of the semiconductor device 300, directly contacting the underlying substrate 110 (including the active regions and insulating regions 101). In one embodiment, the contacts 150 are made of low-resistance metals such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and each contact 150 is insulated from each line 160 by a spacer wall structure 140. In one embodiment, the spacer wall structure 140 may selectively have a single-layer structure or a layered structure. Figure 1 The composite layer structure shown includes, for example, a first spacer 141 (e.g., containing silicon nitride), a second spacer 143 (e.g., containing silicon oxide), and a third spacer 145 (e.g., containing silicon nitride) stacked sequentially on the sidewalls of each line 160, but is not limited thereto.

[0091] Please refer to again Figure 1As shown, a plurality of storage node pads (SN pads) 180 are formed within the dielectric layer 170 on the substrate 110, located above the contacts 150 and bit lines 160 and respectively corresponding to the contacts 150. In one embodiment, the storage node pads 180 also contain low-resistivity metals such as aluminum, titanium, copper, or tungsten, for example, different from the metal material of the contacts 150, but not limited thereto. In another embodiment, the storage node pads may also be integrally formed with the contacts 150 and may contain the same material. Subsequently, a capacitor structure 260 can be formed above the storage node pads 180 to directly contact and electrically connect to the storage node pads 180 below. In one embodiment, the fabrication process of the capacitor structure 260 includes, but is not limited to, the following steps. First, a support layer structure 190 is formed on the dielectric layer 170 above the substrate 110, which includes, for example, at least one oxide layer and at least one nitride layer alternately stacked. In this embodiment, the support layer structure 190 includes, for example, a first support material layer 191 (e.g., silicon oxide), a second support material layer 193 (e.g., silicon nitride or silicon carbonitride), a third support material layer 195 (e.g., silicon oxide), and a fourth support material layer 197 (e.g., silicon nitride or silicon carbonitride, etc., but not limited thereto) stacked sequentially from bottom to top. Preferably, the oxide layer (e.g., including the first support material layer 191 and the third support material layer 195) may have a relatively large thickness, for example, about 5 to 10 times or more the thickness of the nitride layer (the second support material layer 193 or the fourth support material layer 197), and the thickness of the nitride layer disposed away from the substrate 110 is preferably greater than the thickness of the nitride layer disposed adjacent to the substrate, such as... Figure 1 As shown, but not limited to. Thus, the overall thickness of the support layer structure 190 can reach approximately 1600 angstroms to 2000 angstroms, but is not limited to. Those skilled in the art will understand that the specific stacking number of the aforementioned oxide layers (such as the first support material layer 191 or the third support material layer 195) and the aforementioned nitride layers (such as the second support material layer 193 or the fourth support material layer 197) is not limited to the aforementioned number, but can be adjusted according to actual needs, for example, 3 layers, 4 layers, or other numbers. Then, a plurality of openings 192 are formed within the support layer structure 190, sequentially penetrating the fourth support material layer 197, the third support material layer 195, the second support material layer 193, and the first support material layer 191, and exposing the underlying memory node pads 180. Thus, the top surface of each memory node pad 180 can be exposed from each of the aforementioned openings 192, as shown. Figure 1 As shown.

[0092] Next, as Figure 2As shown, an electrode material layer 200 is formed by deposition on the substrate 110. In detail, the electrode material layer 200 is conformally formed on the support layer structure 190, for example, and sequentially covers the top surface of the fourth support material layer 197, the surface of each opening 192, and the top surface of each memory node pad 180. The electrode material layer 200 includes, for example, a low-resistivity metal such as aluminum, titanium, copper, or tungsten, but is not limited thereto.

[0093] Then, as Figure 3 As shown, a first etching process P1 is performed, such as a dry etching process, to remove the electrode material layer 200 covering the top surface of the fourth support material layer 197, forming multiple initial bottom electrode layers 210. Each initial bottom electrode layer 210 is formed within each opening 192, uniformly covering the top surface of each memory node pad 180 and the surface of each opening 192, thus having a uniform thickness T1. Furthermore, each initial bottom electrode layer 210 simultaneously covers two opposite sidewalls of each opening 192, thus having two portions 211 of the same height in the direction perpendicular to the substrate 110. In this way, each initial bottom electrode layer 210 can have a bilaterally symmetrical structure, for example, as shown... Figure 3 The U-shaped structure shown is not limited to this.

[0094] like Figure 4 As shown, multiple mask patterns 220 are formed on the support layer structure 190, covering a portion of the fourth support material layer 197 and a portion of the opening 192. A second etching process P2 is performed through the mask patterns 220, such as another dry etching process. In detail, each mask pattern 220 is sequentially formed on the support layer structure 190 such that it simultaneously covers any opening 192 and the support layer structure 190 on both sides of the opening 192, and exposes two adjacent openings 192 on the left and right sides of the opening 192, thereby covering a portion of the fourth support material layer 197 and a portion of the opening 192, and exposing another portion of the fourth support material layer 197 and another portion of the opening 192. Thus, by performing the second etching process P2 through the mask pattern 220, the fourth support material layer 197, its two side portions 211, and the third support material layer 195 below it, exposed by the mask pattern 220, can be removed. This allows the initial bottom electrode layer 210a in the openings 192 of each of the other portions not covered by the mask pattern 220 to have a relatively short portion 213 (its height is, for example, lower than the top surface of the fourth support material layer 197) and a relatively long portion 211, resulting in an overall asymmetrical U-shaped structure. Meanwhile, the initial bottom electrode layer 210 in the openings 192 of each portion covered by the mask pattern 220 has two relatively long portions 211 of equal height, thus still maintaining a symmetrical U-shaped structure. Figure 4As shown. Then, completely remove mask pattern 220.

[0095] like Figure 5 As shown, a third etching process P3 is performed, such as an isotropic wet etching process, to completely remove the third support material layer 195 of the support layer structure 190. Specifically, the isotropic wet etching process involves introducing an etchant such as tetramethylammonium hydroxide (TMAH) to remove the remaining third support material layer 195 from the space created after removing the other part of the fourth support material layer 197 and the third support material layer 195 below it, but is not limited to the aforementioned etchant. Thus, a portion 213 of the initial bottom electrode layer 210a can be completely exposed on both opposite sidewalls in the upper half, while a portion 211 of the initial bottom electrode layer 210a on one side of the upper half can only be partially exposed because it is partially connected to the fourth support material layer 197. Figure 5 As shown. On the other hand, the two opposite sidewalls of the upper half of the other portion of the initial bottom electrode layer 210 211 are also only partially exposed because they are partially connected to the fourth support material layer 197. It should be noted that in this embodiment, the portion of the two portions 211, 213 of the initial bottom electrode layer 210a that is higher than the top surface of the second support material layer 193, or the portion between the fourth support material layer 197 and the second support material layer 193, is defined as the upper half; while the portion of the two portions 211, 213 of the initial bottom electrode layer 210a that is lower than the top surface of the second support material layer 193, or the portion between the second support material layer 193 and the substrate 110, is defined as the lower half, but this is not a limitation. Furthermore, in both the initial bottom electrode layer 210a and a portion 211 of the other initial bottom electrode layer 210, only one sidewall is exposed in the two opposing sidewalls of the lower half, while the other sidewall is covered by the second support material layer 193 and the first support material layer 191, as shown. Figure 5 As shown.

[0096] After removing the remaining third support material layer 195, then, as Figure 6As shown, a thinning fabrication process P4 is performed, for example, another isotropic wet etching process, to partially remove the sidewalls exposed by portions 211 and 213 of the initial bottom electrode layer 210a and the other portion of the initial bottom electrode layer 210. That is, the etchant in this other isotropic wet etching process partially etches portions 211 and 213 of the initial bottom electrode layer 210a and the other portion of the initial bottom electrode layer 210a on the two opposite sidewalls of the upper half and on one sidewall of the lower half, and the initial bottom electrode layer 210a and the other portion of the initial bottom electrode layer 210 cover the horizontal portion of each memory node pad 180 to form thinned bottom electrode layers 230 and 230a, as shown. Figure 6 As shown. In other words, parts 231 and 233 will have different thicknesses depending on whether or not they are exposed to the etchant due to whether or not the sidewalls on both sides have a stacked layer of the support layer structure 190 in contact with it.

[0097] In detail, the thinned bottom electrode layer 230a still has two parts 231 and 233 with different heights. The lower half of part 231 and part 233 is thinned from the original thickness T1 to the first thickness T2 because only one side is in contact with the etchant, forming first segments 231a and 233a with uniform overall thickness, respectively. The upper half of part 231 and part 233 is further thinned to the second thickness T3 because both sides are in contact with the etchant, forming second segments 231b and 233b with uniform overall thickness, respectively. The second thickness T3 of the second segments 231b and 233b is less than the first thickness T2 of the first segments 231a and 233a. On the other hand, the thinned bottom electrode layer 230 still has two parts 231 of the same height. The lower half of part 231 is also thinned to a first thickness T2 because it only contacts the etchant on one side, forming a first segment 231a with uniform overall thickness. The upper half of part 231, similarly, contacts the etchant on both sides and is further thinned to a second thickness T3, forming a second segment 231b with uniform overall thickness. It should be noted that due to the difference in the degree of thinning between the upper and lower halves of parts 231 and 233, recesses 232 are also formed on the upper halves of parts 231 and 233, which have a uniform thickness in the horizontal direction parallel to the surface of the substrate 110. Figure 6As shown. The bottom and top surfaces of the recess 233 are respectively flush with the top surface of the second support material layer 193 and the bottom surface of the fourth support material layer 197. Furthermore, it should be noted that because the upper portion of part 231 is connected to and shielded by the fourth support material layer 197, the portion connected to the fourth support material layer 197 only contacts the etchant on one side, thus having a third thickness T4, thereby forming a third segment 231c with a uniform overall thickness. The third thickness T4 is the same as the first thickness T2, but this is not a limitation; in other embodiments, the third thickness T4 may be greater than the first thickness T2. In other words, portion 231 is composed of a first segment 231a (first thickness T2, extending from the top surface of each storage node pad 180 to the top surface of the second support material layer 193), a second segment 231b (second thickness T3, extending from the top surface of each second support material layer 193 to the bottom surface of the fourth support material layer 197), and a third segment 231c (third thickness T4, extending from the bottom surface of each fourth support material layer 197 to the top surface), stacked sequentially, while portion 233 is composed of a first segment 233a (first thickness T2, extending from the top surface of each storage node pad 180 to the top surface of the second support material layer 193), stacked sequentially. The third segment 231 has a relatively large overall height, with its recess 232 located between the third segment 231c and the first segment 231a, while the second segment 233 has a relatively small overall height, with its recess 232 located on the second segment 231b. Figure 6 As shown. Thus, the bottom electrode layer 230a has an asymmetrical U-shaped structure because it has two parts 231 and 233 with different heights and thicknesses; while the bottom electrode layer 230 has a symmetrical U-shaped structure because it has two parts 231 with the same height.

[0098] Then, as Figure 7As shown, at least two etching processes are performed sequentially, including, for example, a dry etching process and an isotropic wet etching process. First, the second support material layer 193 and the first support material layer 191 below the fourth support material layer 197 are removed. Then, an etchant such as tetramethylammonium hydroxide is introduced. The remaining first support material layer 191 is removed from both sides through the space created after removing the second support material layer 193 and the first support material layer 191, but not limited to the aforementioned etchant. In this way, the remaining second support material layer 193 and the remaining fourth support material layer 197 respectively form the first support layer 291 and the second support layer 293 arranged sequentially from bottom to top. The first support layer 291 and the second support layer 293 are at least disposed on one side of each bottom electrode layer 230, 230a, so as to jointly form the support structure 290 of the capacitor structure 260. Preferably, the thickness of the second support layer 293 located away from the substrate 110 can be greater than the thickness of the first support layer 291 located adjacent to the substrate 110, such as Figure 7 As shown, but not limited to.

[0099] Subsequently, such as Figure 8 As shown, a capacitor dielectric layer 240 and a top electrode layer 250 are sequentially formed on each bottom electrode layer 230, 230a. The capacitor dielectric layer 240 conformally covers the bottom electrode layers 230, 230a and the first support layer 291, while the top electrode layer 250 fills the remaining space of each opening 192 and further covers the second support layer 293. A portion of the capacitor dielectric layer 240 and a portion of the top electrode layer 250 may further fill the space between the second support layer 293 and the first support layer 291, and also fill the space between the first support layer 291 and the dielectric layer 170. In one embodiment, the capacitor dielectric layer 240 includes, for example, a high dielectric constant dielectric material selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), and zirconium oxide-aluminum oxide-zirconia (ZAZ), preferably zirconium oxide-aluminum oxide-zirconia; the top electrode layer 250 includes, for example, a low resistivity metal material such as aluminum, titanium, copper, or tungsten, preferably titanium, but not limited thereto.

[0100] Thus, the fabrication process of capacitor structure 260 is completed. Capacitor structure 260 includes sequentially stacked bottom electrode layers 230 and 230a, a capacitor dielectric layer 240, and a top electrode layer 250, forming a plurality of vertically extending capacitors 260a to serve as storage nodes (SN) of the semiconductor device 100. These storage nodes can be electrically connected to transistor components (not shown) of the semiconductor device 100 via storage node pads 180 and storage node plugs (i.e., contacts 150), ensuring good contact between capacitor structure 260 and the storage node plugs disposed on substrate 110. Therefore, the semiconductor device 100 of this embodiment can form a dynamic random access memory (DRAM) device, which is composed of at least one transistor component and at least one capacitor 260a forming the smallest unit (memory cell) in the DRAM array to receive voltage information from bit lines 160 and the buried word lines.

[0101] According to the manufacturing method of this embodiment, the semiconductor device 100 in the first embodiment of the present invention is first manufactured using an etching process P2 (e.g., ...). Figure 4 (As shown) Remove the fourth support material layer 197, the initial bottom electrode layer 210 on both sides of it, and the third support material layer 195 below it at a specific location. After completely removing the third support material layer 195, perform an additional thinning process P4 (as shown). Figure 6As shown), all bottom electrode layers 230 and 230a can be thinned. It should be noted that the lower half of all bottom electrode layers 230 and 230a is only thinned on one side to form first segments 231a and 233a with a first thickness, while the upper half of bottom electrode layers 230 and 230a is at least partially thinned on both sides to form second segments 231b and 233b with a second thickness T3. Therefore, each bottom electrode layer 230 and 230a can have a structure that is thinner at the top and thicker at the bottom, thereby achieving the effect of increasing the aperture of the top of each opening 192. Furthermore, in this embodiment, a portion 231 of the bottom electrode layer 230a is composed of a first segment 231a (first thickness T2, extending between each memory node pad 180 and the first support layer 291) located between the first support layer 291 and the substrate 110, a second segment 231b (second thickness T3, extending between the first support layer 291 and the second support layer 293) located between the second support layer 293 and the first support layer 291, and a third segment 231c (third thickness T4, extending between the bottom and top surfaces of the second support layer 293) located on the sidewall of the second support layer 293, while a portion 233 is composed of a first segment 233a (first thickness T2) located between the first support layer 291 and the substrate 110, and a second segment 233b (second thickness T3) located between the first support layer 291 and the second support layer 293, stacked sequentially. Thus, part of the bottom electrode layer 230a has two parts 231 and 233 with different heights and thicknesses, resulting in an asymmetrical U-shaped structure; while the other part of the bottom electrode layer 230 has two parts 231 with the same height, resulting in a symmetrical U-shaped structure, but this is not a limitation. Under this operation, even if the density of memory cells in the semiconductor device 100 continues to increase, problems such as the merging or even closure of the openings 192 due to the excessively narrow apertures at the top of the openings 192 during the deposition of the bottom electrode layers 230 and 230a can be avoided. Similar problems can also be avoided during the subsequent deposition of the capacitor dielectric layer. In addition, the uniform thickness of each part of the thinned bottom electrode layers 230 and 230a can avoid the tip effect and prevent over-discharge leading to unstable performance. Therefore, the fabrication method of the semiconductor device 100 in the first embodiment of the present invention can effectively improve the structural reliability of the memory node, thereby optimizing its function and performance.

[0102] Furthermore, those skilled in the art will readily understand that, to meet actual product requirements, the present invention may have other forms of forming a semiconductor device and its fabrication method, and is not limited to the foregoing. For example, in another embodiment, the first etching process P1 may be omitted, and subsequent etching processes (such as...) Figure 4 The second etching process P2 shown Figure 5In the third etching process (P3) shown, the electrode material layer 200 covering the top surface of the fourth support material layer 197 is also removed. Other embodiments or variations of the method for the semiconductor device of the present invention will be further described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0103] Please refer to Figures 9 to 10 As shown, it illustrates the steps of a method for fabricating a semiconductor device 300 according to a second embodiment of the present invention. The steps for forming the front end of the semiconductor device 300 in this embodiment are generally the same as those for forming the front end of the semiconductor device 100 in the first embodiment described above, such as... Figures 1 to 4 As shown, it will not be repeated here. The main difference between this embodiment and the first embodiment described above is that, in forming... Figure 4 After the semiconductor structure shown is removed, that is, after the fourth support material layer 197, the portions 211 on both sides thereon, and the third support material layer 195 below it are removed, but before the remaining third support material layer 195 is removed, a thinning process P4 is performed.

[0104] In detail, such as Figure 9 As shown, in this embodiment, after the second etching process P2 and the complete removal of the mask pattern 220, a thinning process P4 is performed on the exposed sidewalls of a portion of the initial bottom electrode layer 210a and portions 211 and 213 of the other portion of the initial bottom electrode layer 210. It should be noted that after the second etching process P2, in the lower half of the two opposing sidewalls of the portion of the initial bottom electrode layer 210a and the other portion of the initial bottom electrode layer 210, only one sidewall is fully exposed, while the other sidewall is covered by the first support material layer 191 and the second support material layer 193. In other words, a portion 213 of the initial bottom electrode layer 210a can be fully exposed in the upper half of the two opposing sidewalls, while a portion 211 of the initial bottom electrode layer 210a has only one sidewall fully exposed in the upper half of the two opposing sidewalls, while the other sidewall is covered by the third support material layer 195 (refer to the aforementioned first embodiment). Figure 4(As shown). Thus, the thinning fabrication process P4 in this embodiment, for example, is an isotropic wet etching process, in which a portion 213 of the initial bottom electrode layer 210a is etched on the two opposite sidewalls of the upper half, a portion 211 of the other initial bottom electrode layer 210 is etched on one sidewall of the upper half, a portion of the initial bottom electrode layer 210a, and portions 211 and 213 of the other initial bottom electrode layer 210 are etched on one sidewall of the lower half, and the initial bottom electrode layer 210a and the other initial bottom electrode layer 210 cover the horizontal portion of each memory node pad 180 to form thinned bottom electrode layers 330, 330a, as shown. Figure 9 As shown.

[0105] like Figure 9 As shown, the thinned portion of the bottom electrode layer 330a still has two parts 331 and 333 with different heights and thicknesses, exhibiting an overall asymmetrical U-shaped structure. Specifically, the first segments 331a and 333a of parts 331 and 333 only contact the etchant on one side, causing them to be thinned from their original thickness T1 to a first thickness T2. Similarly, the second segment 331b of part 331 only contacts the etchant on one side, having the same first thickness T2 as the first segments 331a and 333a. On the other hand, the second segment 333b of part 333, because it contacts the etchant on both sides, can be further thinned to a second thickness T3, which is less than the first thickness T2. Furthermore, the thinned portion of the bottom electrode layer 330 still has two parts 331 with the same height, exhibiting an overall symmetrical U-shaped structure. The first part 331a and the second segment 331b of part 331 also only contact the etchant on one side, being thinned to a first thickness T2. Therefore, the recess 232 in the first embodiment will not be formed on part 331, allowing its thickness to be consistent; while the recess 332 will still be formed on part 333, located on the second segment 333b, such as Figure 9 As shown. Then, at least two etching processes are performed in sequence, including, for example, a dry etching process and an isotropic wet etching process. First, the second support material layer 193 and the first support material layer 191 below the fourth support material layer 197 of the other part are removed. Then, an etchant such as tetramethylammonium hydroxide is introduced. The remaining third support material layer 195 and the remaining first support material layer 191 are removed to both sides from the space created after the removal of the second support material layer 193 and the first support material layer 191, but not limited to the aforementioned etchant.

[0106] Thus, the remaining second support material layer 193 and the remaining fourth support material layer 197 respectively form the first support layer 391 and the second support layer 393 sequentially arranged from bottom to top. The first support layer 391 and the second support layer 393 are only disposed on one side of each bottom electrode layer 330, 330a, so as to jointly form the support structure 390 of the capacitor structure 360. Preferably, the thickness of the second support layer 393 located away from the substrate 110 can be greater than the thickness of the first support layer 391 located adjacent to the substrate, such as... Figure 10 As shown, but not limited to.

[0107] Subsequently, for example Figure 10 As shown, a capacitor dielectric layer 340 and a top electrode layer 350 are sequentially formed on each bottom electrode layer 330, 330a. The capacitor dielectric layer 340 conformally covers the bottom electrode layers 330, 330a and the first support layer 391, while the top electrode layer 350 fills the remaining space of each opening 192 and further covers the remaining second support layer 393. A portion of the capacitor dielectric layer 340 and a portion of the top electrode layer 350 may further fill the space between the second support layer 393 and the first support layer 391, and also fill the space between the first support layer 391 and the dielectric layer 170. In one embodiment, the material selection of the capacitor dielectric layer 340 and / or the top electrode layer 350 is, for example, the same as the material selection of the capacitor dielectric layer 240 and / or the top electrode layer 250 in the first embodiment described above, and will not be repeated here.

[0108] Thus, the fabrication process of capacitor structure 360 ​​is completed. Capacitor structure 360 ​​includes sequentially stacked bottom electrode layers 330 and 330a, a capacitor dielectric layer 340, and a top electrode layer 350, forming a plurality of vertically extending capacitors 360a to serve as storage nodes of semiconductor device 300. These capacitors can be electrically connected to transistor components (not shown) of semiconductor device 300 via storage node pads 180 and storage node plugs (i.e., contacts 150), ensuring good contact between capacitor structure 360 ​​and the storage node plugs disposed on substrate 110. Therefore, semiconductor device 300 of this embodiment can also form a dynamic random access memory device.

[0109] According to the manufacturing method of this embodiment, the semiconductor device 300 in the second embodiment of the present invention is subjected to a thinning process P4 immediately after the etching process P2 (e.g., ...). Figure 9As shown, all bottom electrode layers 330 and 330a are thinned. In this embodiment, the lower half of all bottom electrode layers 330 and 330a is thinned only on one side to form first segments 331a and 333a with a relatively large first thickness T2. In a portion of the bottom electrode layer 330a, the upper half of the portion 331 is also thinned only on one side to form a second segment 331b with a relatively large first thickness T2, while the upper half of the portion 333 is thinned on both sides to form a second segment 333b with a relatively small second thickness T3. Therefore, one portion 333 of the partial bottom electrode layer 330a can have a structure that is thinner at the top and thicker at the bottom, thereby increasing the aperture at the top of each opening 192 to facilitate subsequent deposition processes, which can have a significant benefit in improving integration. In addition, when the partial bottom electrode layer 330a has an asymmetrical U-shaped structure, it can more effectively increase the aperture at the top of each opening 192. It should be noted that during the thinning process P4 in this embodiment, the remaining third support material layer 195 still covers the second segment 331b of part 331. Therefore, the first segment 331a and the second segment 331b of part 331 will only contact the etchant on one side, having a uniform first thickness T2 and avoiding the formation of the recess 232 in the first embodiment. Under this operation, the semiconductor device 300 of this embodiment can also avoid problems such as the merging or even closure of the openings 192 due to the excessively narrow aperture at the top of each opening 192 during the deposition of the bottom electrode layers 330 and 330a, while continuously increasing the density of the memory cells. Furthermore, the asymmetrical U-shaped structure of only a portion of the bottom electrode layer 330a further avoids affecting the overall capacitance and structural stability. Thus, the fabrication method of the semiconductor device 300 in the second embodiment of the present invention can also effectively improve the structural reliability of the memory node, thereby optimizing its function and performance.

[0110] Please refer to Figure 11, which illustrates a cross-sectional view of the semiconductor device 500 in the third embodiment of the present invention. The structure of the semiconductor device 500 in this embodiment is generally the same as that of the semiconductor device 100 in the aforementioned first embodiment, as shown below. Figure 8 As shown, it will not be described again here. The main difference between this embodiment and the first embodiment described above is that the thickness of the first support layer 491 located near the substrate 110 may not be less than the thickness of the second support layer 293 located away from the substrate 110.

[0111] In detail, the support structure 490 of this embodiment includes a first support layer 491 and a second support layer 293 arranged sequentially from bottom to top, which are disposed on at least one side of each bottom electrode layer 230, 230a to jointly support the capacitor structure 260. The thickness of the first support layer 491 is, for example, equal to the thickness of the second support layer 293. Thus, a first segment 231a (with a first thickness T2) of part 231 can further extend from the top surface of each memory node pad 180 beyond the bottom surface of the first support layer 491. Figure 11 As shown, but not limited to.

[0112] Overall, this invention involves a bottom electrode layer thinning process performed during the stage of at least partially removing the supporting layer structure from the oxide layer in the upper half, thereby thinning the upper half of at least one side of the bottom electrode layer to a relatively small thickness. In this way, the bottom electrode layer exhibits a thin-at-the-top, thick-at-the-bottom structure, thereby achieving the effect of expanding the capacitor opening. Under this operation, this invention can effectively improve the structural reliability of memory nodes and optimize the function and performance of semiconductor devices, even as memory cell density continues to increase and fabrication process complexity gradually increases.

[0113] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that... Comprising: a substrate; a plurality of storage node pads disposed on the substrate; a support structure disposed on the substrate, the support structure comprising a first support layer and a second support layer disposed sequentially from bottom to top; and a capacitor structure disposed on the substrate, the capacitor structure comprising a plurality of capacitors respectively contacting each of the storage node pads, each of the capacitors comprising a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked sequentially from bottom to top, wherein each of the bottom electrode layers has two portions extending upward, the two portions comprising a first portion and a second portion, the first portion comprising a first thickness extending between each of the storage node pads and the first support layer, and a second thickness extending between the first support layer and the second support layer, the first thickness being greater than the second thickness; wherein a segment of the first portion in direct contact with the second support layer has a third thickness, the second portion being disposed away from the second support layer, a top surface of the second portion having the second thickness, the third thickness being greater than the second thickness.

2. The semiconductor storage device according to claim 1, wherein The second thickness extends to a bottom surface of the second support layer.

3. The semiconductor storage device according to claim 2, wherein The third thickness extends between the bottom surface and a top surface of the second support layer.

4. The semiconductor storage device according to claim 3, wherein The third thickness is the same as the first thickness.

5. The semiconductor memory device according to claim 3, wherein The third thickness is greater than the first thickness.

6. The semiconductor memory device according to claim 3, wherein The two portions have different heights in a direction perpendicular to the substrate.

7. The semiconductor memory device according to claim 1, wherein The second thickness extends beyond a bottom surface of the second support layer.

8. The semiconductor memory device according to claim 1, wherein The first thickness extends to a top surface of the first support layer.

9. The semiconductor memory device according to claim 1, wherein The first thickness extends beyond a bottom surface of the first support layer.

10. The semiconductor memory device according to claim 1, wherein The two portions are not symmetrical to each other.

11. A method of manufacturing a semiconductor memory device, characterized by Comprising: providing a substrate; forming a plurality of storage node pads on the substrate; forming a support structure on the substrate, the support structure comprising a first support layer and a second support layer disposed sequentially from bottom to top; and forming a capacitor structure on the substrate, the capacitor structure comprising a plurality of capacitors respectively contacting each of the storage node pads, each of the capacitors comprising a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked sequentially from bottom to top, wherein each of the bottom electrode layers has two portions extending upward, the two portions comprising a first portion and a second portion, the first portion comprising a first thickness extending between each of the storage node pads and the first support layer, and a second thickness extending between the first support layer and the second support layer, the first thickness being greater than the second thickness; wherein a segment of the first portion in direct contact with the second support layer has a third thickness, the second portion being disposed away from the second support layer, a top surface of the second portion having the second thickness, the third thickness being greater than the second thickness.

12. The method according to claim 11, wherein The forming of the support structure further comprises: forming a first support material layer, a second support material layer, a third support material layer, and a fourth support material layer stacked sequentially on the substrate; forming a plurality of openings through the fourth support material layer, the third support material layer, the second support material layer, and the first support material layer; forming a plurality of mask patterns on the fourth support material layer; removing part of the second support material layer; and completely removing the first support material layer to form the support structure. Further comprising: forming an electrode material layer covering the surface of each of the openings; 13. The method according to claim 12, wherein and performing an etching fabrication process to partially remove the electrode material layer to form a plurality of initial bottom electrode layers; and performing a thinning fabrication process to thin the initial bottom electrode layers to form the bottom electrode layers. The thinning fabrication process is performed after removing the remaining third support material layer. The third thickness extends between a bottom surface and a top surface of the second support layer, and the third thickness is the same as the first thickness.

14. The method according to claim 13, wherein The thinning fabrication process is performed before removing the remaining third support material layer.

15. The method according to claim 14, wherein 17. The method of claim 16, wherein the two portions have different heights in a direction perpendicular to the substrate.

16. The method according to claim 13, wherein The part of the second support material layer and the first support material layer are removed after the thinning fabrication process. Further comprising:

18. The method according to claim 13, wherein forming the capacitor dielectric layer and the top electrode layer on the bottom electrode layer after the thinning fabrication process.

19. The method according to claim 13, wherein ​ ​

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