Integrated circuit structure

Abstract

This disclosure proposes an integrated circuit (IC) architecture layout to improve the performance of a memory array, such as static random access memory (SRAM). An exemplary IC device includes SRAM cells and interconnect structures electrically coupled to the SRAM cells. The interconnect structure includes a first metal layer electrically coupled to the SRAM cells. The first metal layer includes bit lines, a first voltage line having a first voltage, word line landing pads, and a second voltage line having a second voltage different from the first voltage. The first voltage line is adjacent to the bit lines. The word line landing pads are adjacent to the first voltage lines. The second voltage line is adjacent to the word line landing pads. A second metal layer is disposed above the first metal layer. The second metal layer includes word lines electrically coupled to the word line landing pads.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit structure, and more particularly to an integrated circuit structure that requires fewer metal lines in the first metal layer. Background Technology

[0002] Static random access memory (SRAM) generally refers to any memory or storage that retains stored data only when power is applied. As the speed requirements of integrated circuits increase, the read and write speeds of SRAM cells become increasingly important. One technique to improve performance involves placing the bit lines of SRAM cells in the lowest metal layer to reduce capacitance. However, this requirement is difficult to meet as the already very small size of SRAM cells continues to shrink, with the thickness and width of metal constantly decreasing. Due to metal pitch limitations, miniaturization further restricts considerations for logic circuit routing. Therefore, current SRAM cell layouts are not satisfactory in every aspect. Summary of the Invention

[0003] This disclosure provides an integrated circuit structure. The integrated circuit structure includes a memory cell and an interconnect structure. The interconnect structure is disposed above the memory cell and electrically coupled to the memory cell. The interconnect structure includes a first metal layer electrically coupled to the memory cell and a second metal layer disposed above the first metal layer. The first metal layer includes bit lines, a first voltage line configured to receive a first voltage, word line landing pads, complementary bit lines, and a second voltage line configured to receive a second voltage, the second voltage being different from the first voltage. The second metal layer includes word lines electrically coupled to the word line landing pads. The word line landing pads are disposed between the first voltage line and the complementary bit line. The first voltage line and the complementary bit line are disposed between the bit line and the second voltage line.

[0004] This disclosure provides an integrated circuit structure. The integrated circuit structure includes a memory cell and an interconnect structure. The memory cell has a pull-up device, a pull-down device, and a transmission gate device. The pull-up device and the pull-down device share a first gate structure, and the transmission gate device has a second gate structure. The interconnect structure has a first metal layer and a second metal layer above the first metal layer. The first metal layer includes bit lines, a first voltage line connected to the pull-up device and configured to receive a first voltage, a word line landing pad connected to the transmission gate device, a complementary bit line connected to the transmission gate device, and a second voltage line connected to the pull-down device and configured to receive a second voltage, the second voltage being different from the first voltage. The second metal layer includes word lines connected to the word line landing pads. The first voltage line is adjacent to the bit line. The word line landing pad is adjacent to the first voltage line. The complementary bit line is adjacent to the word line landing pad. The second voltage line is adjacent to the complementary bit line. The word line landing pad is located between the pull-up device and the pull-down device.

[0005] This disclosure provides an integrated circuit structure. The integrated circuit structure includes a memory cell and an interconnect structure. The memory cell has a pull-up device, a pull-down device, a first transmission gate device, and a second transmission gate device. The pull-up device and the pull-down device share a first gate structure. The first transmission gate device has a second gate structure, and the second transmission gate device has a third gate structure. The interconnect structure has a first metal layer and a second metal layer above the first metal layer. The first metal layer includes bit lines, a first voltage line configured to receive a first voltage, a word line landing pad connected to the second gate structure, a complementary bit line connected to the first transmission gate device, and a second voltage line configured to receive a second voltage, which is different from the first voltage. The second metal layer includes word lines connected to the word line landing pads. The first voltage line is adjacent to the bit line. The word line landing pad is adjacent to the first voltage line. The complementary bit line is adjacent to the word line landing pad. The second voltage line is adjacent to the complementary bit line. The word line landing pad extends above the first gate structure and the second gate structure. Attached Figure Description

[0006] This disclosure of embodiments can be understood in more detail by reading the following detailed description and examples in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various feature components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various feature components can be arbitrarily increased or decreased.

[0007] Figure 1 Circuit diagrams of two-port static random access memory (SRAM) cells are shown according to various aspects of this disclosure.

[0008] Figure 2 A top view of an exemplary layout of a dual-port SRAM cell is shown according to various aspects of this disclosure.

[0009] Figure 3A , Figure 3B as well as Figure 3C Top views of various layers of an exemplary layout of a dual-port SRAM cell are shown according to various aspects of this disclosure.

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D as well as Figure 4E Cross-sectional views of exemplary layouts of dual-port SRAM cells are shown according to various aspects of this disclosure.

[0011] Figure 5 A top view of an exemplary layout of two dual-port SRAM cells is shown according to various aspects of this disclosure.

[0012] Figure 6A and Figure 6B Top views of exemplary layouts of various layers of an exemplary layout of two dual-port SRAM cells are shown according to various aspects of this disclosure.

[0013] Figure 7 Circuit diagrams of a three-port SRAM cell are shown according to various aspects of this disclosure.

[0014] Figure 8 A top view of an exemplary layout of a three-port SRAM cell is shown according to various aspects of this disclosure.

[0015] Figure 9A , Figure 9B as well as Figure 9C Top views of various layers of an exemplary layout of a three-port SRAM cell are shown according to various aspects of this disclosure.

[0016] The attached figures are labeled as follows:

[0017] 100: Static Random Access Memory (SRAM) unit

[0018] WPU-1: Write pull-up transistor, transistor, pull-up transistor

[0019] WPU-2: Write pull-up transistor, transistor, pull-up transistor

[0020] WPD-1: Write to pull-down transistor, transistor, pull-down transistor

[0021] WPD-2: Write to pull-down transistor, transistor, pull-down transistor

[0022] RPD: Read pull-down transistor, pull-down transistor

[0023] WPG-1: Transfer gate transistor, transistor

[0024] WPG-2: Transfer gate transistor, transistor

[0025] RPG: Reading Transmission Gate Transistor, Transmission Gate Transistor

[0026] W_WL: Write character lines, character lines

[0027] R_WL: Read character lines

[0028] W_BL: Write bit line

[0029] W_BLB: Write complementary bit line

[0030] R_BL: Read bit line

[0031] 102, 104: Data storage nodes

[0032] 106,108: Vdd nodes

[0033] 110, 112, 114: Vss nodes

[0034] Vdd: Positive power node, power supply voltage / line

[0035] Vss: Power supply voltage, power supply voltage / line

[0036] 200: Static Random Access Memory Cell Layout

[0037] AA: line segment

[0038] BB: Line segment

[0039] CC: Line segment

[0040] DD: line segment

[0041] EE: line segment

[0042] 202:N well area

[0043] 204A: P-well area, first P-well area

[0044] 204B: Well P area, second well P area

[0045] 206A~206D: Outer boundary

[0046] 208A~208H: Active Region

[0047] 210A~210E: Gate electrode

[0048] 212A~212J: Source / Drain Contact

[0049] 214A, 214B: Gate contacts

[0050] 216A, 216B, 216C: Gate vias

[0051] 218A~218G: Source / Drain vias

[0052] 220~236: Conductor

[0053] 238A, 238B, 238C: Through holes

[0054] 240, 242, 246, 250: Conductors

[0055] 244, 248: Through holes

[0056] 402:Substrate

[0057] 404: Shallow trench isolation zone

[0058] 406: Gate dielectric

[0059] 500: Static Random Access Memory Cell Layout

[0060] 502A: First Static Random Access Memory Unit

[0061] 502B: Second Static Random Access Memory Unit

[0062] 504A~504G: Outer boundary

[0063] 506A: Well N area, Well N 1

[0064] 506B: Well N area, Second Well N area

[0065] 508A: P-well area, first P-well area

[0066] 508B: P-well area, second P-well area

[0067] 510A~510P: Active Region

[0068] 512A~512I: Gate electrode

[0069] 514A~514S: Source / Drain Contact

[0070] 516A~516D: Gate contacts

[0071] 518A~518E: Gate via

[0072] 520A~520M: Source / Drain vias

[0073] 522~552: Conductors

[0074] 700: Static Random Access Memory Unit

[0075] 702, 704: Data storage nodes

[0076] 706, 708: Vdd nodes

[0077] 710~716: Vss nodes

[0078] RPD-1: Read pull-down transistor, pull-down transistor

[0079] RPD-2: Read pull-down transistor, pull-down transistor

[0080] RPG-1: Transfer Gate Transistor

[0081] RPG-2: Transfer Gate Transistor

[0082] R_WL-A: Character Line

[0083] R_WL-B: Character Line

[0084] R_BL-A: Read bit line

[0085] R_BL-B: Read bit line

[0086] 800: Static Random Access Memory Cell Layout

[0087] 802:N well area

[0088] 804A: P-well area, first P-well area

[0089] 804B: P-well area, second P-well area

[0090] 806A~806D: Outer boundary

[0091] 808A~808J: Active Region

[0092] 810A~810F: Gate electrode

[0093] 812A~812L: Source / Drain Contact

[0094] 814A, 814B: Gate contacts

[0095] 816A~816D: Gate via

[0096] 818A~818H: Source / Drain vias

[0097] 820~840: Conductor

[0098] 842A~842D: Through holes

[0099] 844, 846, 848, 852, 854, 858, 860: Conductors

[0100] 850A, 850B, 856A, 856B: Through holes Detailed Implementation

[0101] This disclosure generally relates to integrated circuit devices, and more specifically, to multi-gate devices, such as gate-all-around (GAA) devices.

[0102] This disclosure provides numerous different embodiments or examples to implement different features. Reference numerals and / or designations may be repeated in the various examples described herein. These repetitions are for simplicity and clarity and are not in themselves intended to limit the relationship between the different embodiments and / or structures discussed. Furthermore, specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, or embodiments where additional features are formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. Furthermore, forming a feature on another feature, forming a feature connected to another feature, and / or forming a feature coupled to another feature in this disclosure may include embodiments where features are formed in direct contact, and may also include embodiments where additional features can be formed to insert features, such that the features are not in direct contact.

[0103] Furthermore, spatially related terms, such as “below,” “above,” “horizontal,” “vertical,” “over,” “on,” “below,” “under,” “up,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used here to facilitate the description of the relationship between one element or feature and another element (or features) or feature (or features). Spatially related terms are intended to include orientations different from those of the apparatus (or system or device) showing the element or feature, including orientations related to the use or operation of the apparatus. The apparatus may be rotated in different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way.

[0104] Static random access memory (SRAM) cells and corresponding SRAM arrays are provided according to various exemplary embodiments. Some variations of some embodiments are discussed. In the various schematic and illustrative embodiments, the same reference numerals are used to denote the same elements.

[0105] Figure 1A circuit diagram of a dual-port SRAM cell 100 is shown according to some embodiments. The dual-port SRAM cell 100 includes eight transistors and can perform one read and one write operation within a single clock cycle. The SRAM cell 100 includes write pull-up transistors WPU-1 and WPU-2, which are P-type metal-oxide-semiconductor (PMOS) transistors, and write pull-down transistors WPD-1 and WPD-2, read pull-down transistor RPD, transfer gate transistors WPG-1 and WPG-2, and read transfer gate transistor RPG, which are N-type metal-oxide-semiconductor (NMOS) transistors. The gates of the transfer gate transistors WPG-1 and WPG-2 are controlled by a write word line W_WL, which determines whether the SRAM cell 100 is selected for writing. The gate of the transfer gate transistor RPG is controlled by the read word line R_WL, which determines whether SRAM cell 100 is selected for reading. A latch formed by write pull-up transistors WPU-1 and WPU-2 and write pull-down transistors WPD-1 and WPD-2 stores a bit, the complementary value of which is stored in storage data (SD) nodes 102 and SD node 104. The stored bit can be written to SRAM cell 100 via complementary bit lines including write bit line W_BL and write complementary bit line W_BLB. The stored bit can be read from SRAM cell 100 via read bit line R_BL. SRAM cell 100 is powered by a positive power supply node Vdd (also denoted as VDD) with a positive power supply voltage. SRAM cell 100 is also connected to the power supply voltage Vss (also denoted as VSS), which can be electrically grounded. Transistors WPU-1 and WPD-1 form a first inverter. Transistors WPU-2 and WPD-2 form a second inverter. The input of the first inverter is connected to the output of transistor WPG-1 and the second inverter. The output of the first inverter is connected to the input of transistor WPG-2 and the second inverter. The output of the second inverter controls the read-down transistor RPD.

[0106] The sources of pull-up transistors WPU-1 and WPU-2 are individually connected to Vdd nodes 106 and 108, which are further connected to the power supply voltage / line Vdd. The sources of pull-down transistors WPD-1 and WPD-2 are individually connected to Vss nodes 110 and 112, which are further connected to the power supply voltage / line Vss. The source of pull-down transistor RPD is connected to Vss node 114, which is further connected to the power supply voltage / line Vss. The drain of pull-down transistor RPD is connected to the source / drain region of the transfer gate transistor RPG. The gates of transistors WPU-1 and WPD-1 are connected to the drains of transistors WPU-2 and WPD-2, forming a connection node referred to as SD node 102. The gates of transistors WPU-2 and WPD-2 are connected to the drains of transistors WPU-1 and WPD-1, forming a connection node referred to as SD node 104. The source of transfer gate transistor WPG-1 is connected to the write bit line W_BL. The source of the transfer gate transistor WPG-2 is connected to the write complementary bit line W_BLB. The source of the transfer gate transistor RPG is connected to the read bit line R_BL.

[0107] Figure 2 A top view of an exemplary dual-port SRAM cell layout 200 of a dual-port SRAM cell 100 is shown according to various aspects of this disclosure. Figures 3A to 3C A top view of each layer of the dual-port SRAM cell layout 200 is shown. Figure 3A It displays the front-end features, including the substrate, active device region, gate structure, and contact. Figure 3B The diagram shows a middle-of-line feature including a gate via, a source / drain (S / D) via, and the first metal layer. Figure 3C The back-end feature is shown, which includes a second metal layer, a third metal layer, a fourth metal layer, and vias connecting each metal layer. Figures 4A to 4E A schematic cross-sectional view of a dual-port SRAM cell layout 200 is shown according to various aspects of this disclosure. Figure 4A Showing along Figure 2 A schematic cross-sectional view of the dual-port SRAM cell layout 200 of line segment AA. Figure 4B Showing along Figure 2 A schematic cross-sectional view of the dual-port SRAM cell layout 200 of line segment BB. Figure 4C Showing along Figure 2 A schematic cross-sectional view of the dual-port SRAM cell layout 200 of line segment CC. Figure 4D Showing along Figure 2A schematic cross-sectional view of the dual-port SRAM cell layout 200 of line segment DD. Figure 4E Showing along Figure 2 A schematic cross-sectional view of the dual-port SRAM cell layout 200 of line segment EE.

[0108] Turn Figure 3A This image shows the front-end features of a dual-port SRAM cell layout 200, including a substrate, active device regions, gate structures, and contacts. The dual-port SRAM cell layout 200 includes a substrate (wafer). In some embodiments, the substrate includes silicon. Alternatively (or additionally), the substrate may include another element, such as germanium; compound semiconductors, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. Alternatively, the substrate is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. SOI substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0109] N-well region 202 and P-well regions 204A and 204B are disposed in the substrate, with the first P-well region 204A disposed to the left of N-well region 202 and the second P-well region 204B disposed to the right of N-well region 202. N-type doped regions, such as N-well region 202, are doped with N-type dopants, such as phosphorus, arsenic, other N-type dopants, or combinations thereof. P-type doped regions, such as P-well regions 204A and 204B, are doped with P-type dopants, such as boron, indium, other P-type dopants, or combinations thereof. Various doped regions can be formed directly on and / or in the substrate, for example, providing P-well structures, N-well structures, dual-well structures, raised structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form various doped regions. The outer boundaries 206A, 206B, 206C, and 206D of the dual-port SRAM cell layout 200 are shown using dashed lines, marking rectangular areas.

[0110] Active regions 208A to 208H are disposed above the substrate. Active regions 208A and 208B are disposed above the first P-well region 204A, active regions 208C and 208D are disposed above the N-well region 202, and active regions 208E, 208F, 208G, and 208H are disposed above the second P-well region 204B. In some embodiments, active regions 208A to 208H include channel regions disposed between the source and drain regions of a finfield-effect transistor (FinFET). In some embodiments, the channel regions and / or the source / drain regions are formed in the fins of the FinFET. In some embodiments, active regions 208A to 208H include channel regions disposed between the source and drain regions of a gate-all-around (GAA) device. In some embodiments, the channel regions are disposed in the suspended semiconductor layer of the GAA device, such as nanosheet channels, nanowire channels, bar-shaped channels, and / or other suitable configurations. Figure 3A As shown, each transistor device may include one or more active regions 208A to 208H.

[0111] Gate electrode 210A forms a write transfer gate transistor WPG-1 in the first P-well region 204A with the underlying active regions 208A and 208B. Gate electrode 210B forms a write pull-down transistor WPD-1 in the first P-well region 204A with the underlying active regions 208A and 208B. Gate electrode 210B further forms a write pull-up transistor WPU-1 in the N-well region 202 with the underlying active region 208C. Gate electrode 210C forms a write pull-up transistor WPU-2 in the N-well region 202 with the underlying active region 208D. Gate electrode 210C further forms a write pull-down transistor WPD-2 in the second P-well region 204B with the underlying active regions 208E and 208F. Gate electrode 210C further forms a read pull-down transistor RPD in the second P-well region 204B with the underlying active regions 208G and 208H. Gate electrode 210D forms a write transfer gate transistor WPG-2 in the second P-well region 204B together with the underlying active regions 208E and 208F. Gate electrode 210E forms a read transfer gate transistor RPG in the second P-well region 204B together with the underlying active regions 208G and 208H. In some embodiments, pull-up transistors WPU-1 and WPU-2, pull-down transistors WPD-1, WPD-2 and RPD, and transfer gate transistors WPG-1, WPG-2 and RPG can be FinFET devices. In some embodiments, pull-up transistors WPU-1 and WPU-2, pull-down transistors WPD-1, WPD-2 and RPD, and transfer gate transistors WPG-1, WPG-2 and RPG can be GAA devices with nanosheet channels, nanowire channels, strip channels and / or other suitable configurations.

[0112] SD node 102 includes a source / drain (S / D) contact 212A and a gate contact 214A. The S / D contact 212A is elongated and has a longitudinal direction in the X direction, parallel to the extension direction of gate electrodes 210A to 210E. The gate contact 214A has a longitudinal direction in the Y direction, perpendicular to the X direction. The gate contact 214A is included above the S / D contact 212A and the gate electrode 210B, and is electrically coupled to portions of the S / D contact 212A and the gate electrode 210B. In some embodiments, the S / D contact 212A and the gate contact 214A may be formed as a single continuous contact or a butted contact. In some embodiments, the S / D contact 212A and the gate contact 214A may be formed in separate processes to form a butted contact.

[0113] SD node 104 includes an S / D contact 212B and a gate contact 214B. The S / D contact 212B is elongated and has a longitudinal orientation in the X direction. The gate contact 214B has a longitudinal orientation in the Y direction. The gate contact 214B is included above the S / D contact 212B and the gate electrode 210C, and is electrically coupled to portions of the S / D contact 212B and the gate electrode 210C. In some embodiments, the S / D contact 212B and the gate contact 214B may be formed as a single continuous contact or a mating contact in a single process. In some embodiments, the S / D contact 212B and the gate contact 214B may be formed in separate processes to form a mating contact.

[0114] S / D contact 212C connects the source region of write transfer gate transistor WPG-1 to write bit line W_BL. S / D contact 212D connects the source region of write pull-down transistor WPD-1 to Vss node 110. S / D contact 212E connects the source region of write pull-up transistor WPU-2 to Vdd node 108. S / D contact 212F connects the source region of write pull-up transistor WPU-1 to Vdd node 106. S / D contact 212G connects the source regions of write pull-down transistor WPD-2 and read pull-down transistor RPD to Vss nodes 112 and 114, respectively. S / D contact 212H connects the source region of write transfer gate transistor WPG-2 to write complementary bit line W_BLB. S / D contact 212I connects the drain region of read transfer gate transistor RPG to read bit line R_BL. S / D contact 212J connects the drain region of the read pull-down transistor RPD to the source region of the read transfer gate transistor RPG. S / D contacts 212C to 212J are elongated and have a longitudinal orientation in the X direction, parallel to gate electrodes 210A to 210E. In some embodiments, one or more elongated S / D contacts 212A to 212J may further extend into adjacent SRAM cells adjacent to SRAM cell 200.

[0115] Turn Figure 3B This illustrates additional features of a dual-port SRAM cell layout 200, including gate vias, source / drain (S / D) vias, and conductors (collectively referred to as the first metal (M1) layer). These features can be disposed in one or more interlayer dielectric layers to form an interconnect structure. For clarity, Figure 3A The front-end features shown were not in Figure 3B The text appears to be incomplete and contains several errors. A more accurate translation would require the full context. Figure 2As shown. Gate vias 216A to 216C and S / D vias 218A to 218G are indicated by circles and an "x" symbol within the circles. Conductors 220 to 236 are indicated by rectangles. Each gate via 216A to 216C is positioned above its corresponding gate electrode and below conductors 220, 228, and 236 of its corresponding M1 layer. Each S / D via 218A to 218G is positioned above its corresponding contact and below conductors 222, 224, 226, 230, 232, and 234 of its corresponding M1 layer.

[0116] Gate via 216A is disposed above gate electrode 210A and electrically coupled to gate electrode 210A, and disposed below wire 220 corresponding to write word line W_WL and electrically coupled to wire 220. Gate via 216B is disposed above gate electrode 210D and electrically coupled to gate electrode 210D, and disposed below wire 228 corresponding to write word line W_WL and electrically coupled to wire 228. Gate via 216C is disposed above gate electrode 210E and electrically coupled to gate electrode 210E, and disposed below wire 236 corresponding to read word line R_WL and electrically coupled to wire 236.

[0117] S / D via 218A is disposed above S / D contact 212D and electrically coupled to S / D contact 212D, and disposed below conductor 222 and electrically coupled to conductor 222. S / D via 218B is disposed above S / D contact 212C and electrically coupled to S / D contact 212C, and disposed below conductor 224 and electrically coupled to conductor 224. S / D via 218C is disposed above S / D contact 212E and electrically coupled to S / D contact 212E, and disposed below conductor 226 and electrically coupled to conductor 226. S / D via 218D is disposed above S / D contact 212F and electrically coupled to S / D contact 212F, and disposed below conductor 226 and electrically coupled to conductor 226. S / D via 218E is disposed above S / D contact 212H and electrically coupled to S / D contact 212H, and disposed below conductor 230 and electrically coupled to conductor 230. S / D via 218F is disposed above S / D contact 212G and electrically coupled to S / D contact 212G, and disposed below conductor 232 and electrically coupled to conductor 232. S / D via 218G is disposed above S / D contact 212I and electrically coupled to S / D contact 212I, and disposed below conductor 234 and electrically coupled to conductor 234.

[0118] The corresponding wires 220 to 236 are as described above. Figure 1The described Vdd, Vss, write and read lines and / or landing pads are described. Wires 220 to 236 extend longitudinally in the Y direction. In some embodiments, wires 220 to 236 extend into adjacent SRAM cells. In some embodiments, one or more wires 220 to 236 may be shared with adjacent SRAM cells. Wire 220 is the first write word line landing pad corresponding to the write word line W_WL of write transfer gate transistor WPG-1. Wire 222 is the first Vss line corresponding to Vss node 110. Wire 224 is the write bit line corresponding to write bit line W_BL. Wire 226 is the first Vdd line corresponding to Vdd node 106. Wire 228 is the second write word line landing pad corresponding to the write word line W_WL of write transfer gate transistor WPG-2. Wire 230 is the write complementary bit line corresponding to the write complementary bit line W_BLB. Wire 232 is the second Vss line corresponding to Vss nodes 112 and 114. Wire 234 is the read bit line corresponding to read bit line R_BL. Wire 236 is the read word line landing pad corresponding to read read word line R_WL of the read transfer gate transistor RPG.

[0119] Turn Figure 3C This shows the back-end features of a dual-port SRAM cell layout 200, including a second metal (M2) layer, a third metal (M3) layer, a fourth metal (M4) layer, and vias connecting each metal layer. The vias are indicated using circles and an "x" symbol within the circles. For clarity, only those shown in the image are explicitly labeled. Figure 3A and Figure 3B The conductors of the M1 layer shown in the front section feature are displayed Figure 3C However, other front-end features still exist, such as Figure 2 As shown. Via 238A is disposed above and electrically coupled to conductor 220 of layer M1, and below and electrically coupled to conductor 240 of layer M2. Conductor 240 of layer M2 is the write word line W_WL. Via 238B is disposed above and electrically coupled to conductor 228 of layer M1, and below and electrically coupled to conductor 240 of layer M2. Via 238C is disposed above and electrically coupled to conductor 236 of layer M1, and below and electrically coupled to conductor 242 of layer M2. Conductor 242 of layer M2 is the read word line R_WL. Conductors 240 and 242 of layer M2 extend longitudinally in the X direction.

[0120] A via 244 is disposed above and electrically coupled to the conductor 242 of layer M2, and disposed below and electrically coupled to the conductor 246 of layer M3, which is the read word line R_WL landing pad. The conductor 246 of layer M3 extends longitudinally in the Y direction.

[0121] A via 248 is disposed above and electrically coupled to the conductor 246 of layer M3, and disposed below and electrically coupled to the conductor 250 of layer M4, which is the read character line R_WL. The conductor 250 of layer M4 extends longitudinally in the X direction.

[0122] Turn Figures 4A to 4E This shows a cross-sectional view of a dual-port SRAM cell layout 200. In addition to previous information... Figures 3A to 3C Beyond the different layers described, Figures 4A to 4E The substrate 402, N-well region 202 disposed in the substrate 402, and P-well regions 204A and 204B disposed in the substrate 402 are further shown. Active regions 208A to 208H extend from the substrate 402 within their respective N-well regions 202 and P-well regions 204A and 204B. A shallow trench isolation (STI) region 404 is disposed above the N-well regions 202 and P-well regions 204A and 204B, and is adjacent to a portion of the active regions 208A to 208H. The STI region 404 is further disposed between gate electrodes 210A to 210E. A gate dielectric 406 is disposed above the gate electrodes 210A to 210E.

[0123] The above about Figures 2 to 4EThe described layout improves the performance of SRAM cell 100. Compared to other SRAM cell layouts, SRAM cell layout 200 increases the width of the N-well. Improved patterning techniques allow the gate pickup (i.e., word line landing pads (e.g., wire 228) and gate via 216B) for the write transfer gate transistor WPG-2 to be placed between the write pull-down transistor WPD-2 (and the write transfer gate transistor WPG-2) and the write pull-up transistor WPU-2 (and the write pull-up transistor WPU-1). This layout creates more space between the Vdd M1 layer and the Vss M1 layer and allows for wider N-wells (e.g., N-type well 202). Increasing the width of the N-well improves the resistance within the N-well and improves well isolation leakage, thus providing better performance for the entire SRAM cell. Wider N-wells also improve latch-up and soft-error-rate immunity. Using this new layout, the VssM1 line (e.g., conductor 232) can be wider than previously possible. A wider VssM1 line reduces the resistance of the Vss line, thereby improving the overall performance of the SRAM cell. Different improvements may exist in different embodiments.

[0124] Figure 5 A top view of an exemplary dual-port SRAM cell layout 500, including two adjacent dual-port SRAM cells 100, is shown according to various aspects of this disclosure. Figure 6A and Figure 6B A top view of each layer of a dual-port SRAM cell layout 500 is shown. Figure 6A The front-end features, including the substrate, active device region, gate structure, and contacts, are shown. Figure 6B The mid-section features, including the gate via, source / drain (S / D) via, and first metal layer, are shown. The cross-section of the dual-port SRAM cell layout 500 is similar to the one described above. Figures 4A to 4E The dual-port SRAM cell layout discussed in 200 is similar to those in the previous discussion.

[0125] Turn Figure 6AThis image shows the front-end features of a dual-port SRAM cell layout 500, including a substrate, active device regions, gate structures, and contacts. The dual-port SRAM cell layout 500 includes a substrate (wafer). In some embodiments, the substrate includes silicon. Alternatively (or additionally), the substrate may include another element, such as germanium; compound semiconductors, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. Alternatively, the substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using oxygen-injected isolation (SIMOX), wafer bonding, and / or other suitable methods.

[0126] The dual-port SRAM cell layout 500 shows an exemplary configuration with a first SRAM cell 502A and a second SRAM cell 502B, wherein the first and second SRAM cells 502A and 502B are adjacent to each other. As will be discussed further below, this configuration allows the first SRAM cell 502A and the second SRAM cell 502B to share different front-end features than those shared by the dual-port SRAM cell layout 200. Outer boundaries 504A, 504B, 504C, and 504D define the first SRAM cell 502A, and outer boundaries 504D, 504E, 504F, and 504G define the second SRAM cell 502B.

[0127] N-well regions 506A and 506B and P-well regions 508A, 508B, and 508C are disposed in the substrate. The first P-well region 508A is disposed to the left of the first N-well region 506A, the second P-well region 508B is disposed to the right of the first N-well region 506A, the second N-well region 506B is disposed to the right of the second P-well region 508B, and the third P-well region 508C is disposed to the right of the second N-well region 506B. A first SRAM cell 502A includes the first N-well region 506A, the first P-well region 508A, and the second P-well region 508B. A second SRAM cell 502B includes the second N-well region 506B, the second P-well region 508B, and the third P-well region 508C. The N-type doped regions, such as N-well regions 506A and 506B, are doped with N-type dopants, such as phosphorus, arsenic, other N-type dopants, or combinations thereof. P-type doped regions, such as P-well regions 508A to 508C, are doped using P-type dopants, such as boron, indium, other P-type dopants, or combinations thereof. Various doped regions can be formed directly on and / or in the substrate, for example, providing P-well structures, N-well structures, dual-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form these various doped regions.

[0128] Active regions 510A to 510P are disposed above the substrate. Active regions 510A to 510D are disposed above the first P-well region 508A, active regions 510E and 510F are disposed above the first N-well region 506A, active regions 510G to 510J are disposed above the second P-well region 508B, active regions 510K and 510L are disposed above the second N-well region 506B, and active regions 510M to 510P are disposed above the third P-well region 508C. In some embodiments, active regions 510A to 510P include a channel region disposed between the source and drain regions of a FinFET. In some embodiments, the channel region and / or the source / drain region are formed in the fins of the FinFET. In some embodiments, active regions 510A to 510P include a channel region disposed between the source and drain regions of a gate-all-around (GAA) device. In some embodiments, the channel region is disposed in the suspended semiconductor layer of the GAA device, such as nanosheet channels, nanowire channels, strip channels, and / or other suitable configurations. Figure 6A As shown, each transistor device may include one or more active regions 510A to 510P.

[0129] The first SRAM cell 502A includes gate electrodes 512A to 512E. Gate electrode 512A forms a read pull-down transistor RPD in the first P-well region 508A with the underlying active regions 510A and 510B. Gate electrode 512A further forms a write pull-down transistor WPD-2 in the first P-well region 508A with the underlying active regions 510C and 510D. Gate electrode 512A also forms a write pull-up transistor WPU-2 in the first N-well region 506A with the underlying active region 510E. Gate electrode 512B forms a read transfer gate transistor RPG in the first P-well region 508A with the underlying active regions 510A and 510B. Gate electrode 512C forms a write transfer gate transistor WPG-2 in the first P-well region 508A with the underlying active regions 510C and 510D. Gate electrode 512D forms a write pull-up transistor WPU-1 in the first N-well region 506A together with the underlying active region 510F. Gate electrode 512D further forms a write pull-down transistor WPD-1 in the second P-well region 508B together with the underlying active regions 510G and 510H. Gate electrode 512E forms a write transfer gate transistor WPG-1 in the second P-well region 508B together with the underlying active regions 510G and 510H.

[0130] The second SRAM cell 502B includes gate electrodes 512E to 512I. Gate electrode 512E further forms a write transfer gate transistor WPG-1 for the second SRAM cell 502B in the second P-well region 508B together with the underlying active regions 510I and 510J. Gate electrode 512F further forms a write pull-down transistor WPD-1 in the second P-well region 508B together with the underlying active regions 510I and 510J. Gate electrode 512F further forms a write pull-up transistor WPU-1 in the second P-well region 508B together with the underlying active region 510K. Gate electrode 512G forms a write pull-up transistor WPU-2 in the second N-well region 506B together with the underlying active region 510L. Gate electrode 512G further forms a write pull-down transistor WPD-2 in the third P-well region 508C together with the underlying active regions 510M and 510N. Gate electrode 512G further forms a read pull-down transistor RPD with the underlying active regions 510O and 510P in the third P-well region 508C. Gate electrode 512H forms a write transfer gate transistor WPG-2 with the underlying active regions 510M and 510N in the third P-well region 508C. Gate electrode 512I forms a read transfer gate transistor RPG with the underlying active regions 510O and 510P in the third P-well region 508C.

[0131] In some embodiments, the pull-up transistors WPU-1 and WPU-2, the pull-down transistors WPD-1, WPD-2 and RPD, and the transfer gate transistors WPG-1, WPG-2 and RPG can be FinFET devices. In some embodiments, the pull-up transistors WPU-1 and WPU-2, the pull-down transistors WPD-1, WPD-2 and RPD, and the transfer gate transistors WPG-1, WPG-2 and RPG can be GAA devices having nanosheet channels, nanowire channels, strip channels and / or other suitable configurations.

[0132] Starting with the first SRAM cell 502A, the SD node includes a source / drain (S / D) contact 514A and a gate contact 516A. The S / D contact 514A is elongated and has a longitudinal direction in the X direction, parallel to the extension direction of the gate electrodes 512A to 512I. The gate contact 516A has a longitudinal direction in the Y direction, perpendicular to the X direction. The gate contact 516A is included above the S / D contact 514A and the gate electrode 512D, and is electrically coupled to portions of the S / D contact 514A and the gate electrode 512D. In some embodiments, the S / D contact 514A and the gate contact 516A may be formed as a single continuous contact or as butt contacts. In some embodiments, the S / D contact 514A and the gate contact 516A may be formed in separate processes to form butt contacts.

[0133] The SD node of the first SRAM cell 502A includes an S / D contact 514B and a gate contact 516B. The S / D contact 514B is elongated and has a longitudinal direction in the X direction. The gate contact 516B has a longitudinal direction in the Y direction. The gate contact 516B is included above the S / D contact 514B and the gate electrode 512A, and is electrically coupled to portions of the S / D contact 514B and the gate electrode 512A. In some embodiments, the S / D contact 514B and the gate contact 516B may be formed as a single continuous contact or a mating contact in a single process. In some embodiments, the S / D contact 514B and the gate contact 516B may be formed in separate processes to form a mating contact.

[0134] Continuing with the first SRAM cell 502A, S / D contact 514C connects the drain region of the read pull-down transistor RPD to the source / drain region of the read transfer gate transistor RPG. S / D contact 514D connects the source region of the read pull-down transistor RPD and the source region of the write pull-down transistor WPD-2 to the power lines of the first Vss node and the second Vss node, respectively. S / D contact 514E connects the source region of the write pull-up transistor WPU-2 to the power line at the Vdd node 108. S / D contact 514F connects the source / drain region of the write transfer gate transistor WPG-1 to the write bit line W_BL. S / D contact 514G connects the source / drain region of the read transfer gate transistor RPG to the read bit line R_BL. S / D contact 514H connects the source / drain region of the write transfer gate transistor WPG-2 to the write complementary bit line W_BLB. S / D contact 514I connects the source region of write pull-up transistor WPU-1 to the power line at the first Vdd node. S / D contact 514J connects the source region of write pull-down transistor WPD-1 to the power line at the third Vss node. S / D contact 514J extends from the first SRAM cell 502A into the second SRAM cell 502B, further connecting the write pull-down transistor WPD-1 of the second SRAM cell 502B to the power line at the third Vss node.

[0135] Turning to the second SRAM cell 502B, the SD node includes a source / drain (S / D) contact 514K and a gate contact 516C. The S / D contact 514K is elongated and has a longitudinal orientation in the X direction. The gate contact 516C has a longitudinal orientation in the Y direction. The gate contact 516C is included above the S / D contact 514K and the gate electrode 512G, and is electrically coupled to portions of the S / D contact 514K and the gate electrode 512G. In some embodiments, the S / D contact 514K and the gate contact 516C may be formed as a single continuous contact or as butt contacts. In some embodiments, the S / D contact 514K and the gate contact 516C may be formed in separate processes to form butt contacts.

[0136] The SD node of the second SRAM cell 502B includes an S / D contact 514L and a gate contact 516D. The S / D contact 514L is elongated and has a longitudinal direction in the X direction. The gate contact 516D has a longitudinal direction in the Y direction. The gate contact 516D is included above the S / D contact 514L and the gate electrode 512F, and is electrically coupled to portions of the S / D contact 514L and the gate electrode 512F. In some embodiments, the S / D contact 514L and the gate contact 516D can be formed as a single continuous contact or a mating contact in a single process. In some embodiments, the S / D contact 514L and the gate contact 516D can be formed in separate processes to form a mating contact.

[0137] Continuing with the second SRAM cell 502B, S / D contact 514J connects the source region of write pull-down transistor WPD-1 to the power supply line at the fourth Vss node. As described above, S / D contact 514J extends from the first SRAM cell 502A into the second SRAM cell 502B. S / D contact 514M connects the source / drain region of write transfer gate transistor WPG-1 to the write bit line W_BL. S / D contact 514N connects the source region of write pull-up transistor WPU-2 to the power supply line at the second Vdd node. S / D contact 514O connects the source region of read pull-down transistor RPD and the source region of write pull-down transistor WPD-2 to the power supply lines at the fifth and sixth Vss nodes, respectively. S / D contact 514P connects the drain region of read pull-down transistor RPD to the source / drain region of read transfer gate transistor RPG.

[0138] S / D contact 514Q connects the source / drain region of the read transfer gate transistor RPG to the read bit line R_BL. S / D contact 514R connects the source / drain region of the write transfer gate transistor WPG-2 to the write complementary bit line W_BLB. S / D contact 514S connects the source region of the write pull-up transistor WPU-1 to the power supply line at the second Vdd node.

[0139] Turn Figure 6B This illustrates additional features of a two-port SRAM cell layout 500, including gate vias, source / drain (S / D) vias, and conductors (collectively referred to as the first metal (M1) layer). These features can be disposed in one or more interlayer dielectric layers to form an interconnect structure. For clarity, Figure 6A The front-end features shown were not in Figure 6B The text appears to be incomplete and contains several errors. A more accurate translation would require the full context. Figure 5As shown. Gate vias 518A to 518C and S / D vias 520A to 520M are indicated using circles and an "x" symbol within the circles. Conductors 522 to 552 are indicated using rectangles. Each gate via 518A to 518C is positioned above its corresponding gate electrode and below its corresponding M1 layer conductors 522, 530, 540, 544, and 552. Each S / D via 520A to 520M is positioned above its corresponding contact and below its corresponding M1 layer conductors 524, 526, 528, 532, 534, 536, 538, 542, 546, 548, and 550.

[0140] Gate via 518A is disposed above gate electrode 512B and electrically coupled to gate electrode 512B, and is disposed below and electrically coupled to wire 522 of the read word line R_WL landing pad of the first SRAM cell 502A corresponding to the dual-port. Gate via 518B is disposed above gate electrode 512C and electrically coupled to gate electrode 512C, and is disposed below and electrically coupled to wire 530 of the write word line W_WL landing pad of the first SRAM cell 502A corresponding to the dual-port. Gate via 518C is disposed above gate electrode 512E and electrically coupled to gate electrode 512E, and is disposed below and electrically coupled to wire 540 of the write word line W_WL landing pad of the second SRAM cell 502B corresponding to the dual-port. A gate via 518D is disposed above and electrically coupled to the gate electrode 512H, and is disposed below and electrically coupled to the conductor 544 of the write word line W_WL landing pad of the corresponding dual-port second SRAM cell 502B. A gate via 518E is disposed above and electrically coupled to the gate electrode 512I, and is disposed below and electrically coupled to the conductor 552 of the read word line R_WL landing pad of the corresponding dual-port second SRAM cell 502B. Therefore, the second SRAM cell 502B includes two write word line landing pads (e.g., 540, 544) and one read word line landing pad (e.g., 552), and the first SRAM cell 502A includes one write word line landing pad (e.g., 530) and one read word line landing pad (e.g., 522). Read the character line landing pads on the cell boundary and write the character line landing pads inside the cell boundary.

[0141] S / D via 520A is disposed above S / D contact 514G and electrically coupled to S / D contact 514G, and disposed below the conductor 524 of the read bit line R_BL of the first SRAM cell 502A corresponding to the dual-port, and electrically coupled to conductor 524. S / D via 520B is disposed above S / D contact 514D and electrically coupled to S / D contact 514D, and disposed below the conductor 526 of the first Vss line of the first SRAM cell 502A corresponding to the dual-port, and electrically coupled to conductor 526. S / D via 520C is disposed above S / D contact 514H and electrically coupled to S / D contact 514H, and disposed below the conductor 528 of the write complementary bit line W_BLB of the first SRAM cell 502A corresponding to the dual-port, and electrically coupled to conductor 528. S / D via 520D is disposed above S / D contact 514E and electrically coupled to S / D contact 514E, and disposed below the conductor 532 of the Vdd line of the first SRAM cell 502A corresponding to the dual-port, and electrically coupled to conductor 532. S / D via 520E is disposed above S / D contact 514I and electrically coupled to S / D contact 514I, and disposed below the conductor 532 of the first Vdd line of the first SRAM cell 502A corresponding to the dual-port, and electrically coupled to conductor 532. S / D via 520F is disposed above S / D contact 514F and electrically coupled to S / D contact 514F, and disposed below the conductor 534 of the write bit line W_BL of the first SRAM cell 502A corresponding to the dual-port, and electrically coupled to conductor 534. S / D via 520G is disposed above S / D contact 514J and electrically coupled to S / D contact 514J, and disposed below and electrically coupled to the conductor 536 of the second Vss line shared between the first SRAM cell 502A and the second SRAM cell 502B in the dual-port configuration. S / D via 520H is disposed above S / D contact 514M and electrically coupled to S / D contact 514M, and disposed below and electrically coupled to the conductor 538 of the write bit line W_BL of the second SRAM cell 502B in the dual-port configuration. S / D via 520I is disposed above S / D contact 514N and electrically coupled to S / D contact 514N, and disposed below and electrically coupled to the conductor 542 of the Vdd line of the second SRAM cell 502B in the dual-port configuration. The S / D via 520J is disposed above the S / D contact 514S and electrically coupled to the S / D contact 514S, and is disposed below the conductor 542 of the Vdd line of the corresponding dual-port second SRAM cell 502B and electrically coupled to the conductor 542.S / D via 520K is disposed above S / D contact 514R and electrically coupled to S / D contact 514R, and disposed below the write complementary bit line W_BLB of the corresponding dual-port second SRAM cell 502B and electrically coupled to wire 546. S / D via 520L is disposed above S / D contact 514O and electrically coupled to S / D contact 514O, and disposed below the third Vss line of the corresponding dual-port second SRAM cell 502B and electrically coupled to wire 548. S / D via 520M is disposed above S / D contact 514Q and electrically coupled to S / D contact 514Q, and disposed below the read bit line R_BL of the corresponding dual-port second SRAM cell 502B and electrically coupled to wire 550.

[0142] The conductors in the first metal layer (i.e., 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552) have a longitudinal direction in the Y direction, which is substantially parallel to the longitudinal direction of the active regions 510A to 510P and substantially perpendicular to the longitudinal direction of the gate electrodes 512A to 512I. The landing pads (e.g., 522, 530, 540, 544, 552) in the M1 layer are shorter than the bit lines (e.g., 524, 528, 534, 538, 546, 550) and voltage lines (e.g., 526, 532, 542, 548) in the M1 layer. For example, in Figure 6A and Figure 6BIn this configuration, the length of the landing pad is less than the width of the first SRAM cell 502A and the second SRAM cell 502B, while the lengths of the bit lines and voltage lines are greater than the widths of the first SRAM cell 502A and the second SRAM cell 502B. In some embodiments, the bit lines and voltage lines are shared by more than one SRAM cell, such as SRAM cells in the same row. The first SRAM cell 502A and the second SRAM cell 502B each have a write word line landing pad located between the write complementary bit line and the Vdd line. For example, the first SRAM cell 502A has a write word line W_WL landing pad (e.g., 530) located between its write complementary bit line W_BLB (e.g., 528) and its Vdd line (e.g., 532) (or, in other words, located between its write pull-down transistor WPD-2 and write pull-up transistor WPU-2), and the second SRAM cell 502B has a write word line W_WL landing pad (e.g., 544) located between its write bit line W_BL (e.g., 546) and its Vdd line (e.g., 542) (or, in other words, located between the write pull-down transistor WPD-2 and write pull-up transistor WPU-2). The second SRAM cell 502B further includes a write word line W_WL landing pad (e.g., 540) located between its write bit line W_BL (e.g., 538) and its Vdd line (e.g., 542) (or, in other words, located between the write pull-down transistor WPD-1 and the write pull-up transistor WPU-1). Furthermore, the first SRAM cell 502A and the second SRAM cell 502B each have a Vss line located between the write complementary bit line and the read bit line. For example, the first SRAM cell 502A has a Vss line (e.g., 526) located between its read bit line R_BL (e.g., 524) and its write complementary bit line W_BLB (e.g., 528), and the second SRAM cell 502B has a Vss line (e.g., 548) located between its read bit line R_BL (e.g., 550) and its write complementary bit line W_BLB (e.g., 546). As described above, the first SRAM cell 502A and the second SRAM cell 502B further share a Vss line (e.g., 536), which is located between the write bit lines of adjacent SRAM cells, such as the write bit line W_BL of the first SRAM cell 502A (e.g., 534) and the write bit line W_BL of the second SRAM cell 502B (e.g., 538).

[0143] The rear-end features of the dual-port SRAM cell layout 500 include a second metal (M2) layer, a third metal (M3) layer, a fourth metal (M4) layer, and vias connecting each metal layer, as described above. Figure 3CThe descriptions are similar. A via is disposed above and electrically coupled to conductor 522 of layer M1, and disposed below and electrically coupled to a first portion of a first conductor of layer M2, the first portion of which is the read word line R_WL landing pad. A via is disposed above and electrically coupled to conductor 530 of layer M1, and disposed below and electrically coupled to a second conductor of layer M2, the second conductor of layer M2 being the write word line W_WL. A via is disposed above and electrically coupled to conductor 540 of layer M1, and disposed below and electrically coupled to a second conductor of layer M2, the second conductor of layer M2 being the write word line W_WL. A via is disposed above and electrically coupled to conductor 544 in layer M1, and disposed below and electrically coupled to a second conductor in layer M2, which is the write character line W_WL. A via is disposed above and electrically coupled to conductor 552 in layer M1, and disposed below and electrically coupled to a second portion of a first conductor in layer M2, which is the read character line R_WL landing pad. The first and second conductors in layer M2 extend longitudinally in the X direction.

[0144] A via is disposed above a first portion of the first conductor in layer M2 and electrically coupled to that first portion, and disposed below a first conductor in layer M3 and electrically coupled to that first conductor. The first conductor in layer M3 is the read word line R_WL landing pad. A via is disposed above a second portion of the first conductor in layer M2 and electrically coupled to that second portion, and disposed below a second conductor in layer M3 and electrically coupled to that second conductor. The second conductor in layer M3 is the read word line R_WL landing pad. The conductor in layer M3 extends longitudinally in the Y direction.

[0145] A via is disposed above and electrically coupled to the first conductor of layer M3, and disposed below and electrically coupled to the conductor of layer M4, which is the read character line R_WL. A via is disposed above and electrically coupled to the second conductor of layer M3, and disposed below and electrically coupled to the conductor of layer M4, which is the read character line R_WL. The conductor of layer M3 extends longitudinally in the X direction.

[0146] Figure 7A circuit diagram of a three-port SRAM cell 700 is shown according to some embodiments. The three-port SRAM cell 700 includes ten transistors and can perform a read and a write operation in a single time cycle. The SRAM cell 700 includes pull-up transistors WPU-1 and WPU-2, which are P-type metal-oxide-semiconductor (PMOS) transistors, and pull-down transistors WPD-1, WPD-2, RPD-1, and RPD-2, and transfer-gate transistors WPG-1, WPG-2, RPG-1, and RPG-2, which are N-type metal-oxide-semiconductor (NMOS) transistors. The gates of transfer-gate transistors WPG-1 and WPG-2 are controlled by word lines W_WL, which determine whether the SRAM cell 700 is selected for writing. The gates of transfer-gate transistors RPG-1 and RPG-2 are individually controlled by word lines R_WL-A and R_WL-B, which determine whether the SRAM cell 700 is selected for reading. A latch formed by pull-up transistors WPU-1 and WPU-2 and pull-down transistors WPD-1 and WPD-2 stores a bit, wherein the complementary value of the bit is stored in storage data (SD) nodes 702 and SD node 704. The stored bit can be written to SRAM cell 700 via complementary bit lines including write bit line W_BL and write complementary bit line W_BLB. The stored bit can be read from SRAM cell 700 via read bit line R_BL-A or read bit line R_BL-B. SRAM cell 700 is powered by a positive power supply node Vdd (also denoted as VDD) with a positive power supply voltage. SRAM cell 700 is also connected to power supply voltage Vss (also denoted as VSS), which can be electrically grounded. Transistors WPU-1 and WPD-1 form a first inverter. Transistors WPU-2 and WPD-2 form a second inverter. The input of the first inverter is connected to the output of transistor WPG-1 and the second inverter. The output of the first inverter is connected to transistor WPG-2 and the input of the second inverter. The output of the first inverter controls the read-down transistor RPD-1. The output of the second inverter controls the read-down transistor RPD-2.

[0147] The sources of pull-up transistors WPU-1 and WPU-2 are individually connected to Vdd nodes 706 and 708, which are further connected to the power supply voltage (and line) Vdd. The sources of pull-down transistors WPD-1 and WPD-2 are individually connected to Vss nodes 710 and 714, which are further connected to the power supply voltage / line Vss. The sources of pull-down transistors RPD-1 and RPD-2 are individually connected to Vss nodes 712 and 716, which are further connected to the power supply voltage / line Vss. The drain of pull-down transistor RPD-1 is connected to the source / drain region of transfer gate transistor RPG-1. The drain of pull-down transistor RPD-2 is connected to the source / drain region of transfer gate transistor RPG-2. The gates of transistors WPU-1 and WPD-1 are connected to the drains of transistors WPU-2 and WPD-2, forming a connection node referred to as SD node 702. The gates of transistors WPU-2, WPD-2, and RPD-2 are connected to the drains of transistors WPU-1 and WPD-1, forming a connection node known as SD node 704. The source / drain region of transfer gate transistor WPG-1 is connected to the write bit line W_BL. The source / drain region of transfer gate transistor WPG-2 is connected to the write complementary bit line W_BLB. The source / drain region of transfer gate transistor RPG-1 is connected to the read bit line R_BL-A. The source / drain region of transfer gate transistor RPG-2 is connected to the read bit line R_BL-B.

[0148] Figure 8 A top view of an exemplary three-port SRAM cell layout 800 is shown according to various aspects of this disclosure, including a three-port SRAM cell 700. Figures 9A to 9C The top view of each layer of the three-port SRAM cell layout 800 is shown. Figure 9A The front-end features, including the substrate, active device region, gate structure, and contacts, are shown. Figure 9B The diagram shows mid-section features including a gate via, a source / drain (S / D) via, and a first metal layer. Figure 9C The rear section features include a second metal layer, a third metal layer, a fourth metal layer, and vias connecting each metal layer.

[0149] Turn Figure 9AThis diagram illustrates the front-end features of a three-port SRAM cell layout 800, including a substrate, an active device region, a gate structure, and contacts. The three-port SRAM cell layout 800 includes a substrate (wafer). In some embodiments, the substrate comprises silicon. Alternatively (or additionally), the substrate may include another element, such as germanium; compound semiconductors, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. Alternatively, the substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using oxygen-injected isolation (SIMOX), wafer bonding, and / or other suitable methods.

[0150] N-well region 802 and P-well regions 804A and 804B are disposed in the substrate, with the first P-well region 804A located to the left of N-well region 802 and the second P-well region 804B located to the right of N-well region 802. N-type doped regions, such as N-well region 802, are doped with N-type dopants, such as phosphorus, arsenic, other N-type dopants, or combinations thereof. P-type doped regions, such as P-well regions 804A and 804B, are doped using P-type dopants, such as boron, indium, other P-type dopants, or combinations thereof. Various doped regions can be formed directly on and / or in the substrate, for example, providing P-well structures, N-well structures, dual-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form various doped regions. The outer boundaries 806A, 806B, 806C, and 806D of the three-port SRAM cell layout 800 are shown using dashed lines, marking rectangular areas.

[0151] Active regions 808A to 808J are disposed above the substrate. Active regions 808A, 808B, 808C, and 808D are disposed above the first P-well region 804A, active regions 808E and 808F are disposed above the N-well region 802, and active regions 808G, 808H, 808I, and 808J are disposed above the second P-well region 804B. In some embodiments, active regions 808A to 808J may be FinFETs. In some embodiments, active regions 808A to 808J may be gate-all-around (GAA) devices. In some embodiments, active regions 808A to 808J may include channel regions configured as nanosheet channels, nanowire channels, strip channels, and / or other suitable configurations. (See above regarding...) Figure 9AEach transistor device under discussion may include one or more active regions 808A to 808J.

[0152] Gate electrode 810A forms a read transfer gate transistor RPG-1 in the first P-well region 804A together with the underlying active regions 808A and 808B. Gate electrode 810B forms a read pull-down transistor RPD-1 in the first P-well region 804A together with the underlying active regions 808A and 808B. Gate electrode 810B further forms a write pull-down transistor WPD-1 in the first P-well region 804A together with the underlying active regions 808C and 808D. Gate electrode 810B further forms a write pull-up transistor WPU-1 in the N-well region 802 together with the underlying active region 808E. Gate electrode 810C forms a write transfer gate transistor WPG-1 in the first P-well region 804A together with the underlying active regions 808C and 808D. Gate electrode 810D forms a write pull-up transistor WPU-2 in the N-well region 802 together with the underlying active region 808F. Gate electrode 810D further forms a write pull-down transistor WPD-2 in the second P-well region 804B together with the underlying active regions 808G and 808H. Gate electrode 810D further forms a read pull-down transistor RPD-2 in the second P-well region 804B together with the underlying active regions 808I and 808J. Gate electrode 810E forms a write transfer gate transistor WPG-2 in the second P-well region 804B together with the underlying active regions 808G and 808H. Gate electrode 810F forms a read transfer gate transistor RPG-2 in the second P-well region 804B together with the underlying active regions 808I and 808J. In some embodiments, pull-up transistors WPU-1 and WPU-2, pull-down transistors WPD-1, WPD-2, RPD-1 and RPD-2, and transfer gate transistors WPG-1 and WPG-2, RPG-1 and RPG-2 may be FinFET devices. In some embodiments, pull-up transistors WPU-1 and WPU-2, pull-down transistors WPD-1, WPD-2, RPD-1 and RPD-2, and transfer gate transistors WPG-1 and WPG-2, RPG-1 and RPG-2 may be GAA devices having nanosheet channels, nanowire channels, strip channels and / or other suitable configurations.

[0153] SD node 802 includes a source / drain (S / D) contact 812A and a gate contact 814A. The S / D contact 812A is elongated and has a longitudinal direction in the X direction, parallel to the extension direction of gate electrodes 810A to 810F. The gate contact 814A has a longitudinal direction in the Y direction, perpendicular to the X direction. The gate contact 814A is included above the S / D contact 812A and the gate electrode 810B, and is electrically coupled to portions of the S / D contact 812A and the gate electrode 810B. In some embodiments, the S / D contact 812A and the gate contact 814A may be formed as a single continuous contact or as butt contacts. In some embodiments, the S / D contact 812A and the gate contact 814A may be formed in separate processes to form butt contacts.

[0154] SD node 804 includes an S / D contact 812B and a gate contact 814B. The S / D contact 812B is elongated and has a longitudinal orientation in the X direction. The gate contact 814B has a longitudinal orientation in the Y direction. The gate contact 814B is included above the S / D contact 812B and the gate electrode 810D, and is electrically coupled to portions of the S / D contact 812B and the gate electrode 810D. In some embodiments, the S / D contact 812B and the gate contact 814B may be formed as a single continuous contact or a mating contact in a single process. In some embodiments, the S / D contact 812B and the gate contact 814B may be formed in separate processes to form a mating contact.

[0155] S / D contact 812C connects the source / drain region of the read transfer gate transistor RPG-1 to the drain region of the read pull-down transistor RPD-1. S / D contact 812D connects the source / drain region of the read transfer gate transistor RPG-1 to the read bit line R_BL-A. S / D contact 812E connects the source / drain region of the write transfer gate transistor WPG-1 to the write bit line W_BL. S / D contact 812F connects the source region of the write pull-up transistor WPU-2 to Vdd at node 708. S / D contact 812G connects the source regions of the write pull-down transistor WPD-2 and the read pull-down transistor RPD-2 to nodes 714 and 716 of Vss, respectively. S / D contact 812H connects the source / drain region of the read transfer gate transistor RPG-2 to the drain region of the read pull-down transistor RPD-2. S / D contact 812I connects the source / drain region of the read transfer gate transistor RPG-2 to the read bit line R_BL-B. S / D contact 812J connects the source / drain region of the write transfer gate transistor WPG-2 to the write bit line W_BLB. S / D contact 812K connects the source region of the write pull-up transistor WPU-1 to the Vdd node 706. S / D contact 812L connects the source regions of the write pull-down transistor WPD-1 and the read pull-down transistor RPD-1 to the Vss nodes 710 and 712 respectively.

[0156] S / D contacts 812C to 812L are elongated and have a longitudinal orientation in the X direction, parallel to gate electrodes 810A to 810F. In some embodiments, one or more elongated S / D contacts 812A to 812L may further extend into adjacent SRAM cells adjacent to SRAM cell 800.

[0157] Turn Figure 9B This illustrates additional front-end features of a three-port SRAM cell layout 800, including gate vias, source / drain (S / D) vias, and conductors (collectively referred to as the first metal (M1) layer). These features can be disposed in one or more interlayer dielectric layers to form interconnect structures. For clarity, Figure 9A The front-end features shown were not in Figure 9B The text appears to be incomplete and contains several errors. A more accurate translation would require the full context. Figure 8As shown. Gate vias 816A to 816D and S / D vias 818A to 818H are indicated by circles and an "x" symbol within the circles. Conductors 820 to 840 are indicated by rectangles. Each gate via 816A to 816D is positioned above its corresponding gate electrode and below its corresponding M1 layer conductors 820, 828, 832, and 840. Each S / D via 818A to 818H is positioned above its corresponding contact and below its corresponding M1 layer conductors 822, 824, 826, 830, 834, 836, and 838.

[0158] Gate via 816A is disposed above gate electrode 810A and electrically coupled to gate electrode 810A, and disposed below conductor 220 corresponding to read word line R_WL-A and electrically coupled to conductor 820. Gate via 816B is disposed above gate electrode 810C and electrically coupled to gate electrode 810C, and disposed below conductor 828 corresponding to write word line W_WL and electrically coupled to conductor 828. Gate via 816C is disposed above gate electrode 810E and electrically coupled to gate electrode 810E, and disposed below conductor 832 corresponding to write word line W_WL and electrically coupled to conductor 832. Gate via 816D is disposed above gate electrode 810F and electrically coupled to gate electrode 810F, and disposed below conductor 840 corresponding to read word line R_WL-B and electrically coupled to conductor 840.

[0159] S / D via 818A is located above S / D contact 812D and electrically coupled to S / D contact 812D, and is located below the conductor 822 of the corresponding read bit line R_BL-A and electrically coupled to conductor 822. S / D via 818B is located above S / D contact 812L and electrically coupled to S / D contact 812L, and is located below the conductor 824 of the corresponding Vss nodes 710 and 712 and electrically coupled to conductor 824. S / D via 818C is located above S / D contact 812E and electrically coupled to S / D contact 812E, and is located below the conductor 826 of the corresponding write bit line W_BL and electrically coupled to conductor 826. S / D via 818D is disposed above S / D contact 812F and electrically coupled to S / D contact 812F, and disposed below the corresponding Vdd conductor 830 and electrically coupled to conductor 830. S / D via 818E is disposed above S / D contact 812K and electrically coupled to S / D contact 812K, and disposed below the corresponding Vdd conductor 830 and electrically coupled to conductor 830. S / D via 818F is disposed above S / D contact 812J and electrically coupled to S / D contact 812J, and disposed below the corresponding write complementary bit line W_BLB conductor 834 and electrically coupled to conductor 834. S / D via 818G is disposed above S / D contact 812G and electrically coupled to S / D contact 812G, and disposed below the conductor 836 of the corresponding Vss nodes 714 and 716 and electrically coupled to conductor 836. S / D via 818H is disposed above S / D contact 812I and electrically coupled to S / D contact 812I, and disposed below the conductor 838 of the corresponding read bit line R_BL-B and electrically coupled to conductor 838.

[0160] The wires 820 to 840 correspond to the above information. Figure 7 The described Vdd, Vss, write, and read lines are described. Wires 820 to 840 extend longitudinally in the Y direction. In some embodiments, wires 820 to 840 extend into adjacent SRAM cells. In some embodiments, one or more wires 820 to 840 may be shared with adjacent SRAM cells.

[0161] Wire 820 is the read word line landing pad corresponding to the read word line R_WL-A of the read transfer gate transistor RPG-1. Wire 822 is the read bit line landing pad corresponding to the read bit line R_BL-A of the read transfer gate transistor RPG-1. Wire 824 is the first Vss line corresponding to Vss nodes 710 and 712. Wire 826 is the write bit line landing pad corresponding to the write bit line W_BL. Wire 828 is the first write word line landing pad corresponding to the write word line W_WL of the write transfer gate transistor WPG-1. Wire 830 is the first Vdd line corresponding to Vdd node 706. Wire 832 is the second write word line landing pad corresponding to the write word line W_WL of the write transfer gate transistor WPG-2. Wire 834 is the write complementary bit line landing pad corresponding to the write complementary bit line W_BLB. Wire 836 is the second Vss line corresponding to Vss nodes 714 and 716. Wire 838 is the read bit line landing pad corresponding to the read bit line R_BL-B of the read transfer gate transistor RPG-2. Wire 840 is the read word line landing pad corresponding to the read word line R_WL-B of the read transfer gate transistor RPG-2.

[0162] Turn Figure 9C This shows the back-end features of a three-port SRAM cell layout 800, including a second metal (M2) layer, a third metal (M3) layer, a fourth metal (M4) layer, and vias connecting each metal layer. The vias are indicated using circles and an "x" symbol within the circles. For clarity, only those shown in the image are explicitly highlighted. Figure 9B The conductors of the M1 layer shown in the front section feature are displayed Figure 9C However, other front-end features still exist, such as Figure 8 As shown.

[0163] Via 842A is disposed above and electrically coupled to conductor 820 of layer M1, and disposed below and electrically coupled to conductor 844 of layer M2, which serves as the landing pad for the corresponding read word line R_WL-A. Via 842B is disposed above and electrically coupled to conductor 828 of layer M1, and disposed below and electrically coupled to conductor 846 of layer M2, which corresponds to write word line W_WL. Via 842C is disposed above and electrically coupled to conductor 832 of layer M1, and disposed below and electrically coupled to conductor 846 of layer M2, which corresponds to write word line W_WL. Through-hole 842D is disposed above conductor 840 of layer M1 and electrically coupled to conductor 840 of layer M1, and disposed below conductor 848 of layer M2, which serves as the landing pad for the corresponding read character line R_WL-B, and electrically coupled to conductor 848 of layer M2. Conductors 844, 846, and 848 of layer M2 extend longitudinally in the X direction.

[0164] Through-hole 850A is disposed above and electrically coupled to conductor 844 of layer M2, and disposed below and electrically coupled to conductor 852 of layer M3, which serves as a landing pad for read character lines. Through-hole 850B is disposed above and electrically coupled to conductor 848 of layer M2, and disposed below and electrically coupled to conductor 854 of layer M3, which serves as a landing pad for read character lines. Conductors 852 and 854 of layer M3 extend longitudinally in the Y direction, which is perpendicular to the X direction.

[0165] Through-hole 856A is disposed above and electrically coupled to conductor 852 of layer M3, and disposed below and electrically coupled to conductor 858 of layer M4 corresponding to read character line R_WL-A. Through-hole 856B is disposed above and electrically coupled to conductor 854 of layer M3, and disposed below and electrically coupled to conductor 860 of layer M4 corresponding to read character line R_WL-B. Conductors 858 and 860 of layer M4 extend longitudinally in the X direction.

[0166] The dual-port SRAM cell layout 500 and the triple-port SRAM cell layout 800 offer additional improvements over those discussed above regarding the dual-port SRAM cell layout 200. The new connection structures of the dual-port SRAM cell layout 500 and the triple-port SRAM cell layout 800 require fewer M1 metal lines to complete critical cell connections compared to previous layout methods. Generally, fewer M1 metal lines improve the scalability of the cell layout. Combining the reduction in M1 metal lines with the aforementioned advantages further improves the speed and performance of the SRAM cells.

[0167] As used throughout this disclosure, the gate structure may include a gate dielectric layer, a gate electrode, and a gate spacer. The gate structure may include many other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In the illustrated embodiments, the gate dielectric includes a high-k dielectric layer comprising a high-k dielectric material, such as hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicate (HfSiO4), hafnium silicon oxynitride (HfSiON), hafnium lanthanum oxide (HfLaO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or hafnium aluminum oxide (HfAlO). x Zirconia (ZrO), zirconium dioxide (ZrO2), zirconium silicon dioxide (ZrSiO2), aluminum monoxide (AlO), aluminum silicon dioxide (AlSiO), aluminum oxide (Al2O3), titanium monoxide (TiO), titanium dioxide (TiO2), lanthanum monoxide (LaO), lanthanum silicon oxide (LaSiO), tantalum trioxide (Ta2O3), tantalum pentoxide (Ta2O5), yttrium trioxide (Y2O3), strontium titanate (SrTiO3), barium zirconium oxide (BaZrO), barium titanate (BaTiO3(BTO)), barium strontium titanate ((Ba,Sr)TiO3(BST)), silicon nitride (Si3N4), hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, such as a dielectric constant greater than that of silicon oxide (k≈3.9). High-k dielectric layers are formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), oxidation-based deposition processes, other suitable processes, or combinations thereof. In some embodiments, the gate dielectric includes an interface layer disposed between the high-k dielectric layer and the channel layer.

[0168] The gate electrode comprises a conductive material, such as polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer tuned to have a desired work function (e.g., an N-type work function or a P-type work function), and a conductive bulk layer is a conductive layer formed above the work function layer. In some embodiments, the work function layer is an N-type work function layer and includes any suitable work function material, such as titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum silicon carbide (TiAlSiC), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminide (TaAl), tantalum aluminum carbide (TaAlC), tantalum silicon aluminum carbide (TaSiAlC), titanium aluminum nitride (TiAlN), other N-type work function materials, or combinations thereof. In some embodiments, the work function layer includes P-type work function materials, such as ruthenium (Ru), molybdenum (Mo), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), other suitable P-type work function materials, or combinations thereof. The bulk (or filled) conductive layer comprises a suitable conductive material, such as aluminum (Al), tungsten (W), and / or copper (Cu). The bulk conductive layer may additionally or collectively comprise polycrystalline silicon, titanium (Ti), tantalum (Ta), metal alloys, other suitable materials, or combinations thereof. The work function layer and / or conductive bulk layer are formed by ALD, CVD, PVD, electroplating, other deposition processes, or combinations thereof.

[0169] The gate spacer dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbide nitride (SiCN), silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOCN)). For example, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may be deposited over the gate structure and subsequently etched (e.g., anisotropic etching) to form the gate spacer. In some embodiments, the gate spacer comprises a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the gate structure. In such embodiments, different sets of spacers may comprise materials with different etch rates. For example, a first dielectric layer comprising silicon and oxygen (e.g., silicon oxide) can be deposited and etched to form a first spacer set adjacent to the gate structure, and a second dielectric layer comprising silicon and nitrogen (e.g., silicon nitride) can be deposited and etched to form a second spacer set adjacent to the first spacer set.

[0170] This disclosure provides numerous different embodiments. An exemplary device includes an integrated circuit structure comprising a memory cell and an interconnect structure disposed above and electrically coupled to the memory cell. The interconnect structure includes a first metal layer having bit lines, a first voltage line configured to receive a first voltage, a word line landing pad, a complementary bit line, and a second voltage line configured to receive a second voltage different from the first voltage. The first metal layer is electrically coupled to the memory cell. The interconnect structure also includes a second metal layer disposed above the first metal layer, wherein the second metal layer includes word lines electrically coupled to the word line landing pad. The word line landing pad is disposed between the first voltage line and the complementary bit line, and the first voltage line and the complementary bit line are disposed between the bit line and the second voltage line.

[0171] In some embodiments, the first metal layer further includes a third voltage line configured to receive a second voltage, wherein a bit line is disposed between the third voltage line and the first voltage line.

[0172] In some embodiments, the character line landing pad is a first character line landing pad, and the first metal layer further includes a second character line landing pad, wherein a third voltage line is disposed between the second character line landing pad and the bit line.

[0173] In some embodiments, the word lines of the second metal layer are electrically coupled to the second word line landing pad.

[0174] In some embodiments, the bit line is the first bit line, wherein the integrated circuit structure further includes a second bit line, and a second voltage line is disposed between the second bit line and the complementary bit line.

[0175] In some embodiments, the character line landing pad is a first character line landing pad, and the first metal layer further includes a second character line landing pad, wherein a second voltage line is disposed between the second character line landing pad and the complementary bit line.

[0176] In some embodiments, the integrated circuit structure further includes a third metal layer, wherein the third metal layer is electrically coupled to the second word line landing pad.

[0177] Another exemplary device includes an integrated circuit structure having memory cells and interconnect structures. The memory cells have pull-up devices, pull-down devices, and transmission gate devices. The pull-up and pull-down devices share a first gate structure, and the transmission gate devices have a second gate structure. The interconnect structures include a first metal layer and a second metal layer. The first metal layer includes bit lines, a first voltage line connected to the pull-up devices and configured to receive a first voltage, a word line landing pad connected to the transmission gate devices, a complementary bit line connected to the transmission gate devices, and a second voltage line connected to the pull-down devices and configured to receive a second voltage different from the first voltage. The second metal layer is disposed above the first metal layer and includes word lines connected to the word line landing pads. The first voltage line is adjacent to the bit lines, the word line landing pad is adjacent to the first voltage line, the complementary bit line is adjacent to the word line landing pad, and the second voltage line is adjacent to the complementary bit line. The word line landing pad is located between the pull-up and pull-down devices.

[0178] In some embodiments, the pull-up device is a first pull-up device, wherein the memory cell further includes a second pull-up device, wherein the first voltage line is connected to the second pull-up device.

[0179] In some embodiments, the transmission gate device is a first transmission gate device, wherein the memory cell further includes a second transmission gate device, and the bit line is connected to the second transmission gate device.

[0180] In some embodiments, the pull-down device is a first pull-down device, wherein the memory cell further includes a second pull-down device, and the first metal layer further includes a third voltage line connected to the second pull-down device, the third voltage line being configured to receive a second voltage, and the third voltage line being adjacent to a bit line.

[0181] In some embodiments, the pull-down device is a first pull-down device, wherein the memory cell further includes a second pull-down device that shares a first gate structure with the pull-up device and the first pull-down device, and a second voltage line is connected to the second pull-down device.

[0182] In some embodiments, the transmission gate device is a first transmission gate device, and the bit line is the first bit line, wherein the memory cell further includes a second transmission gate device, and the first metal layer further includes a second bit line connected to the second transmission gate device, and the second bit line is adjacent to the second voltage line.

[0183] In some embodiments, the character line landing pad is a first character line landing pad, wherein the first metal layer further includes a second character line landing pad connected to the second transmission gate device, and the second character line landing pad is adjacent to the second character line.

[0184] An exemplary device includes an integrated circuit structure having memory cells and interconnect structures. The memory cells include pull-up devices, pull-down devices, a first transmission gate device, and a second transmission gate device. The pull-up and pull-down devices share a first gate structure, the first transmission gate device has a second gate structure, and the second transmission gate device has a third gate structure. The interconnect structures include a first metal layer and a second metal layer. The first metal layer includes bit lines, a first voltage line configured to receive a first voltage, word line landing pads connected to the second gate structure, complementary bit lines connected to the first transmission gate device, and a second voltage line configured to receive a second voltage different from the first voltage. The second metal layer is disposed above the first metal layer. The second metal layer includes word lines connected to the word line landing pads. The first voltage line is adjacent to the bit line, the word line landing pad is adjacent to the first voltage line, the complementary bit line is adjacent to the word line landing pad, and the second voltage line is adjacent to the complementary bit line. The word line landing pads extend above the first and second gate structures.

[0185] In some embodiments, the second gate structure has a first end adjacent to the first voltage line and a second opposite end adjacent to the third gate structure, wherein the interconnect structure further includes a via connecting the second gate structure to the word line landing pad, and the via is disposed at the first end of the second gate structure.

[0186] In some embodiments, the bit line is the first bit line, wherein the first metal layer further includes a second bit line connected to the second transmission gate device, and the second bit line is adjacent to the second voltage line.

[0187] In some embodiments, the word line landing pad is a first word line landing pad, wherein the first metal layer further includes a second word line landing pad connected to the third gate structure, and the second word line landing pad is adjacent to the second bit line.

[0188] In some embodiments, the character line is a first character line, wherein the interconnect structure further includes a third metal layer above the second metal layer, wherein the third metal layer includes a second character line different from the first character line, wherein the second character line is connected to the second character line landing pad.

[0189] In some embodiments, the first voltage line has a first width, and the second voltage line has a second width greater than the first width.

[0190] The foregoing outlines features of numerous embodiments to enable those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. An integrated circuit structure, comprising: One memory unit; as well as An interconnect structure is disposed above the memory cell and electrically coupled to the memory cell, wherein the interconnect structure includes: A first metal layer electrically coupled to the memory cell, wherein the first metal layer includes a bit line, a first voltage line configured to receive a first voltage, a word line landing pad, a complementary bit line, and a second voltage line configured to receive a second voltage, wherein the second voltage is different from the first voltage. A second metal layer is disposed above the first metal layer, wherein the second metal layer includes a character line electrically coupled to the character line landing pad; and The aforementioned character line landing pad is disposed between the aforementioned first voltage line and the aforementioned complementary bit line, and the aforementioned first voltage line and the aforementioned complementary bit line are disposed between the aforementioned bit line and the aforementioned second voltage line.

2. The integrated circuit structure of claim 1, wherein the first metal layer further includes a third voltage line configured to receive the second voltage, wherein the bit line is disposed between the third voltage line and the first voltage line.

3. The integrated circuit structure as claimed in claim 2, wherein the word line landing pad is a first word line landing pad, and the first metal layer further includes a second word line landing pad, wherein the third voltage line is disposed between the second word line landing pad and the bit line.

4. The integrated circuit structure of claim 3, wherein the word line of the second metal layer is electrically coupled to the second word line landing pad.

5. The integrated circuit structure as claimed in claim 1, wherein the bit line is a first bit line, wherein the integrated circuit structure further includes a second bit line, and the second voltage line is disposed between the second bit line and the complementary bit line.

6. The integrated circuit structure of claim 1, wherein the word line landing pad is a first word line landing pad, and the first metal layer further includes a second word line landing pad, wherein the second voltage line is disposed between the second word line landing pad and the complementary bit line.

7. The integrated circuit structure of claim 6 further includes a third metal layer, wherein the third metal layer is electrically coupled to the second word line landing pad.

8. An integrated circuit structure, comprising: A memory cell includes a pull-up device, a pull-down device, and a transmission gate device, wherein the pull-up device and the pull-down device share a first gate structure, and the transmission gate device has a second gate structure; and An interconnect structure having: A first metal layer includes a bit line, a first voltage line connected to the pull-up device and configured to receive a first voltage, a bit line landing pad connected to the transmission gate device, a complementary bit line connected to the transmission gate device, and a second voltage line connected to the pull-down device and configured to receive a second voltage, the second voltage being different from the first voltage. A second metal layer above the first metal layer, wherein the second metal layer includes a character line connected to the character line landing pad; Wherein, the first voltage line is adjacent to the bit line, the word line landing pad is adjacent to the first voltage line, the complementary bit line is adjacent to the word line landing pad, and the second voltage line is adjacent to the complementary bit line; and The aforementioned character line landing pad is located between the aforementioned pull-up device and the aforementioned pull-down device.

9. The integrated circuit structure of claim 8, wherein the pull-up device is a first pull-up device, wherein the memory cell further includes a second pull-up device, and wherein the first voltage line is connected to the second pull-up device.

10. The integrated circuit structure of claim 8, wherein the transmission gate device is a first transmission gate device, wherein the memory cell further includes a second transmission gate device, and the bit line is connected to the second transmission gate device.

11. The integrated circuit structure of claim 10, wherein the pull-down device is a first pull-down device, wherein the memory cell further includes a second pull-down device, and the first metal layer further includes a third voltage line connected to the second pull-down device, the third voltage line being configured to receive the second voltage, and the third voltage line being adjacent to the bit line.

12. The integrated circuit structure of claim 8, wherein the pull-down device is a first pull-down device, wherein the memory cell further includes a second pull-down device that shares the first gate structure with the pull-up device and the first pull-down device, and the second voltage line is connected to the second pull-down device.

13. The integrated circuit structure of claim 8, wherein the transmission gate device is a first transmission gate device and the bit line is a first bit line, wherein the memory cell further includes a second transmission gate device, and the first metal layer further includes a second bit line connected to the second transmission gate device, and the second bit line is adjacent to the second voltage line.

14. The integrated circuit structure of claim 13, wherein the word line landing pad is a first word line landing pad, wherein the first metal layer further includes a second word line landing pad connected to the second transmission gate device, and the second word line landing pad is adjacent to the second bit line.

15. An integrated circuit structure, comprising: A memory cell includes a pull-up device, a pull-down device, a first transmission gate device, and a second transmission gate device, wherein the pull-up device and the pull-down device share a first gate structure, the first transmission gate device has a second gate structure, and the second transmission gate device has a third gate structure; and An interconnect structure having: A first metal layer includes a bit line, a first voltage line configured to receive a first voltage, a word line landing pad connected to the second gate structure, a complementary bit line connected to the first transmission gate device, and a second voltage line configured to receive a second voltage, the second voltage being different from the first voltage. A second metal layer above the first metal layer, wherein the second metal layer includes a character line connected to the character line landing pad; Wherein, the first voltage line is adjacent to the bit line, the word line landing pad is adjacent to the first voltage line, the complementary bit line is adjacent to the word line landing pad, and the second voltage line is adjacent to the complementary bit line; and The aforementioned character line landing pad extends above the aforementioned first gate structure and the aforementioned second gate structure.

16. The integrated circuit structure of claim 15, wherein the second gate structure has a first end adjacent to the first voltage line and a second opposite end adjacent to the third gate structure, wherein the interconnect structure further includes a through hole connecting the second gate structure to the word line landing pad, and the through hole is disposed at the first end of the second gate structure.

17. The integrated circuit structure of claim 15, wherein the bit line is a first bit line, wherein the first metal layer further includes a second bit line connected to the second transmission gate device, and the second bit line is adjacent to the second voltage line.

18. The integrated circuit structure of claim 17, wherein the word line landing pad is a first word line landing pad, wherein the first metal layer further includes a second word line landing pad connected to the third gate structure, and the second word line landing pad is adjacent to the second bit line.

19. The integrated circuit structure of claim 18, wherein the word line is a first word line, wherein the interconnect structure further includes a third metal layer above the second metal layer, wherein the third metal layer includes a second word line different from the first word line, wherein the second word line is connected to the second word line landing pad.

20. The integrated circuit structure of claim 15, wherein the first voltage line has a first width, and the second voltage line has a second width greater than the first width.

21. A method for forming an integrated circuit structure, comprising: Form a memory cell; as well as An interconnect structure is formed above and electrically coupled to the memory cell, wherein the operation of forming the interconnect structure includes: A first metal layer is formed electrically coupled to the memory cell, wherein the first metal layer includes a bit line, a first voltage line configured to receive a first voltage, a word line landing pad, a complementary bit line, and a second voltage line configured to receive a second voltage, the second voltage being different from the first voltage. as well as A second metal layer is formed above the first metal layer, wherein the second metal layer includes a word line electrically coupled to the word line landing pad, the word line landing pad being between the first voltage line and the complementary bit line, and the first voltage line and the complementary bit line being between the bit line and the second voltage line.

22. The method for forming an integrated circuit structure as claimed in claim 21, wherein the first metal layer further includes a third voltage line configured to receive the second voltage, wherein the bit line is disposed between the third voltage line and the first voltage line.

23. The method for forming an integrated circuit structure as described in claim 22, wherein the word line landing pad is a first word line landing pad, and the first metal layer further includes a second word line landing pad, wherein the third voltage line is disposed between the second word line landing pad and the bit line.

24. The method of forming an integrated circuit structure as claimed in claim 23, wherein the word line of the second metal layer is electrically coupled to the second word line landing pad.

25. The method for forming an integrated circuit structure as claimed in claim 21, wherein the bit line is a first bit line, and the method for forming the integrated circuit structure further includes forming a second bit line, wherein the second voltage line is disposed between the second bit line and the complementary bit line.

26. The method for forming an integrated circuit structure as claimed in claim 21, wherein the word line landing pad is a first word line landing pad, and the first metal layer further includes a second word line landing pad, wherein the second voltage line is disposed between the second word line landing pad and the complementary bit line.

27. The method of forming an integrated circuit structure as claimed in claim 26, further comprising forming a third metal layer, wherein the third metal layer is electrically coupled to the second word line landing pad.

28. A method for forming an integrated circuit structure, comprising: A memory cell is formed having a pull-up device, a pull-down device, and a transmission gate device, wherein the pull-up device and the pull-down device share a first gate structure, and the transmission gate device has a second gate structure. as well as Forming an interconnect structure, wherein the operations for forming the interconnect structure include: A first metal layer is formed, the first metal layer including a bit line, a first voltage line connected to the pull-up device and configured to receive a first voltage, a bit line landing pad connected to the transmission gate device, a complementary bit line connected to the transmission gate device, and a second voltage line connected to the pull-down device and configured to receive a second voltage, the second voltage being different from the first voltage. A second metal layer is formed above the first metal layer, wherein the second metal layer includes a character line connected to the character line landing pad; Wherein, the first voltage line is adjacent to the bit line, the word line landing pad is adjacent to the first voltage line, the complementary bit line is adjacent to the word line landing pad, and the second voltage line is adjacent to the complementary bit line; and The aforementioned character line landing pad is located between the aforementioned pull-up device and the aforementioned pull-down device.

29. The method for forming an integrated circuit structure as described in claim 28, wherein the pull-up device is a first pull-up device, wherein the memory cell further includes a second pull-up device, and wherein the first voltage line is connected to the second pull-up device.

30. The method for forming an integrated circuit structure as claimed in claim 28, wherein the transmission gate device is a first transmission gate device, wherein the memory cell further includes a second transmission gate device, and the bit line is connected to the second transmission gate device.

31. The method for forming an integrated circuit structure as claimed in claim 30, wherein the pull-down device is a first pull-down device, the memory cell further includes a second pull-down device, the first metal layer further includes a third voltage line connected to the second pull-down device, the third voltage line is configured to receive the second voltage, and the third voltage line is adjacent to the bit line.

32. The method for forming an integrated circuit structure as claimed in claim 28, wherein the pull-down device is a first pull-down device, the memory cell further includes a second pull-down device that shares the first gate structure with the pull-up device and the first pull-down device, and the second voltage line is connected to the second pull-down device.

33. The method for forming an integrated circuit structure as described in claim 28, wherein the transmission gate device is a first transmission gate device, the bit line is a first bit line, the memory cell further includes a second transmission gate device, the first metal layer further includes a second bit line connected to the second transmission gate device, and the second bit line is adjacent to the second voltage line.

34. The method of forming an integrated circuit structure as described in claim 33, wherein the word line landing pad is a first word line landing pad, the first metal layer further includes a second word line landing pad connected to the second transmission gate device, and the second word line landing pad is adjacent to the second bit line.

35. A method for forming an integrated circuit structure, comprising: A memory cell is formed having a pull-up device, a pull-down device, a first transmission gate device, and a second transmission gate device, wherein the pull-up device and the pull-down device share a first gate structure, the first transmission gate device has a second gate structure, and the second transmission gate device has a third gate structure; and Forming an interconnect structure, wherein the operations for forming the interconnect structure include: A first metal layer is formed, the first metal layer including a bit line, a first voltage line configured to receive a first voltage, a word line landing pad connected to the second gate structure, a complementary bit line connected to the first transmission gate device, and a second voltage line configured to receive a second voltage, the second voltage being different from the first voltage. A second metal layer is formed above the first metal layer, wherein the second metal layer includes a character line connected to the character line landing pad; Wherein, the first voltage line is adjacent to the bit line, the word line landing pad is adjacent to the first voltage line, the complementary bit line is adjacent to the word line landing pad, and the second voltage line is adjacent to the complementary bit line; and The aforementioned character line landing pad extends above the aforementioned first gate structure and the aforementioned second gate structure.

36. The method for forming an integrated circuit structure as described in claim 35, wherein: The second gate structure described above has a first end adjacent to the first voltage line and a second opposite end adjacent to the third gate structure, and The operation of forming the above interconnect structure also includes forming a through hole to connect the second gate structure to the word line landing pad, wherein the through hole is disposed at the first end of the second gate structure.

37. The method of forming an integrated circuit structure as claimed in claim 35, wherein the bit line is a first bit line, the first metal layer further includes a second bit line connected to the second transmission gate device, and the second bit line is adjacent to the second voltage line.

38. The method of forming an integrated circuit structure as described in claim 37, wherein the word line landing pad is a first word line landing pad, the first metal layer further includes a second word line landing pad connected to the third gate structure, and the second word line landing pad is adjacent to the second bit line.

39. The method of forming an integrated circuit structure as claimed in claim 38, wherein the word line is a first word line, and the operation of forming the interconnect structure further includes forming a third metal layer above the second metal layer, wherein the third metal layer includes a second word line different from the first word line, wherein the second word line is connected to the second word line landing pad.

40. The method for forming an integrated circuit structure as claimed in claim 35, wherein the first voltage line has a first width, and the second voltage line has a second width greater than the first width.

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