Metal grid structure integrated with deep trench isolation structure

Abstract

The present disclosure relates to a metal grid structure integrated with a deep trench isolation structure. A high-k passivation layer, an anti-reflective coating, and a buffer layer are disposed above a semiconductor substrate, the semiconductor substrate including a photodiode formed therein. A trench is etched into the semiconductor substrate through the buffer layer, the anti-reflective coating, and the high-k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high-k passivation layer is lined inside the trench in the semiconductor substrate. An adhesive and a barrier layer are deposited above the high-k passivation layer lining the inside of the trench. A deep trench isolation DTI structure is formed with a conductive material deposited into the trench over the adhesive and barrier layer to fill the trench. A grid structure is formed above the DTI structure and above the plane of the buffer layer. The grid structure is formed by the conductive material.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to image sensors having pixels isolated by metal grid structures integrated with deep trench isolation structures. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and the like (e.g., resolution, power consumption, dynamic range, etc.) of image sensors in as many ways as possible, both through device architecture design as well as image acquisition processing.

[0003] A typical complementary metal oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges upon absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on the column bit lines that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, is read out from the column bit lines as an analog signal, and is converted into a digital value to generate a digital image (i.e., image data) representing the external scene. Summary of the invention

[0004] One embodiment of the present disclosure provides a pixel array, comprising: a photodiode array formed in a semiconductor substrate; a first high-k passivation layer disposed over the semiconductor substrate; an anti-reflective coating disposed over the first high-k passivation layer; a buffer layer disposed over the anti-reflective coating; a plurality of trenches etched into the semiconductor substrate through the buffer layer, through the anti-reflective coating, and through the first high-k passivation layer, wherein the plurality of trenches are etched in the semiconductor substrate in a grid-like pattern surrounding each of the photodiodes of the photodiode array in the semiconductor substrate; a second high-k passivation layer lining the interior of the plurality of trenches in the semiconductor substrate; an adhesive and barrier layer deposited over the second high-k passivation layer lining the interior of the plurality of trenches; a deep trench isolation (DTI) structure formed of a conductive material deposited into the plurality of trenches over the adhesive and barrier layer to fill the plurality of trenches; and a grid structure formed over the DTI structure and above a plane of the buffer layer, wherein the grid structure is formed of the conductive material.

[0005] Another embodiment of the present disclosure provides a method for making a pixel array, which includes: forming a photodiode array in a semiconductor substrate; depositing a first high-k passivation layer over the semiconductor substrate; depositing an anti-reflective coating over the first high-k passivation layer; depositing a buffer layer over the anti-reflective coating; etching a plurality of trenches into the semiconductor substrate through the buffer layer, through the anti-reflective coating and through the first high-k passivation layer; lining the interior of the plurality of trenches in the semiconductor substrate with a second high-k passivation layer; depositing an adhesive and a barrier layer over the second high-k passivation layer lining the interior of the plurality of trenches; filling the plurality of trenches with a conductive material deposited into the plurality of trenches over the adhesive and barrier layer to form a deep trench isolation (DTI) structure including the conductive material; and forming a grid structure over the DTI structure and on a plane of the buffer layer, wherein the grid structure is formed by the conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 One example of an imaging system including a pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention is illustrated.

[0008] Figure 2 Illustrated is a plan view of an example pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention.

[0009] Figures 3A to 3N Illustrated are cross-sectional views of various examples of a pixel array having a metal grid structure integrated with a deep trench isolation structure during various stages of fabrication in accordance with the teachings of the present invention.

[0010] Figure 4A Illustrated is a cross-sectional view of the center of an example pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention.

[0011] Figure 4B Illustrated is a cross-sectional view of the left side of an example pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention.

[0012] Figure 4C Illustrated is a cross-sectional view of the right side of an example pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention.

[0013] Figure 5is a flow chart illustrating an example process of fabricating a pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention.

[0014] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to help improve understanding of the various embodiments of the present invention, the sizes of some of the elements in the various figures may be exaggerated relative to other elements. In addition, common and well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate less obstructed viewing of these various embodiments of the present invention. DETAILED DESCRIPTION

[0015] Various examples are described herein for imaging systems, including pixel arrays having metal grid structures integrated with deep trench isolation structures and various examples of methods for making the pixel arrays. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0016] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present invention. Thus, the appearance of the phrase "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0017] In addition, spatially relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another (or some) element or feature, as illustrated in the various figures. It will be understood that in addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device when in use or operation. For example, if the device in the various figures is rotated or flipped, the element described as being "below" or "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the exemplary terms "below" and "below" can cover both the above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or there can also be one or more intervening elements.

[0018] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context in which they are used clearly implies otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, the two have the same meaning.

[0019] As will be discussed, various examples of imaging systems are described, including various examples of pixel arrays having metal grid structures integrated with deep trench isolation structures and methods for making the pixel arrays. In various examples, the metal grid structure is integrated with a deep trench isolation structure formed in a semiconductor substrate, wherein a high-k passivation layer, an anti-reflective coating, and a buffer layer are disposed above the semiconductor substrate. As will be shown in various examples, the high-k passivation layer, the anti-reflective coating, and the buffer layer are deposited above the semiconductor substrate before etching the trenches in the semiconductor substrate in which the deep trench isolation structure is formed. Therefore, the critical dimensions of the trenches etched into the semiconductor material are larger than the trenches etched before the high-k passivation layer, the anti-reflective coating, and the buffer layer are deposited above the semiconductor substrate. The larger critical dimensions of the trenches help avoid potential blocking problems that may occur at the top portion of the trenches due to the deposition of anti-reflective material. In various examples, the conductive material can also be deposited using multiple deposition steps in accordance with the teachings of the present invention, which enables improved etching control.

[0020] For illustration purposes, Figure 1One example of an imaging system 100 including a pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention is shown. As will be discussed, in various examples, a high-k passivation layer, an anti-reflective coating, and a buffer layer are deposited over a semiconductor substrate before etching trenches in the semiconductor substrate in which the deep trench isolation structure is formed in accordance with the teachings of the present invention. As shown in the illustrated example, the imaging system 100 includes a pixel array 102, a control circuit 110, a readout circuit 106, and function logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array including a plurality of pixels 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc.

[0021] As will be discussed in more detail below, in various examples, in accordance with the teachings of the present invention, pixels 104 are separated or isolated from each other by a grid structure 114 formed over a deep trench isolation (DTI) structure that provides isolation between adjacent pixels 104 within a semiconductor substrate in the pixel array 102.

[0022] In various examples, each pixel 104 may include one or more photodiodes configured to photogenerate image charge in response to incident light. The image charge generated in each photodiode in pixel 104 is transferred to a corresponding floating diffusion in each pixel 104, converted into an image signal, and then read out from each pixel 104 by readout circuitry 106 via column bit lines 112. In various examples, the image charge from each row of pixels 104 may be read out in parallel by readout circuitry 106 via column bit lines 112.

[0023] In various examples, the analog image charge signal may be converted to a digital value by an analog-to-digital converter (ADC) included in readout circuitry 106. In various examples, readout circuitry 106 may also include amplification circuitry or other. The digital representation of the image charge value may then be transmitted to function logic 108.

[0024] Function logic 108 may simply store the image charge values ​​or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or other). In one example, readout circuitry 106 may read out the image charge values ​​one row at a time along column bit lines 112 (illustrated) or may read out the image charge values ​​using various other techniques (not illustrated), such as serial readout or full parallel readout of all pixels 104 at the same time.

[0025] In one example, the control circuit 110 is coupled to the pixel array 102 to control the operating characteristics of the pixel array 102. For example, in one example, the control circuit 110 generates a transfer gate signal, a reset signal, a row selection signal, etc. to control the acquisition of image data and the readout of image data from all pixels 104 of the pixel array 102. In addition, the control circuit 110 may generate a shutter signal to control image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels 104 within the pixel array 102 to simultaneously capture their corresponding image charge values ​​during a single acquisition window. In another example, the shutter signal is a rolling shutter signal so that each row, each column, or each group of pixels is sequentially enabled during continuous acquisition windows. The shutter signal can also establish an exposure time, which is the length of time the shutter remains open. In one embodiment, the exposure time is set to be the same for each of the frames.

[0026] Figure 2 Illustrated is a plan view of an example pixel array 202 having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention. It should be appreciated that Figure 2 The pixel array 202 may be Figure 1 1. An example of a pixel array 102 is shown in FIG. 1, and similarly named and numbered elements described above are similarly coupled and function below.

[0027] As shown in the depicted example, pixel array 202 is a two-dimensional (2D) array including a plurality of pixels 204 arranged in rows and columns to acquire image data of a person, place, object, etc., which may then be used to reproduce an image of the person, place, object, etc. In various examples, pixels 204 are separated or isolated from one another by a grid structure 214 formed over a deep trench isolation (DTI) structure in pixel array 202 in accordance with the teachings of the present invention.

[0028] Figure 2The example shown in also illustrates that the pixel array 202 includes a color filter array disposed over each of the pixels 204. In various embodiments, the color filter array includes color filters arranged according to a particular color pattern (e.g., a Bayer pattern), which in the depicted example is a mosaic of red 216R, green 216G, and blue 216B color filters (e.g., R, G, B) to respectively transmit respective wavelengths of light. The depicted example also illustrates that a plurality of microlenses 218 are disposed over each pixel 204 of the pixel array 202 to direct incident light onto each respective pixel 204. Thus, in the depicted example, each pixel 204 is optically coupled to receive incident light through a respective one of the plurality of microlenses and a respective one of the plurality of color filters (e.g., red 216R, green 216G, blue 216B) of the color filter array.

[0029] Figures 3A to 3N Illustrated are cross-sectional views of various examples of a pixel array 302 having a metal grid structure integrated with a deep trench isolation structure during various stages of fabrication in accordance with the teachings of the present invention. Figures 3A to 3N Various examples of the pixel array 302 illustrated in FIG. Figure 2 An example of a pixel array 202 along the dashed line AA' shown in FIG. Figure 1 0 and 1. The example of pixel array 102 shown in FIG. 1 is shown in FIG. 1 and similarly named and numbered elements described above are similarly coupled and function below.

[0030] For example, Figure 3A The example illustrated in FIG. 1 shows a cross-section of a portion of pixel array 302, which may correspond to Figure 2 20 along the dashed line AA'. As shown in the depicted example, the pixel array 302 includes a semiconductor substrate 320 in which an array of photodiodes 322 are formed. Figure 3A , each photodiode 322 corresponds to a respective one of the pixels of pixel array 302. In one example, semiconductor substrate 320 may include silicon.

[0031] Continuing with the depicted example, a high-k passivation layer 324 is disposed over the semiconductor substrate 320. In one example, the high-k passivation layer 324 is disposed over the backside surface 368 (or illustrated surface) of the semiconductor substrate 320. In various examples, the high-k passivation layer 324 may include hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or a combination of both. In one embodiment, the high-k passivation layer 324 includes a high dielectric material having a dielectric constant greater than 3.9. In various examples, the high-k passivation layer 324 is deposited to a thickness of approximately 3 nanometers to 9 nanometers.

[0032] As shown in the example, an anti-reflective coating 326 is disposed over the high-k passivation layer 324. In various examples, the anti-reflective coating 326 may include tantalum oxide (e.g., Ta2O5). In various examples, the anti-reflective coating 326 is deposited to a thickness of approximately 50 to 80 nanometers.

[0033] Continuing with the example, a buffer layer 328 is disposed over the anti-reflective coating 326. In various examples, the buffer layer 328 is an oxide layer, including, for example, a silicon oxide material (e.g., SiO2). In various examples, the buffer layer 328 is deposited to a thickness of approximately 100 nanometers to 300 nanometers. In various examples, a chemical mechanical polishing process is applied to the buffer layer 328 to planarize the buffer layer 328, which forms a plane or planar surface 370 on the buffer layer 328, as shown.

[0034] Figure 3B 3 shows a plurality of trenches 344 being etched into the semiconductor substrate 320 through the buffer layer 328, through the anti-reflective coating 326, through the high-k passivation layer 324, and through the backside surface 368 of the semiconductor substrate 320. In various examples, it is understood that the plurality of trenches 334 are etched in the semiconductor substrate 320 in a grid-like pattern surrounding each of the photodiodes 322 of the photodiode array in the semiconductor substrate 320. In one example, the plurality of trenches 334 have a depth in the semiconductor substrate 320 of approximately 1.5 microns to 2.5 microns from the backside surface 368 of the semiconductor substrate 320. In one embodiment, the thickness of the semiconductor substrate 320 may range from 3 microns to 6 microns. It is understood that by etching the plurality of trenches 344 after depositing the high-k passivation layer 324, the anti-reflective coating 326, and the buffer layer 328, blocking issues at the top portions of the plurality of trenches 344 due to later deposition of anti-reflective material may be avoided in accordance with the teachings of the present invention.

[0035] Figure 3CThe interior of a plurality of trenches 344 is shown lined with an additional high-k passivation layer 325 in the semiconductor substrate 320. Similar to the high-k passivation layer 324 disposed over the backside surface 368 of the semiconductor substrate 320, the additional high-k passivation layer 325 lining the interior of the trenches 344 may include hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or a combination of both. In various examples, the additional high-k passivation layer 325 lining the interior of the trenches 344 is deposited to a thickness of approximately 3 nanometers to 9 nanometers.

[0036] Continuing with the example depicted, Figure 3D Adhesive and barrier layers 330 are shown deposited over additional high-k passivation layer 325 lining the interior of the plurality of trenches 344. In one example, adhesive and barrier layers 330 include titanium (eg, Ti) for adhesive material and titanium nitride (eg, TiN) for barrier material.

[0037] Figure 3E A plurality of deep trench isolation (DTI) structures 372 are shown formed with a conductive material 332 blanket deposited on a backside surface 368 of the semiconductor substrate 320 over a plane 370 of the buffer layer 328 and blanket deposited over the adhesive and barrier layer 330 into the plurality of trenches 334 to fill the plurality of trenches 334. In one example, the conductive material 332 used to fill the plurality of trenches 334 as shown includes tungsten (e.g., W).

[0038] Figures 3F to 3H The diagram illustrates that during the fabrication of pixel array 302, Figures 3A to 3E An example of a processing step for forming a grid structure 314 formed above the DTI structure 372 and above the plane 370 of the buffer layer 328 occurs after the processing steps illustrated in FIG. Figure 3F As shown in the example depicted in , the conductive material 332 outside of the plurality of trenches 334 in which the DTI structures 372 are formed is patterned and etched to form the grid structure 314 .

[0039] In one example, it is noted that the patterning and etching performed to form the grid structure 314 may include patterning a photoresist layer over the conductive material 332, and then etching the conductive material 332 and the adhesive and barrier layers 330, followed by removing the photoresist to form the grid structure 314. In one example, the additional high-k passivation layer 325 disposed above the plane 370 of the buffer layer 328 may also be removed during the etching of the conductive material 332, which may result in the loss of some of the oxide material of the buffer layer 328 and some of the conductive material 332 in the DTI structure 372 (e.g., <20 nanometers).

[0040] In one instance, it should be noted that Figure 3F 302 illustrates a central region of the pixel array 302 when the grid structure 314 is centered between adjacent photodiodes 322 in the semiconductor substrate 320 or aligned with an underlying DTI structure 372. As such, a chief ray angle (e.g., CRA) of incident light in the central region of the pixel array 302 is substantially perpendicular to a plane 370 of the buffer layer 328 in the central region of the pixel array 302.

[0041] In comparison, Figure 3G The portion of the example pixel array 302 shown in FIG. 3 illustrates that when the grid structure 314 is toward the center of the pixel array 302 (e.g., at Figure 3G , toward the right) when shifted 336 toward the left-hand edge of pixel array 302, as shown. Figure 3G The partial illustration of the example pixel array 302 shown in FIG. 1 illustrates the region toward the left-hand edge of the pixel array 302, so the chief ray angle of the incident light originates from Figure 3G 302 and toward the right. As such, the shift 336 toward the center of pixel array 302 accommodates the chief ray angle of incident light in accordance with the teachings of the present invention. In the depicted example, it should be noted that with the shift 336 toward the center of pixel array 302, portions of grid structure 314 are also disposed above portions of buffer layer 328 toward the center of pixel array 302, as shown.

[0042] Similarly, Figure 3H The portion of the example pixel array 302 shown in FIG. 3 illustrates that when the grid structure 314 is toward the center of the pixel array 302 (e.g., at Figure 3H , toward the left) when shifted 336 toward the right-hand edge of pixel array 302, as shown. Figure 3H The partial illustration of the example pixel array 302 shown in FIG. 1 illustrates the region toward the right-hand edge of the pixel array 302, so the chief ray angle of the incident light originates from Figure 3H 302 and toward the left. As such, the shift 336 toward the center of pixel array 302 accommodates the chief ray angle of incident light in accordance with the teachings of the present invention. In the depicted example, it should be noted that with the shift 336 toward the center of pixel array 302, portions of grid structure 314 are also disposed above portions of buffer layer 328 toward the center of pixel array 302, as shown.

[0043] In various examples, it should be appreciated that sulfur hexafluoride gas (e.g., SF6) may be used to etch the conductive material 332 and chloride gas may be used to etch the adhesive and barrier layer 330. Sulfur hexafluoride gas has a high etching rate for tungsten. However, one consideration when using sulfur hexafluoride gas to etch the conductive material 332 is that the use of sulfur hexafluoride gas may result in over-etching of tungsten filler in the DTI structure 372, which may lead to reliability issues, especially when the DTI structure 372 has a small trench critical dimension. Under-etching of the tungsten conductive material 332 may result in unwanted residues covering the backside surface 368 of the semiconductor substrate 320 covering portions of the exposed surface of the underlying photodiode 322, which may adversely affect the quantum efficiency (e.g., QE) of the corresponding photodiode 322.

[0044] Figures 3I to 3N The diagram illustrates that during the fabrication of pixel array 302, Figures 3A to 3E Another example of processing steps for forming a grid structure 314 formed above the DTI structure 372 and above the plane 370 of the buffer layer 328 occurs after the processing steps illustrated in FIG. Figures 3I to 3N It will be shown in the example illustrated in that the above-mentioned challenges faced in etching the conductive material 332 are addressed according to the teachings of the present invention by adding another adhesive and barrier layer 330 to act as an etch stop layer to provide improved etch control.

[0045] For example, briefly referring back to Figure 3E , a plurality of deep trench isolation (DTI) structures 372 are formed with a conductive material 332 blanket deposited over a backside surface 368 of a semiconductor substrate 320 and blanket deposited into a plurality of trenches 334 over an adhesive and barrier layer 330 to fill the plurality of trenches 334. In the example, the conductive material 332 shown for filling the plurality of trenches 334 includes tungsten (e.g., W).

[0046] Next, jump to Figures 3I to 3N In another example illustrated in FIG. 1 , the conductive material 332 over the backside surface 368 of the semiconductor substrate 320 is then blanket etched to remove the conductive material 332 outside the plurality of trenches 334, which removes the conductive material 332 outside and above the DTI structure 372, such as Fig. 3I As shown in .

[0047] Figure 3JAn additional adhesive and barrier layer 330 is then blanket deposited over the backside surface 368 of the semiconductor substrate 320, including the conductive material 332 of the DTI structure 372 in the plurality of trenches 334 and the buffer material 328, as shown. In the example, the adhesive and barrier layer 330 forms an etch stop layer over the planar surface 370 of the buffer layer 328 and the conductive material 332 of the DTI structure 372 in accordance with the teachings of the present invention.

[0048] Figure 3K Shown is a case where the additional adhesive and barrier layer 330 is blanket deposited over the planar surface 370 of the buffer layer 328 and the conductive material 332 of the DTI structure 372 (as shown), followed by an additional or second deposit of conductive material 333 being blanket deposited over the additional adhesive and barrier layer 330. In one example, as shown, the second deposit of conductive material 333 blanket deposited over the additional adhesive and barrier layer 330 includes tungsten (e.g., W).

[0049] Figure 3L With the second deposit of conductive material 333 shown blanket deposited over additional adhesive and barrier layer 330 , grid structure 314 may then be formed by patterning and etching the second deposit of conductive material 333 formed over additional adhesive and barrier layer 330 , as shown.

[0050] In one example, it is noted that patterning and etching performed to form grid structure 314 may include patterning a photoresist layer over conductive material 333, and then etching conductive material 333 with sulfur hexafluoride gas (e.g., SF6), and then etching adhesive and barrier layer 330 with a chloride gas to form grid structure 314, in accordance with the teachings of the present invention. It is appreciated that improved etching control is provided by etch stop layer properties, such as those provided by the etching stop layer properties. Figure 3J The additional adhesive and barrier layer 330 deposited as shown in FIG.

[0051] In one instance, it should be noted that Figure 3L 302 illustrates a central region of the pixel array 302 when the grid structure 314 is centered between adjacent photodiodes 322 in the semiconductor substrate 320 or aligned with an underlying DTI structure 372. As such, a chief ray angle (e.g., CRA) of incident light in the central region of the pixel array 302 is substantially perpendicular to a plane 370 of the buffer layer 328 in the central region of the pixel array 302.

[0052] In comparison, Figure 3MThe portion of the example pixel array 302 shown in FIG. 3 illustrates that when the grid structure 314 is toward the center of the pixel array 302 (e.g., at Figure 3M , toward the right) when shifted 336 toward the left-hand edge of pixel array 302, as shown. Figure 3M The partial illustration of the example pixel array 302 shown in FIG. 1 illustrates the region toward the left-hand edge of the pixel array 302, so the chief ray angle of the incident light originates from Figure 3M 302 and toward the right. As such, the shift 336 toward the center of pixel array 302 accommodates the chief ray angle of incident light in accordance with the teachings of the present invention. In the depicted example, it should be noted that with the shift 336 toward the center of pixel array 302, portions of grid structure 314 are also disposed above portions of buffer layer 328 toward the center of pixel array 302, as shown.

[0053] Similarly, Figure 3N The portion of the example pixel array 302 shown in FIG. 3 illustrates that when the grid structure 314 is toward the center of the pixel array 302 (e.g., at Figure 3N , toward the right) when shifted 336 toward the right hand edge of pixel array 302, as shown. Figure 3N The partial illustration of the example pixel array 302 shown in FIG. 1 illustrates the region toward the right-hand edge of the pixel array 302, so the chief ray angle of the incident light originates from Figure 3N 302 and toward the left. As such, the shift 336 toward the center of pixel array 302 accommodates the chief ray angle of incident light in accordance with the teachings of the present invention. In the depicted example, it should be noted that with the shift 336 toward the center of pixel array 302, portions of grid structure 314 are also disposed above portions of buffer layer 328 toward the center of pixel array 302, as shown.

[0054] Figure 4A Illustrated is a cross-sectional view of the center of an example pixel array 402 having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention. It should be appreciated that Figure 4A The example pixel array 402 shown in FIG. Figure 3L Another example of a pixel array 302 shown in FIG. 1 , and / or Figure 2 An example of the pixel array 202 along the dashed line AA' shown in FIG. 1 , and / or Figure 1 Another example of a pixel array 102 is shown in , and similarly named and numbered elements described above are similarly coupled and function below.

[0055] like Figure 4A, pixel array 402 includes a photodiode array 422 formed in a semiconductor substrate 420. A high-k passivation layer 424 is disposed over a backside surface 468 of the semiconductor substrate 420. An anti-reflective coating 426 is disposed over the high-k passivation layer 424, and a buffer layer 428 is disposed over the anti-reflective coating 426.

[0056] In the example, the DTI structure 472 is formed of a conductive material (or a first deposited conductive material) 432 that fills a plurality of trenches etched into the semiconductor substrate 420 through the buffer layer 428, through the anti-reflective coating 426, and through the high-k passivation layer 424. In the example, the plurality of trenches in which the DTI structure 472 is formed are etched in the semiconductor substrate 420 in a grid-like pattern surrounding each of the photodiodes 422 of the photodiode array in the semiconductor substrate 420. The DTI structure 472 provides electrical and optical isolation between the photodiodes 422.

[0057] An additional high-k passivation layer 425 is deposited to line the interior of the plurality of trenches in the semiconductor substrate 420, and an adhesive and barrier layer 430 is deposited over the additional high-k passivation layer 425 lining the interior of the plurality of trenches in which the DTI structure 472 is formed. As shown, the DTI structure 472 is formed by a conductive material 432 deposited into the plurality of trenches over the adhesive and barrier layer 430 to fill the plurality of trenches. A grid structure 414 is formed over the DTI structure 472 and above the plane 470 of the buffer layer 428. In the example, the grid structure 414 is formed by a second deposited conductive material 433, which may include the same material (e.g., W) used in the conductive material 432 forming the DTI structure 472.

[0058] As shown in the depicted example, pixel array 402 also includes a color filter array disposed above plane 470 of buffer layer 428. Figure 4A In the example shown in FIG. 1 , the color filter array is Figure 2 An example of a color filter array along the dashed line AA' is shown in FIG. Thus, Figure 4A4. The color filter array shown in FIG. 4 includes a red filter 416R and a green filter 416G. As shown in the depicted example, each color filter 416R, 416G of the color filter array is optically aligned with a corresponding one of the photodiodes 422 of the photodiode array in the semiconductor substrate 420. In the example, each color filter 416R, 416G of the color filter array is disposed in a corresponding opening defined by the grid structure 414. In the example, the opening defined by the grid structure 414 forms an aperture that is optically aligned with an exposure area of ​​the underlying photodiode 422. In the example, the pixel array 402 also includes a microlens array disposed above the color filter array, wherein each microlens 418 of the microlens array is optically aligned with a corresponding color filter 416R, 416G of the color filter array and a corresponding underlying photodiode 422 in the semiconductor substrate 420.

[0059] In the example depicted, it should be noted that Figure 4A 4 illustrates a central region of the pixel array 402 when the grid structure 414 is centered between adjacent photodiodes 422 in the semiconductor substrate 420 or aligned with an underlying DTI structure 472. As such, a chief ray angle (e.g., CRA) of incident light 438 in the central region of the pixel array 402 is substantially perpendicular to a plane 470 of the buffer layer 428 in the central region of the pixel array 402.

[0060] Figure 4B Illustrated is a cross-sectional view of the left side of an example pixel array 402 having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention. It should be appreciated that Figure 4B The example pixel array 402 shown in FIG. Figure 3M Another example of a pixel array 302 shown in FIG. 1 , and / or Figure 2 An example of the pixel array 202 along the dashed line AA' shown in FIG. 1 , and / or Figure 1 0048. Another example of a pixel array 102 is shown in 0048. and similarly named and numbered elements described above are similarly coupled and function below.

[0061] We should further understand that Figure 4B The example pixel array 402 shown in FIG. Figure 4A The example pixel array 402 shown in FIG. 4 shares many similarities. For example, Figure 4BThe example depicted in shows that the pixel array 402 includes a photodiode array 422 formed in a semiconductor substrate 420. A high-k passivation layer 424 is disposed over a backside surface 468 of the semiconductor substrate 420. An anti-reflective coating 426 is disposed over the high-k passivation layer 424, and a buffer layer 428 is disposed over the anti-reflective coating 426.

[0062] In the example, the DTI structure 472 is formed of a conductive material 432 filling a plurality of trenches etched into the semiconductor substrate 420 through the buffer layer 428, through the anti-reflective coating 426, and through the high-k passivation layer 424. In the example, the plurality of trenches in which the DTI structure 472 is formed are etched in the semiconductor substrate 420 in a grid-like pattern surrounding each of the photodiodes 422 of the photodiode array in the semiconductor substrate 420.

[0063] An additional high-k passivation layer 425 is deposited to line the interior of the plurality of trenches in the semiconductor substrate 420, and an adhesive and barrier layer 430 is deposited over the additional high-k passivation layer 425, the additional high-k passivation layer forming a high-k liner lining the interior of the plurality of trenches in which the DTI structure 472 is formed. As shown, the DTI structure 472 is formed by a conductive material 432 deposited into the plurality of trenches over the adhesive and barrier layer 430 to fill the plurality of trenches. A grid structure 414 is formed over the DTI structure 472 and above the plane 470 of the buffer layer 428. In the example, the grid structure 414 is formed by a second deposited conductive material 433, which may include the same material (e.g., W) used in the conductive material 432 forming the DTI structure 472.

[0064] As shown in the depicted example, the pixel array 402 also includes a color filter array including color filters (e.g., red filter 416R, green filter 416G) disposed above the plane 470 of the buffer layer 428. As shown in the depicted example, each color filter 416R, 416G of the color filter array is optically aligned with a corresponding one of the photodiodes 422 of the photodiode array in the semiconductor substrate 420. In the example, each color filter 416R, 416G of the color filter array is disposed in a corresponding opening defined by the grid structure 414. In the example, the pixel array 402 also includes a microlens array disposed above the color filter array, wherein each microlens 418 of the microlens array is optically aligned with a corresponding color filter 416R, 416G of the color filter array and a corresponding underlying photodiode 422 in the semiconductor substrate 420.

[0065] In the example depicted, it should be noted that Figure 4BThe portion of the example pixel array 402 shown in FIG. 4 illustrates that when the grid structure 414 is toward the center of the pixel array 402 (e.g., at Figure 4B , toward the right) when shifted 436 toward the left-hand edge of pixel array 402, as shown. Figure 4B The portion of the example pixel array 402 shown in FIG. 4 illustrates a region toward the left-hand edge of the pixel array 402, so the chief ray angle 438 of the incident light originates from Figure 4B 402 and toward the right. As such, the shift 436 toward the center of pixel array 402 accommodates the chief ray angle of incident light 438 in accordance with the teachings of the present invention. In the depicted example, it should be noted that with the shift 436 toward the center of pixel array 402, portions of grid structure 414 are also disposed over portions of buffer layer 428 toward the center of pixel array 402, as shown.

[0066] Figure 4C The diagram illustrates a cross-sectional view of the right side of an example pixel array 402 having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention. It should be appreciated that Figure 4C The example pixel array 402 shown in FIG. Figure 3N Another example of a pixel array 302 shown in FIG. 1 , and / or Figure 2 An example of the pixel array 202 along the dashed line AA' shown in FIG. 1 , and / or Figure 1 0048. Another example of a pixel array 102 is shown in 0048. and similarly named and numbered elements described above are similarly coupled and function below.

[0067] We should further understand that Figure 4C The example pixel array 402 shown in FIG. Figures 4A to 4B The examples of pixel array 402 shown in FIG. 4 share many similarities. For example, Figure 4C The example depicted in shows that the pixel array 402 includes a photodiode array 422 formed in a semiconductor substrate 420. A high-k passivation layer 424 is disposed over a backside surface 468 of the semiconductor substrate 420. An anti-reflective coating 426 is disposed over the high-k passivation layer 424, and a buffer layer 428 is disposed over the anti-reflective coating 426.

[0068] In the example, the DTI structure 472 is formed of a conductive material 432 filling a plurality of trenches etched into the semiconductor substrate 420 through the buffer layer 428, through the anti-reflective coating 426, and through the high-k passivation layer 424. In the example, the plurality of trenches in which the DTI structure 472 is formed are etched in the semiconductor substrate 420 in a grid-like pattern surrounding each of the photodiodes 422 of the photodiode array in the semiconductor substrate 420.

[0069] An additional high-k passivation layer 425 is deposited to line the interior of the plurality of trenches in the semiconductor substrate 420, and an adhesive and barrier layer 430 is deposited over the additional high-k passivation layer 425 lining the interior of the plurality of trenches in which the DTI structure 472 is formed. As shown, the DTI structure 472 is formed by a conductive material 432 deposited into the plurality of trenches over the adhesive and barrier layer 430 to fill the plurality of trenches. A grid structure 414 is formed over the DTI structure 472 and above the plane 470 of the buffer layer 428. In the example, the grid structure 414 is formed by a second deposited conductive material 433, which may include the same material (e.g., W) used in the conductive material 432 forming the DTI structure 472.

[0070] As shown in the depicted example, the pixel array 402 also includes a color filter array including color filters (e.g., red filter 416R, green filter 416G) disposed above the plane 470 of the buffer layer 428. As shown in the depicted example, each color filter 416R, 416G of the color filter array is optically aligned with a corresponding one of the photodiodes 422 of the photodiode array in the semiconductor substrate 420. In the example, each color filter 416R, 416G of the color filter array is disposed in a corresponding opening defined by the grid structure 414. In the example, the pixel array 402 also includes a microlens array disposed above the color filter array, wherein each microlens 418 of the microlens array is optically aligned with a corresponding color filter 416R, 416G of the color filter array and a corresponding underlying photodiode 422 in the semiconductor substrate 420.

[0071] In the example depicted, it should be noted that Figure 4C The portion of the example pixel array 402 shown in FIG. 4 illustrates that when the grid structure 414 is toward the center of the pixel array 402 (e.g., at Figure 4C , toward the left) is shifted 436 toward the right-hand edge of pixel array 402, as shown. Figure 4C The partial illustration of the example pixel array 402 shown in FIG. 4 illustrates the region toward the right-hand edge of the pixel array 402, so the chief ray angle 438 of the incident light originates from Figure 4C 402 and toward the left. As such, the shift 436 toward the center of pixel array 402 accommodates the chief ray angle of incident light 438 in accordance with the teachings of the present invention. In the depicted example, it should be noted that with the shift 436 toward the center of pixel array 402, portions of grid structure 414 are also disposed above portions of buffer layer 428 toward the center of pixel array 402, as shown.

[0072] Figure 5 5 is a flow chart illustrating an example process 540 for fabricating a pixel array having a metal grid structure integrated with a deep trench isolation structure in accordance with the teachings of the present invention. It should be appreciated that the example pixel array fabricated using process 540 may be Figures 4A to 4C The example of the pixel array 402 shown in FIG. 4 , and / or Figures 3A to 3N The example of the pixel array 302 shown in FIG. 1 , and / or Figure 2 The example of the pixel array 202 shown in FIG. 1 , and / or Figure 1 1 and similarly named and numbered elements described above are similarly coupled and function similarly below.

[0073] like Figure 5 As shown in process 540 of , processing begins at process block 542 where a photodiode array is formed in a semiconductor substrate. In one example, the semiconductor substrate provided in process block 542 may be a semi-fabricated substrate after front-end processing (e.g., forming pixel circuitry including photodiodes, floating diffusions, transistors, and metal interconnect structures, etc.).

[0074] Process block 544 shows that a first high-k passivation layer is then deposited on the surface of the semiconductor substrate. In one example, the first high-k passivation layer can be, for example, hafnium oxide, aluminum oxide, or a combination of both. In one example, the first high-k passivation layer is deposited on the backside surface of the semiconductor substrate to a thickness of, for example, 3 nanometers to 9 nanometers.

[0075] Process block 546 shows that an anti-reflective coating is then deposited on the first high-k passivation layer. In one example, the anti-reflective coating may include tantalum oxide. In one example, the anti-reflective coating is deposited to a thickness of, for example, 50 nanometers to 80 nanometers.

[0076] Process block 548 shows that a buffer layer is then deposited on the anti-reflective coating. In one example, the buffer layer may include a silicon oxide material. In one example, the buffer layer is deposited on the anti-reflective coating to a thickness of, for example, 100 nanometers to 300 nanometers.

[0077] Process block 550 shows that the buffer layer is then planarized. In one example, planarization of the buffer layer is performed using a chemical mechanical polishing (CMP) process.

[0078] Process block 552 shows that deep trenches are then patterned and etched into the semiconductor substrate. In one example, patterning and etching the trenches into the semiconductor substrate can be performed by depositing a photoresist on the buffer layer. The photoresist can be patterned by a photolithography process. In various examples, etching deep trenches into the semiconductor substrate to a depth is then performed through the stack of the first high-k passivation layer, the anti-reflective coating, and the buffer layer. In various examples, the buffer layer provides protection for the underlying layers during the etching process.

[0079] Process block 554 shows that a second high-k passivation layer is then deposited into the etched deep trench, forming a high-k liner layer lining the inner surface of the deep trench and within the buffer layer.

[0080] Process block 556 shows depositing an adhesive and barrier layer (first adhesive and barrier layer) on the high-k liner layer deposited into the deep trench.

[0081] Process block 558 shows depositing a conductive material into the deep trench to form a conductive material structure filling the trench. In one example, the conductive material structure filling the trench forms a deep trench isolation structure. In one example, the conductive material includes tungsten.

[0082] In one example, after block 558, processing may jump to process block 566, as shown in FIG. Figure 5 In this example, the processing that occurs in process block 566 corresponds to the processing described above in Figures 3F to 3H A process is shown in which a conductive material is patterned and etched to form a grid structure, the grid structure being formed of the conductive material.

[0083] In another example, after block 558, processing may proceed to process blocks 560, 562, and 564, as shown in FIG. Figure 5 In this example, the processing that occurs in process blocks 560, 562, and 564 corresponds to Figures 3I to 3K The processing shown in .

[0084] For example, process block 560 shows blanket etching the conductive material to remove excess conductive material outside the trench. In one example, high-k liner material and adhesive and barrier layers (first adhesive and barrier layers) outside the trench are also removed during process block 560.

[0085] Process block 562 shows that another adhesive and barrier layer (a second adhesive and barrier layer) is then blanket deposited as an etch stop layer.

[0086] Process block 564 shows that a conductive material is then deposited a second time over the second deposited adhesive and barrier layer that was blanket deposited as an etch stop layer.

[0087] In this example, after process block 564, processing then proceeds to process block 566, which in this example corresponds to Figures 3L to 3N , wherein the second deposited conductive material is patterned and etched to form a grid structure, the grid structure being formed of the conductive material.

[0088] Process block 568 shows that a color filter array and a microlens array are then formed over the buffer layer and the grid structure. In one example, process block 568 includes depositing the color filter array over the buffer layer such that each color filter of the color filter array is optically aligned with a corresponding one of the photodiodes of the photodiode array in the semiconductor substrate. In one example, each color filter of the color filter array is disposed in a corresponding opening defined by the grid structure. In the example, process block 568 also includes disposing a microlens array over the color filter array and the grid structure such that each microlens of the microlens array is optically aligned with a corresponding color filter of the color filter array.

[0089] The above description of the illustrated examples of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the present invention are described herein for illustrative purposes, as those skilled in the art will recognize, various modifications may be made within the scope of the present invention.

[0090] These modifications may be made to the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific examples disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with established claim interpretation principles.

Claims

1. A pixel array, comprising: a photodiode array formed in a semiconductor substrate; a first high-k passivation layer disposed above the semiconductor substrate; an anti-reflective coating disposed over the first high-k passivation layer; a buffer layer disposed above the anti-reflective coating; a plurality of trenches etched into the semiconductor substrate through the buffer layer, through the antireflective coating, and through the first high-k passivation layer, wherein the plurality of trenches are etched in the semiconductor substrate in a grid-like pattern surrounding each of the photodiodes of the photodiode array in the semiconductor substrate; a second high-k passivation layer lining the interior of the plurality of trenches in the semiconductor substrate; an adhesive and barrier layer deposited over the second high-k passivation layer lining the interior of the plurality of trenches; a deep trench isolation (DTI) structure formed by a conductive material deposited over the adhesive and barrier layer into the plurality of trenches to fill the plurality of trenches; and A grid structure is formed above the DTI structure and above the plane of the buffer layer, wherein the grid structure is formed of the conductive material.

2. The pixel array of claim 1 , further comprising a color filter array disposed above the buffer layer, wherein each color filter of the color filter array is optically aligned with a corresponding one of the photodiodes of the photodiode array in the semiconductor substrate, wherein each color filter of the color filter array is disposed in a corresponding opening defined by the grid structure.

3. The pixel array of claim 2, further comprising a microlens array disposed above the color filter array, wherein each microlens of the microlens array is optically aligned with a corresponding color filter of the color filter array. 4 . The pixel array of claim 1 , wherein the grid structure at an edge of the pixel array is shifted toward a center of the pixel array. 5 . The pixel array of claim 4 , wherein a portion of the grid structure at the edge of the pixel array that is shifted toward a center of the pixel array is further disposed over a portion of the buffer layer. 6 . The pixel array of claim 1 , further comprising the adhesive and barrier layer deposited between the grid structure and the DTI structure. The pixel array of claim 1 , wherein the semiconductor substrate comprises silicon. The pixel array of claim 1 , wherein the conductive material comprises tungsten. 9 . The pixel array of claim 1 , wherein the first high-k passivation layer and the second high-k passivation layer include one or more of hafnium oxide and aluminum oxide. 10 . The pixel array of claim 1 , wherein each of the first high-k passivation layer and the second high-k passivation layer has a thickness of 3 to 9 nanometers.

11. The pixel array of claim 1, wherein the antireflective coating comprises tantalum oxide. 12 . The pixel array of claim 1 , wherein the anti-reflective coating has a thickness of 50 nanometers to 80 nanometers.

13. The pixel array of claim 1, wherein the buffer layer comprises silicon oxide. 14 . The pixel array according to claim 1 , wherein the buffer layer has a thickness of 100 nanometers to 300 nanometers.

15. The pixel array of claim 1, wherein the adhesive and barrier layers comprise titanium and titanium nitride. 16 . The pixel array of claim 1 , wherein the plurality of trenches have a depth in the semiconductor substrate of 1.5 microns to 2.5 microns from a backside surface of the semiconductor substrate.

17. A method for making a pixel array, comprising: forming a photodiode array in a semiconductor substrate; depositing a first high-k passivation layer over the semiconductor substrate; depositing an antireflective coating over the first high-k passivation layer; depositing a buffer layer over the antireflective coating; etching a plurality of trenches into the semiconductor substrate through the buffer layer, through the antireflective coating, and through the first high-k passivation layer; lining the interior of the plurality of trenches in the semiconductor substrate with a second high-k passivation layer; depositing an adhesive and a barrier layer over the second high-k passivation layer lining the interior of the plurality of trenches; filling the plurality of trenches with a conductive material deposited into the plurality of trenches over the adhesive and barrier layer to form a deep trench isolation (DTI) structure including the conductive material; and A grid structure is formed above the DTI structure and on a plane of the buffer layer, wherein the grid structure is formed of the conductive material. 18 . The method of claim 17 , further comprising planarizing the buffer layer after depositing the buffer layer and before etching the plurality of trenches into the semiconductor substrate.

19. The method of claim 17, wherein etching the plurality of trenches into the semiconductor substrate comprises: The plurality of trenches are etched in the semiconductor substrate in a grid-like pattern surrounding each of the photodiodes of the photodiode array in the semiconductor substrate.

20. The method of claim 17, wherein forming the grid structure above the DTI structure and above the plane of the buffer layer comprises: The conductive material outside the plurality of trenches is patterned and etched to form the grid structure.

21. The method of claim 17, further comprising: After filling the plurality of trenches with the conductive material deposited into the plurality of trenches over the adhesive and barrier layer, blanket etching the first deposit of conductive material outside the plurality of trenches to remove the first deposit of conductive material outside the plurality of trenches; depositing a second adhesive and barrier layer over the conductive material and the buffer layer deposited into the plurality of trenches to form an etch stop layer; and depositing a second deposit of the conductive material over the second adhesive and barrier layer, The forming of the grid structure above the DTI structure and above the plane of the buffer layer comprises: patterning and etching the second deposit of the conductive material deposited above the second adhesive and barrier layer to form the grid structure above the DTI structure and above the plane of the buffer layer.

22. The method of claim 17, further comprising depositing a color filter array over the buffer layer, wherein each color filter of the color filter array is optically aligned with a corresponding one of the photodiodes of the photodiode array in the semiconductor substrate, wherein each color filter of the color filter array is disposed in a corresponding opening defined by the grid structure.

23. The method of claim 22, further comprising disposing a microlens array over the color filter array, wherein each microlens of the microlens array is optically aligned with a corresponding color filter of the color filter array.

24. The method of claim 17, further comprising shifting the grid structure at an edge of the pixel array toward a center of the pixel array. 25 . The method of claim 24 , wherein portions of the grid structure at the edge of the pixel array that are displaced toward a center of the pixel array are further disposed over portions of the buffer layer.

26. The method of claim 17, wherein the semiconductor substrate comprises silicon.

27. The method of claim 17, wherein the conductive material comprises tungsten.

28. The method of claim 17, wherein the first high-k passivation layer and the second high-k passivation layer comprise one or more of hafnium oxide and aluminum oxide.

29. The method of claim 17, wherein the antireflective coating comprises tantalum oxide.

30. The method of claim 17, wherein the buffer layer comprises silicon oxide.

31. The method of claim 17, wherein the adhesive and barrier layers comprise titanium and titanium nitride.

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