A reverse-voltage-free thyristor structure and its manufacturing method

Abstract

This invention relates to a reverse-voltage-free thyristor structure and its manufacturing method. The reverse-voltage-free thyristor structure includes an aluminum layer, an oxide layer, and Si3N4, N+ region, N- region, P+ region, P++ region, and P- region. The manufacturing method includes the following steps: (1) polishing; (2) oxidation; (3) boron diffusion; (4) oxide layer removal; (5) aluminum layer on the unpolished surface; (6) diffusion; (7) oxidation; (8) boron diffusion by photolithography; (9) N-region on the front side by photolithography; (10) phosphorus diffusion; (11) passivation layer deposition; (12) contact hole on the front side by photolithography; (13) aluminum layer on the front side of the silicon wafer; (14) metal front electrode by photolithography; (15) back side thinning; (16) aluminum layer on the back side and aluminum alloy treatment; and back electrode Cr, Ni, Sn, three-layer metal. The product of this invention has a short cycle time, slightly smaller VTM parameter, and superior performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a reverse-voltage-free thyristor structure and its manufacturing method. Background Technology

[0002] Among discrete semiconductor devices, the non-reverse voltage thyristor is a commonly used device, typically used in areas such as holiday lights and toys as a switch and phase control. It usually has a PNPN four-layer structure, and the die is generally smaller than 1.0mm*1.0mm, with a reverse blocking voltage. Existing technology uses boron expansion technology to form the back P region, that is, the first P layer of the PNPN structure. Its disadvantage is that it can easily lead to a slightly larger VTM. Simple aluminum expansion is also prone to the problem of surface doping concentration decreasing due to subsequent oxidation. Summary of the Invention

[0003] The purpose of this invention is to provide a reverse-pressure-free thyristor structure and its manufacturing method, thereby solving the above-mentioned problems.

[0004] To achieve the above objectives, the following technical solutions are provided:

[0005] A reverse-voltage-free thyristor structure and its manufacturing method are disclosed. The reverse-voltage-free thyristor structure includes an aluminum layer, an oxide layer, and Si3N4, as well as N+, N-, P+, P++, and P- regions. A P++ region is located below the P+ region, an N- region is located above the P+ region, a P- region is located in the middle of the top of the N- region, N+ regions are located at both ends of the top of the N- region, and an N+ region is located in the middle of the top of the P- region. The N+, N-, and P- regions are located on the left side, and the N+ region is located in the middle of the P- region. An oxide layer and Si3N4 are provided between the upper parts of the regions. An oxide layer and Si3N4 are provided between the upper right end of the N+ region located in the middle of the P- region and the upper part of the P- region. An oxide layer and Si3N4 are provided between the upper part of the N+ region located on the right side and the P- region. An aluminum layer is provided between the N+ regions located at both ends and the oxide layer and Si3N4. An aluminum layer is provided between the N+ region located in the middle of the P- region and the oxide layer and Si3N4. An aluminum layer is provided between the P- region and the oxide layer and Si3N4.

[0006] Preferably, the manufacturing method includes the following steps:

[0007] (1) Select N-type (111) silicon wafers with resistivity of 5~80Ω·cm for single-sided mechanical polishing, with a final thickness of 150~300μm;

[0008] (2) Oxidation temperature 1100℃, diffusion atmosphere is nitrogen, hydrogen and oxygen, time is 6~9h; remove oxide layer on unpolished surface;

[0009] (3) Boron diffusion is carried out on the unpolished surface. The diffusion atmosphere is nitrogen and oxygen, the surface concentration is 1E18-1E20 / cm3, the diffusion temperature is 1100-1200℃, and the time is 10 minutes to 120 minutes.

[0010] (4) Remove the oxide layer on the back side, which is now an unpolished surface;

[0011] (5) A 1-2 μm aluminum layer is formed by back-side electron beam evaporation or sputtering;

[0012] (6) Diffusion at 1250-1280℃ for 3-10 hours; the diffusion atmosphere is nitrogen and oxygen;

[0013] (7) The oxidation temperature is 1100℃, the diffusion atmosphere is nitrogen, hydrogen and oxygen, and the time is 6~9h;

[0014] (8) The base region window is formed on the front side of the photolithography. The front side is a polished surface. The boron expansion region is carried out. The diffusion atmosphere is nitrogen and oxygen. The diffusion temperature is 1200-1255℃ for 20-30 hours.

[0015] (9) Photolithography of the front N-region, i.e., the second N-type region of the PNPN structure;

[0016] (10) Phosphorus diffusion, generally with a surface concentration of 1E18-1E20 / cm3, a diffusion atmosphere of nitrogen and oxygen, a diffusion temperature of 900-1200℃, and a time of 10 to 120 minutes;

[0017] (11) LPCVD deposition of passivation layer Si3N4, with a thickness of 1000 to 2000 angstroms;

[0018] (12) Front-side photolithographic contact holes;

[0019] (13) A 3-6 μm aluminum layer is formed on the front side of the silicon wafer by electron beam evaporation or sputtering;

[0020] (14) Photolithography of the metal front electrode;

[0021] (15) Backside thinning by 10-15 μm;

[0022] (16) A 1-2 μm aluminum layer is formed on the back side by electron beam evaporation or sputtering; aluminum alloy treatment is performed.

[0023] (17) Make a back electrode of Cr, Ni and Sn, a three-layer metal.

[0024] The beneficial effects of this invention are as follows:

[0025] This invention pertains to reverse-pressure-free thyristors, typically smaller than 1.0mm*1.0mm. The P++ region on the back side of the thyristor is doped with concentrated boron to increase surface concentration, and a back-side diffusion source is formed using electron beam evaporation or sputtering. Diffusion takes 3-20 hours to form the back-side P+ region, with a back-side P layer width of 80-200μm. The concentration of boron and aluminum doping on the surface is 1E18-1E20 / cm3. Compared to boron diffusion technology, this shortens the production time by 4-10 days. The terminal technologies involved can be either a single-sided etched groove for a glass passivation layer (tabletop terminal) or a planar terminal with an aluminum plate. This invention results in a shorter product cycle, slightly lower VTM parameters, and superior performance. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the present invention;

[0027] The figures shown are labeled as follows: 1. Aluminum layer, 2. Oxide layer and Si3N4, 3. N+ region (phosphorus expansion region), 4. N- region, 5. P+ region (aluminum doped region), 6. P++ region (mixed doping region of high concentration boron and aluminum), 7. P- region (low concentration boron doped region). Detailed Implementation

[0028] The following is a detailed description of this design scheme with reference to the accompanying drawings.

[0029] A reverse-voltage-free thyristor structure and its manufacturing method are disclosed. The reverse-voltage-free thyristor structure includes an aluminum layer 1, an oxide layer and Si3N4 2, an N+ region 3 (phosphorus expansion region), an N- region 4, a P+ region 5 (aluminum doped region), a P++ region 6 (high-concentration boron and aluminum mixed doping region), and a P- region 7 (low-concentration boron doped region). The P++ region 6 is located below the P+ region 5, the N- region 4 is located above the P+ region 5, the P- region 7 is located in the middle of the top of the N- region 4, and N+ regions 3 are located at both ends of the top of the N- region 4. The N+ region 3 is located in the middle of the top of the P- region 7. An oxide layer and Si3N4 2 are located between the N+ region 3, N- region 4, P- region 7 on the left side and the upper part of the N+ region 3 in the middle of the P- region 7. An oxide layer and Si3N4 2 are located between the upper right end of the N+ region 3 in the middle of the P- region 7 and the upper part of the P- region 7. 2. An oxide layer and Si3N4 2 are provided between the upper part of the N+ region 3 and the P- region 7 on the right side. An aluminum layer 1 is provided between the N+ region 3 at both ends and the oxide layer and Si3N4 2. An aluminum layer 1 is provided between the N+ region 3 in the middle of the P- region 7 and the oxide layer and Si3N4 2. An aluminum layer 1 is provided between the P- region 7 and the oxide layer and Si3N4 2.

[0030] The manufacturing method includes the following steps:

[0031] (1) Select N-type (111) silicon wafers with resistivity of 5~80Ω·cm for single-sided mechanical polishing, with a final thickness of 150~300μm;

[0032] (2) Oxidation temperature 1100℃, diffusion atmosphere is nitrogen, hydrogen and oxygen, time is 6~9h; remove oxide layer on unpolished surface;

[0033] (3) Boron diffusion is carried out on the unpolished surface. The diffusion atmosphere is nitrogen and oxygen, the surface concentration is 1E18-1E20 / cm3, the diffusion temperature is 1100-1200℃, and the time is 10 minutes to 120 minutes.

[0034] (4) Remove the oxide layer from the unpolished (back) side;

[0035] (5) A 1-2 μm aluminum layer is formed on the unpolished surface (back side) by electron beam evaporation or sputtering.

[0036] (6) Diffusion at 1250-1280℃ for 3-10 hours; the diffusion atmosphere is nitrogen and oxygen;

[0037] (7) The oxidation temperature is 1100℃, the diffusion atmosphere is nitrogen, hydrogen and oxygen, and the time is 6~9h;

[0038] (8) The photolithographic polished surface (front side) forms the base region window, and the boron expansion region is carried out. The diffusion atmosphere is nitrogen and oxygen, and the diffusion temperature is 1200-1255℃ for 20-30 hours.

[0039] (9) Photolithography of the front N-region, i.e., region 3 of the PNPN structure shown in the diagram;

[0040] (10) Phosphorus diffusion, generally with a surface concentration of 1E18-1E20 / cm3, a diffusion atmosphere of nitrogen and oxygen, a diffusion temperature of 900-1200℃, and a time of 10 to 120 minutes;

[0041] (11) LPCVD deposition of passivation layer Si3N4, with a thickness of 1000 to 2000 angstroms;

[0042] (12) Front-side photolithographic contact holes;

[0043] (13) A 3-6 μm aluminum layer is formed on the front side of the silicon wafer by electron beam evaporation or sputtering.

[0044] (14) Photolithography of the metal front electrode;

[0045] (15) Backside thinning by 10-15 μm;

[0046] (16) A 1-2 μm aluminum layer is formed on the back side by electron beam evaporation or sputtering; aluminum alloy treatment is performed.

[0047] (17) Make a back electrode of Cr, Ni and Sn, a three-layer metal.

[0048] Example 1

[0049] like Figure 1 As shown, an N-type (111) silicon wafer with a resistivity of 5 Ω·cm was selected for single-sided mechanical polishing, resulting in a final thickness of 150 μm; the oxidation temperature was 1100℃, the diffusion atmosphere was nitrogen, hydrogen, and oxygen, and the time was 6 h; the oxide layer on the unpolished surface was removed; boron diffusion was performed on the unpolished surface, with a diffusion atmosphere of nitrogen and oxygen, a surface concentration of 1E18 / cm3, a diffusion temperature of 1100℃, and a time of 10 minutes; the oxide layer on the unpolished surface (back side) was removed; a 1-2 μm aluminum layer was formed on the unpolished surface (back side) by electron beam evaporation or sputtering; diffusion was performed at 1250℃ for 3-10 hours; the diffusion atmosphere was nitrogen and oxygen; the oxidation temperature was 1100℃, the diffusion atmosphere was nitrogen, hydrogen, and oxygen, and the time was 6 h; photolithography was then performed. The smooth (front) side forms the base region window, and boron diffusion is performed in the diffusion atmosphere of nitrogen and oxygen at 1200℃ for 20 hours (Figure 7). The front N-region is photolithographically etched, i.e., the PNPN structure shown in Figure 3. Phosphorus diffusion is performed with a surface concentration of 1E18 / cm3 in the diffusion atmosphere of nitrogen and oxygen at 900℃ for 10 minutes. A passivation layer of Si3N4 with a thickness of 1000 angstroms is deposited by LPCVD. Contact holes are photolithographically etched on the front side. A 3μm aluminum layer 1 is fabricated on the front side of the silicon wafer by electron beam evaporation or sputtering. Metal front electrode is photolithographically etched. The back side is thinned by 10μm. A 1μm aluminum layer 1 is fabricated on the back side by electron beam evaporation or sputtering. Aluminum alloy treatment is performed. The back electrode is fabricated with Cr, Ni, and Sn, a three-layer metal.

[0050] Example 2

[0051] like Figure 1As shown, an N-type (111) silicon wafer with a resistivity of 80 Ω·cm was selected for single-sided mechanical polishing, resulting in a final thickness of 300 μm; oxidation temperature was 1100℃, diffusion atmosphere was nitrogen, hydrogen, and oxygen, and time was 9 h; oxide layer on the unpolished side was removed; boron diffusion was performed on the unpolished side, diffusion atmosphere was nitrogen and oxygen, surface concentration was 1E20 / cm3, diffusion temperature was 1200℃, and time was 120 minutes; oxide layer on the unpolished side (back side) was removed; a 2 μm aluminum layer was formed on the unpolished side (back side) by electron beam evaporation or sputtering; diffusion was performed at 1280℃ for 10 hours; diffusion atmosphere was nitrogen and oxygen; oxidation temperature was 1100℃, diffusion atmosphere was nitrogen, hydrogen, and oxygen, and time was 9 h; photolithography was performed. The polished surface (front side) forms the base region window, and boron diffusion is performed in a nitrogen and oxygen atmosphere at 1255℃ for 30 hours. The front N region is photolithographically etched, i.e., region 3 of the PNPN structure shown in the diagram. Phosphorus diffusion is performed with a surface concentration of 1E20 / cm3 in a nitrogen and oxygen atmosphere at 1200℃ for 120 minutes. A passivation layer of Si3N4 with a thickness of 2000 angstroms is deposited by LPCVD. Contact holes are photolithographically etched on the front side. A 6μm aluminum layer 1 is fabricated on the front side of the silicon wafer by electron beam evaporation or sputtering. Metal front electrode is photolithographically etched. The back side is thinned by 15μm. A 2μm aluminum layer 1 is fabricated on the back side by electron beam evaporation or sputtering. Aluminum alloy treatment is performed. The back electrode is fabricated as a three-layer metal of Cr, Ni, and Sn.

Claims

1. A reverse-voltage-free thyristor structure, characterized in that, The reverse-voltage-free thyristor structure includes an aluminum layer, an oxide layer, and Si3N4, as well as N+, N-, P+, P++, and P- regions. The P++ region is a high-concentration boron and aluminum mixed-doped region. A P++ region is located at the bottom of the P+ region, an N- region is located at the top of the P+ region, a P- region is located in the middle of the top of the N- region, N+ regions are located at both ends of the top of the N- region, and an N+ region is located in the middle of the top of the P- region. The N+, N-, and P- regions are located on the left side, and the P- region is located in the middle of the P- region. An oxide layer and Si3N4 are provided between the upper part of the N+ region. An oxide layer and Si3N4 are provided between the upper right end of the N+ region located in the middle of the P- region and the upper part of the P- region. An oxide layer and Si3N4 are provided between the upper part of the N+ region located on the right side and the P- region. An aluminum layer is provided between the N+ regions located at both ends and the oxide layer and Si3N4. An aluminum layer is provided between the N+ region located in the middle of the P- region and the oxide layer and Si3N4. An aluminum layer is provided between the P- region and the oxide layer and Si3N4.

2. A method for manufacturing a reverse-voltage-free thyristor structure, wherein the reverse-voltage-free thyristor structure as described in claim 1 is characterized in that, The manufacturing method includes the following steps: (1) Select N-type (111) silicon wafers with resistivity of 5~80Ω·cm for single-sided mechanical polishing, with a final thickness of 150~300μm; (2) Oxidation temperature 1100℃, diffusion atmosphere is nitrogen, hydrogen and oxygen, time is 6~9h; remove oxide layer on unpolished surface; (3) Boron diffusion is performed on the unpolished surface in a nitrogen and oxygen atmosphere with a surface concentration of 1E18-1E20 / cm³. 3 The diffusion temperature is 1100-1200℃, and the time is 10 to 120 minutes. (4) Remove the oxide layer on the back side, which is now an unpolished surface; (5) A 1-2 μm aluminum layer is formed by back-side electron beam evaporation or sputtering; (6) Diffusion at 1250-1280℃ for 3-10 hours; the diffusion atmosphere is nitrogen and oxygen; (7) The oxidation temperature is 1100℃, the diffusion atmosphere is nitrogen, hydrogen and oxygen, and the time is 6~9h; (8) The base region window is formed on the front side of the photolithography. The front side is a polished surface. The boron expansion region is carried out. The diffusion atmosphere is nitrogen and oxygen. The diffusion temperature is 1200-1255℃ for 20-30 hours. (9) Photolithography of the front N-region, i.e., the second N-type region of the PNPN structure; (10) Phosphorus diffusion, generally with a surface concentration of 1E18-1E20 / cm³ 3 The diffusion atmosphere is nitrogen and oxygen, the diffusion temperature is 900-1200℃, and the time is 10 to 120 minutes; (11) LPCVD deposition of passivation layer Si3N4, with a thickness of 1000 to 2000 angstroms; (12) Front-side photolithographic contact holes; (13) A 3-6 μm aluminum layer is formed on the front side of the silicon wafer by electron beam evaporation or sputtering; (14) Photolithography of the metal front electrode; (15) Backside thinning by 10-15 μm; (16) A 1-2 μm aluminum layer is formed on the back side by electron beam evaporation or sputtering; aluminum alloy treatment is performed. (17) Make a back electrode of Cr, Ni and Sn, three layers of metal.

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