Power converter

Abstract

A power converter includes a switched-capacitor conversion circuit and an inductive buck circuit. The switched-capacitor conversion circuit receives an input voltage at an input terminal and performs a switching operation to convert the input voltage to an intermediate voltage. The inductive buck circuit is coupled to an output terminal of the switched-capacitor conversion circuit to receive the intermediate voltage and operates at a constant on-time to generate an output voltage at a conversion output terminal from the intermediate voltage. The inductive buck circuit includes an inductor. When a state of an inductor current charging the inductor corresponds to a preset condition, a switching action of the switching operation is initiated to switch the switched-capacitor conversion circuit from a first on-state to a second on-state. The present application can improve the efficiency of the power converter.

Description

Technical Field

[0001] This invention relates to a power converter, and more particularly to a hybrid power converter employing constant on-time control. Background Technology

[0002] For known buck converters, achieving high efficiency is difficult due to the significant voltage stress at the output relative to the input when the voltage conversion rate is high. Subsequently, a hybrid switched-capacitor converter was proposed, comprising a first-stage switched-capacitor converter and a second-stage buck converter. Compared to known buck converters, the switched-capacitor converter exhibits better efficiency at larger voltage drops. However, the hybrid switched-capacitor converter requires more control circuitry to switch the switches in both the switched-capacitor converter and the buck converter, leading to increased quiescent current. Since the converter's efficiency depends almost entirely on the quiescent current consumed when the output current is close to zero, this increased quiescent current results in poor efficiency under light or very light load conditions. Summary of the Invention

[0003] This invention provides a power converter. The power converter includes a switching capacitor conversion circuit and an inductive buck converter. The switching capacitor conversion circuit receives an input voltage at an input terminal and performs a switching operation to convert the input voltage into an intermediate voltage. The inductive buck converter is coupled to an output terminal of the switching capacitor conversion circuit to receive the intermediate voltage and operates for a constant on-time to generate an output voltage at a converted output terminal based on the intermediate voltage. The inductive buck converter includes an inductor. When the state of the inductor current charging the inductor corresponds to a preset condition, all switching actions are initiated, causing the switching capacitor conversion circuit to switch from a first on-state to a second on-state. This application can improve the efficiency of the power converter. Attached Figure Description

[0004] Figure 1 This refers to a power converter according to an embodiment of the present invention.

[0005] Figure 2 The circuit diagram shows a switching capacitor conversion circuit and an inductive step-down circuit according to an embodiment of the present invention.

[0006] Figure 3 This describes a switching control circuit for a power converter according to an embodiment of the present invention.

[0007] Figure 4A and Figure 4B This diagram illustrates the timing of the main signals and voltages of a power converter according to an embodiment of the present invention.

[0008] Figure 5 This describes a switching control circuit for a power converter according to another embodiment of the present invention.

[0009] Icon labels:

[0010] 1: Power converter;

[0011] 10: Switching capacitor conversion circuit;

[0012] 11: Inductive step-down circuit;

[0013] 12, 13: Switching control circuit;

[0014] 30: Constant On-Time (COT) Control Circuit;

[0015] 31: Reset circuit;

[0016] 32: Determine the circuit;

[0017] 33: Signal generation circuit;

[0018] 50: Current detector;

[0019] 51: Comparator;

[0020] 52: Signal generation circuit;

[0021] 100: Capacitor;

[0022] 101, 102, 103, 104: Switches;

[0023] 110: Input capacitor;

[0024] 111: High-side switch;

[0025] 112: Low-side switch;

[0026] 113: Inductor;

[0027] 114: Output capacitor;

[0028] 300: Current source;

[0029] 301: Capacitor;

[0030] 302, 303: Inverters;

[0031] 304: Switch;

[0032] 305: Buffer circuit;

[0033] CLK: Clock signal;

[0034] CLK0, CLK1, CLK(N-1), CLKN, CLK1~CLKN, CLK0~CLKN: Input clock signals;

[0035] CLK_SEL: Selection signal;

[0036] GND: Ground terminal;

[0037] I L Inductor current;

[0038] N10, N11, N12, N30: ​​Nodes;

[0039] RST: Detection signal;

[0040] S310: Comparison result signal;

[0041] S31: Control signal;

[0042] S IL Current status signal;

[0043] SW10, SW11: Switching signals;

[0044] SWH: Switching signal;

[0045] T10: Input terminal;

[0046] T11: Output terminal;

[0047] T12: Input terminal;

[0048] T13: Conversion output terminal;

[0049] V50: Detection voltage;

[0050] Vramp: Ramp voltage;

[0051] V REF Reference voltage;

[0052] V IN Input voltage;

[0053] V OUT Output voltage;

[0054] V TH Critical voltage;

[0055] V UNREG Intermediate voltage. Detailed Implementation

[0056] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, a preferred embodiment is described below in detail with reference to the accompanying drawings.

[0057] Figure 1 This refers to a power converter according to an embodiment of the present invention. See also... Figure 1 The power converter 1 is a hybrid power converter, comprising a first-stage switched capacitor converter circuit 10 and a second-stage inductive step-down circuit 11, and further including switching control circuits 12 and 13. Switching control circuit 12 generates switching signals SW10 and SW11, while switching control circuit 13 generates a switching signal SWH. The switched capacitor converter circuit 10 receives the input voltage V. IN The switching capacitor conversion circuit 10 receives switching signals SW10 and SW11. Based on these signals, it performs a switching operation to change the input voltage V. IN Converted to intermediate voltage V UNREG The inductive step-down circuit 11 is coupled to the switching capacitor conversion circuit 10 to receive the intermediate voltage V. UNREG The inductive step-down circuit 11 operates for a constant on-time (COT) to reduce the intermediate voltage V. UNREG Converted to output voltage V OUT .

[0058] In this embodiment, the switching control circuit 12 receives a current state signal S. IL It is related to the inductor current I that charges an inductor in the inductive step-down circuit 11. L The state is associated with the current. Switching control circuit 12 switches based on the current state signal S. IL The switching control circuit 12 determines whether the inductor current corresponds to or meets a preset condition. When the switching control circuit 12 determines that the inductor current corresponds to or meets the preset condition, it changes the levels of switching signals SW10 and SW11 to initiate a switching action in the switching operation of the switching capacitor conversion circuit 10. The switching control circuit 13 provides a constant time (COT) period and generates the switching signal SWH based on the constant time period. In addition, the switching control circuit 13 also determines the switching signal SWH based on the output voltage V. OUT The size of the value determines whether to restart the constant time period.

[0059] The following will describe in detail the circuit architecture and operation of the switching capacitor conversion circuit 10, the inductive step-down circuit 11, and the switching control circuits 12 and 13.

[0060] Figure 2 This is a circuit diagram of a switching capacitor converter circuit 10 and an inductive step-down circuit 11 according to an embodiment of the present invention. (See also...) Figure 2 The input terminal T10 of the switching capacitor conversion circuit 10 receives the input voltage V. INFurthermore, the inductive step-down circuit 11 is connected in series with the output terminal T11 of the switching capacitor converter circuit 10. The switching capacitor converter circuit 10 includes two switch groups and a capacitor. One switch group and the capacitor are connected in series between the input terminal T10 and the output terminal T11, and the other switch group and the capacitor are connected in series between the ground terminal GND and the output terminal T11. The state (on or off) of these two switch groups of the switching capacitor converter circuit 10 is controlled by two different switching signals, causing the two switch groups to be turned on alternately to achieve the switching operation, thereby changing the input voltage V. IN Converted to intermediate voltage V UNREG In this embodiment, the switching operation includes multiple switching actions, wherein each state change of the two switch groups corresponds to one switching action. The circuit architecture and operation of the switching capacitor conversion circuit 10 will be illustrated below with an example. See [reference needed]. Figure 2 The switching capacitor conversion circuit 10 includes, for example, switches 101, 102, 103, and 104, and a capacitor 100. Switches 101 and 104 form a first switch group, while switches 102 and 103 form a second switch group. Switch 101 is coupled between the input terminal T10 and node N10, switch 102 is coupled between node N10 and the output terminal T11, switch 103 is coupled between the ground terminal GND and node N11, and switch 104 is coupled between node N11 and the output terminal T11. The capacitor 100 is coupled between nodes N10 and N11. According to the connection structure of switches 101, 102, 103, 104, and capacitor 100 described above, the first switch group formed by switches 101 and 104 is connected in series with capacitor 100 between input terminal T10 and output terminal T11, and the second switch group formed by switches 102 and 103 is connected in series with capacitor 100 between ground terminal GND and output terminal T11. Switches 101 and 104 in the first switch group are controlled by the same switching signal SW10 to switch between on and off states. Switches 102 and 103 in the second switch group are controlled by the same switching signal SW11 to switch between on and off states. In this embodiment, the switching signals SW10 and SW11 are controlled by the switching control circuit 12 based on the current state signal S. ILThis is generated based on the timing of switching signals SW10 and SW11. The conduction times of switches 101 and 104 do not overlap with the conduction times of switches 102 and 103. In one embodiment, switching signals SW10 and SW11 have the same frequency, but their phases are opposite. Thus, switches 101 and 104 can conduct simultaneously, and switches 102 and 103 can conduct simultaneously, but switches 101 and 104 will not conduct simultaneously with switches 102 and 103. In this embodiment, the timing of the level transition between switching signals SW10 and SW11 is based on the current state signal S. IL This is determined by the current state signal S. In other words, the timing of each switching action in the switching operation is based on the current state signal S. IL The switching capacitor conversion circuit 10 is determined to switch from a first on state to a second on state. In one embodiment, the first on state of the switching capacitor conversion circuit 10 is when one of the first switch groups (switches 101 and 104) or the second switch group (switches 102 and 103) is on while the other is off, and the second on state is the opposite of the first on state. For example, the first on state of the switching capacitor conversion circuit 10 is when the first switch group (switches 101 and 104) is on while the second switch group (switches 102 and 103) is off, and the second on state is when the first switch group (switches 101 and 104) is off while the second switch group (switches 102 and 103) is on. In this example, assuming the switching capacitor conversion circuit 10 is in the first on state, when a switching action is performed according to the current state signal S... IL When activated, the first switch group (switches 101 and 104) switches from the on state to the off state, while the second switch group (switches 102 and 103) switches from the off state to the on state, meaning the switching capacitor conversion circuit 10 switches to the second on state. Conversely, assuming the switching capacitor conversion circuit 10 is in the second on state, when a switching action is performed according to the current state signal S... IL When activated, the first switch group (switches 101 and 104) switches from the off state to the on state, while the second switch group (switches 102 and 103) switches from the on state to the off state, meaning the switching capacitor conversion circuit 10 switches to the first on state. Through multiple switching actions corresponding to the state changes of switches 101, 102, 103, and 104, the switching capacitor conversion circuit 10 performs a switching operation to change the input voltage V. IN Converted to the intermediate voltage V on the output terminal T11 UNREG .

[0061] See Figure 2The input terminal T12 of the inductive step-down circuit 11 is connected to the output terminal T11 of the switching capacitor conversion circuit 10, thus connecting the inductive step-down circuit 11 and the switching capacitor conversion circuit 10 in series. The inductive step-down circuit 11 includes an input capacitor 110, a high-side switch 111, a low-side switch 112, an inductor 113, and an output capacitor 114. The input capacitor 110 is coupled between the input terminal T12 and the ground terminal GND, and is connected by an intermediate voltage V. UNREG Charging. High-side switch 111 is coupled between input terminal T12 and node N12. Low-side switch 112 is coupled between node N12 and ground terminal GND. Inductor 113 is coupled between node N12 and conversion output terminal T13. Output capacitor 114 is coupled between conversion output terminal T13 and ground terminal GND. High-side switch 111 is controlled by switching signal SWH to switch between an on and off state. Specifically, high-side switch 111 turns on whenever a start pulse occurs in switching signal SWH. The control terminal of low-side switch 112 is grounded. In this embodiment, switching signal SWH is generated by a switching control circuit. Through the state switching of high-side switch 111, the inductive buck circuit 11 adjusts according to the intermediate voltage V. UNREG An output voltage V is generated at the conversion output terminal T13. OUT .

[0062] Figure 3 This illustrates a switching control circuit 12 and a switching control circuit 13 according to an embodiment of the present invention. To provide a detailed explanation of the operation of the switching control circuit 12 and the switching control circuit 13, Figure 3 The high-side switch 111 and the low-side switch 112 are also shown. Figure 3 In this embodiment, the high-side switch 111 is implemented using a P-type metal-oxide-semiconductor (PMOS) field-effect transistor MP, while the low-side switch 112 is implemented using an N-type metal-oxide-semiconductor (NMOS) field-effect transistor MN. The source of the PMOS transistor MP is coupled to the input terminal T12, and its drain is coupled to node N12. The drain of the NMOS transistor MN is coupled to node N12, and its source is coupled to ground GND. Furthermore, the gate of the NMOS transistor MN serves as the control terminal of the low-side switch 112, see [reference]. Figure 3 The gate of the NMOS transistor MN is coupled to the ground terminal GND.

[0063] See Figure 3The switching control circuit 13 includes a constant on-time (COT) control circuit 30 and a reset circuit 31. The constant on-time (COT) control circuit 30 includes a current source 300, a capacitor 301, a buffer circuit 305, and a switch 304. The current source 300 is coupled between the power converter's operating voltage VDD and node N30, and provides a charging current I. CH Capacitor 301 is coupled between node N30 and ground GND. Buffer circuit 305 has an input coupled to node N30 to receive the ramp voltage Vramp and an output that generates a switching signal SWH. In this embodiment, buffer circuit 305 is implemented using inverters 302 and 303. The input of inverter 302 is coupled to node N30. The input of inverter 303 is coupled to the output of inverter 302, and its output is coupled to the gate of the PMOS transistor MP, but the invention is not limited to this embodiment. The switching signal SWH is generated at the output of inverter 303. Switch 304 is coupled between node N30 and ground GND and is controlled by the reset signal RST.

[0064] The reset circuit 31 includes a latching comparator 310, a pulse generator 311, and a multiplexer 312. The positive input (+) of the latching comparator 310 receives the output voltage V. OUT And its negative input terminal (-) receives the reference voltage V. REF The latching comparator 310 compares the output voltage V based on the clock signal CLK. OUT With reference voltage V REF And based on the comparison result, a comparison result signal S310 is generated. When the output voltage V OUT Less than the reference voltage V REF When a single pulse occurs on the comparison result signal S310, a pulse generator 311 is coupled to the latching comparator 310 to receive the comparison result signal S310. The pulse generator 311 generates a reset signal RST based on the comparison result signal S310. Whenever a single pulse occurs on the comparison result signal S310, a single pulse also occurs on the reset signal RST to turn on the switch 304.

[0065] In this embodiment, the clock signal CLK is provided by the multiplexer 312. See also... Figure 3The multiplexer 312 receives multiple input clock signals CLK0, CLK1, ..., CLK(N-1), CLKN at its N input terminals. The multiplexer 312 selects one of the input clock signals CLK0 to CLKN as the clock signal CLK based on the selection signal CLK_SEL. The clock signals CLK0 to CLKN have different frequencies. For example, the frequencies of the input clock signals CLK0 to CLKN decrease sequentially. In one embodiment, the multiplexer 312 selects one of the input clock signals CLK0 to CLKN as the clock signal CLK based on the load current flowing through the load of the power converter. Specifically, the value of the selection signal CLK_SEL represents the magnitude of the load current flowing through the load of the power converter, and the multiplexer 312 selects one of the input clock signals CLK0 to CLKN as the clock signal CLK based on the value of the selection signal CLK_SEL.

[0066] In one embodiment, the input clock signals CLK0 to CLKN are associated with the system clock of the device in which the power converter is located. For example, the frequency of the input clock signal CLK0 is the same as the frequency of the system clock, while the frequency of the system clock is a multiple of the frequency of each of the input clock signals CLK1 to CLKN, and the multiple values ​​between the system clock frequency and the input clock signals CLK1 to CLKN are different from each other.

[0067] The following will be referred to Figure 3 and Figure 4A To illustrate the operation of the switching control circuit 13.

[0068] See Figure 3 When switch 304 is turned off according to reset signal RST, the charging current I of current source 300... CH Capacitor 301 is charged. Therefore, the ramp voltage Vramp on node N30 gradually rises from the voltage level of ground GND. While the ramp voltage Vramp is still below the threshold voltage of inverter 302, the switching signal SWH generated by inverter 303 is at a low voltage level to turn on the PMOS transistor MP through the operation of inverters 302 and 303. See also... Figure 4A Because the PMOS transistor MP is turned on, the inductor current I... L A peak value occurs. This is reflected in the inductor current I. L Peak value, output voltage V OUT Instant boost, and intermediate voltage V UNREGThe voltage drops. Once the ramp voltage Vramp exceeds the threshold voltage of inverter 302, the switching signal SWH generated by inverter 303 is at a high voltage level to turn off the PMOS transistor MP, and the inductor current I... L The current will flow through the body diode of the NMOS transistor MN. Since the load of the power converter draws current from the output terminal T13, the output voltage V... OUT After an initial surge, the current gradually decreases. In this embodiment, the current source 300 is a constant current source to provide a fixed charging current I. CH Due to the charging of capacitor 301 by constant current source 300 and the critical voltage of inverter 302, the conduction time of PMOS transistor MP remains fixed. Therefore, the inductive buck converter 11 operates under the control of constant on-time (COT) control circuit 30 for a constant on-time.

[0069] In this embodiment of the invention, the latching comparator 310 compares the output voltage V when the falling edge of the clock signal CLK occurs. OUT With reference voltage V REF See also Figure 4A At the output voltage V OUT During the gradual decrease, when the output voltage V OUT Greater than the reference voltage V REF When the comparison result signal S310 is at a high voltage level, the output voltage V... OUT Gradually decrease until it falls below the reference voltage V REF When the comparison result signal S310 changes from a high voltage level to a low voltage level, that is, a falling edge occurs in the comparison result signal S310. For example... Figure 4A As shown, the falling edge of the comparison result signal S310 is aligned with the falling edge of the clock signal CLK, and when the clock signal CLK experiences a series of rising edges, the comparison result signal S310 returns to a high voltage level, i.e., a rising edge occurs in the comparison result signal S310. Based on the above, it can be seen that once the output voltage V... OUT Below the reference voltage V REF At that time, the comparison result signal S310 generates a single pulse P310 with a fixed duration, and this fixed duration is equal to half the period of the clock signal CLK.

[0070] When a single pulse P310 is generated in the comparison result signal S310, the pulse generator 311 generates a single pulse on the reset signal RST based on this pulse P310, so as to turn on the switch 304 during the single pulse period to reset the constant on-time (COT) control circuit 30. At this time, the capacitor 301 discharges through the turned-on switch 304, so the ramp signal Vramp drops to the voltage level of the ground terminal GND. As the single pulse on the reset signal RST disappears, the switch 304 switches from the on state to the off state, and the current source 300 starts charging with the charging current I. CH Capacitor 301 is charged, and the ramp voltage Vramp gradually rises from the voltage level of the ground terminal GND. Afterwards, the operation of the constant on-time (COT) control circuit 30 is as described above and will not be repeated here. In the above operation, the time interval between two consecutive resets of the constant on-time (COT) control circuit 30 is called a COT cycle. In other words, whenever the constant on-time (COT) control circuit 30 is reset, the COT cycle restarts, and the constant current source 300 begins charging capacitor 301.

[0071] Based on the above, once the output voltage V OUT Below the reference voltage V REF At this time, a single pulse P310 is generated in response to the comparison result signal S310. In response to this single pulse P310 in the comparison result signal S310, the constant on-time (COT) control circuit 30 is reset, and the inductor current I... L A peak value occurs, and the output voltage V OUT Instant boost. Output voltage V OUT After a brief surge, the voltage gradually decreases until it reaches a minimum, at which point the output voltage V... OUT Again below the reference voltage V REF The comparison result signal S310 generates the next single pulse P310. (See also...) Figure 4A In the inductor current I L At each peak value, the intermediate voltage V UNREG It decreases once. Therefore, over time, the inductor current I... L The peak value is getting lower and lower, and the output voltage V OUT The maximum value during the boost also decreases. At this time, the COT period of the constant on-time (COT) control circuit 30 becomes shorter and shorter, and the switching of switch 111 in the switching capacitor conversion circuit 10 becomes faster and faster, such as... Figure 4B As shown, this is to maintain the driving capability of the power converter. However, if multiple comparison result signals S310 are generated by a single pulse P310 within a preset time, it indicates that the inductor current I... LThe peak voltage is too low, resulting in insufficient driving capability of the power converter. At this point, it is necessary to activate the switching action of the switching capacitor conversion circuit 10 to increase the intermediate voltage V. UNREG This enables the driving capability of the recovery rate converter 1.

[0072] In this embodiment, the voltage level change of the comparison result signal S310 is reflected in the output voltage V. OUT The magnitude of the inductor current I is such that when a single pulse P310 is generated from the comparison result signal S310 to reset the control circuit 31, the inductor current I... L A peak value occurs. Therefore, it can be concluded that the comparison result signal S310 at this time can represent the inductor current I. L The state. Specifically, a single pulse P310 of the comparison result signal S310 can represent the inductor current I. L A peak occurs, therefore, within a preset time period, the number of single pulses P310 of the comparison result signal S310 is equal to the inductor current I. L The number of peak values. In this way, the comparison result signal S310 can represent the inductor current I. L The number of peak values ​​occurring within this preset time period. As can be seen from the above, with the inductor current I... L The peak value decreases and the number of single pulses P310 of the comparison result signal S310 increases within the preset time.

[0073] In another embodiment, switch 112 (implemented as an NMOS transistor MN) can be controlled instead by an inductor current detection signal and a switching signal SWH. The inductor current detection signal represents the inductor current I. L Is it zero? When the switching signal SWH is at a low voltage level, the NMOS transistor MN is turned off, and the inductor current I... L Rising; when the switching signal SWH is at a high voltage level, the NMOS transistor MN turns on, and the inductor current I... L Decrease; when the inductor current I L When the current drops to zero, the inductor current detection signal turns off the NMOS transistor MN again.

[0074] The following will be referred to Figure 3 , Figure 4A and Figure 4B To illustrate the operation of the switching control circuit 13.

[0075] The switching control circuit 12 includes a judgment circuit 32 and a signal generation circuit 33. The judgment circuit 32 receives the current status signal S. ILThe circuit generates a clock signal CLK and a control signal S32. The signal generation circuit 33 generates switching signals SW10 and SW11, and determines whether to change the voltage levels of switching signals SW10 and SW11 based on the control signal S32, thereby initiating the switching operation of the switching capacitor conversion circuit 10. Based on the above, the comparison result signal S310 can represent the inductor current I. L Therefore, in this embodiment, the judgment circuit 32 of the switching control signal 12 receives the comparison result signal S310 as the current state signal S. IL Calculate the inductor current I in circuit 32. L The number of peak values ​​occurring within a preset time period is used to generate a count value, and it is determined whether the obtained count value is greater than a preset number. In this embodiment, the preset condition refers to the count value (representing the inductor current I). L The number of peaks occurring within the preset time period is greater than the preset number. The judgment circuit 32 generates a control signal S32 based on the judgment result. In this embodiment, the preset time is two cycles of the clock signal CLK, and the preset number is 2. In one case, such as... Figure 4A In the scenario shown, when the judgment circuit 32 determines that the count value obtained within two cycles of the clock signal CLK is not greater than a preset number (e.g., 2), it generates a control signal S32 with a low voltage level VL. At this time, the signal generation circuit 33 maintains the voltage levels of the switching signals SW10 and SW11 without changing them. In another scenario, such as... Figure 4B As shown, when the judgment circuit 32 determines that the count value obtained by counting within two cycles of the clock signal CLK is greater than a preset number (e.g., 2) (i.e., the inductor current I...), L The state corresponds to the preset conditions, and a control signal S32 with a high voltage level VH is generated. At this time, the signal generation circuit 33 changes the voltage levels of the switching signals SW10 and SW11 to start the switching action of the switching capacitor conversion circuit 10.

[0076] Based on the above, when the inductor current I L When the peak voltage is too low, the driving capability of the power converter is insufficient. At this point, it is necessary to activate the switching action of the switching capacitor conversion circuit 10 to increase the intermediate voltage V. UNREG This allows for the recovery of the driving capability of the rate converter 1. Therefore, in some embodiments, the driving capability can be determined based on the inductor current I. L The size determines whether the switching action of the switching capacitor conversion circuit 10 is triggered.

[0077] Figure 5 This illustrates a switching control circuit 12 and a switching control circuit 13 according to an embodiment of the present invention. See also... Figure 5The circuit architecture and operation of the switching control circuit 13 Figure 3 The embodiments are the same. Figure 5 Implementation examples and Figure 3 The differences between the embodiments are that, Figure 5 The control switching circuit 12 includes a current detector 50, a comparator 51, and a signal generation circuit 52. The current detector 50 is coupled to the inductor 113 at node N12 (shown in...). Figure 2 To detect the inductor current I L In detail, the current detector 50 is connected in parallel with the PMOS transistor MP of the high-side switch 111 to detect the drain voltage V of the PMOS transistor MP. D With source voltage V S And based on the detected drain voltage V D With source voltage V S The inductor current I is obtained by the drain-source voltage difference between the two sources. L In order to realize the inductor current I L The detection is performed due to the drain-source voltage difference and the inductor current I. L Correlated, therefore, drain voltage V D With source voltage V S It can represent the inductor current I L The state. In this embodiment, the switching control signal 12 receives the drain voltage V. D With source voltage V S As the current state signal S IL The current detector 50 generates a detection voltage V50 based on the magnitude of the drain-source voltage difference. Therefore, based on the drain voltage V... D With source voltage V S The obtained detection voltage V50 can represent the inductor current I. L The size of the voltage. Comparator 51 is coupled to current detector 50 to receive the detected voltage V50, and compares the detected voltage V50 with a threshold voltage V. TH Critical voltage V TH Corresponding inductor current I L The critical current value is determined by comparing the detection voltage V50 with the critical voltage V. TH The inductor current I can be determined. L Is it less than the critical current value? In this embodiment, the preset condition refers to the detection voltage V50 (representing the inductor current I). L The magnitude of the voltage is less than the critical voltage V. TH (i.e., inductor current I) L(Less than the critical current value). Comparator 51 generates a control signal S51 based on the comparison result. Signal generation circuit 52 generates switching signals SW10 and SW11, and determines whether to change the voltage levels of switching signals SW10 and SW11 based on the control signal S51 to initiate the switching operation of the switching capacitor conversion circuit 10. In one case, when comparator 51 compares and finds that the detected voltage V50 is greater than the critical voltage V... TH (i.e., inductor current I) L When the current exceeds the critical current value, a control signal S51 with a low voltage level is generated. At this time, the signal generation circuit 52 maintains the voltage levels of switching signals SW10 and SW11 without changing them. In another case, when comparator 51 compares and finds that the detected voltage V50 is less than the critical voltage V... TH At this time, a control signal S51 with a high voltage level is generated. At this time, the signal generation circuit 52 changes the voltage levels of the switching signal SW10 and the switching signal SW11 to start the switching operation of the switching capacitor conversion circuit 10.

[0078] Based on the above, the switching control circuit 13 proposed in this application uses a constant on-time method to control the second-stage inductive buck circuit 11, replacing the inductor current limiting method of traditional hybrid power converters. Therefore, the switching control circuit 13 of this application has a simpler circuit design, resulting in a reduction in quiescent current. Consequently, under light or ultra-light load conditions, the lower quiescent current improves the efficiency of the power converter. Furthermore, when using a constant on-time method to control the inductive buck circuit 11, the switching control circuit 12 can control the inductor current I... L When the state meets or corresponds to one of the preset conditions mentioned above, the switching action of the switching capacitor conversion circuit 10 is initiated. In other embodiments, the switching control circuit 12 may initiate the switching action of the switching capacitor conversion circuit 10 when the power converter enters a critical current mode from a discontinuous current mode.

Claims

1. A power converter, characterized in that, include: A switching capacitor converter circuit receives an input voltage at an input terminal and performs a switching operation to convert the input voltage into an intermediate voltage. as well as An inductive step-down circuit is coupled to an output of the switching capacitor conversion circuit to receive the intermediate voltage, and operates for a constant on-time to generate an output voltage at a switching output based on the intermediate voltage. The inductive step-down circuit includes an inductor. When the inductor current charging the inductor reaches a preset number of peak values ​​within a preset time, or when the inductor current is less than a critical current value, all switching actions of the switching operation are activated, causing the switching capacitor conversion circuit to switch from a first conducting state to a second conducting state, so as to improve the intermediate voltage. The inductive step-down circuit includes a high-side switch and an inductor connected in series between the output terminal and the conversion output terminal of the switching capacitor converter circuit, and the power converter further includes: A constant on-time control circuit provides a constant time period and generates a switching signal based on the constant time period to control the high-side switch; According to the switching signal, the high-side switch is turned on for a fixed period of time during the constant time cycle; The constant on-time control circuit includes: A current source provides a charging current; A capacitor has a first terminal coupled to a constant current source at a first node and a second terminal coupled to a ground terminal, wherein a ramp voltage is generated at the first node; A buffer circuit has an input terminal coupled to the first node to receive the ramp voltage and an output terminal to generate a switching signal; The high-side switch is controlled by the switching signal; and The inductive step-down circuit further includes a low-side switch coupled between the conversion output terminal and the ground terminal, and a control terminal of the low-side switch is grounded.

2. The power converter as described in claim 1, characterized in that, The switching capacitor conversion circuit includes: A capacitor is coupled between a first node and a second node; A first switch group, connected in series with the capacitor between the input terminal and the output terminal; and A second switch group is connected in series with the capacitor between a ground terminal and the output terminal; Wherein, when the switching capacitor conversion circuit is in the first conducting state, the first switch group is connected to one of the switch groups in the second switch group; and When the switching capacitor conversion circuit is in the second conducting state, the first switch group is connected to another switch group in the second switch group.

3. The power converter as described in claim 1, characterized in that, The switching action of the switching capacitor conversion circuit can be initiated when the power converter transitions from a discontinuous current mode to a critical current mode.

4. The power converter as described in claim 1, characterized in that, It further includes a reset circuit for resetting the constant on-time control circuit to restart the constant time period, wherein the reset circuit includes: A latching comparator receives the output voltage and a reference voltage, compares the output voltage and the reference voltage according to a clock signal, and generates a comparison result signal based on the comparison result of the output voltage and the reference voltage. When the output voltage is lower than the reference voltage, a single pulse is generated in the comparison result signal to reset the constant on-time control circuit.

5. The power converter as described in claim 4, characterized in that, The frequency of the clock signal is determined by the load current flowing through a load of the power converter.

6. The power converter as described in claim 1, characterized in that, Including: A latching comparator receives an output voltage and a reference voltage, compares the output voltage with the reference voltage, and generates a comparison result signal based on the comparison result. The comparison result signal generates a single pulse whenever the output voltage is lower than the reference voltage, and each single pulse of the comparison result signal corresponds to a peak value of the inductor current. A judgment circuit receives the comparison result signal and counts the number of at least one single pulse on the comparison result signal within a preset time according to a clock signal to obtain a count value; The determination circuit determines whether the count value is greater than the preset number to generate a control signal to the switching capacitor conversion circuit; and When the judgment circuit determines that the count value is greater than the preset number, the switching action of the switching capacitor conversion circuit is activated according to the control signal.

7. The power converter as claimed in claim 1, characterized in that, Including: A current detector detects the current in the inductor to generate a detection voltage; A comparator receives the detected voltage, compares the detected voltage with a threshold voltage, and generates a control signal to the switching capacitor conversion circuit based on the comparison result of the detected voltage and the threshold voltage. When the comparator determines that the detected voltage is less than the threshold voltage, the switching action of the switching capacitor conversion circuit is initiated according to the control signal.

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