Analog-to-digital converter device and clock skew correction method

Abstract

An analog-to-digital converter apparatus and a method for correcting clock skew. The analog-to-digital converter apparatus includes a plurality of analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The analog-to-digital conversion circuits are used to convert an input signal according to a plurality of clock signals to generate a plurality of first quantized outputs. The correction circuit is used to correct the first quantized outputs to generate a plurality of second quantized outputs. The skew adjustment circuit includes an estimation circuit and a feedback circuit. The estimation circuit is used to analyze the second quantized outputs to generate a plurality of detection signals, wherein the skew adjustment circuit outputs the detection signals as a plurality of adjustment signals to reduce a clock skew of the analog-to-digital conversion circuits. The feedback circuit is used to analyze the detection signals generated by the estimation circuit to generate a feedback signal to the estimation circuit. By analyzing the signals generated by the skew adjustment circuit to generate the feedback signal, phase errors among the plurality of analog-to-digital conversion circuits can be avoided to produce incorrect convergence.

Description

Technical Field

[0001] This disclosure relates to an analog-to-digital converter device and a clock skew correction method, and more particularly to a time-interleaved analog-to-digital converter device and a clock skew correction method. Background Technology

[0002] Analog-to-digital converters (ADCs) are commonly used in various electronic devices to convert analog signals to digital signals for signal processing. In practical applications, ADCs can suffer from gain errors, offset errors, or timing errors, affecting their resolution or linearity. In particular, current techniques for correcting timing errors are not accurate enough, potentially causing phase errors between different channels to converge incorrectly. Summary of the Invention

[0003] One aspect of this invention is an analog-to-digital converter (ADC) device. This ADC device includes multiple analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The analog-to-digital conversion circuits convert an input signal based on multiple clock signals to generate multiple first quantized outputs. The correction circuit performs at least one correction operation based on these first quantized outputs to generate multiple second quantized outputs. The skew adjustment circuit includes an estimation circuit and a feedback circuit. The estimation circuit analyzes the second quantized outputs to generate multiple detection signals, wherein these detection signals are associated with multiple time difference information of the clock signals. The skew adjustment circuit outputs these detection signals as multiple adjustment signals to reduce the clock skew of the analog-to-digital conversion circuits. The feedback circuit analyzes the detection signals generated by the estimation circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the detection signals based on the feedback signal.

[0004] In another embodiment, the estimation circuit includes: a delay circuit for delaying the last of the second quantization outputs to generate a delayed quantization output; a plurality of first arithmetic circuits for sequentially receiving the delayed quantization output and the second quantization outputs, and the first arithmetic circuits for generating a plurality of difference signals based on two signals of the delayed quantization output and the second quantization outputs respectively; a plurality of absolute value circuits for outputting a plurality of absolute value signals, wherein each absolute value circuit is configured to perform an absolute value operation based on a corresponding difference signal of the difference signals to generate a corresponding absolute value signal of the absolute value signals; a plurality of statistical circuits for receiving the absolute value signals within a predetermined period and performing a maximum value operation or an average operation to output a plurality of calculated signals; an averaging circuit for performing an averaging operation to average the calculated signals to generate an average signal; a second arithmetic circuit for performing an addition operation based on the average signal and the feedback signal to generate a reference signal; and a plurality of comparison circuits for comparing each calculated signal with the reference signal to generate the detection signals.

[0005] In another embodiment, the feedback circuit includes: a summing circuit for performing a summing operation to sum the detection signals to generate a summed signal; a filtering circuit for generating a trigger signal based on the summed signal and at least one threshold value; and an integrating circuit for accumulating the trigger signal and outputting the accumulated trigger signal as the feedback signal.

[0006] In another embodiment, the feedback circuit further includes an amplifier circuit coupled between the filter circuit and the integrator circuit, and is used to amplify the trigger signal.

[0007] In another embodiment, the at least one threshold value includes a positive threshold value and a negative threshold value, and the filter circuit compares the summed signal with the positive threshold value and the negative threshold value to generate the trigger signal.

[0008] Another aspect of this case is an analog-to-digital converter (ADC) device. This ADC device includes multiple analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The analog-to-digital conversion circuits convert an input signal based on multiple clock signals to generate multiple first quantized outputs. The correction circuit performs at least one correction operation based on these first quantized outputs to generate multiple second quantized outputs. The skew adjustment circuit includes an estimation circuit, an adjustment circuit, and a feedback circuit. The estimation circuit analyzes the second quantized outputs to generate multiple detection signals, wherein these detection signals are associated with multiple time difference information of the clock signals. The adjustment circuit generates multiple adjustment signals based on these detection signals, wherein these adjustment signals reduce a clock skew of the analog-to-digital conversion circuits. The feedback circuit analyzes multiple first trigger signals generated by the adjustment circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the detection signals based on the feedback signal.

[0009] In another embodiment, the adjustment circuit includes: a plurality of first filtering circuits for generating the first trigger signals based on the detection signals and at least a first threshold; and a plurality of first integrating circuits, wherein each of the integrating circuits is used to accumulate a corresponding first trigger signal among the first trigger signals and output the accumulated corresponding first trigger signal as a corresponding adjustment signal among the adjustment signals.

[0010] In another embodiment, the feedback circuit includes: a summing circuit for performing a summing operation to sum the first trigger signals to generate a summed signal; a second filtering circuit for generating a second trigger signal based on the summed signal and at least one second threshold value, wherein the at least one second threshold value includes a positive threshold value and a negative threshold value; and a second integrating circuit for accumulating the second trigger signal and outputting the accumulated second trigger signal as the feedback signal.

[0011] In another embodiment, the feedback circuit further includes an amplifier circuit coupled between the second filter circuit and the second integrator circuit, and is used to amplify the second trigger signal.

[0012] Another aspect of this case is a clock skew correction method. This clock skew correction method includes: performing at least one correction operation based on multiple first quantization outputs generated by multiple analog-to-digital converter circuits to generate multiple second quantization outputs; analyzing these second quantization outputs through an estimation circuit of a skew adjustment circuit to generate multiple detection signals, wherein these detection signals are associated with multiple time difference information of multiple clock signals received by the analog-to-digital converter circuits, the skew adjustment circuit outputting these detection signals as multiple adjustment signals to reduce a clock skew of the analog-to-digital converter circuits; and analyzing these detection signals generated by the estimation circuit through a feedback circuit of the skew adjustment circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the detection signals according to the feedback signal.

[0013] In another embodiment, generating these detection signals includes: delaying the last of the second quantization outputs to generate a delayed quantization output; sequentially receiving the delayed quantization output and the second quantization outputs, and generating a plurality of difference signals based on two signals from the delayed quantization output and the second quantization outputs respectively; performing an absolute value operation based on a corresponding difference signal from the plurality of difference signals to generate a corresponding absolute value signal from the plurality of absolute value signals; receiving the absolute value signals within a predetermined period, and performing a maximum value operation or an averaging operation to output a plurality of calculated signals; performing an averaging operation to average the calculated signals to generate an average signal; performing an addition operation based on the average signal and the feedback signal to generate a reference signal; and comparing each calculated signal with the reference signal to generate the detection signals.

[0014] In another embodiment, generating the feedback signal includes: performing a summation operation to sum the detection signals to generate a summed signal; generating a trigger signal based on the summed signal and at least one threshold value; and accumulating the trigger signal and outputting the accumulated trigger signal as the feedback signal.

[0015] In another embodiment, the trigger signal is amplified after it is generated.

[0016] In another embodiment, the at least one threshold value includes a positive threshold value and a negative threshold value, and generating the trigger signal includes comparing the summed signal with the positive threshold value and the negative threshold value.

[0017] Another aspect of this case is a clock skew correction method. This clock skew correction method includes: performing at least one correction operation based on a plurality of first quantization outputs generated by a plurality of analog-to-digital converter circuits to generate a plurality of second quantization outputs; analyzing these second quantization outputs through an estimation circuit to generate a plurality of detection signals, wherein these detection signals are associated with a plurality of time difference information of a plurality of clock signals received by the analog-to-digital converter circuits; generating a plurality of adjustment signals based on these detection signals through an adjustment circuit, wherein these adjustment signals are used to reduce a clock skew of the analog-to-digital converter circuits; and analyzing a plurality of first trigger signals generated by the adjustment circuit through a feedback circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the detection signals based on the feedback signal.

[0018] In another embodiment, generating these adjustment signals includes: generating the first trigger signals based on the detection signals and at least a first threshold; and accumulating a corresponding first trigger signal among the first trigger signals and outputting the accumulated corresponding first trigger signal as a corresponding adjustment signal among the adjustment signals.

[0019] In another embodiment, generating the feedback signal includes: performing a summation operation to sum the first trigger signals to generate a summed signal; generating a second trigger signal based on the summed signal and at least one second threshold value, wherein the at least one second threshold value includes a positive threshold value and a negative threshold value; and accumulating the second trigger signal and outputting the accumulated second trigger signal as the feedback signal.

[0020] In another embodiment, the second trigger signal is amplified after it is generated.

[0021] In summary, the analog-to-digital converter device disclosed herein generates a feedback signal by analyzing multiple signals produced by the skew adjustment circuit through the design of the feedback circuit. This feedback signal compensates for the reference signal used to correct the phase error between multiple analog-to-digital conversion circuits. In this way, the phase error between the multiple analog-to-digital conversion circuits can be prevented from converging towards the upper or lower limit of the circuit. Attached Figure Description

[0022] Figure 1A This is a schematic diagram illustrating an analog-to-digital converter device according to some embodiments of this case;

[0023] Figure 1B The illustration is based on some embodiments of this case. Figure 1A A waveform diagram of multiple clock signals;

[0024] Figure 2 This is a schematic diagram of a skew adjustment circuit in an analog-to-digital converter device, illustrated according to some embodiments of this case;

[0025] Figure 3 This is a circuit diagram illustrating a skew adjustment circuit in an analog-to-digital converter device according to some embodiments of this case;

[0026] Figure 4 This is a schematic diagram of a feedback circuit in an analog-to-digital converter device, illustrated according to some embodiments of this case;

[0027] Figure 5 This is another schematic diagram illustrating a feedback circuit in an analog-to-digital converter device according to some embodiments of the present invention;

[0028] Figure 6 This is a flowchart illustrating a clock skew correction method based on some embodiments of this case;

[0029] Figure 7 This is another schematic diagram of a skew adjustment circuit in an analog-to-digital converter device, illustrated according to some embodiments of this case.

[0030] [Symbol Explanation]

[0031] 100: Analog-to-digital converter device

[0032] 110: Analog-to-digital conversion circuit

[0033] 120: Correction circuit

[0034] 130: Skew adjustment circuit

[0035] 131: Estimation Circuit

[0036] 133: Adjustment Circuit

[0037] 135: Feedback Circuit

[0038] 140: Output Circuit

[0039] 201: Delay Circuit

[0040] 211: First operational circuit

[0041] 221: Absolute value circuit

[0042] 231: Statistical Circuits

[0043] 241: Average Circuit

[0044] 251: Second operational circuit

[0045] 261: Comparator Circuit

[0046] 215: Summarizing circuit

[0047] 213, 225: Filtering circuits

[0048] 223, 235: Integrating circuits

[0049] 245: Amplifier Circuit

[0050] 600: Clock Skew Correction Method

[0051] CLK0~CLK M-1 Clock signal

[0052] Q0~Q M-1 CQ -1 ~CQ M-1 Quantization output

[0053] D0~D M-1 Difference signal

[0054] A0~A M-1 Absolute value signal

[0055] M0~M M-1 : Calculate signal

[0056] SD0~SD M-1 Detection signal

[0057] TR10~TR1 M-1 TR2: Trigger signal

[0058] T0~T M-1 Adjust signal

[0059] SIN: Input signal

[0060] SOUT: Output signal

[0061] AVG: Average Signal

[0062] F: Feedback signal

[0063] REF: Reference signal

[0064] STR1: Summarized signal

[0065] TH1, TH2 + TH2 - Critical value

[0066] fs: Sampling frequency

[0067] SP: Sampling Period

[0068] ST: Booking Period

[0069] S610~S640: Steps Detailed Implementation

[0070] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure that is recombined with elements and produces a device with equivalent function is within the scope of this disclosure.

[0071] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0072] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0073] Please see Figure 1A , Figure 1B , Figure 1A This is a schematic diagram illustrating an analog-to-digital converter (ADC) device 100 according to some embodiments of this case. Figure 1B The illustration is based on some embodiments of this case. Figure 1A Multiple clock signals CLK0~CLK M-1 The waveform diagram is shown below. In some embodiments, the ADC device 100 operates as a multi-channel time-interleaved ADC.

[0074] In some embodiments, the ADC device 100 includes a plurality of analog-to-digital conversion circuits 110, a correction circuit 120, a skew adjustment circuit 130, and an output circuit 140. Notably, each analog-to-digital conversion circuit 110 operates as a single channel. In other words, the ADC device 100 includes M channels. In some embodiments, M is an even number. Figure 1A As shown, multiple analog-to-digital converter circuits 110 are used to convert multiple clock signals CLK0 to CLK0. M-1 One of the input signals SIN is converted from analog to digital to generate the corresponding quantized outputs Q0 to Q1. M-1 .

[0075] like Figure 1B As shown, multiple clock signals CLK0~CLK M-1There is a time interval between two adjacent clock signals. Therefore, two adjacent channels will perform sampling operations and analog-to-digital conversion at different times. For example, the first channel (i.e., the analog-to-digital converter 110 operating according to clock signal CLK0) samples the input signal SIN at the first sampling time S1 and performs analog-to-digital conversion; the second channel (i.e., the analog-to-digital converter 110 operating according to clock signal CLK-1) samples the input signal SIN at the second sampling time S2 and performs analog-to-digital conversion; and the third channel (i.e., the analog-to-digital converter 110 operating according to clock signal CLK-2) samples the input signal SIN at the third sampling time S3 and performs analog-to-digital conversion. The difference between sampling times S1 and S2 is the sampling period SP (the corresponding sampling frequency is fs, i.e., SP = 1 / fs). And so on, M channels can operate according to multiple interleaved timing sequences.

[0076] As described above, the correction circuit 120 is coupled to each analog-to-digital converter circuit 110 to receive multiple quantization outputs Q0 to Q10. M-1 The correction circuit 120 can output Q0~Q based on quantization. M-1 Perform at least one correction operation to correct the offset and gain errors in multiple analog-to-digital conversion circuits 110, and generate multiple corrected quantized outputs CQ0 to CQ0. M-1 .

[0077] In some embodiments, the correction circuit 120 may be a foreground correction circuit or a background correction circuit. For example, the correction circuit 120 may include a pseudo-random number generator circuit (not shown) and a digital processing circuit (not shown), wherein the pseudo-random number generator circuit generates a correction signal (not shown) to the analog-to-digital converter circuit 110, and the digital processing circuit can output multiple quantization outputs Q0 to Q10. M-1 An adaptive algorithm (i.e., at least one of the aforementioned correction operations) is executed to reduce the quantization output Q0 to Q1. M-1 The offset or error. The correction circuit 120 described above is for illustrative purposes only and is not intended to be limited thereto. Various types of correction operations and correction circuits 120 are within the scope of this disclosure.

[0078] As described above, the skew adjustment circuit 130 is electrically coupled to the correction circuit 120 to receive multiple corrected quantization outputs CQ0 to CQ0. M-1 In some embodiments, the skew adjustment circuit 130 can adjust the skew outputs CQ0 to CQ based on the corrected quantization outputs. M-1 The clock skew (equivalent to phase error) between multiple analog-to-digital converter circuits 110 is analyzed to generate multiple adjustment signals T0 to T1. M-1In some embodiments, the skew adjustment circuit 130 converts multiple adjustment signals T0 to T1. M-1 The signals are output to multiple analog-to-digital converters 110, and multiple adjustment signals T0 to T1 are respectively output to these circuits. M-1 Used to indicate the timing adjustments required for multiple analog-to-digital conversion circuits 110 due to clock skew.

[0079] In detail (taking an even number of M as an example), the skew adjustment circuit 130 outputs multiple quantizations CQ0 to CQ0. M-1 The clock skew (equivalent to time difference information) between multiple analog-to-digital conversion circuits 110 is analyzed to generate multiple adjustment signals T0 to T1. M-1 Due to quantization output CQ 0- The first sampling time S1 corresponds to the first sampling time, and the quantization output CQ1 corresponds to the second sampling time S2. The time difference between these two corresponding times is one sampling period SP. Therefore, the quantization output CQ1 is analyzed. 0- Furthermore, the quantization output CQ1 reveals the time difference between clock signals CLK0 and CLK1 within one sampling period SP. Similarly, through this configuration, the skew adjustment circuit 130 can analyze the clock signals CLK0 to CLK1. M-1 The time difference information of each pair of adjacent clock signals within one sampling period SP.

[0080] The above analysis uses clock signals CLK0~CLK M-1 The setting of the time difference information of each pair of adjacent clock signals within one sampling period SP is only for illustration and is not limited thereto. In some embodiments, the skew adjustment circuit 130 can analyze the even-numbered clock signals CLK0, CLK2, ..., CLK respectively. M-2 The time difference information within two sampling periods SP and the odd-numbered clock signals CLK1, CLK3, ..., CLK M-1 The time difference information within two sampling periods (SP).

[0081] In some embodiments, the plurality of analog-to-digital conversion circuits 110 can adjust according to the plurality of adjustment signals T0 to T10. M-1 The timing of sampling operations and / or analog-to-digital conversion operations is adjusted to effectively correct clock skew. In other embodiments, multiple clock signals CLK0 to CLK... M-1 The timing can be directly determined based on multiple adjustment signals T0 to T1. M-1 Adjustments are made to effectively reduce clock skew. For example, multiple adjustment signals T0 to T... M-1 Input to generate multiple clock signals CLK0~CLK M-1 A clock generator, phase interpolator, or a digital delay control line can be used to adjust multiple clock signals CLK0 to CLK0.M-1 The phase. The above is based on the adjustment signals T0~T M-1 The method for reducing clock skew is for illustrative purposes only and is not intended to be limiting.

[0082] As described above, the output circuit 140 is electrically coupled to the correction circuit 120 to receive the corrected multiple quantized outputs CQ0 to CQ0. M-1 The output circuit 140 outputs CQ0 to CQ based on the corrected multiple quantizations. M-1 Perform a data combination operation to generate the digital signal SOUT. Through this data combination operation, multiple quantized outputs CQ0 to CQ from M channels can be converted into digital signals. M-1 The signal is combined into a single digital signal SOUT with a sampling frequency fs, where the sampling frequency fs is M times the clock signal frequency. In some embodiments, the output circuit 140 may be implemented by a multiplexer circuit, but this disclosure is not limited thereto.

[0083] Please see Figure 2 , Figure 2 This is a schematic diagram illustrating a skew adjustment circuit 130 according to some embodiments of the present invention. The skew adjustment circuit 130 includes an estimation circuit 131, an adjustment circuit 133, and a feedback circuit 135. The estimation circuit 131 performs statistical calculations to determine the corrected quantization outputs CQ0 to CQ. M-1 The corresponding multiple calculation signals (e.g., Figure 3 M0~M M-1 ), and average these calculated signals to generate a reference signal (e.g., for Figure 3 The estimation circuit 131 further compares the reference signal with multiple calculated signals to generate multiple detection signals SD0 to SD0. M-1 The adjustment circuit 133 is used to adjust the detection signals SD0 to SD1. M-1 The aforementioned multiple adjustment signals T0 to T1 are generated. M-1 The procedures described here will be explained in later paragraphs. Figure 3 Detailed explanation.

[0084] Please see Figure 3 , Figure 3 The illustration is based on some embodiments of this case. Figure 2 The circuit diagram of the skew adjustment circuit 130 is shown. The estimation circuit 131 includes a delay circuit 201, multiple first operation circuits 211, multiple absolute value circuits 221, multiple statistical circuits 231, an averaging circuit 241, a second operation circuit 251, and a comparison circuit 261.

[0085] As mentioned above, the delay circuit 201 is used to delay the quantization output CQ. M-1 To produce a delayed quantized output CQ -1In some embodiments, the delay time introduced by the delay circuit 201 is equivalent to... Figure 1B The sampling period SP is M times the current period. The delay circuit 201 can be implemented by various digital circuits, such as buffers, inverters, filters, etc. The above implementation of the delay circuit 201 is for illustrative purposes only, and this disclosure is not limited thereto.

[0086] Multiple first operational circuits 211 are electrically coupled to Figure 1A The correction circuit 120 is included. Multiple first operational circuits 211 sequentially receive the quantization output CQ. -1 ~CQ M-1 The two components are used to generate multiple difference signals D0 to D1 respectively. M-1 Taking the first operational circuit 211 as an example, the first operational circuit 211 receives the quantized output CQ. -1 The quantized output CQ is subtracted from the quantized output CQ by CQ0. -1 This generates a difference signal D0. The configuration and operation of the remaining first arithmetic circuits 211 can be deduced similarly, and therefore will not be repeated. In some embodiments, the first arithmetic circuit 211 may be implemented by a subtractor or other processing circuits with the same function. All circuits implementing the first arithmetic circuit 211 are within the scope of this disclosure.

[0087] Multiple absolute value circuits 221 are electrically coupled to multiple first operational circuits 211 to receive multiple difference signals D0 to D10 respectively. M-1 Each absolute value circuit 221 is based on multiple difference signals D0 to D1. M-1 An absolute value operation is performed on each corresponding difference signal to generate multiple absolute value signals A0 to A1. M-1 The first absolute value circuit 221 is an example. It receives the difference signal D0 and performs an absolute value operation to obtain the absolute value of the difference signal D0, thereby generating the absolute value signal A0. The configuration and operation of the remaining absolute value circuits 221 can be deduced similarly, and therefore will not be repeated. In some embodiments, the absolute value circuit 221 can be implemented by a processing circuit or a rectifier circuit; all circuits implementing the absolute value circuit 221 are within the scope of this disclosure.

[0088] As described above, the multiple statistical circuits 231 are respectively coupled to the multiple absolute value circuits 221 to receive the multiple absolute value signals A0 to A0 respectively. M-1 Each statistical circuit 231 is used to continuously receive multiple absolute value signals A0 to A1 within a predetermined period ST. M-1 One of the corresponding absolute value signals is used, and statistical operations are performed to output multiple calculated signals M0 to M1. M-1 One corresponding entity in the system.

[0089] In some embodiments, the aforementioned statistical operation may be a maximum value operation or an average operation. Taking the first statistical circuit 231 as an example, the first statistical circuit 231 continuously receives the absolute value signal A0 within a predetermined period ST, and performs a maximum value operation to output the largest absolute value signal A0 received within the predetermined period ST as the calculation signal M0. Alternatively, the first statistical circuit 231 continuously receives the absolute value signal A0 within the predetermined period ST, and performs an average operation to average all the absolute value signals A0 received within the predetermined period ST as the calculation signal M0. The configuration and operation of the remaining statistical circuits 231 can be deduced similarly, and therefore will not be repeated.

[0090] In some embodiments, the statistical circuit 231 may be implemented by a digital processing circuit, a comparator circuit, and / or a temporary register circuit, but this disclosure is not limited thereto. Various circuits that implement the statistical circuit 231 are within the scope of this application.

[0091] As described above, the averaging circuit 241 is electrically coupled to multiple statistical circuits 231 to receive multiple calculation signals M0 to M1. M-1 The averaging circuit 241 is used to calculate multiple signals M0 to M... M-1 Perform an averaging operation to average multiple calculated signals M0 to M... M-1 This generates the average signal AVG. In some embodiments, the averaging circuit 241 may be implemented by digital processing circuitry, but this disclosure is not limited thereto.

[0092] As described above, the second operational circuit 251 is electrically coupled to the averaging circuit 241 and the feedback circuit 135 to receive the average signal AVG and the feedback signal F. The second operational circuit 251 receives the average signal AVG and the feedback signal F to generate a reference signal REF. For example, the second operational circuit 251 receives the average signal AVG and the feedback signal F, and adds or subtracts the feedback signal F from the average signal AVG to generate the reference signal REF. In some embodiments, the second operational circuit 251 may be implemented by an adder, a subtractor, or other processing circuits with the same function. Various circuits implementing the first operational circuit 251 are within the scope of this disclosure.

[0093] Multiple comparator circuits 261 are coupled to the second operational circuit 251 to receive a reference signal REF. Each comparator circuit 261 is used to compare and calculate signals M0 to M... M-1 The corresponding signal in the signal is used in conjunction with the reference signal REF to generate detection signals SD0 to SD0. M-1This corresponds to one of the following. Taking the first comparison circuit 261 as an example, comparison circuit 261 compares the calculated signal M0 with the reference signal REF to generate the detection signal SD0. The configuration and operation of the remaining comparison circuits 261 can be deduced similarly, so they will not be repeated here. In some embodiments, comparison circuit 261 can be implemented by a comparator. In other embodiments, comparison circuit 261 can be implemented by a subtractor circuit, and the reference signal REF is subtracted from the corresponding calculated signal to generate the detection signal. The above-described implementation of comparison circuit 261 is for illustrative purposes only, and this disclosure is not limited thereto.

[0094] In some embodiments, multiple detection signals SD0 to SD M-1 It can be directly output as Figure 1A Multiple adjustment signals T0~T M-1 In some embodiments, multiple difference signals D0 to D... M-1 (or multiple detection signals SD0~SD) M-1 Associated with multiple channels (or multiple clock signals CLK0~CLK) M-1 The timing information of the clock skew in the circuit reflects the clock skew generated on the corresponding analog-to-digital converter circuit 110. Taking the operation of the second first operational circuit 211 as an example, such as... Figure 3 As shown, since the adjustment signal T1 is generated based on the difference between the quantization output CQ0 and the quantization output CQ1, the adjustment signal T1 can be used to indicate the time difference between the sampling time S1 corresponding to the quantization output CQ0 and the sampling time S2 corresponding to the quantization output CQ1.

[0095] By comparing the calculated signal M0 with the reference signal REF, it can be determined that clock skew affects the clock signal CLK. -0 The effect of the resulting time difference. For example, if the calculated signal M0 is greater than the reference signal REF, the effect of the time difference is positive. Under this condition, clock skew causes the clock signal CLK0 to have an incorrect phase lead. Or, if the calculated signal M0 is lower than the reference signal REF, the effect of the time difference is negative. Under this condition, clock skew causes the clock signal CLK0 to have an incorrect phase lead. -0 The phase is incorrectly lagging. Therefore, depending on the comparison results, the detection signal SD0 will have different logic values ​​to reflect the phase information that the first analog-to-digital converter 110 needs to adjust due to clock skew. Similarly, the above operations can be applied to each adjustment signal T0 to T1. M-1 and detection signals SD0 to SD M-1 Therefore, I will not repeat the details here.

[0096] In other embodiments, such as Figure 3As shown, the adjustment circuit 133 includes multiple filter circuits 213 and multiple integrator circuits 223. The multiple filter circuits 213 are respectively coupled to multiple comparator circuits 261 to receive multiple detection signals SD0 to SD0. M-1 .

[0097] As described above, multiple filter circuits 213 filter based on multiple detection signals SD0 to SD0. M-1 Multiple trigger signals TR10 to TR1 are generated with at least one threshold value TH1. M-1 Multiple integrating circuits 223 are respectively coupled to multiple filtering circuits 213 to receive multiple trigger signals TR10 to TR1. M-1 Multiple integrating circuits 223 respond to multiple trigger signals TR10~TR1 M-1 The aforementioned multiple adjustment signals T0 to T1 are generated. M-1 .

[0098] As described above, taking the first filter circuit 213 and the first integrator circuit 223 as examples, the filter circuit 213 is electrically coupled to the first operational circuit 261 to receive the detection signal SD0. In some embodiments, the filter circuit 213 can continuously accumulate the detection signal SD0 and compare the accumulated detection signal SD0 with at least one threshold value TH1 to output one or more trigger signals TR10. For example, when the accumulated detection signal SD0 is greater than at least one threshold value TH1, the filter circuit 213 outputs the accumulated detection signal SD0 as the corresponding trigger signal TR10. The first integrator circuit 223 is coupled to the first filter circuit 213 to receive the trigger signal TR10. The integrator circuit 223 is used to accumulate the trigger signal TR10 and outputs the accumulated trigger signal TR10 as an adjustment signal T0 to cooperate with different control timing methods. The configuration and operation of the remaining filter circuits 213 and integrator circuits 223 can be deduced by analogy, so they will not be repeated.

[0099] By setting up the filter circuit 213, the number of times the clock skew correction is performed can be reduced, thereby reducing the dynamic power consumption of the ADC device 100. Simultaneously, setting up the filter circuit 213 can also reduce jitter caused by clock skew correction. By setting up the integrator circuit 223, a corresponding value adjustment method can be implemented in conjunction with the timing adjustment method. In practical applications, the filter circuit 213 and the integrator circuit 223 can be selectively set according to actual needs. Furthermore, the aforementioned threshold value TH1 can also be adjusted according to actual requirements.

[0100] In different embodiments, the aforementioned filter circuit 213 and integrator circuit 223 may be implemented by at least one comparator (e.g., for comparing a trigger signal with a threshold value TH1 or comparing accumulated trigger signals), at least one register (e.g., for storing the aforementioned accumulated signal or accumulated trigger signal, etc.), at least one clear circuit (e.g., for clearing the data in the aforementioned register), and / or at least one arithmetic circuit (e.g., for generating an accumulated signal or for accumulating trigger signals). The above-described configuration of the filter circuit 213 and integrator circuit 223 is for illustrative purposes only, and this disclosure is not limited thereto.

[0101] As explained above, based on each calculation signal M0 to M M-1 The comparison with the reference signal REF reveals the phase information that each analog-to-digital converter 110 needs to adjust due to clock skew. However, if the reference signal REF generated by the estimation circuit 131 is inaccurate, the previously obtained phase information that each analog-to-digital converter 110 needs to adjust due to clock skew may also be inaccurate, causing the phase error between the multiple analog-to-digital converters 110 to converge incorrectly after adjustment by the skew adjustment circuit 130. Assuming the reference signal REF is inaccurate, such as... Figure 2 , Figure 3 As shown, this disclosure utilizes the feedback circuit 135 to analyze multiple signals generated by the adjustment circuit 133 (e.g., for example...). Figure 3 TR10~TR1 M-1 The estimation circuit 131 generates a feedback signal F to the estimation circuit 131. Based on this, the estimation circuit 131 can adjust the inaccurate reference signal REF according to the feedback signal F, making the reference signal REF approach accuracy. Therefore, based on the accurate reference signal REF, the estimation circuit 131 can generate multiple accurate detection signals SD0 to SD0. M-1 (equivalent to adjusting multiple detection signals SD0~SD) M-1 This allows for more accurate adjustment of the phase information required for each analog-to-digital converter circuit 110 to compensate for clock skew.

[0102] Please see Figure 4 , Figure 4 The illustration is based on some embodiments of this case. Figure 2 , Figure 3 A schematic diagram of the feedback circuit 135 is shown. The feedback circuit 135 includes a summing circuit 215, a filtering circuit 225, and an integrating circuit 235.

[0103] In some embodiments, the summing circuit 215 is electrically coupled to multiple filter circuits 213 to receive multiple trigger signals TR10 to TR1. M-1 The summing circuit 215 is used to sum multiple trigger signals TR10 to TR1. M-1Perform a summation operation to sum multiple trigger signals TR10 to TR1 M-1 This generates the summing signal STR1.

[0104] In some embodiments, the summing circuit 215 may be implemented by a digital processing circuit and / or an arithmetic circuit, but this disclosure is not limited thereto.

[0105] As described above, the filter circuit 225 is electrically coupled to the summing circuit 215 to receive the summed signal STR1. In some embodiments, the filter circuit 225 can continuously accumulate the summed signal STR1 and compare the accumulated summed signal STR1 with at least one threshold value (e.g., ). Figure 4 TH2 in + TH2 - The comparison operation is performed to output one or more trigger signals TR2. Depending on the result of the comparison operation, the trigger signal TR2 will have different logic values ​​(e.g., 1, 0, -1) to reflect whether the phase error between the multiple analog-to-digital converters 110 will converge correctly after adjustment by the skew adjustment circuit 130.

[0106] like Figure 4 As shown, in some embodiments, the filter circuit 225 compares the accumulated summed signal STR1 with a positive threshold value TH2. + And a negative critical value TH2 - Comparison operations are performed. For example, when the accumulated summed signal STR1 is greater than the positive threshold TH2... + When the phase error is adjusted by the skew adjustment circuit 130, the filter circuit 225 will output a corresponding trigger signal TR2 (e.g., 1) to reflect that the phase error may converge towards an upper limit of the circuit. When the accumulated summation signal STR1 is less than the negative threshold TH2... - When the phase error is adjusted by the skew adjustment circuit 130, the filter circuit 225 will output a corresponding trigger signal TR2 (e.g., -1) to reflect that the phase error may converge towards the lower limit of the circuit. When the accumulated summation signal STR1 is between the positive threshold TH2... + With the negative critical value TH2 - During this period, filter circuit 225 will output a corresponding trigger signal TR2 (e.g., 0) to reflect that the phase error may correctly converge to 0 after adjustment by skew adjustment circuit 130. In some embodiments, the implementation of filter circuit 225 is similar to that of filter circuit 213, and will not be described again here.

[0107] As described above, the integrator circuit 235 is electrically coupled to the filter circuit 225 to receive the trigger signal TR2. The integrator circuit 235 accumulates the trigger signal TR2 and outputs the accumulated trigger signal TR2 as a feedback signal F to be transmitted to... Figure 3The second operational circuit 251 is described above. As mentioned, the second operational circuit 251 can add or subtract the feedback signal F from the average signal AVG to adjust the reference signal REF. Accordingly, multiple comparison circuits 261 can calculate each of the calculated signals M0 to M... M-1 The signals are compared with the adjusted reference signal REF to generate the corresponding detection signals SD0 to SD0. M-1 The subsequent operations are similar to those described above and will not be repeated here. In this way, the phase error between the multiple analog-to-digital conversion circuits 110 can be adjusted by the skew adjustment circuit 130 to avoid incorrect convergence. In some embodiments, the implementation of the integrator circuit 235 is similar to that of the integrator circuit 223, and will not be repeated here.

[0108] Please see Figure 5 In another embodiment, the feedback circuit 135 further includes an amplifier circuit 245. The amplifier circuit 245 is electrically coupled between the filter circuit 225 and the integrator circuit 235 to amplify the trigger signal TR2 output by the filter circuit 225. Subsequent operations are similar to those described above; the integrator circuit 235 receives and accumulates the amplified trigger signal TR2 to output a feedback signal F. Subsequent operations are similar to those described above and will not be repeated here.

[0109] Please see Figure 6 , Figure 6 This is a flowchart illustrating a clock skew correction method 600 according to some embodiments of this case. For ease of understanding, the clock skew correction method 600 will be described with reference to the foregoing figures. In some embodiments, the clock skew correction method 600 may be... Figure 1A The ADC device 100 performs the operation. In one embodiment, the clock skew correction method 600 first performs step S610, by using the correction circuit 120 to perform the correction based on the multiple quantization outputs Q0 to Q10 generated by the multiple analog-to-digital converter circuits 110. M-1 Perform at least one correction operation to generate multiple quantized outputs CQ0 to CQ. M-1 .

[0110] The clock skew correction method 600 then executes step S620, analyzing multiple quantization outputs CQ0 to CQ0 through the estimation circuit 131. M-1 To generate a reference signal REF and multiple detection signals SD0 to SD0. M-1 .

[0111] Clock skew correction method 600 then executes step S630, adjusting circuit 133 according to multiple detection signals SD0 to SD0. M-1 Generate multiple adjustment signals T0~T M-1 .

[0112] Clock skew correction method 600 then executes step S640, analyzing multiple signals generated by adjustment circuit 133 (e.g., signals generated by feedback circuit 135) through feedback circuit 135. Figure 3 TR10~TR1 M-1 The estimation circuit 131 generates a feedback signal F based on the feedback signal F, thereby generating a reference signal REF. The descriptions and implementation methods of the foregoing steps can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0113] At Figures 2-6 In this embodiment, the feedback circuit 135 is used to analyze the multiple trigger signals TR10 to TR1 generated by the adjustment circuit 133. M-1 This generates a feedback signal F to the estimation circuit 131. However, this disclosure is not limited thereto. Please refer to... Figure 7 In another embodiment, the feedback circuit 135 can be used to analyze and estimate the multiple detection signals SD0 to SD0 generated by the estimation circuit 131. M-1 This generates a feedback signal F to the estimation circuit 131. That is, the summing circuit 215 is coupled to multiple comparison circuits 261 to receive multiple detection signals SD0 to SD0. M-1 The feedback circuit 135 detects signals SD0 to SD0. M-1 The operation of generating the feedback signal F is similar to that described above, so it will not be repeated here.

[0114] In summary, the ADC device 100 disclosed herein generates a feedback signal F by analyzing multiple signals generated by the skew adjustment circuit 130 through the design of the feedback circuit 135, in order to compensate for the reference signal REF used to correct the phase error between multiple analog-to-digital conversion circuits 110. In this way, the phase error between the multiple analog-to-digital conversion circuits 110 can be prevented from converging towards the upper or lower limit of the circuit.

[0115] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope defined in the appended claims.

Claims

1. An analog-to-digital converter device, characterized in that, Include: Multiple analog-to-digital conversion circuits are used to convert an input signal according to multiple clock signals to generate multiple first quantized outputs; A correction circuit for performing at least one correction operation based on the plurality of first quantization outputs to generate a plurality of second quantization outputs; and A skew adjustment circuit, comprising: An estimation circuit is configured to analyze the plurality of second quantization outputs through statistical operations and a first averaging operation to generate a reference signal, and to use the reference signal for comparison operations to generate a plurality of detection signals, wherein the plurality of detection signals are associated with a plurality of time difference information of the plurality of clock signals, and the skew adjustment circuit outputs the plurality of detection signals as a plurality of adjustment signals, the plurality of adjustment signals being used to reduce a clock skew of the plurality of analog-to-digital conversion circuits; as well as A feedback circuit is provided to analyze the plurality of detection signals generated by the estimation circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit uses the feedback signal to perform an addition operation to adjust the reference signal, uses the reference signal to perform the comparison operation to adjust the plurality of detection signals, and outputs the adjusted plurality of detection signals.

2. The analog-to-digital converter device according to claim 1, characterized in that, The estimation circuit includes: A delay circuit is used to delay the last of the plurality of second quantization outputs to produce a delayed quantization output; A plurality of first operational circuits are configured to receive the delayed quantization output and the plurality of second quantization outputs sequentially, and the plurality of first operational circuits are configured to generate a plurality of difference signals based on two signals in the delayed quantization output and the plurality of second quantization outputs respectively. Multiple absolute value circuits are used to output multiple absolute value signals, wherein each of the absolute value circuits is used to perform an absolute value operation based on a corresponding difference signal among the multiple difference signals to generate a corresponding absolute value signal among the multiple absolute value signals; Multiple statistical circuits, wherein the multiple statistical circuits are configured to receive the multiple absolute value signals within a predetermined period and perform the statistical operation to output multiple calculated signals, wherein the statistical operation includes a maximum value operation or a second average operation; An averaging circuit is used to perform the first averaging operation to average the plurality of calculated signals to generate an average signal; A second operational circuit is configured to perform the addition operation based on the average signal and the feedback signal to generate the reference signal; as well as Multiple comparison circuits are used to compare each of the calculated signals with the reference signal to generate the multiple detection signals.

3. The analog-to-digital converter device according to claim 1, characterized in that, The feedback circuit includes: A summing circuit is used to perform a summing operation to sum the plurality of detection signals to generate a summing signal; A filter circuit for generating a trigger signal based on the summed signal and at least one threshold value; as well as An integrating circuit is used to accumulate the trigger signal and output the accumulated trigger signal as the feedback signal.

4. The analog-to-digital converter device according to claim 3, characterized in that, The feedback circuit further includes an amplifier circuit coupled between the filter circuit and the integrator circuit, which is used to amplify the trigger signal.

5. The analog-to-digital converter device according to claim 3, characterized in that, The at least one threshold value includes a positive threshold value and a negative threshold value. The filter circuit compares the summed signal with the positive threshold value and the negative threshold value to generate the trigger signal.

6. An analog-to-digital converter device, characterized in that, Include: Multiple analog-to-digital conversion circuits are used to convert an input signal according to multiple clock signals to generate multiple first quantized outputs; A correction circuit for performing at least one correction operation based on the plurality of first quantization outputs to generate a plurality of second quantization outputs; and A skew adjustment circuit, comprising: An estimation circuit is configured to analyze the plurality of second quantization outputs through statistical operations and a first averaging operation to generate a reference signal, and to use the reference signal for comparison operations to generate a plurality of detection signals, wherein the plurality of detection signals are associated with a plurality of time difference information of the plurality of clock signals; An adjustment circuit is configured to generate multiple adjustment signals based on the multiple detection signals, wherein the multiple adjustment signals are configured to reduce a clock skew of the multiple analog-to-digital conversion circuits; as well as A feedback circuit is used to analyze a plurality of first trigger signals generated by the adjustment circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit uses the feedback signal to perform an addition operation to adjust the reference signal, uses the reference signal to perform the comparison operation to adjust the plurality of detection signals, and outputs the adjusted plurality of detection signals.

7. The analog-to-digital converter device according to claim 6, characterized in that, The estimation circuit includes: A delay circuit is used to delay the last of the plurality of second quantization outputs to produce a delayed quantization output; A plurality of first operational circuits are configured to receive the delayed quantization output and the plurality of second quantization outputs sequentially, and the plurality of first operational circuits are configured to generate a plurality of difference signals based on two signals in the delayed quantization output and the plurality of second quantization outputs respectively. Multiple absolute value circuits are used to output multiple absolute value signals, wherein each of the absolute value circuits is used to perform an absolute value operation based on a corresponding difference signal among the multiple difference signals to generate a corresponding absolute value signal among the multiple absolute value signals; Multiple statistical circuits, wherein the multiple statistical circuits are configured to receive the multiple absolute value signals within a predetermined period and perform the statistical operation to output multiple calculated signals, wherein the statistical operation includes a maximum value operation or a second average operation; An averaging circuit is used to perform the first averaging operation to average the plurality of calculated signals to generate an average signal; A second operational circuit is configured to perform the addition operation based on the average signal and the feedback signal to generate the reference signal; as well as Multiple comparison circuits are used to compare each of the calculated signals with the reference signal to generate the multiple detection signals.

8. The analog-to-digital converter device according to claim 6, characterized in that, The adjustment circuit includes: A plurality of first filter circuits are configured to generate the plurality of first trigger signals based on the plurality of detection signals and at least one first threshold value; as well as A plurality of first integrating circuits, wherein each of the plurality of integrating circuits is used to accumulate a corresponding first trigger signal among the plurality of first trigger signals, and output the accumulated corresponding first trigger signal as a corresponding adjustment signal among the plurality of adjustment signals.

9. The analog-to-digital converter device according to claim 8, characterized in that, The feedback circuit includes: A summing circuit is used to perform a summing operation to sum the plurality of first trigger signals to generate a summing signal; A second filter circuit is configured to generate a second trigger signal based on the summed signal and at least one second threshold value, wherein the at least one second threshold value includes a positive threshold value and a negative threshold value; and A second integrating circuit is used to accumulate the second trigger signal and output the accumulated second trigger signal as the feedback signal.

10. The analog-to-digital converter device according to claim 9, characterized in that, The feedback circuit further includes an amplifier circuit coupled between the second filter circuit and the second integrator circuit, and is used to amplify the second trigger signal.

11. A clock skew correction method, characterized in that, Include: At least one correction operation is performed based on multiple first quantization outputs generated by multiple analog-to-digital conversion circuits to generate multiple second quantization outputs; An estimation circuit of a skew adjustment circuit analyzes the plurality of second quantization outputs through statistical operations and a first averaging operation to generate a reference signal, and uses the reference signal for comparison operations to generate a plurality of detection signals, wherein the plurality of detection signals are associated with a plurality of time difference information of a plurality of clock signals received by a plurality of analog-to-digital conversion circuits, and the skew adjustment circuit outputs the plurality of detection signals as a plurality of adjustment signals to reduce the clock skew of the plurality of analog-to-digital conversion circuits; as well as The skew adjustment circuit analyzes the plurality of detection signals generated by the estimation circuit through a feedback circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit uses the feedback signal to perform an addition operation to adjust the reference signal, uses the reference signal to perform the comparison operation to adjust the plurality of detection signals, and outputs the adjusted plurality of detection signals.

12. The clock skew correction method according to claim 11, characterized in that, Generating the plurality of detection signals includes: Delay the last of the plurality of second quantization outputs to produce a delayed quantization output; The delayed quantization output and the plurality of second quantization outputs are received sequentially, and a plurality of difference signals are generated based on two signals from the delayed quantization output and the plurality of second quantization outputs, respectively. An absolute value operation is performed on a corresponding difference signal among the plurality of difference signals to generate a corresponding absolute value signal among the plurality of absolute value signals; The plurality of absolute value signals are received within a predetermined period, and the statistical operation is performed to output a plurality of calculated signals, wherein the statistical operation includes a maximum value operation or a second average operation; Perform the first averaging operation to average the plurality of calculated signals to generate an average signal; The addition operation is performed based on the average signal and the feedback signal to generate the reference signal; as well as Each of the calculated signals is compared with the reference signal to generate the plurality of detection signals.

13. The clock skew correction method according to claim 11, characterized in that, The generation of this feedback signal includes: Perform a summation operation to sum the multiple detection signals to generate a summed signal; A trigger signal is generated based on the summed signal and at least one threshold value; and The trigger signal is accumulated, and the accumulated trigger signal is output as the feedback signal.

14. The clock skew correction method according to claim 13, characterized in that, After the trigger signal is generated, the trigger signal is amplified.

15. The clock skew correction method according to claim 13, characterized in that, The at least one threshold value includes a positive threshold value and a negative threshold value, and generating the trigger signal includes: The summed signal is compared with the positive threshold and the negative threshold.

16. A clock skew correction method, characterized in that, Include: At least one correction operation is performed based on multiple first quantization outputs generated by multiple analog-to-digital conversion circuits to generate multiple second quantization outputs; An estimation circuit analyzes the plurality of second quantization outputs through statistical operations and a first averaging operation to generate a reference signal, and uses the reference signal for comparison operations to generate a plurality of detection signals, wherein the plurality of detection signals are associated with a plurality of time difference information of a plurality of clock signals received by the plurality of analog-to-digital conversion circuits. An adjustment circuit generates multiple adjustment signals based on the multiple detection signals, wherein the multiple adjustment signals are used to reduce a clock skew of the multiple analog-to-digital conversion circuits; as well as A feedback circuit analyzes multiple first trigger signals generated by the adjustment circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit uses the feedback signal to perform an addition operation to adjust the reference signal, uses the reference signal to perform the comparison operation to adjust the multiple detection signals, and outputs the adjusted multiple detection signals.

17. The clock skew correction method according to claim 16, characterized in that, Generating the plurality of detection signals includes: Delay the last of the plurality of second quantization outputs to produce a delayed quantization output; The delayed quantization output and the plurality of second quantization outputs are received sequentially, and a plurality of difference signals are generated based on two signals from the delayed quantization output and the plurality of second quantization outputs, respectively. An absolute value operation is performed on a corresponding difference signal among the plurality of difference signals to generate a corresponding absolute value signal among the plurality of absolute value signals; The plurality of absolute value signals are received within a predetermined period, and the statistical operation is performed to output a plurality of calculated signals, wherein the statistical operation includes a maximum value operation or a second average operation; Perform the first averaging operation to average the plurality of calculated signals to generate an average signal; The addition operation is performed based on the average signal and the feedback signal to generate the reference signal; as well as Each of the calculated signals is compared with the reference signal to generate the plurality of detection signals.

18. The clock skew correction method according to claim 16, characterized in that, Generating the plurality of adjustment signals includes: The plurality of first trigger signals are generated based on the plurality of detection signals and at least one first threshold; and Accumulate one corresponding first trigger signal from the plurality of first trigger signals, and output the accumulated corresponding first trigger signal as one corresponding adjustment signal from the plurality of adjustment signals.

19. The clock skew correction method according to claim 18, characterized in that, The generation of this feedback signal includes: Perform a summation operation to sum the plurality of first trigger signals to generate a summed signal; A second trigger signal is generated based on the summed signal and at least one second threshold value, wherein the at least one second threshold value includes a positive threshold value and a negative threshold value; and The second trigger signal is accumulated, and the accumulated second trigger signal is output as the feedback signal.

20. The clock skew correction method according to claim 19, characterized in that, After the second trigger signal is generated, the second trigger signal is amplified.

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