A digital-to-analog conversion circuit, a successive approximation type analog-to-digital conversion circuit

Abstract

This application relates to the field of electronic technology, and provides a digital-to-analog converter (DAC) circuit and a successive approximation DAC circuit. The DAC circuit includes a combined capacitor-type and resistor-type DAC structure. The capacitor-type DAC structure includes a capacitor array with n capacitors and a one-bit redundant capacitor. One end of each capacitor is connected to a common output terminal, and the other end is connected to the input signal via a first switch and to a first or second reference signal via a second switch. One end of the redundant capacitor is connected to the output terminal via the first switch, and the other end is connected to the first or second reference signal via the second switch. The weights among the n capacitors and the redundant capacitor are not powers of 2. The resistor-type DAC structure includes a 2-bit capacitor connected in series between the first and second reference signals. m Each resistor has a node between adjacent resistors and one end of a resistor connected to the second reference signal connected to one end of a third switch. The other end of each third switch is connected to a capacitor-type DAC structure.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a digital-to-analog converter circuit and a successive approximation analog-to-digital converter circuit. Background Technology

[0002] An ADC (Analog-to-Digital Converter) is a circuit that converts analog signals into digital signals. ADCs have a wide range of applications, including communication equipment, testing instruments, and audio equipment. With the development of integrated circuit technology, SAR ADCs (Successive-Approximation-Register ADCs) have gained increasing attention due to their low power consumption and less susceptibility to process technology limitations. Figure 1 This is a common system block for SARADC. Figure 1 For example, an 8-bit SAR ADC.

[0003] exist Figure 1 In the system block diagram shown, the part within the dashed box is the DAC (Digital-to-Analog Converter), whose function is to generate the signal used for sampling and the successive approximation signal DAC_OUT used for comparison during conversion. The specific waveforms in its circuit are shown below. Figure 2 As shown, the final conversion result can be obtained after 8 comparisons for different input signals.

[0004] This type of DAC uses an all-capacitor structure. Figure 1 An 8-bit ADC requires 2^8 unit capacitors, and the total number of capacitor units used increases exponentially with the number of bits in the ADC. Due to the limitations of matching characteristics in CMOS technology, there is a lower limit to the value of a unit capacitor. Therefore, this all-capacitor DAC structure will occupy a lot of capacitor units in SAR ADCs with a large number of bits, making the ADC area very large. Summary of the Invention

[0005] The purpose of this application is to provide a digital-to-analog converter circuit that reduces the mismatch requirements of capacitive DACs and can correct comparison errors in the capacitive DAC section, thereby reducing the capacitance value per unit capacitor.

[0006] Another objective of this application is to provide a successive approximation analog-to-digital converter circuit that can reduce the overall area and power consumption of the ADC, and whose calibration logic can convert the code system inside the DAC into a normal code system.

[0007] This application discloses a digital-to-analog converter circuit, including:

[0008] A capacitor-type DAC structure, wherein the capacitor-type DAC structure includes:

[0009] A capacitor array having n capacitors, one end of each capacitor being connected together as an output terminal, and the other end of each capacitor being connected to an input signal via a first switch and to a first reference signal or a second reference signal via a second switch.

[0010] A redundant capacitor is provided, one end of which is connected to the output terminal via a first switch, and the other end of which is connected to a first reference signal or a second reference signal via a second switch. The weight between the n-bit capacitor and the redundant capacitor is not a power of 2.

[0011] A resistive DAC structure includes 2m resistors connected in series between the first reference signal and the second reference signal. The nodes between adjacent resistors and one end of the resistor connected to the second reference signal are each connected to one end of a third switch. The other end of each third switch is connected to the capacitive DAC structure.

[0012] In a preferred embodiment, the capacitive DAC structure has a 5-bit capacitor, with weights of 1, 2, 3, 5, 8, and 12 for the 5-bit capacitor and the redundant capacitor, respectively, and the least significant bit pseudo capacitor is used as the reference.

[0013] In a preferred embodiment, the capacitive DAC structure has a 5-bit capacitor, with weights of 1, 2, 2, 5, 9, and 12 for the 5-bit capacitor and the redundant capacitor, respectively, and the least significant bit pseudo capacitor is used as the reference.

[0014] In a preferred embodiment, m equals 3, and the resistive DAC structure comprises eight resistors connected in series.

[0015] In a preferred embodiment, the capacitor-type DAC structure further includes:

[0016] A pseudo capacitor, one end of which is connected to the output terminal via a first switch, and the other end of which is connected to the second reference signal or the other end of each of the third switches in the resistive DAC structure via a second switch.

[0017] In a preferred embodiment, the first switch is controlled by a sampling clock signal, and the second switch is controlled by an inverted sampling clock signal.

[0018] In a preferred embodiment, the first reference signal is at a high level and the second reference signal is at a low level.

[0019] This application also discloses a successive approximation analog-to-digital converter circuit, including:

[0020] As described above, the digital-to-analog converter circuit;

[0021] An amplifier, wherein the first input terminal of the amplifier is connected to a first reference signal and a second reference signal respectively, and the second input terminal is connected to its output terminal;

[0022] A comparator, wherein the first input terminal of the comparator is connected to the output terminal of the amplifier, the second input terminal is connected to the output terminal of the digital-to-analog converter circuit, and a first switch is connected between the first input terminal and the second input terminal;

[0023] Successive approximation logic, which is connected to the output of the comparator and outputs an m+n bit digital signal to control the digital-to-analog converter circuit;

[0024] The digital error correction module is used to convert the m+n-bit digital signal into an m+n-1-bit digital signal.

[0025] In a preferred embodiment, the digital error correction module converts an n-bit digital signal into an n-1-bit digital signal.

[0026] In a preferred embodiment, the capacitive DAC structure has a 5-bit capacitor, and the weights between the 5-bit capacitor and the redundant capacitor are 1, 2, 3, 5, 8, and 12, respectively, with the least significant bit pseudo capacitor as the reference. The digital error correction module converts the 6-bit digital signal into a 5-bit digital signal according to the weights.

[0027] Compared with the prior art, this application has at least the following beneficial effects:

[0028] This invention integrates redundancy technology in the capacitive DAC section, which maintains the original input range of the SAR ADC while reducing the power consumption and area of ​​the DAC, making it more suitable for high-speed ADC applications.

[0029] This specification contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0030] Figure 1 A schematic diagram of a prior art all-capacitor SAR ADC is shown.

[0031] Figure 2 It shows Figure 1 The waveform diagram of the signal comparison.

[0032] Figure 3 A schematic diagram of another SAR ADC in the prior art is shown.

[0033] Figure 4 A schematic diagram of a digital-to-analog converter circuit in one embodiment of this application is shown.

[0034] Figure 5 A schematic diagram of a SAR ADC in one example of this application is shown. Detailed Implementation

[0035] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Those skilled in the art can employ a combined capacitor and resistor DAC structure (R+C structure) in high-bit SAR ADCs, as described in the reference. Figure 3As shown. This combination method can reduce the number of unit capacitors used. For example, in the same 8-bit SAR ADC, the capacitive (C) part uses 5 bits (MSB) and the resistive (R) part uses 3 bits (LSB). Therefore, the total number of capacitors used is 2^5 unit capacitors. However, this combination structure still has the following disadvantages:

[0037] Firstly, in high-speed and high-precision SAR ADCs, the establishment problem between the R and C parts will become apparent. Under certain power consumption, the capacitance value per unit capacitor will limit the performance of high-speed SAR ADCs.

[0038] Secondly, this type of DAC structure does not have an error correction mechanism. When an error occurs during comparison in the C part, subsequent comparisons cannot correct the error, resulting in a quantization error and causing a decrease in the performance of the SAR ADC.

[0039] Third, this combination structure has no tolerance for capacitor mismatch in the C section. Capacitor mismatch will cause the comparison signal generated by the DAC to deviate from the ideal value, resulting in deviation in the final output of the SAR ADC.

[0040] To address the aforementioned issues, this application proposes a novel DAC structure for use in SAR ADCs. Based on an R+C DAC structure, this structure incorporates redundancy techniques, reducing the capacitance mismatch requirements of the C-DAC section and correcting comparison errors in the C-DAC section, thus reducing the capacitance per unit capacitor.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] The first embodiment of this application discloses a digital-to-analog converter (DAC) 100. Figure 4 shows a schematic diagram of the DAC 100. The DAC includes a capacitor-type DAC structure (C-DAC) 10 and a resistor-type DAC structure (R-DAC) 20. The capacitor-type DAC structure includes a capacitor array 11 with n-bit capacitors, a one-bit redundant capacitor 12, and a one-bit dummy capacitor 13. Figure 4 The example uses n=5, but it should be understood that n can be any positive integer, such as 8, 12, etc. The resistor-type DAC structure 20 includes 2 resistors connected in series between the first reference signal VTOP and the second reference signal VBOT. mEach resistor, the node between adjacent resistors, and one end of the resistor connected to the second reference signal VBOT are each connected to one end of a third switch S0 to S7. The other end of each third switch S0 to S7 is connected to the capacitive DAC structure 10. Here, m is 3. The resistive DAC structure 20 includes 8 resistors R1 to R8. It should be understood that m can be any positive integer; for example, n can also be 8, 12, etc.

[0043] In this embodiment, the first reference signal VTOP is at a high level, and the second reference signal VBOT is at a low level.

[0044] In this embodiment, the DAC includes a capacitive DAC structure 10 as the MSB portion and a resistive DAC structure 20 as the LSB portion.

[0045] The capacitor array 11 has n capacitors. One end of each capacitor is connected to the common output terminal DAC_OUT, and the other end of each capacitor is connected to the input signal VAIN through a first switch S and to the first reference signal VTOP or the second reference signal VBOT through a second switch S'. One end of the redundant capacitor 12 is connected to the output terminal DAC_OUT through the first switch S, and the other end is connected to the first reference signal VTOP or the second reference signal VBOT through the second switch S'. In this embodiment, the first switch S is controlled by the sampling clock signal sampclk, and the second switch S' is controlled by the sampling clock signal sampclkb. The sampling clock signals sampclk and sampclkb are a pair of inverted clock signals.

[0046] In one embodiment, the capacitive DAC structure 10 further includes a pseudo capacitor 13, one end of which is connected to the output terminal DAC_OUT via a first switch S, and the other end of which is connected to the second reference signal VBOT or the other end of each of the third switches in the resistive DAC structure 20 via a second switch S'.

[0047] The weights between the n-bit capacitor and the redundant capacitor 12 are not powers of 2. In one embodiment, the capacitor-type DAC structure 10 has 5-bit capacitors, and the weights between the 5-bit capacitors and the redundant capacitors are 1, 2, 3, 5, 8, and 12, respectively. That is, taking the least significant pseudo-capacitor as a reference and its capacitance as C, the capacitance values ​​of the 5-bit capacitors and the redundant capacitor 12 in the capacitor array 11 are 1C, 2C, 3C, 5C, 8C, and 12C, respectively.

[0048] In other embodiments of this application, the capacitive DAC structure 10 has a 5-bit capacitor, and the weights between the 5-bit capacitor and the redundant capacitor are 1, 2, 2, 5, 9, and 12, respectively. That is, taking the least significant pseudo-capacitor as a reference and taking its capacitance as C, the capacitance values ​​of the 5-bit capacitor and the redundant capacitor 12 in the capacitor array 11 are 1C, 2C, 2C, 5C, 9C, and 12C, respectively.

[0049] The second embodiment of this application discloses a successive approximation analog-to-digital converter (SAR ADC) 200. Figure 5 A schematic diagram of a successive approximation analog-to-digital converter circuit 200 is shown, which includes a digital-to-analog converter circuit 100 as described above, an amplifier 30, a comparator 40, successive approximation logic 50, and a digital error correction module 60.

[0050] The amplifier 30 has its first input terminal connected to a first reference signal VTOP and a second reference signal VBOT, and its second input terminal connected to its output terminal. In this embodiment, the first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal.

[0051] The first input terminal of the comparator 40 is connected to the output terminal of the amplifier 30, and the second input terminal is connected to the output terminal DAC_OUT of the digital-to-analog converter circuit 100. In this embodiment, the first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal. A first switch S is connected between the first and second input terminals of the comparator 40, wherein the first switch S is controlled by the sampling clock signal sampleclk.

[0052] The successive approximation logic 50 is connected to the output of the comparator 40 and outputs an m+n-bit digital signal to control the digital-to-analog converter 100. The digital error correction module 60 is used to convert the m+n-bit digital signal into m+n-1-bit digital signals XD0 to XD7. Specifically, digital signals S0 to S7 control the eight third switches S0 to S7 of the resistive DAC structure; digital signals B3 to B7 connect the capacitors of the capacitor array in the capacitive DAC structure to the first reference signal VTOP or the second reference signal VBOT; and digital signal B8 connects the redundant capacitors of the capacitive DAC structure to the first reference signal VTOP or the second reference signal VBOT.

[0053] In one embodiment, the digital error correction module 60 is only used to convert the digital signal of a capacitive DAC structure, without converting the digital signal of a resistive DAC structure. Specifically, it converts the n-bit digital signal of the capacitive DAC structure to an n-1-bit digital signal. The capacitive DAC structure has a 5-bit capacitor, and the weights between the 5-bit capacitor and the redundant capacitor are 1, 2, 3, 5, 8, and 12, respectively. The digital error correction module converts the 6-bit digital signal to a 5-bit digital signal according to these weights.

[0054] To better understand the technical solution in this specification, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0055] refer to Figure 4 and Figure 5 As shown in the diagram, this structure, based on the R+C DAC structure, applies redundancy technology to the C-DAC section. In this ADC, the C-DAC section is rearranged, changing the weights of each bit and altering the ratio between bits, which is no longer 2. This reduces the capacitance mismatch requirement of the C-DAC section and corrects comparison errors, thus reducing the capacitance per unit capacitor.

[0056] by Figure 5 Taking an 8-bit SAR ADC as an example, a redundant bit B8 is added to the C-DAC section, with each bit using a weight of [1 2 3 5 8 12]. Because a redundant bit is added to this C-DAC section, the 9-bit data of the SAR logic needs to be converted back to the original 8-bit data. The DEC module can convert the conversion control bits S0~S7 and B3~B8 used in the R-DAC and C-DAC to the normally used XD0~XD7, resulting in a total of 8 bits of output. The conversion principle can be obtained through the following formula:

[0057] B3·1+B4·2+B5·3+B6·5+B7·8+B8·12

[0058] =B3·1+B4·2+B5·(1+2)+B6·(1+4)+B7·8+B8·(4+8)

[0059] =(B3+B5+B6)·1+(B4+B5)·2+(B6+B8)·4+(B7+B8)·8

[0060] =D3·1+D4·2+D5·4+D6·8+D7·16

[0061] Among them, B3 to B8 can be converted into number systems through full addition with carry.

[0062] Incorporating redundancy techniques into a C-DAC offers the following advantages:

[0063] Firstly, it can maintain the original input range of the SAR ADC unchanged. Figure 5 Taking an 8-bit SAR ADC as an example, the total weight sum is still 2^5, meaning the total number of unit capacitors used remains unchanged, and all capacitors participate in sampling, so the original input range can be maintained.

[0064] Secondly, it can correct comparison errors at higher levels. Figure 5 Taking an 8-bit SAR ADC as an example, the weights used are [1 23 5 8 12]. The redundancy space for each bit is [0 0 1 2 4 8]. The redundancy space for each bit is calculated as follows: the sum of the weights of the preceding bits minus the weight of the current bit, plus 1. For example, the redundancy space for a capacitor with a weight of 8 is (1+2+3+5)-8+1, which is 4. Therefore, comparison errors in higher bits can be corrected in lower bits.

[0065] Third, redundancy provides some tolerance for capacitor mismatch, allowing for a reduction in the unit capacitor used. When capacitor mismatch exists, the generated DAC_OUT will deviate, which can be equivalent to an error in the high-order comparison. Therefore, capacitor mismatch can be corrected. Because the requirement for capacitor mismatch is reduced, a smaller unit capacitor can be used.

[0066] Fourth, it can improve the settling problem of the DAC section. Because the unit capacitor used is smaller, the settling time constant is smaller under the same power consumption, so the signal changes to the theoretical value more quickly, that is, the settling time is shorter. Therefore, it is suitable for higher speed applications.

[0067] Furthermore, in this application, the capacitor-type DAC structure with weights of [1 2 3 5 8 12] is superior to the capacitor-type DAC structure with weights of [1 2 25 912] because the capacitor-type DAC structure with weights of [1 2 3 5 8 12] has a larger total redundancy space.

[0068] It should be noted that in this patent application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. In this patent application, if it refers to performing an action according to a certain element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0069] All references to this specification are considered to be incorporated integrally into the disclosure herein so that they can serve as a basis for modifications where necessary. Furthermore, it should be understood that the above are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A digital-to-analog converter circuit, characterized in that, include: A capacitor-type DAC structure, wherein the capacitor-type DAC structure includes: A capacitor array having n capacitors, one end of each capacitor being connected together as an output terminal, and the other end of each capacitor being connected to an input signal via a first switch and to a first reference signal or a second reference signal via a second switch. A redundant capacitor is provided, one end of which is connected to the output terminal via a first switch, and the other end is connected to a first reference signal or a second reference signal via a second switch. The weight between the n-bit capacitor and the redundant capacitor is not a power of 2. The capacitor-type DAC structure has a 5-bit capacitor, and the weights between the 5-bit capacitor and the redundant capacitor are 1, 2, 3, 5, 8, 12 or 1, 2, 2, 5, 9, 12, with the least significant pseudo-capacitor as the reference. A resistive DAC structure, wherein the resistive DAC structure includes two resistors connected in series between the first reference signal and the second reference signal. m Each resistor has a node between adjacent resistors and one end of a resistor connected to the second reference signal connected to one end of a third switch, and the other end of each third switch is connected to the capacitor-type DAC structure.

2. The digital-to-analog converter circuit according to claim 1, characterized in that, The value of m is 3, and the resistive DAC structure includes 8 resistors connected in series.

3. The digital-to-analog converter circuit according to claim 1, characterized in that, The capacitive DAC structure also includes: A pseudo capacitor, one end of which is connected to the output terminal via a first switch, and the other end of which is connected to the second reference signal or the other end of each of the third switches in the resistive DAC structure via a second switch.

4. The digital-to-analog converter circuit according to claim 1, characterized in that, The first switch is controlled by a sampling clock signal, and the second switch is controlled by an inverted sampling clock signal.

5. The digital-to-analog converter circuit according to claim 1, characterized in that, The first reference signal is at a high level, and the second reference signal is at a low level.

6. A successive approximation analog-to-digital converter circuit, characterized in that, include: A digital-to-analog converter (DAC) circuit includes a capacitor-type DAC structure and a resistive DAC structure. The capacitor-type DAC structure includes: a capacitor array having n capacitors, one end of each capacitor being connected to a common output terminal, and the other end of each capacitor being connected to an input signal via a first switch and to a first reference signal or a second reference signal via a second switch; a single redundant capacitor, one end of which is connected to the output terminal via a first switch, and the other end of which is connected to the first reference signal or the second reference signal via a second switch. The weights among the n capacitors and the redundant capacitor are not powers of 2. The resistive DAC structure includes a 2-bit resistor connected in series between the first reference signal and the second reference signal. m Each resistor, the node between adjacent resistors and one end of the resistor connected to the second reference signal are each connected to one end of a third switch, and the other end of each third switch is connected to the capacitor-type DAC structure; An amplifier, wherein the first input terminal of the amplifier is connected to a first reference signal and a second reference signal respectively, and the second input terminal is connected to its output terminal; A comparator, wherein the first input terminal of the comparator is connected to the output terminal of the amplifier, the second input terminal is connected to the output terminal of the digital-to-analog converter circuit, and a first switch is connected between the first input terminal and the second input terminal; Successive approximation logic, which is connected to the output of the comparator and outputs an m+n bit digital signal to control the digital-to-analog converter circuit; The digital error correction module is used to convert the m+n-bit digital signal into an m+n-1-bit digital signal.

7. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The digital error correction module converts an n-bit digital signal into an n-1-bit digital signal.

8. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The capacitor-type DAC structure has a 5-bit capacitor, and the weights between the 5-bit capacitor and the redundant capacitor are 1, 2, 3, 5, 8, and 12, respectively. The least significant bit pseudo capacitor is used as the reference. The digital error correction module converts the 6-bit digital signal into a 5-bit digital signal according to the weights.

9. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The capacitor-type DAC structure has a 5-bit capacitor, and the weights between the 5-bit capacitor and the redundant capacitor are 1, 2, 2, 5, 9, 12 respectively. The least significant bit pseudo capacitor is used as the reference. The digital error correction module converts the 6-bit digital signal into a 5-bit digital signal according to the weights.

10. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The capacitive DAC structure also includes: A pseudo capacitor, one end of which is connected to the output terminal via a first switch, and the other end of which is connected to the second reference signal or the other end of each of the third switches in the resistive DAC structure via a second switch.

11. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The first switch is controlled by a sampling clock signal, and the second switch is controlled by an inverted sampling clock signal.

12. The successive approximation analog-to-digital converter circuit according to claim 6, characterized in that, The first reference signal is at a high level, and the second reference signal is at a low level.

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