A method, system, storage medium, and device for evaluation based on data sorting.

Abstract

This invention provides a data sorting-based evaluation method, system, storage medium, and device. The method includes: responding to obtaining the nth data after sorting from m data, determining the operation mode of the operation implementation circuit based on the relationship between m and n. The operation implementation circuit includes n cascaded comparators and a controller. Each comparator includes a first input terminal, a second input terminal, and a data output terminal. The data to be compared is input to the second input terminal of the current comparator according to a clock delay, and compared with the temporary data stored at its first input terminal. Based on the comparison result, the data that conforms to the operation mode is temporarily stored at the first input terminal of the current comparator, and another data is output from its data output terminal to the second input terminal of the next-level comparator. Based on the m data, the timing for the controller to acquire the output data of the last comparator is determined, and the acquired output data is used as the nth data. This invention has the advantages of high-speed evaluation and reduced hardware circuit area.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a method, system, storage medium, and device for evaluating data based on sorting. Background Technology

[0002] Algorithms often require sorting data and then selecting one or more data points that meet the order requirements for output. For example, Wiener filtering based on infrared images can effectively remove noise from images, restoring them to a clearer state. The Wiener filtering operation is typically optimized using methods such as FFT (Fast Fourier Transform) or covariance matrix analysis to reduce computational complexity or improve denoising effectiveness to varying degrees.

[0003] Wiener filtering was originally implemented through software computation. However, with the expansion of application scenarios, technological advancements, and changing demands, there is now an increasing need for hardware implementations of Wiener filtering with varying precision and speed requirements. In the hardware module of the Wiener filtering algorithm, most operations are standard multiplication and addition. These can be achieved by utilizing a multiply-add module, dividing the computation into parallel operations based on the corresponding frame rate requirements, and then pipelined to connect the entire operation. However, besides multiply-add operations, there are some operations that are difficult to implement through circuits, such as calculating the median, which is a sorting and evaluation operation.

[0004] Such functionality is simple to implement in algorithms, but often more complex to implement in circuits. Summary of the Invention

[0005] In view of this, the purpose of this invention is to propose a data sorting-based evaluation method, system, storage medium, and device, which can achieve the goal of evaluating only a single value in the sorting operation through circuitry, without requiring the sorting and output of all the data.

[0006] To achieve the above objectives, this invention provides a method for evaluating data based on sorting, comprising the following steps:

[0007] In response to obtaining the sorted nth data from m data, the operation mode of the operation implementation circuit is determined based on the relationship between m and n. The operation implementation circuit includes n cascaded comparators and a controller connected to each comparator. Each comparator includes a first input terminal, a second input terminal, and a data output terminal.

[0008] The data to be compared is input to the second input of this stage comparator according to the clock delay number, and compared with the temporary data at its first input to obtain the comparison result;

[0009] Based on the comparison result, the data that meets the operation method is temporarily stored in the first input of the current comparator, and the other data is output from its data output to the second input of the next comparator.

[0010] Based on m data points, the timing for the controller to acquire the output data of the last stage comparator is determined, and the acquired output data is used as the nth data point.

[0011] In some embodiments, the operation methods include sorting operations based on smaller values ​​and sorting operations based on larger values.

[0012] In some embodiments, temporarily storing data that conforms to the operation method to the first input of the current comparator based on the comparison result, and outputting another data from its data output to the second input of the next-level comparator includes:

[0013] In response to a sorting operation based on the smallest value, the data with smaller values ​​is temporarily stored at the first input of the current comparator according to the comparison result, and the data with larger values ​​is output from the data output of the current comparator to the second input of the next comparator.

[0014] In response to the sorting operation based on the largest value, the data with the larger value is temporarily stored at the first input of the current comparator according to the comparison result, and the data with the smaller value is output from the data output of the current comparator to the second input of the next comparator.

[0015] In some embodiments, determining the operation mode of the operation implementation circuit based on the relationship between m and n includes:

[0016] Compare the sizes of n and m / 2;

[0017] If n≤m / 2, the operation method is a sorting operation based on the smallest value;

[0018] If n > m / 2, the operation method is a sorting operation based on the largest value.

[0019] In some embodiments, the method further includes:

[0020] The corresponding reset value is determined based on the calculation method.

[0021] In some embodiments, determining the timing for the controller to acquire the output data of the last-stage comparator based on m data points includes:

[0022] In response to the requirement of retrieving the nth sorted data from the first m data at any given time, the controller obtains the output data of the last-stage comparator based on the time when the value needs to be retrieved.

[0023] In some embodiments, determining the timing for the controller to acquire the output data of the last-stage comparator based on m data points further includes:

[0024] In response to obtaining the nth sorted data from every m data, the circuit operates for m+n-1 cycles, and the controller obtains the output data of the last comparator. After each acquisition, the circuit is reset.

[0025] Another aspect of the present invention provides an evaluation system based on data sorting, comprising:

[0026] The circuit module is configured to respond to obtaining the sorted nth data from m data, and to determine the operation mode of the operation implementation circuit based on the relationship between m and n. The operation implementation circuit includes n cascaded comparators and a controller connected to each comparator. Each comparator includes a first input terminal, a second input terminal, and a data output terminal.

[0027] The comparison module is configured to input the data to be compared to the second input terminal of the comparator at this stage according to the clock delay number, and compare it with the temporary data stored at its first input terminal to obtain the comparison result;

[0028] The result processing module is configured to temporarily store data that conforms to the calculation method into the first input of the current comparator based on the comparison result, and output another data from its data output to the second input of the next-level comparator; and

[0029] The acquisition module is configured to determine when the controller acquires the output data of the last stage comparator based on m data points, and to use the acquired output data as the nth data point.

[0030] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method.

[0031] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs the above-described method.

[0032] The present invention has at least the following beneficial technical effects:

[0033] The data sorting-based evaluation method of this invention uses a pipelined ranking and evaluation circuit as the computation implementation circuit. Data is input once per cycle or multiple working cycles, and comparison and ranking are performed in cascaded comparators using a pipelined approach. Finally, a data that meets the sorting and evaluation criteria is output, thereby reducing redundant comparison work, minimizing the area loss of the ranking and evaluation circuit based on output requirements, and controlling the data flow in a pipelined manner to achieve the fastest speed while conforming to the input relationship. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a data sorting-based evaluation method provided according to an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the operation implementation circuit provided by an embodiment of the present invention when m=8 and n=4.

[0037] Figure 3 This is a schematic diagram of the pipeline data format provided by an embodiment of the present invention when n=4;

[0038] Figure 4 This is a schematic diagram of a data sorting-based evaluation system provided according to an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of a computer-readable storage medium for implementing a data sorting-based evaluation method according to an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the hardware structure of a computer device for executing a data sorting-based evaluation method according to an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0042] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0043] To achieve the above objectives, a first aspect of the present invention provides an embodiment of a data sorting-based evaluation method. Figure 1The diagram shown is a schematic representation of an embodiment of the data sorting-based evaluation method provided by the present invention. For example... Figure 1 As shown, the embodiments of the present invention include the following steps:

[0044] Step S10: In response to obtaining the sorted nth data from m data, the operation mode of the operation implementation circuit is determined based on the relationship between m and n. The operation implementation circuit includes n cascaded comparators and controllers connected to each comparator. Each comparator includes a first input terminal, a second input terminal, and a data output terminal.

[0045] Step S20: Input the data to be compared to the second input terminal of the comparator at this stage according to the clock delay number, and compare it with the temporary data stored at its first input terminal to obtain the comparison result;

[0046] Step S30: Based on the comparison result, temporarily store the data that meets the operation method to the first input terminal of the current comparator, and output the other data from its data output terminal to the second input terminal of the next level comparator;

[0047] Step S40: Determine the timing for the controller to acquire the output data of the last stage comparator based on m data, and use the acquired output data as the nth data.

[0048] In this embodiment of the invention, m ≥ n > 1.

[0049] Sorting is a common operation in algorithms. It involves comparing and sorting finite or continuously changing data values ​​according to ascending or descending order, ultimately outputting values ​​that conform to the sorted order. Common sorting outputs include finding the maximum, minimum, or median value.

[0050] A common method for sorting in circuits is to prepare all inputs and then use polling or binary tree comparison to obtain the desired sorted value. This process requires first combining all input data and inputting it into the corresponding ports, then using a relatively large circuit for traversal and comparison, and finally outputting the complete sorted result.

[0051] However, the scenario differs in operations such as Wiener filtering. First, Wiener filtering operates on a pixel-by-pixel basis, so the data for the ratio is generated one by one. Using traditional sorting circuits, waiting for all the data to be processed and input to the corresponding ports would waste a significant amount of time. Second, Wiener filtering only needs the median value; it doesn't care about the other sorted values. This eliminates the need to sort all the data before outputting it.

[0052] Therefore, the data sorting-based evaluation method of this invention uses a pipelined ranking evaluation circuit as the computation implementation circuit. Data is input once per cycle or multiple working cycles. The data is compared and ranked in a pipelined manner in cascaded comparators, and finally outputs data that meets the sorting evaluation criteria. This reduces redundant comparison work, minimizes the area loss of the sorting evaluation circuit based on output requirements, and controls the data flow in a pipelined manner to achieve the fastest speed while meeting the input relationship.

[0053] In some embodiments, the operation methods include sorting operations based on smaller values ​​and sorting operations based on larger values.

[0054] In some embodiments, temporarily storing data that conforms to the operation method to the first input of the current level comparator according to the comparison result, and outputting another data from its data output to the second input of the next level comparator includes: in response to the operation method being a sorting operation based on smaller values, temporarily storing the data with smaller values ​​to the first input of the current level comparator according to the comparison result, and outputting the data with larger values ​​from the data output of the current level comparator to the second input of the next level comparator; in response to the operation method being a sorting operation based on larger values, temporarily storing the data with larger values ​​to the first input of the current level comparator according to the comparison result, and outputting the data with smaller values ​​from the data output of the current level comparator to the second input of the next level comparator.

[0055] In some embodiments, determining the operation mode of the operation implementation circuit based on the relationship between m and n includes: comparing the size of n and m / 2; if n≤m / 2, the operation mode is a sorting operation based on the smaller value; if n>m / 2, the operation mode is a sorting operation based on the larger value.

[0056] In some embodiments, the method further includes: determining the corresponding reset value based on the calculation method.

[0057] In some embodiments, determining the timing for the controller to acquire the output data of the last-stage comparator based on m data includes: in response to retrieving the nth sorted data from the first m data at any given time, the controller acquires the output data of the last-stage comparator based on the time when the value needs to be retrieved.

[0058] In some embodiments, determining the timing for the controller to acquire the output data of the last stage comparator based on m data further includes: in response to obtaining the sorted nth data from each of the m data, the controller acquires the output data of the last stage comparator after the operation of the calculation circuit for m+n-1 cycles, and resets the calculation circuit after each acquisition.

[0059] An exemplary embodiment of the evaluation method based on data sorting of the present invention is as follows:

[0060] This embodiment proposes a pipelined ranking evaluation circuit as the computation implementation circuit. This circuit can be applied to perform pipelined comparison and evaluation on input data to obtain any similar data value that meets the sorting output requirements.

[0061] The circuit implementation process is as follows:

[0062] 1. First, determine the position of the value to be calculated, thereby determining whether the operation implementation circuit is based on large value comparison or small value comparison.

[0063] Assuming the comparison algorithm requires the value of the nth data out of m data points, then:

[0064]

[0065] As shown in formula (1), the circuit is first determined based on the relationship between m and n, whether it is based on the operation method of small value or the operation method of large value.

[0066] For example, if m=8 and n=4, it means that we need to find the fourth data (median value) in the order of size from smallest to largest among every 8 data. Based on the formula (1), we select the smaller value.

[0067] 2. Implement the circuit

[0068] As mentioned above, when the judgment is based on the smaller value, n comparators and corresponding temporary storage are set up. Assuming n=4, the implemented circuit is as follows: Figure 2 As shown. Figure 2 This is a schematic diagram of the circuit structure for implementing computation when m=8 and n=4, according to an embodiment of the present invention.

[0069] like Figure 2 The circuit shown implements the above operations mainly based on Comp modules (i.e. comparators). Each Comp module has two inputs. After comparison, the data result is temporarily stored and sent back to input port A of the Comp module, or passed through to input port B of the next Comp module.

[0070] Figure 2 The relationship in is:

[0071] a. Comp module 1: Comp module 1 has two input ports, A and B. Port B is used to input the data to be compared according to the number of beats, and port A is connected to the temporary storage module attached to this level of Comp module.

[0072] The data is controlled by the control module (i.e., the controller), which activates the control every time (clock delay) to compare the data between port A and port B.

[0073] Since m = 8 and n = 4, the comparison is based on the smaller value. Therefore, when A ≤ B, C = A and D = B; otherwise, C = B and D = A.

[0074] b.Comp modules 2 and 3: The working mode is similar to Comp1. They are controlled by the control module and triggered by clock delay. Input from the upper level is given to port B through the connection relationship. Port A obtains the data buffered locally. After each clock delay, the data is compared. The comparison relationship and the operation performed are in accordance with the operation description in a.

[0075] After each comparison, the smaller value is updated in the cache of the current Comp level, and the other value is transmitted to the next level through the D port.

[0076] The Comp2 and 3 parts can be interconnected in multiple levels based on the relationship between m and n. For example, when m = 10 and n = 5, according to the above description, a total of 5 Comps are needed. Then, disregarding Comp1 and 5 as the head and tail Comps respectively, the Comps in the middle are Comp2, 3, and 4.

[0077] c. Tail Comp: Tail Comp controls the actual output of the sorting evaluation. Taking the above case as an example, in order to take the median value, when m=8 and n=4, the sorting is based on the smaller value, then the tail Comp in this case is Comp4.

[0078] At this point, the input from the upper level enters port B, while the data buffered at this level is on port A. The buffer is updated after comparison. Because there are no lower-level connections at this time, there is no output to the lower-level port. The data buffer is temporarily stored in the tail Comp. When the median value at this time needs to be retrieved, the control module retrieves the data from the tail Comp and outputs it.

[0079] The control module needs to select the appropriate time to retrieve the median value of all the inputs being compared. Taking the example of m=8 and n=4 above, after comparing 8 data points, since the data is input in steps according to the number of steps, it takes 8 steps for the data to be completely input. An additional n-1=3 steps are needed for the last Comp data to be the median data among the first 8 data points. At this time, the control module can output the data.

[0080] In the circuit described above, a reset value needs to be set at the start of each round of operation. When comparing the smaller value, the reset value is set to "1" of the full width of the buffer. For example, if the data is all 8 bits, the reset value is set to 255 in decimal.

[0081] If the circuit operates based on the median value of the first m data at any given time, the controller can continuously output the buffered data of the tail Comp based on the time when the value needs to be taken.

[0082] If the circuit operates based on the median value of every m data points, the controller circuit will perform a reset after each value acquisition operation. After working for m+n-1 cycles, the value of the last value, Comp, will be output, which is the median value of every m data points.

[0083] If the judgment in formula (1) of the above circuit is implemented based on the large value, then the circuit structure and Figure 2 Same. But the specific module functions need to be changed:

[0084] Comp1: Port B is the input, and port A is linked to the buffer of this level Comp. The control module controls the operation based on the clock delay and activates the comparison. When B≤A, C=A,D=B; otherwise, C=B,D=A.

[0085] Comp2,3: Similar to the linking and comparison relationships in Comp1.

[0086] The tail Comp is Comp4: The same link relationship as above, the comparison method is the same, the cache is updated, and it no longer penetrates. The control module takes the median of m+n-1 data after the work is completed by one reset, or takes the median of any m data.

[0087] At this point, the value of reset is 0.

[0088] As shown above, the circuit in this embodiment has a data input port and a data output port. The core operation module is the Comp module. Data passes through each Comp level to achieve sequential comparison, thereby obtaining the sorting and evaluation of the nth data that conforms to m data.

[0089] This circuit operates via pipeline, with one data input per cycle, while other components perform their respective comparisons. The specific pipeline data structure is as follows: Figure 3 As shown. Figure 3 This is a schematic diagram of the pipeline data format provided by an embodiment of the present invention when n=4.

[0090] like Figure 3 As can be seen, in this pipeline format, each Comp works simultaneously, with one data input per cycle. The first m+n-1 cycles will complete the comparison of m data, thereby outputting the desired sorted value.

[0091] This embodiment presents a circuit implementation based on ranking and evaluation requirements. The circuit employs a pipelined design, with the basic module being the Comp module. The circuit first determines the number of units that Comp needs to connect, the connection relationships, the working order, and the comparison algorithm by judging the working scenario and requirements. Then, through interconnection, and using a control module based on clock delay control, ranking and evaluation circuits with different requirements can be implemented. The pipelined operation makes it suitable for dynamic ranking of multiple numerical ratios, as well as static ranking and evaluation of fixed numbers. The pipelined implementation effectively utilizes the sequential input of data, ensuring each Comp module completes its work. The Comp module allows for efficient combination of circuits to meet different requirements, achieving operation with a relatively small footprint. Therefore, it offers advantages in high speed and low area, and is suitable for streaming data input and dynamic / static ratio operations. This ranking and evaluation circuit can be used to calculate different order values ​​under any requirement.

[0092] A second aspect of this invention also provides a data sorting-based evaluation system. Figure 4 The diagram shown is a schematic representation of an embodiment of the data sorting-based evaluation system provided by the present invention. For example... Figure 4 As shown, a data sorting-based evaluation system includes: a circuit module 10 configured to determine the operation mode of the operation implementation circuit based on the relationship between m and n in response to obtaining the nth sorted data from m data, wherein the operation implementation circuit includes n cascaded comparators and a controller connected to each comparator, each comparator including a first input terminal, a second input terminal, and a data output terminal; a comparison module 20 configured to input the data to be compared to the second input terminal of the current comparator according to the clock delay number, and compare it with the temporary data stored at its first input terminal to obtain a comparison result; a result processing module 30 configured to temporarily store the data that meets the operation mode to the first input terminal of the current comparator according to the comparison result, and output another data from its data output terminal to the second input terminal of the next level comparator; and an acquisition module 40 configured to determine the timing of the controller acquiring the output data of the last level comparator based on the m data, and take the acquired output data as the nth data.

[0093] A third aspect of the present invention also provides a computer-readable storage medium. Figure 5 A schematic diagram of a computer-readable storage medium implementing a data sorting-based evaluation method according to an embodiment of the present invention is shown. Figure 5 As shown, the computer-readable storage medium 3 stores computer program instructions 31. When executed by a processor, the computer program instructions 31 implement the method of any of the above embodiments.

[0094] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the data sorting-based evaluation method according to the present invention are equally applicable to the data sorting-based evaluation system and storage medium according to the present invention.

[0095] A fourth aspect of the present invention also provides a computer device, including as follows: Figure 6 The memory 402 and processor 401 shown are provided. The memory 402 stores a computer program that, when executed by the processor 401, implements the method of any of the above embodiments.

[0096] like Figure 6 The diagram shown is a hardware structure schematic of an embodiment of a computer device for executing a data sorting-based evaluation method provided by the present invention. Figure 6 Taking the computer device shown as an example, this computer device includes a processor 401 and a memory 402, and may also include an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 6 Taking a bus connection as an example, input device 403 can receive input digital or character information, and generate key signal inputs related to user settings and function control of the data sorting-based evaluation system. Output device 404 may include display devices such as a display screen.

[0097] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the data sorting-based evaluation method in this embodiment. Memory 402 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by using the data sorting-based evaluation method, etc. In addition, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0098] The processor 401 executes various functional applications and data processing of the server by running non-volatile software programs, instructions and modules stored in the memory 402, that is, it implements the data sorting-based evaluation method of the above method embodiment.

[0099] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0100] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0101] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0102] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0103] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0104] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. An evaluation method based on data ordering, characterized in that, Includes the following steps: In response to obtaining the nth sorted data from m data, the operation mode of the operation implementation circuit is determined based on the relationship between m and n. The operation implementation circuit includes n cascaded comparators and a controller connected to each comparator. Each comparator includes a first input terminal, a second input terminal, and a data output terminal. The data to be compared is input to the second input of this stage comparator according to the clock delay number, and compared with the temporary data at its first input to obtain the comparison result; Based on the comparison result, the data that conforms to the operation method is temporarily stored at the first input of the current comparator, and another data is output from its data output to the second input of the next level comparator. Based on the m data, the timing for the controller to acquire the output data of the last stage comparator is determined, and the acquired output data is used as the nth data. The operation methods include sorting operations based on smaller values ​​and sorting operations based on larger values; The operational methods for determining the circuit based on the relationship between m and n include: Compare the sizes of n and m / 2; If n≤m / 2, then the operation method is the sorting operation based on the smaller value; If n > m / 2, then the operation method is the sorting operation based on the largest value.

2. The method of claim 1, wherein, Based on the comparison result, temporarily storing data conforming to the operation method at the first input of the current comparator, and outputting another data from its data output to the second input of the next-level comparator includes: In response to the operation method being the sorting operation based on the smallest value, the data with smaller values ​​is temporarily stored at the first input of the current level comparator according to the comparison result, and the data with larger values ​​is output from the data output of the current level comparator to the second input of the next level comparator. In response to the operation method being the sorting operation based on the largest value, the data with larger values ​​is temporarily stored at the first input of the current level comparator according to the comparison result, and the data with smaller values ​​is output from the data output of the current level comparator to the second input of the next level comparator.

3. The method of claim 1, wherein, Also includes: The corresponding reset value is determined based on the aforementioned calculation method.

4. The method of claim 1, wherein, Determining the timing for the controller to acquire the output data of the last-stage comparator based on the m data includes: In response to obtaining the nth sorted data from the first m data at any given time, the controller obtains the output data of the last-stage comparator based on the time when the value needs to be obtained.

5. The method according to claim 1, characterized in that, Determining the timing for the controller to acquire the output data of the last-stage comparator based on the m data also includes: In response to obtaining the nth sorted data from every m data, the circuit operates for m+n-1 cycles, and the controller obtains the output data of the last comparator. After each acquisition, the circuit is reset.

6. An evaluation system based on data sorting, characterized in that, include: A circuit module is configured to respond to obtaining the nth sorted data from m data, and to determine the operation mode of the operation implementation circuit based on the relationship between m and n. The operation implementation circuit includes n cascaded comparators and a controller connected to each comparator. Each comparator includes a first input terminal, a second input terminal, and a data output terminal. The operation mode includes sorting operation based on the smallest value and sorting operation based on the largest value. The comparison module is configured to input the data to be compared to the second input terminal of the comparator at this stage according to the clock delay number, and compare it with the temporary data stored at its first input terminal to obtain the comparison result; The result processing module is configured to temporarily store data conforming to the operation method to the first input of the current-level comparator based on the comparison result, and output another data from its data output to the second input of the next-level comparator; and The acquisition module is configured to determine the timing for the controller to acquire the output data of the last stage comparator based on the m data, and to use the acquired output data as the nth data. The circuit module is also configured to: compare the size of n and m / 2; if n≤m / 2, the operation method is the sorting operation based on the smaller value; if n>m / 2, the operation method is the sorting operation based on the larger value.

7. A computer-readable storage medium, characterized in that, The system stores computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1-5.

8. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the method as described in any one of claims 1-5.

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