A DMA device
By providing contiguous storage space for DMA descriptors in the cache, an optimized DMA descriptor is generated, which solves the problem of high complexity caused by non-contiguous data storage in DMA transfer and achieves more efficient data transfer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI YIXIN IND CO LTD
- Filing Date
- 2018-09-14
- Publication Date
- 2026-08-04
AI Technical Summary
In existing DMA transfer technologies, the data indicated by DMA descriptors is not stored contiguously in host memory and device memory, resulting in high data transfer complexity, increasing the number of DMA descriptor entries, and affecting transfer efficiency.
Provide contiguous storage space for DMA descriptors in the cache. By allocating contiguous storage space in the cache, optimized DMA descriptors are generated, the number of DMA descriptor entries is reduced, multiple descriptors are processed concurrently, and data transfer from the cache to memory is realized.
It reduces the complexity of the DMA transfer process, speeds up data transfer, and improves memory utilization and transfer efficiency.
Smart Images
Figure CN115168257B_ABST
Abstract
Description
Technical Field
[0001] This application relates to DMA transfer technology, and more specifically, to optimizing DMA transfer using caching. Background Technology
[0002] DMA (Direct Memory Access) is a technology that moves data directly between memory locations without relying on the CPU. DMA technology is used in various electronic devices. This application uses a solid-state storage device as an example to introduce a technical solution that optimizes DMA transfer using caching. Figure 1 A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.
[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), and RRAM (Resistive Random Access Memory) are common types of NVM.
[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.
[0005] Control unit 104 is used to control data transfer between interface 103, NVM chip 105, and DRAM 110, and is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. Control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, control unit 104 can be in the form of an FPGA (Field-programmable gate array), ASIC (Application Specific Integrated Circuit), or a combination thereof. Control unit 104 may also include a processor or controller, in which software is executed to manipulate the hardware of control unit 104 to process I / O (Input / Output) commands. Control unit 104 can also be coupled to DRAM 110 and can access data in DRAM 110. FTL tables and / or cached I / O command data can be stored in DRAM. I / O command data can be transferred between the host and DRAM 110 using, for example, DMA technology.
[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.
[0007] Figure 2 A schematic diagram illustrating existing DMA transfer techniques is provided.
[0008] Taking DMA transfer between the host and the solid-state storage device as an example, the DMA module moves the data in the host memory 210 to the device memory 220 of the storage device.
[0009] Host memory 210 stores data to be moved to device memory 220 by the DMA module. The DMA module performs the data transfer from host memory 210 to device memory 220 based on a DMA descriptor (L1, L2, L3, or L4). A DMA descriptor includes multiple entries, each indicating one data transfer. Each DMA descriptor entry indicates, for example, a source address (e.g., host memory 210 address), a destination address (e.g., device memory 220 address), and the length of data to be transferred. For example, DMA descriptor L2 includes six entries; see [link to documentation]. Figure 2 Entry 0 indicates that data of length 0x0800 is moved from source address 0x0000 to destination address 0x0800, and entry 1 indicates that data of length 0x04000 is moved from source address 0x0800 to destination address 0x2400. Figure 2 The numbers indicating memory addresses are all in hexadecimal. For the sake of brevity, the "0x" symbol before the hexadecimal numbers has been omitted.
[0010] To improve memory utilization, the data to be moved indicated by the DMA descriptor can be stored non-contiguously in both host memory 210 and device memory 220. Data indicated by DMA descriptor L2 is stored in three regions in host memory 210 and in six regions in device memory (regions shown in shaded areas). However, multiple data chunks in memory are not conducive to optimized data transfer, as each chunk requires a DMA descriptor entry, increasing complexity with each additional entry.
[0011] Continue reading Figure 2 Each DMA descriptor (L1, L2, L3, or L4) is indicated by a different style of shading. DMA descriptor L1 has no shading, DMA descriptor L2 has a shading indicated by a horizontal line, DMA descriptor L3 has a shading indicated by a vertical line, and DMA descriptor L4 has a shading indicated by a diagonal line. In host memory 210 and device memory 220, patterned regions indicate the DMA descriptor corresponding to each region. For example, in host memory 210, the region at addresses 0x5000-0x5FFF has no shading, indicating that the data stored in this region is indicated by DMA descriptor L1. Device memory 220 also has regions not allocated to any of the DMA descriptors (L1, L2, L3, or L4), these regions are indicated by shading indicated by dots. The numbers in host memory 210 and device memory 220 indicate the size of the corresponding storage space.
[0012] The host memory 210 and / or device memory 220 each include multiple memory pages, each page being, for example, 4KB in size.
[0013] The control unit of the host and / or storage device generates a DMA descriptor and provides a DMA module. If the host generates a DMA descriptor, the host manages the allocation and release of host memory 210 and device memory 220; if the storage device generates a DMA descriptor, the control unit of the storage device manages the allocation and release of host memory 210 and device memory 220; or the host and storage device jointly generate a DMA descriptor, with the host managing its own host memory 210 and the device's control unit managing its own device memory 220. Summary of the Invention
[0014] This application provides contiguous storage space for DMA descriptors in the cache, avoiding the storage of data on multiple storage devices, thereby reducing the number of entries in the DMA descriptor in some cases, and thus reducing the complexity of generating the DMA transfer process; contiguous storage space also helps to optimize data transfer, thereby speeding up the DMA transfer process.
[0015] According to a first aspect of this application, a first DMA device is provided for moving data from a first memory to a second memory, comprising: a first DMA module, a second DMA module, and a cache; the first DMA module moves data to be transferred from the first memory to the cache according to a first DMA descriptor; wherein the data to be transferred is stored in contiguous storage space in the cache; and the second DMA module moves the data to be transferred from the cache to the second memory according to a second DMA descriptor.
[0016] According to a first aspect of this application, a first DMA device is provided, wherein the data to be transferred is stored in a second memory in a non-contiguous storage space.
[0017] According to the first or second DMA device of the first aspect of this application, a first DMA descriptor is generated by using the storage space address of the first memory indicated by the DMA descriptor in the IO command as the source address and the storage space address allocated in the cache as the destination address.
[0018] According to the third DMA device of the first aspect of this application, for each entry of the DMA descriptor in the IO command, each entry of the corresponding first DMA descriptor is generated by adding the address of the cache as the destination address.
[0019] According to the first aspect of this application, a fourth DMA device is provided, wherein the data length is recorded in the entry of the first DMA descriptor.
[0020] According to one of the first to fifth DMA devices of the first aspect of this application, a second DMA descriptor is generated using the destination address of the first DMA descriptor as the source address and the memory space address allocated in the second memory as the destination address.
[0021] According to one of the first to sixth DMA devices of the first aspect of this application, for each entry of the first DMA descriptor, its destination address is used as the source address of the entry of the second DMA descriptor, and the address of one of the storage space segments obtained from the second memory is used as the destination address of the entry of the second DMA descriptor.
[0022] According to the seventh DMA device of the first aspect of this application, if the size of the first storage space segment of the second memory is insufficient to accommodate all the data indicated by the first entry of the first DMA descriptor, a second DMA descriptor is generated in which the length of the data to be transmitted is equal to the size of the first storage space segment, and a second entry of the second DMA descriptor is also generated to continue transmitting the data indicated by the first entry of the first DMA descriptor.
[0023] According to one of the first to eighth DMA devices of the first aspect of this application, in response to the completion of data transfer corresponding to the first DMA descriptor, the memory space occupied by the data corresponding to the first DMA descriptor in the first memory is released.
[0024] According to one of the first to ninth DMA devices of the first aspect of this application, in response to the completion of data transfer corresponding to the second DMA descriptor, the memory space occupied by the data corresponding to the second DMA descriptor in the cache is released.
[0025] According to one of the first to tenth DMA devices of the first aspect of this application, wherein a first DMA module concurrently processes a plurality of first DMA descriptors, and / or a second DMA module concurrently processes a plurality of second DMA descriptors.
[0026] According to one of the first to eleventh DMA devices of the first aspect of this application, wherein the cache is SRAM.
[0027] According to one of the first to twelfth DMA devices of the first aspect of this application, the cache is an external memory coupled to the DMA device.
[0028] According to one of the first to thirteenth DMA devices of the first aspect of this application, wherein the first DMA module and the second DMA module are both integrated DMA modules.
[0029] According to one of the first to fourteenth DMA devices of the first aspect of this application, in response to the completion of data transfer indicated by the first DMA descriptor, an I / O command execution is indicated to the first memory.
[0030] According to one of the first to fifteenth DMA devices of the first aspect of this application, a second DMA descriptor is generated in response to an entry for generating a first DMA descriptor or generating a first DMA descriptor.
[0031] According to one of the first to sixteenth DMA devices of the first aspect of this application, in response to generating a second DMA descriptor, the second DMA module initiates a data transfer from a cache to a second memory.
[0032] According to a second aspect of this application, a first DMA device according to the second aspect of this application is provided, comprising: a cache and a second DMA module; wherein the cache stores data moved into the cache by the first DMA module according to a first DMA descriptor, the data being stored in contiguous storage space in the cache; and the second DMA module moves data to be transferred from the cache to a second memory according to a second DMA descriptor.
[0033] According to a second aspect of this application, a first DMA device is provided, wherein the data is stored in a non-contiguous storage space in a second memory.
[0034] According to a third aspect of this application, a first storage device according to the third aspect of this application is provided, comprising: a DMA device as described in any of the preceding claims, and further comprising: a first memory or a second memory; wherein the first memory and the second memory are both memories coupled external to the DMA device.
[0035] According to a third aspect of this application, the first storage device or the second storage device is DRAM.
[0036] According to the third aspect of this application, the first or second storage device is an NVM chip or a page cache of the NVM chip.
[0037] According to a third aspect of this application, the third storage device further includes a media interface controller; the media interface controller provides data in the cache to the NVM chip or writes data to the page cache of the NVM chip.
[0038] According to a third aspect of this application, the third storage device further includes a media interface controller; the media interface controller provides data to the NVM chip or data written to the page cache of the NVM chip.
[0039] According to a fourth aspect of this application, a first DMA transfer method according to the fourth aspect of this application is provided, comprising: allocating a contiguous address space in a cache for an I / O command; generating a first DMA descriptor for describing a DMA transfer from a first memory space to a cache space; initiating a first DMA transfer; generating a second DMA descriptor for describing a DMA transfer from a cache space to a second memory space; and initiating a second DMA transfer.
[0040] According to the first DMA transfer method of the fourth aspect of this application, the second DMA descriptor indicates that the address of the data stored in the second memory space is a non-contiguous address.
[0041] According to the first or second DMA transfer method of the fourth aspect of this application, a first DMA descriptor is generated by using the storage space address of the first memory indicated by the DMA descriptor in the IO command as the source address and the storage space address allocated in the cache as the destination address.
[0042] According to the third DMA transfer method of the fourth aspect of this application, each entry of the corresponding first DMA descriptor is generated by adding a cached address as the destination address to each entry of the DMA descriptor in the IO command.
[0043] According to one of the first to fourth DMA transfer methods of the fourth aspect of this application, a second DMA descriptor is generated by using the destination address of a first DMA descriptor as the source address and the memory space address allocated in the second memory space as the destination address.
[0044] According to the fifth DMA transfer method of the fourth aspect of this application, for each entry of the first DMA descriptor, its destination address is used as the source address of the entry of the second DMA descriptor, and the address of one of the memory space segments obtained from the second memory space is used as the destination address of the entry of the second DMA descriptor.
[0045] According to the sixth DMA transfer method of the fourth aspect of this application, if the size of the first storage space segment of the second memory is insufficient to accommodate all the data indicated by the first entry of the first DMA descriptor, the length of the data to be transferred in the first entry of the second DMA descriptor is equal to the size of the first storage space segment, and a second entry of the second DMA descriptor is also generated to continue transferring the data indicated by the first entry of the first DMA descriptor.
[0046] According to one of the first to seventh DMA transfer methods of the fourth aspect of this application, in response to the completion of data transfer corresponding to the first DMA descriptor, the storage space occupied by the data corresponding to the first DMA descriptor in the first memory space is released.
[0047] According to one of the first to eighth DMA transfer methods of the fourth aspect of this application, in response to the completion of data transfer corresponding to the second DMA descriptor, the storage space occupied by the data corresponding to the second DMA descriptor in the cache space is released.
[0048] According to one of the first to ninth DMA transfer methods of the fourth aspect of this application, a plurality of first DMA descriptors are processed concurrently, and / or a plurality of second DMA descriptors are processed concurrently.
[0049] According to one of the first to tenth DMA transfer methods of the fourth aspect of this application, in response to the completion of data transfer indicated by the first DMA descriptor, the execution of the IO command is indicated to the first memory space.
[0050] According to one of the first to eleventh DMA transfer methods of the fourth aspect of this application, a second DMA descriptor is generated in response to the generation of a first DMA descriptor or an entry for generating the first DMA descriptor.
[0051] According to one of the first to twelfth DMA transfer methods of the fourth aspect of this application, in response to generating a second DMA descriptor, a data transfer from a cache space to a second memory space is initiated. Attached Figure Description
[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.
[0053] Figure 1 A block diagram of a solid-state storage device is shown.
[0054] Figure 2 A schematic diagram illustrating existing DMA transfer technology is provided.
[0055] Figure 3 A block diagram illustrating the use of caching to optimize DMA transfer according to an embodiment of this application is shown;
[0056] Figure 4 A schematic diagram illustrating DMA transfer according to an embodiment of this application is shown;
[0057] Figure 5A A schematic diagram illustrating DMA descriptor generation in the prior art;
[0058] Figure 5B A schematic diagram illustrating the generation of a DMA descriptor according to an embodiment of this application is shown;
[0059] Figure 6 This is a flowchart of DMA transfer according to an embodiment of this application;
[0060] Figure 7 A block diagram illustrating DMA transfer optimization using caching according to yet another embodiment of this application is shown. Detailed Implementation
[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0062] Figure 3 A block diagram illustrating the use of caching to optimize DMA transfer according to an embodiment of this application is shown.
[0063] A control unit is coupled to the storage device. The control unit includes DMA module 0, DMA module 1, and memory 0. The control unit is also coupled to memory 1, which is external to the control unit. Memory 0 is integrated internally into the control unit, thus giving it relatively high access speed and relatively high cost per unit storage capacity; memory 1 has relatively low access speed and relatively high capacity. For example, memory 0 is SRAM, while memory 1 is DRAM. Optionally, memory 0 is an external memory coupled to the control unit.
[0064] DMA module 0 performs data transfer between the host and memory 0, while DMA module 1 performs data transfer between memory 0 and memory 1. Memory 0 acts as a cache to optimize DMA data transfer between the host and the storage device. As a storage device, to provide storage functionality, the control unit also writes data transferred from the host to memory 1 to the NVM chip, or transfers data read from the NVM chip and stored in memory 1 to the host.
[0065] The control unit generates DMA descriptors for DMA module 0 and DMA module 1 respectively, to indicate DMA transfers between them. To generate DMA descriptors, the control unit manages the allocation and release of memory 0 and memory 1. For example, the I / O command provided by the host to the control unit indicates the address of the data to be transferred in the host memory. In memory 0, to improve DMA transfer efficiency, the control unit allocates contiguous storage space for the data to be transferred by the I / O command and generates a DMA descriptor for DMA module 0. In memory 1, the control unit allocates storage space for the data to be transferred by the I / O command and generates a DMA descriptor for DMA module 1. To improve the utilization of memory 1, the storage space allocated for the I / O command in memory 1 can be non-contiguous.
[0066] Optionally, DMA module 0 and DMA module 1 are integrated DMA modules.
[0067] Optionally, the host provides DMA module 0, and the memory 0 of the control unit is mapped to the host's storage space, for example, as the BAR space of a PCIe device, or as a CMB (Controller Memory Buffer) or PMB (Persistent Memory Buffer) provided to the host according to the NVMe protocol. A technical solution for mapping the memory of a storage device to the host's storage space is also provided in Chinese patent application 201810094060.2, the entire text of which is incorporated herein by reference. For example, the host generates a DMA descriptor for DMA module 0 to instruct DMA module 0 to move data from the host memory to memory 0. And the control unit generates a DMA descriptor for DMA module 1 to instruct DMA module 1 to move data from memory 0 to memory 1.
[0068] Figure 4 A schematic diagram of DMA transfer according to an embodiment of this application is shown.
[0069] DMA module 0 (see also) Figure 3 The data in the host memory is transferred to memory 0 via DMA, and DMA module 1 transfers the data in memory 0 to memory 1 via DMA.
[0070] DMA module 0 performs DMA transfers based on host DMA descriptors (HL1, HL2, HL3, and HL4). Each host DMA descriptor contains multiple entries, each recording information such as the source address, destination address, and data length. Figure 4In the example, the source address of the host DMA descriptor entry is the host memory address, and the destination address is the address of memory 0, which is used as a cache (also called the cache address). Optionally, the host DMA descriptor also describes the DMA transfer from memory 0 to host memory.
[0071] In host memory 410 and memory 0, patterned areas indicate the DMA descriptors corresponding to those areas. For example, the shading indicated by the horizontal line indicates the host DMA descriptor (HL2) and the data corresponding to the host DMA descriptor (HL2) in host memory 410 and memory 0. The numbers in host memory 410, memory 0, and memory 1 indicate the size of the corresponding storage space.
[0072] See Figure 4 The data corresponding to the host DMA descriptor (HL2) is stored in three regions in host memory 410, and continuously stored in memory 0 (R2-0x2000). According to an embodiment of this application, in memory 0, which serves as a cache, contiguous storage space is allocated for the data indicated by the DMA descriptor, serving as the destination address for DMA transfer. The host DMA descriptor (HL2) includes three entries, recording the address of each of the three regions in host memory 410 where the data corresponding to the host DMA descriptor (HL2) is stored, and the address in memory 0 where the data corresponding to the host DMA descriptor (HL2) is stored. DMA module 0 moves the corresponding data between host memory 410 and memory 0 based on the host DMA descriptor (HL2).
[0073] Because memory 0 provides contiguous storage space for the DMA descriptors, the number of host DMA descriptor entries can not exceed the area occupied by the data corresponding to the host DMA descriptor in host memory 410. Taking host DMA descriptor (HL2) as an example, using only 3 host DMA descriptor entries and initiating 3 corresponding DMA transfers, the process of moving the data corresponding to host DMA descriptor (HL2) from the host to the storage device is completed. Figure 2 Compared to the previous scheme (6 DMA descriptor entries), this reduces the number of DMA entries, decreases the complexity of generating the DMA transfer process, and speeds up the DMA transfer process.
[0074] The allocation and release of host memory 410, memory 0, and memory 1 are managed. After DMA module 0 moves data corresponding to a DMA descriptor from host memory 410 to memory 0, the memory space occupied by the data corresponding to the DMA descriptor in host memory 410 can be released. Similarly, after DMA module 1 moves data corresponding to a DMA descriptor from memory 0 to memory 1, the memory space occupied by the data corresponding to the DMA descriptor in memory 0 can be released.
[0075] DMA module 1 performs DMA transfers based on device DMA descriptors (DL1, DL2, DL3, and DL4). Each device DMA descriptor contains multiple entries, each recording information such as the source address, destination address, and data length. Figure 4 In this example, the source address of the device DMA descriptor entry is the address of cached memory 0 (also known as the cache address), and the destination address is the address of memory 1. Optionally, the device DMA descriptor also describes the DMA transfer from memory 1 to memory 0.
[0076] Continue reading Figure 4 In memory 0 and memory 1, the DMA descriptors corresponding to each region are also indicated by patterned areas. For example, the shading indicated by the horizontal line indicates the host DMA descriptor (HL2) and the device descriptor (DL2) corresponding to the host DMA descriptor (HL2), the large data in host memory 410, and the data in memory 0 and memory 1.
[0077] The data corresponding to the device DMA descriptor (DL2) is stored contiguously in memory 0 (R2-0x2000), and in six regions in memory 1. According to an embodiment of this application, the storage space of memory 0 serves as the source address for the DMA transfer indicated by the device descriptor, and the storage space of memory 1 serves as the destination address for the DMA transfer indicated by the device descriptor. The device DMA descriptor (DL2) includes six entries, each recording the address of one of the six regions in memory 1 where the data corresponding to the device DMA descriptor (DL2) is stored, serving as the destination address. DMA module 1 moves the corresponding data between memory 0 and memory 1 according to the device DMA descriptor (DL2).
[0078] Since memory 0 provides contiguous storage space for DMA descriptors, the number of device DMA descriptor entries can not exceed the area occupied by the data corresponding to the device DMA descriptor in memory 1. Taking device DMA descriptor (DL2) as an example, using 6 device DMA descriptor entries, 6 corresponding DMA transfers are initiated to move the data corresponding to device DMA descriptor (DL2) from memory 0 to memory 1.
[0079] Thus, through the DMA transfer of DMA module 0 and DMA module 1 respectively, the data in the host memory 410 is moved to the slave memory 1.
[0080] Optionally, multiple host DMA descriptors (HL0, HL1, HL2, and HL3) are simultaneously provided to DMA module 0, which processes the multiple host DMA descriptors concurrently. DMA module 1 also processes multiple device DMA descriptors concurrently.
[0081] Optionally, the data corresponding to the host DMA descriptor and the device DMA descriptor with a corresponding relationship are transferred sequentially. For example, after all the data corresponding to the host DMA descriptor HL2 has been moved to memory 0, DMA module 1 then initiates data transfer according to the device DMA descriptor DL2.
[0082] Figure 5A and Figure 5B This diagram illustrates the generation of a DMA descriptor based on IO commands.
[0083] Figure 5A This demonstrates the existing DMA descriptor generation process, applied to, for example... Figure 2 DMA transfer system; Figure 5B The DMA descriptor generation process shown according to embodiments of this application is applied to, for example... Figure 4 DMA transfer system.
[0084] See Figure 5A For example, the I / O command provided by the host to the storage device indicates a DMA descriptor 510 for transferring data to the storage device. The DMA descriptor 510 includes entries indicating the address and length of the data to be transferred in the host memory, and that the data to be transferred is stored non-contiguously in the host memory.
[0085] The DMA descriptor 510 provided by the host does not indicate the device memory (e.g. Figure 4 1) Memory address. The control unit of the storage device, in response to receiving an I / O command, allocates storage space in the device memory for the data to be transferred by the DMA descriptor 510 receiving the I / O command. See also Figure 2 For example, the data to be transferred by DMA descriptor 510 is accommodated in six regions allocated in the device memory. The control unit generates a DMA descriptor 520 comprising six entries to describe six consecutive DMA transfers from host memory to device memory, each with a contiguous source and destination address.
[0086] See Figure 5BFor example, the I / O command provided by the host to the storage device indicates the DMA descriptor 510 for transferring data to the storage device.
[0087] The control unit of the storage device, in response to receiving an I / O command, transfers the complete data to be transferred for the DMA descriptor 510 that received the I / O command, while the memory 0 (also see) acts as a cache. Figure 4 The control unit allocates contiguous storage space in memory 0 such that the contiguous storage space allocated in memory 0 can accommodate the complete data to be transferred by DMA descriptor 510. Optionally, if memory 0 cannot temporarily provide contiguous storage space to accommodate the complete data to be transferred by DMA descriptor 510, the control unit suspends processing of DMA descriptor 510 until sufficient contiguous storage space is available from memory 0. The control unit generates DMA descriptor 540 using the address of the storage space in memory 0 allocated to the complete data to be transferred by DMA descriptor 510. DMA descriptor 540 includes multiple entries, each entry indicating a data transfer from host memory to memory 0. For each entry of DMA descriptor 510, each entry of the corresponding DMA descriptor 540 is generated by adding the address of memory 0 as the destination address. Optionally, DMA descriptor 540 describes three DMA transfers from host memory to memory 0, each with a contiguous source address and destination address.
[0088] In response to the generation of DMA descriptor 540, DMA module 0 (see...) Figure 4 Initiate a DMA transfer from the host to memory 0. In response to the completion of the DMA transfer indicated by DMA descriptor 540, the host can be notified of the completion of the execution of the IO command (write command) corresponding to DMA descriptor 510.
[0089] And in response to the generation of DMA descriptor 540, or the generation of an entry for DMA descriptor 540, DMA descriptor 550 is generated. DMA descriptor 550 is used to describe a DMA transfer from memory 0 to memory 1. The control unit allocates one or more memory segments in memory 1 to accommodate the complete data to be moved by DMA descriptor 510 (DMA descriptor 540). As an example, six memory segments are allocated from memory 1 to accommodate the complete data to be moved by DMA descriptor 510. For each entry of DMA descriptor 540, its cache address is used as the source address of the entry of DMA descriptor 550 (e.g., cache 0x2C00 for entry 0 of DMA descriptor 540), and the address of one of the memory segments obtained from memory 1 (denoted as S1) (e.g., address 0x0800 of device memory (memory 1)) is used as the destination address of the entry of DMA descriptor 550. Since the size of storage segment S1 of memory 1 is 0x0800, it is insufficient to hold all the data indicated by entry 0 of DMA descriptor 540. In entry 0 of DMA descriptor 550, the data length indicated for transmission is equal to the size of storage segment S1. DMA descriptor entry 1 is also generated to continue transmitting the data indicated by entry 0 of cache descriptor 540. The remaining data of entry 0 of descriptor 540 (address 0x3400 and length 0x0400 in memory 0) is moved to another storage segment (S2) of memory 1 (e.g., address 0x2400 of device memory (memory 1)). Thus, entry 1 of DMA descriptor 550 has a source address (address 0x3400 of memory 0), a destination address (address 0x2400 of memory 1), and a data length of 0x0400.
[0090] In response to the generation of DMA descriptor 550, DMA module 1 (see...) Figure 4 Initiate a DMA transfer from memory 0 to memory 1. And in response to the completion of the DMA transfer corresponding to DMA descriptor 550, the storage space occupied by DMA descriptor 550 in memory 0 can be released.
[0091] Figure 6 This is a flowchart of DMA transfer according to an embodiment of this application.
[0092] Step 610: The control unit acquires the DMA descriptor from the I / O command; wherein the I / O command can be a read command or a write command sent by the host to the storage device. The acquired DMA descriptor is provided, for example, to DMA module 0 (see also...). Figure 3 The DMA descriptor in an I / O command indicates the memory address where the data is stored in the first memory. See also... Figure 5BFor example, the I / O command provided by the host to the storage device indicates the DMA descriptor 510. The various entries included in the DMA descriptor 510 indicate the address and data length of the data to be transferred in the host memory, respectively.
[0093] Step 620: The control unit allocates a contiguous address space in the cache for IO commands.
[0094] Step 630: The control unit generates a first DMA descriptor to describe a DMA transfer from the first memory space to the cache space. The control unit uses the memory space address of the first memory space indicated by the DMA descriptor in the IO command as the source address and the memory space address allocated in the cache as the destination address to generate the first DMA descriptor. For example, the control unit generates each entry of the corresponding first DMA descriptor for each entry of the DMA descriptor in the IO command by adding the cache address as the destination address.
[0095] For example, see also Figure 5B The control unit of the storage device, in response to receiving an I / O command, transfers the complete data to be transferred for the DMA descriptor 510 that received the I / O command, while the memory 0 (also see) acts as a cache. Figure 4 The control unit allocates contiguous storage space in memory 0 such that the contiguous storage space allocated in memory 0 can accommodate the complete data to be transferred by DMA descriptor 510. The control unit generates DMA descriptor 540 (first DMA descriptor) using the address of the storage space in memory 0 allocated to the complete data to be transferred by DMA descriptor 510. DMA descriptor 540 includes multiple entries, each indicating a data transfer from host memory to memory 0. For each entry of DMA descriptor 510, a corresponding entry of DMA descriptor 540 is generated by adding the address of memory 0 as the destination address. Optionally, DMA descriptor 540 describes three DMA transfers from host memory to memory 0, each with a contiguous source and destination address.
[0096] Step 640: The first DMA module initiates a first DMA transfer. The first DMA module moves data from the first memory space to the cache via DMA transfer. Optionally, in response to the completion of the transfer of data corresponding to the first DMA descriptor, the storage space occupied by the data corresponding to the first DMA descriptor in the first memory space is released. Still optionally, in response to the completion of the data transfer indicated by the first DMA descriptor, the first memory space can also be indicated that the execution of the IO command (read command or write command) has been completed. Still optionally, in response to the generation of the first DMA descriptor or the entry for generating the first DMA descriptor, the generation of the second DMA descriptor begins during the first DMA transfer.
[0097] The first DMA module can process multiple first DMA descriptors concurrently to perform DMA data transfer quickly.
[0098] Step 650: The control unit generates a second DMA descriptor to describe the DMA transfer from the cache space to the second memory space. The destination address of the first DMA descriptor is used as the source address, and the address of the memory space allocated in the second memory space is used as the destination address. For example, for each entry in the first DMA descriptor, its destination address is used as the source address of the entry in the second DMA descriptor, and the address of one of the memory space segments obtained from the second memory space is used as the destination address of the entry in the second DMA descriptor.
[0099] As an example, in response to the generation of DMA descriptor 550, DMA module 1 (see...) Figure 4 Initiate a DMA transfer from memory 0 to memory 1. And in response to the completion of the DMA transfer corresponding to DMA descriptor 550, the storage space occupied by DMA descriptor 550 in memory 0 can be released.
[0100] To improve memory utilization, the second DMA descriptor indicates that the address of the data stored in the second memory space is a non-contiguous address.
[0101] Step 660: Initiate a second DMA transfer. The second DMA module moves the data in the cache to the second memory via DMA. In response to the completion of the data transfer corresponding to the second DMA descriptor, the storage space occupied by the data corresponding to the second DMA descriptor in the cache space is released.
[0102] In the aforementioned second DMA transfer, the second DMA module can concurrently process multiple second DMA descriptors to quickly perform DMA data transfer.
[0103] Figure 7 A block diagram illustrating DMA transfer optimization using caching according to yet another embodiment of this application is shown.
[0104] A control unit is coupled to the storage device. The control unit includes DMA module 0, DMA module 1, and memory 0. The control unit is also coupled to memory 1 external to the control unit. Memory 0 is integrated, for example, within the control unit, thus giving it relatively high access speed and relatively high cost per unit storage capacity; memory 1 has relatively low access speed and relatively high capacity. The control unit also includes a media interface controller. The media interface controller couples to one or more NVM chips. Optionally, the NVM chip includes a page cache (…). Figure 7In the diagram, the letter P is used to indicate that the interface is coupled to the NVM chip. The media interface controller transmits data with the NVM chip or its page buffer.
[0105] DMA module 0 performs data transfer between the host and memory 0. Memory 0 acts as a cache to optimize DMA data transfer between the host and the storage device.
[0106] according to Figure 7 In the illustrated embodiment, DMA module 1 performs data transfer between memory 0 and memory 1, and / or between memory 0 and an NVM chip coupled to a media interface controller. Taking an I / O command where the host writes data to the storage device as an example, the destination address indicated by the DMA descriptor provided to DMA module 1 is an address of memory 1, an address indicating the NVM chip, or an address of the NVM chip's page cache. Thus, in some cases, DMA module 1 directly moves data from memory 0 to the NVM chip, speeding up I / O command processing by reducing the overhead of moving data in and out of memory 1.
[0107] The control unit provides an address space for each NVM chip and / or its page cache. DMA module 1 uses the address of this address space of the NVM chip and / or its page cache as the destination address for the DMA transfer. DMA module 1 instructs the media interface controller to provide data to the NVM chip or write data to the page cache of the NVM chip by providing data obtained from memory 0 to the media interface controller and providing the destination address indicated by the DMA descriptor. The media interface controller provides data to the NVM chip or writes data to the page cache of the NVM chip via, for example, a command to access the NVM chip (e.g., a command following the ONFI protocol).
[0108] Optionally, DMA module 1 can also move data from the NVM chip or the page cache of the NVM chip to memory 0.
[0109] Alternatively, the media interface controller (instead of DMA module 1) handles data transfer between memory 1 and the NVM chip (or the page cache of the NVM chip).
[0110] In some cases, the NVM chip or its page cache may be temporarily unable to respond to data transfers with memory 0 due to processing other commands accessing the NVM chip, for example. In this situation, DMA module 1 uses data transfers between memory 0 and memory 1 as a substitute.
[0111] The control unit generates DMA descriptors for DMA module 0 and DMA module 1 respectively, to indicate DMA transfers between them. For example, the destination address in the DMA descriptor entry provided to DMA module 1 indicates the address of memory 1 or the address of the NVM chip (or the page cache of the NVM chip).
[0112] This application also provides a program including program code, which, when loaded into a host and executed on the host, causes the host's processor to perform one of the methods provided above according to the embodiments of this application.
[0113] It should be understood that each box in a block diagram and flowchart, as well as combinations of boxes in block diagrams and flowcharts, can be implemented by various means including computer program instructions. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data control equipment to produce a machine, such that the instructions, which execute on the computer or other programmable data control equipment, create means for implementing the functions specified in one or more flowchart boxes.
[0114] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data control device to function in a particular manner, thereby enabling the manufacture of an article of art comprising computer-readable instructions for implementing the functions specified in one or more flowchart blocks using the instructions stored in the computer-readable storage medium. The computer program instructions may also be loaded onto a computer or other programmable data control device to cause a series of operations to be performed on the computer or other programmable data control device, thereby producing a computer-implemented process, wherein the instructions, which execute on the computer or other programmable data control device, provide operations for implementing the functions specified in one or more flowchart blocks.
[0115] Therefore, the blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of operations for performing a specified function, and combinations of program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, as well as combinations of blocks in block diagrams and flowcharts, can be implemented by a hardware-based dedicated computer system that performs the specified function or operation, or by a combination of dedicated hardware and computer instructions.
[0116] Although the examples referred to in the present invention are described, they are for illustrative purposes only and not for limiting the scope of this application. Changes, additions and / or deletions to the implementation may be made without departing from the scope of this application.
[0117] Those skilled in the art who benefit from the teachings presented in the above description and associated drawings will recognize many modifications and other embodiments of the present application described herein. Therefore, it should be understood that the present application is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in its general and descriptive sense and not for limiting purposes.
Claims
1. A DMA device for transferring data from a first memory to a second memory, characterized in that, include: First DMA module, second DMA module, and cache; The first DMA module moves the data to be transferred from the first memory to the cache according to the first DMA descriptor; The data to be transmitted is stored in contiguous storage space in the cache; The second DMA module moves the data to be transferred from the cache to the second memory according to the second DMA descriptor, wherein the first DMA descriptor indicates the DMA transfer of the first DMA module, and the second DMA descriptor indicates the DMA transfer of the second DMA module; the data to be transferred is stored in multiple areas in the first memory, and one or more storage spaces are allocated in the second memory to accommodate the data to be transferred.
2. The DMA device according to claim 1, characterized in that, in, The first DMA descriptor is generated using the memory space address of the first memory indicated by the DMA descriptor in the IO command as the source address and the memory space address allocated in the cache as the destination address.
3. The DMA device according to claim 2, characterized in that, in, If the DMA descriptor in the IO command indicates through multiple entries that the data to be transferred is stored in multiple regions of the first memory, the first DMA descriptor includes multiple entries; wherein, for each entry in the first DMA descriptor, the storage space address of each region in the first memory is used as the source address of the first DMA descriptor entry, and the storage space address allocated for the region in the cache is used as the destination address of the first DMA descriptor entry.
4. The DMA device according to claim 3, characterized in that, in, For each entry of the DMA descriptor in the IO command, a corresponding first DMA descriptor entry is generated by adding the cached address as the destination address.
5. The DMA device according to any one of claims 1-4, characterized in that, in, The second DMA descriptor is generated using the destination address of the first DMA descriptor as the source address and the memory space address allocated in the second memory as the destination address.
6. The DMA device according to claim 5, characterized in that, in, If the data to be transmitted is stored in multiple non-contiguous storage spaces in the second memory, the second DMA descriptor includes multiple entries; wherein, for each entry in the second DMA descriptor, the destination address of the first DMA descriptor is used as the source address of the second DMA descriptor entry, and the address of each storage space in the second memory is used as the destination address of the second DMA descriptor entry.
7. The DMA device according to claim 6, characterized in that, in, For each entry of the first DMA descriptor, its destination address is used as the source address of the entry of the second DMA descriptor, and the address of one of the memory segments obtained from the second memory is used as the destination address of the entry of the second DMA descriptor.
8. The DMA device according to claim 7, characterized in that, in, If the size of the first storage segment of the second memory is insufficient to accommodate all the data indicated by the first entry of the first DMA descriptor, the data length indicated in the first entry of the second DMA descriptor is equal to the size of the first storage segment, and a second entry of the second DMA descriptor is also generated to continue transmitting the data indicated by the first entry of the first DMA descriptor.
9. The DMA device according to any one of claims 1-8, characterized in that, The first DMA module concurrently processes multiple first DMA descriptors, and / or the second DMA module concurrently processes multiple second DMA descriptors.
10. The DMA device according to any one of claims 1-8, wherein, In response to the completion of the data transfer corresponding to the second DMA descriptor, the memory space occupied by the data corresponding to the second DMA descriptor in the cache is released.