Communication circuit and board, electronic device

Abstract

The present disclosure relates to the technical field of computer communication, and specifically provides a communication circuit, a board card and an electronic device. The communication circuit comprises a connection terminal, a board card management circuit and a target memory. The connection terminal is adapted to establish a communication connection with an external device. The board card management circuit comprises a first slave port and a first master port, and the first slave port is connected to the connection terminal. The target memory is configured with a second slave port, and the first master port of the board card management circuit is connected to the second slave port of the target memory. The target memory is used to store relevant information of a target device. According to the present disclosure, the access communication between any two of the server host, the board card management circuit and the target memory of the FRU board card is realized, and the communication capability between devices of the board card is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer communication technology, specifically to a communication circuit and board, and electronic equipment. Background Technology

[0002] Server hosts can expand their functionality through pluggable cards. For example, PCIe cards can be plugged into PCIe slots on the server host and connected to PCIe cards. The server host can communicate with PCIe cards via SMBUS or I2C bus to expand its functionality.

[0003] In related technologies, access between various components on the board and between the components and the server host is restricted, resulting in limitations on the board's functionality. Summary of the Invention

[0004] To improve the communication performance of a circuit board, this disclosure provides a communication circuit and a circuit board having the communication circuit.

[0005] In a first aspect, embodiments of this disclosure provide a communication circuit, including:

[0006] Connection terminals, suitable for establishing communication connections with external devices;

[0007] The board management circuit includes a first slave port and a first master port, the first slave port being connected to the connection terminal; and

[0008] The target memory is configured with a second slave port, and the first master port of the board management circuit is connected to the second slave port of the target memory; the target memory is used to store relevant information of the target device.

[0009] In some implementations, the board management circuit and the target memory are located in the auxiliary power domain and are powered by the auxiliary power circuit.

[0010] In some implementations, when the board management circuit receives an access signal from an external device through the first slave port, it determines the target device based on the slave address carried by the access signal.

[0011] In response to the target device being the board management circuit, the board management circuit establishes data communication with the external device.

[0012] In some implementations, when the board management circuit receives an access signal from an external device through the first slave port, it determines the target device based on the slave address carried by the access signal.

[0013] In response to the target device being the target memory, the board management circuit sends the access signal to the target memory through the first host port, receives the return signal from the target memory, and sends the return signal to the external device through the first slave port.

[0014] In some embodiments, the connection terminal is connected to the first slave port of the board management circuit via a first bus, and the first master port of the board management circuit is connected to the second slave port of the target memory via a second bus.

[0015] In some implementations, the first bus includes an SMBUS bus or an I2C bus.

[0016] In some implementations, the second bus includes an I2C bus or an SPI bus.

[0017] In some implementations, the board management circuit includes an MCU chip circuit, and the power supply of the MCU chip circuit is no greater than 3.3V.

[0018] In some implementations, the second slave port of the target memory is communicatively connected to the connection terminal.

[0019] In some embodiments, the communication circuit described in this disclosure further includes:

[0020] The selector circuit includes a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal and the second input terminal are controlled to switch to be connected to the first output terminal.

[0021] Wherein, the connection terminal is connected to the first input terminal, the first host port is connected to the second input terminal, the first slave port is connected to the connection terminal or the first output terminal, and the first output terminal is connected to the second slave port.

[0022] In some implementations, the board management circuit is located in the main power domain and is powered by the main power circuit; the target memory and the selector circuit are located in the auxiliary power domain and are powered by the auxiliary circuit.

[0023] In some implementations, the first slave port of the board management circuit is connected to the first output terminal or the connection terminal through a first buffer circuit;

[0024] The first buffer circuit includes a first terminal, a second terminal, and a first enable terminal. The first terminal is connected to the first slave port, the second terminal is connected to the first output terminal or the connection terminal, and the first enable terminal is enabled by the main power supply circuit to control the on / off state of the first terminal and the second terminal.

[0025] In some embodiments, the first buffer circuit further includes a first port power supply for supplying power to the first end and a second port power supply for supplying power to the second end, wherein the first port power supply is connected to the main power supply circuit and the second port power supply is connected to the auxiliary power supply circuit.

[0026] In some implementations, the first host port of the board management circuit is connected to the second input terminal of the selector circuit via a second buffer circuit;

[0027] The second buffer circuit includes a third terminal, a fourth terminal, and a second enable terminal. The third terminal is connected to the first host port, the fourth terminal is connected to the second input terminal, and the second enable terminal is powered by the main power supply circuit to control the on / off state of the third terminal and the fourth terminal.

[0028] In some embodiments, the second buffer circuit further includes a third port power supply for powering the third terminal and a fourth port power supply for powering the fourth terminal, the third port power supply being connected to the main power supply circuit and the fourth port power supply being connected to the auxiliary power supply circuit.

[0029] In some implementations, the connection terminal, the board management circuit, and the target memory are connected via an I2C bus.

[0030] Secondly, this disclosure provides a board, including:

[0031] The communication circuit according to any embodiment of the first aspect; and

[0032] The gold fingers are adapted for pluggable communication with the slot of the external device, and the connection terminals are provided on the gold fingers.

[0033] In some implementations, the board is a PCIe board.

[0034] Thirdly, embodiments of this disclosure provide an electronic device, including:

[0035] The board according to any embodiment of the second aspect.

[0036] The communication circuit of this disclosure includes a connection terminal, a board management circuit, and a target memory. The connection terminal is adapted to establish a communication connection with an external device. A first slave port of the board management circuit is connected to the connection terminal, thereby establishing a communication connection between the external device and the board management circuit. A second slave port of the target memory is connected to a first master port of the board management circuit, thereby establishing a communication connection between the board management circuit and the target memory. Simultaneously, the server host can establish a communication connection with the target memory through the board management circuit. This disclosure enables access and communication between any two of the server host, the board management circuit, and the target memory of the FRU board, improving the communication capabilities between the various components of the board. Furthermore, since the server can access all the data information of the board, and the board management circuit can also access the FRU information of the board, it helps to monitor the operating status of the board, ensure the normal operation of the server, and improve communication performance. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a communication circuit or board according to some embodiments of this disclosure.

[0039] Figure 2 This is a schematic diagram of the structure of a communication circuit according to some embodiments of this disclosure.

[0040] Figure 3 This is a schematic diagram of the structure of a communication circuit or board according to some embodiments of this disclosure.

[0041] Figure 4 This is a communication timing diagram of a communication circuit according to some embodiments of this disclosure.

[0042] Figure 5 This is a communication timing diagram of a communication circuit according to some embodiments of this disclosure.

[0043] Figure 6 This is a structural block diagram of the board and communication circuit according to some embodiments of this disclosure.

[0044] Figure 7 This is a schematic diagram of the structure of the board and communication circuit according to some embodiments of this disclosure.

[0045] Figure 8This is a schematic diagram of the structure of the board and communication circuit according to some embodiments of this disclosure.

[0046] Figure 9 This is a schematic diagram of the structure of the board and communication circuit according to some embodiments of this disclosure.

[0047] Figure 10 This is a schematic diagram of the structure of the board and communication circuit according to some embodiments of this disclosure.

[0048] Figure 11 This is a circuit structure diagram of a selector circuit according to some embodiments of the present disclosure. Detailed Implementation

[0049] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. Furthermore, the technical features involved in the different embodiments of this disclosure described below can be combined with each other as long as they do not conflict with each other.

[0050] Currently, server hosts can expand their functionality and performance by plugging in and removing expansion cards through various reserved bus interfaces. For example, various types of PCIe expansion cards can be connected through the PCIe (peripheral component interconnect express) slot on the motherboard. PCIe expansion cards can improve the server's computing performance or expand various interface functions.

[0051] FRU (Field Replacement Unit) refers to a field replaceable unit. Various devices can be connected to the server host through pluggable interfaces. These pluggable devices are FRUs. For example, the PCIe card mentioned above is an FRU.

[0052] Each FRU device typically includes a storage unit, which can be a device such as EEPROM or FLASH. The storage unit stores relevant information about the FRU device, such as the device manufacturer, version number, model number, and serial number. The server host's BMC (Baseboard Management Controller) can read the device information from the FRU storage unit, which helps monitor the server status and ensure the server's normal operation.

[0053] In addition, FRU devices generally also include a board management module, which is mainly used to manage the power-on / power-off data, power consumption data, heat dissipation information, etc. of the FRU device, thereby detecting the working status of the FRU device and improving its operational stability.

[0054] In related technologies, the storage unit of an FRU can be connected to the terminals on its gold fingers via the system management bus. This allows the server host to access the FRU's storage unit and read FRU-related information when the FRU is inserted into the server host. However, in some FRU devices, the board management module is not connected to the gold finger terminals, preventing the server from accessing it. In other FRU devices, the board management module is mounted as a slave on the system bus, allowing the server to access both the storage unit and the board management module. However, the board management module cannot access the FRU's storage unit, preventing it from reading FRU-related information and thus hindering differentiated control over different FRUs.

[0055] Therefore, it can be seen that in related technologies, the access between various devices on the board and between the devices and the server host is restricted, resulting in limitations on the board's functional storage.

[0056] Based on this, the present disclosure provides a communication circuit and a board having the communication circuit, which aims to realize data communication between any two of the board management module, the FRU memory and the server host, thereby improving the communication function of the board.

[0057] In a first aspect, embodiments of this disclosure provide a communication circuit that can be applied to a board. The board can be any type of board, such as a PCIe board, and this disclosure does not limit it.

[0058] like Figure 1 As shown, in some embodiments, the communication circuitry of this disclosure may include a connection terminal 200, a board management circuit 300, and a target memory 400.

[0059] The connection terminal 200 refers to the interface through which the board 100 communicates with external devices, such as server hosts.

[0060] In some implementations, the board has gold fingers 110, which have multiple connection terminals 200, such as SMBUS terminals, I2C terminals, and power cord terminals. The server host has a slot; when the gold fingers 110 of the board are inserted into the slot on the server host, the server host can establish a communication connection with the board 100. In one example, the gold fingers 110 of the board 100 are PCIe gold fingers, and correspondingly, the slot on the server host is a PCIe slot.

[0061] The board management circuit 300 refers to the board management module of the board. Each FRU board is equipped with this board management circuit, which is mainly used to manage the board's power-on / power-off data, power consumption data and heat dissipation information, thereby ensuring the normal operation of the board.

[0062] In this embodiment of the disclosure, the board management circuit 300 includes a first slave port and a first master port. It is understood that data communication includes communication between master and slave devices. Taking I2C communication as an example, the master device includes an I2C Master port, and the slave device includes an I2C Slave port. The master port and slave port establish a connection through an I2C bus to realize I2C communication between the master and slave devices.

[0063] Therefore, in this embodiment, the board management circuit 300 includes a first slave port as a slave device and a first master port as a master device. Furthermore, the first slave port is connected to a connection terminal 200, which is used to connect to the server host. Thus, the server host can act as a master device and access the board management circuit through the connection terminal 200 and the first slave port, thereby realizing communication between the server host and the board management circuit.

[0064] The target memory 400 refers to the storage unit of the FRU board, which is used to store relevant information of the FRU board, such as the device manufacturer, version number, model and serial number. The target memory 400 can be an EEPROM or a FLASH memory, and this disclosure does not limit it.

[0065] The target memory 400 is configured with a second slave port, which is connected to the first master port of the board management circuit 300. Therefore, the board management circuit 300 can act as a master device, accessing the target memory 400 as a slave device, reading or writing its contents, thus realizing communication between the board management circuit 300 and the target memory 400 of the FUR board. When the board management circuit 300 can read the contents of the target memory, it can obtain various relevant information about the current board, thereby performing specific processing operations on the board and improving its functionality.

[0066] Meanwhile, in this embodiment, since two "master-slave communications" are established sequentially between the server host (connection terminal 200), the board management circuit 300, and the target memory 400, the board management circuit 300 can also act as a data relay device to realize indirect communication between the server host and the target memory 400. This enables the server host to access the target memory 400 of the FRU board, allowing the server to read device information from the FRU storage unit, which helps monitor the board status and ensures the normal operation of the server.

[0067] As described above, the communication circuit of this embodiment enables access and communication between any two of the server host, the board management circuit, and the target memory of the FRU board, thereby improving the communication capabilities between the various components of the board. Furthermore, since the server can access all the data information of the board, and the board management circuit can also access the FRU information of the board, this helps to monitor the board's operating status, ensure the normal operation of the server, and improve communication performance.

[0068] It's worth noting that in computer communication standards, the power supplied by a server to the circuit boards can be divided into main power and auxiliary power (AUX). Main power refers to the primary power supply that drives the various high-power components on the circuit boards; it is a controllable power supply, meaning it is provided after the server host is powered on. Auxiliary power, on the other hand, is the constant power supply that drives the essential components on the circuit boards. In other words, as long as the server host is powered on, regardless of whether it is actually powered on, it can provide the circuit boards with its auxiliary power (AUX).

[0069] For example, taking a PCIe board as an example, the server host can provide three types of power to the PCIe board: +3.3V, +12V, and +3.3V AUX power. The +3.3V and +12V power supplies, along with the power generated on the board, are called the main power supply, and their corresponding power circuits are called the main power supply circuits or main power domains. The +3.3V AUX power supply, along with the power generated on the board, is called the auxiliary power supply, and its corresponding power circuits are called the auxiliary power supply circuits or auxiliary power domains.

[0070] In traditional circuit boards, to ensure stable server operation, the target memory 400 of the FUR board is configured in the auxiliary power domain (AUX), allowing the server to access the target memory 400 even when the main power supply (Main) is off. However, the board management circuit 300 is configured in the main power domain (Main), meaning the server cannot access it when the main power supply (Main) is off. Furthermore, because the connection terminal 200 and the board management circuit 300 are in different power domains, the server needs to use a buffer circuit as a signal relay to communicate with the board management circuit 300, further increasing circuit complexity.

[0071] Therefore, in some embodiments of this disclosure, both the board management circuit 300 and the target memory 400 are configured in the board's auxiliary power domain AUX, for example... Figure 2As shown. In this embodiment, since both the board management circuit 300 and the target memory 400 are configured in the auxiliary power domain AUX, that is, both the board management circuit 300 and the target memory 400 are powered by the constant power of the auxiliary power domain, even when the server host is not powered on and the main power supply is off, the server host can still access the board management circuit 300 and the target memory 400, thereby further improving the communication capability of the board 100 and improving the stability of the server operation.

[0072] Furthermore, since the board management circuit 300 is configured in the auxiliary power domain AUX, there is no need to set up a buffer circuit for isolation between the board management circuit 300 and the connection terminal 200, which reduces the complexity of the circuit and further improves the communication effect.

[0073] Furthermore, it is understood that the voltage provided by the auxiliary power supply (AUX) is generally relatively low; for example, in a PCIe board, the AUX power supply voltage is typically +3.3V. To meet the power supply requirements, the board management circuit 300 in this embodiment can employ a low-power circuit, thereby ensuring that the board management circuit 300 can operate normally under the drive of the AUX power supply.

[0074] For example, in some implementations, the board management circuit 300 may use a low-power MCU (Microcontroller Unit) chip circuit, and the power supply of the MCU chip circuit shall not exceed +3.3V.

[0075] Continue to refer to Figure 2 In this embodiment of the disclosure, the bus connecting the connection terminal 200 to the first slave port of the board management circuit 300 is defined as the first bus, and the bus connecting the first master port of the board management circuit 300 to the second slave port of the target memory 400 is defined as the second bus.

[0076] It is worth noting that in related technologies, the connection terminals 200 on the gold fingers 110 of the circuit board generally use SMBUS (System Management Bus) terminals or I2C terminals to establish a communication connection with the server host. Therefore, in this embodiment, the first bus can use an SMBUS bus or an I2C bus, thus without changing the original circuit board gold finger structure and adapting to the existing circuit board circuit.

[0077] As for the second bus, it is not limited to I2C bus or SMBUS bus. It can adopt any bus type suitable for implementation, such as I2C bus, SPI (Serial Peripheral Interface) bus, etc., which can realize more design schemes.

[0078] Figure 3 A schematic diagram of the communication circuit structure in some embodiments of this disclosure is shown. In this example, both the first bus and the second bus are described using the I2C bus as an example. The following description, in conjunction with... Figure 3 The principle of the communication circuit according to the embodiments of this disclosure will be explained.

[0079] like Figure 3 As shown, in some embodiments, board 100 can be connected to a slot on a server host via gold fingers 110, so that the server host can communicate with board management circuitry 300 and target memory 400 of board 100 via the I2C Master terminal on gold fingers 110.

[0080] When the server host needs to access the board management circuit 300 or the target memory 400, the server host sends an access signal to the first slave port of the board management circuit 300 through the connection terminal 200. The access signal includes a start signal (star), a slave address (usually a 7-bit address), and a read / write flag (W / R).

[0081] When the board management circuit 300 receives an access signal, it can determine whether the server host is accessing the board management circuit 300 or the target memory 400 based on the slave address. Since the slave addresses of the board management circuit 300 and the target memory 400 are different, the board management circuit 300 can determine the target device that the server needs to access based on the slave address in the access signal sent by the server host.

[0082] In some implementations, when the board management circuit 300 determines that the target device accessed by the server host is the board management circuit 300, the board management circuit 300 can directly establish I2C communication with the server host. This situation is no different from conventional I2C communication, and will not be described in detail here.

[0083] In other embodiments, when the board management circuit 300 determines that the target device accessed by the server host is the target memory 400, the board management circuit 300 needs to act as a relay device for communication between the server host and the target memory 400. The following is in conjunction with... Figure 4 The communication timing diagram illustrates this process.

[0084] like Figure 4As shown, the server host sends an access signal to the board management circuit 300 via the first bus. The access signal includes a start signal (star), a 7-bit slave address (target memory address), and a 1-bit read / write flag (W / R). When the board management circuit 300 determines the target device to be the target memory 400 based on the slave address, it pulls the clock line (SCL) of the first bus low, thereby pausing first bus communication. Then, via the second bus, the board management circuit 300 forwards the access signal to the target memory 400. After receiving the acknowledgment signal (ACK) from the target memory 400, it pulls the clock line (SCL) of the second bus low while releasing the clock line of the first bus, thereby pausing second bus communication, resuming first bus communication, and simultaneously forwarding the acknowledgment signal to the server host.

[0085] Then, the server host can begin sending data. After sending one byte of data to the board management circuit 300, the board management circuit 300 can pull the clock line of the first bus low again, pausing the first bus communication. The board management circuit 300 then forwards this one byte of data to the target memory 400 via the second bus. After receiving the acknowledgment signal (ACK) from the target memory 400, it pulls the second bus clock line low again and releases the first bus clock line, thus pausing the second bus communication and resuming the first bus communication to continue receiving data. This alternating transmission achieves I2C communication between the server host and the target memory 400.

[0086] Of course, it's understandable that the second bus in the above example could also be an SPI bus, for example... Figure 5 As shown, Figure 5 China Data Communication Principles and Figure 4 Similarly, this disclosure will not elaborate further.

[0087] In addition, when the board management circuit 300 needs to access the target memory 400, the board management circuit 300 can communicate directly through the second bus connected to the first host port and the second slave port, which will not be described in detail in this disclosure.

[0088] As described above, in this embodiment, communication between the server host and the target memory of the FRU board is achieved through alternating operation of the I2C bus. This enables communication between any two of the server host, the board management circuit, and the storage unit of the FRU board, improving the board's communication capabilities and ensuring normal server operation. Furthermore, since both the board management circuit and the target memory are configured in the auxiliary power domain, communication between any two can still be achieved even when the main power supply is off, further enhancing the board's communication capabilities.

[0089] In the above embodiments, the server host communicates indirectly with the target memory 400 through the board management circuit 300. In other embodiments of this disclosure, a direct communication connection can also be established between the connection terminal 200 and the target memory 400, so that the server host can directly access the target memory 400, which will be described in detail below.

[0090] like Figure 6 As shown, in some embodiments, in the communication circuit of this disclosure example, the target memory 400 is configured with a second slave port as a slave device. The second slave port is connected to the connection terminal 200 on the gold finger 110, so that when the board is inserted into the server host, the server host can establish a communication connection with the target memory 400, that is, realize access communication between the server host and the target memory 400. Thus, the server can read the device information in the FRU storage unit, which helps to monitor the board status and ensure the normal operation of the server.

[0091] Meanwhile, in this embodiment, the second slave port of the target memory 400 is connected to the first master port of the board management circuit 300. Therefore, the board management circuit 300 can act as a master device, accessing the target memory 400 as a slave device, reading or writing the target memory content, thus realizing access communication between the board management circuit 300 and the target memory 400 of the FUR board. When the board management circuit 300 can read the target memory content, it can obtain various relevant information about the current board, thereby performing specific processing operations on the board in a targeted manner to improve the board's functionality.

[0092] In addition, the first slave port of the board management circuit 300 is connected to the connection terminal 200. It can be understood that the connection terminal 200 is used to connect to the server host, so that the server host can act as a master device and access the board management circuit through the connection terminal 200 and the first slave port, thereby realizing access communication between the server host and the board management circuit.

[0093] As described above, the communication circuit of this embodiment enables access and communication between any two of the server host, the board management circuit, and the target memory of the FRU board, thereby improving the communication capabilities between the various components of the board. Furthermore, since the server can access all the data information of the board, and the board management circuit can also access the FRU information of the board, this helps to monitor the board's operating status, ensure the normal operation of the server, and improve communication performance.

[0094] In this embodiment of the disclosure, to ensure stable server operation, the target memory 400 of the FUR board is configured in the auxiliary power domain AUX, so that the server can still access the target memory 400 even when the main power supply is powered off. However, considering that the voltage of the auxiliary power supply AUX is relatively low and the power consumption of some board management circuits 300 is relatively high, the auxiliary power supply AUX cannot meet the power supply requirements. Therefore, in some embodiments of this disclosure, the board management circuit 300 is configured in the main power domain Main, that is, the board management circuit 300 can only be powered on and operated when the main power supply Main is powered on.

[0095] Since the target memory 400 and the board management circuit 300 are configured in different power domains, their power supply voltages may be different. Therefore, if the target memory 400 and the board management circuit 300 are directly connected to the connection terminal 200, the devices may be damaged when the main power supply is powered on.

[0096] Therefore, in some embodiments of this disclosure, the communication circuit further includes a selector circuit, which switches the conduction of each communication link. The following describes the specific implementation of the selector circuit. Figure 7 , Figure 8 The implementation method is described below.

[0097] like Figure 7 As shown, in some embodiments, the communication circuit of this disclosure example further includes a selector circuit 500. The selector circuit 500 may be a Master Selector chip circuit, which functions to controllably select different communication channels. In one example, the selector circuit 500 may employ a PCA9541 chip.

[0098] In this embodiment of the disclosure, the selector circuit 500 includes two input terminals, namely a first input terminal and a second input terminal, and also includes a first output terminal. The selector circuit 500 can switch the connection between the two input terminals and the first output terminal by modifying the contents of its internal register according to server commands.

[0099] See Figure 7 As shown, the first input terminal of the selector circuit 500 is connected to the connection terminal 200 on the gold finger 110, the second input terminal is connected to the first host port of the board management circuit 300, and the first output terminal is connected to the first slave port of the board management circuit 300 and the second slave port of the target memory 400, respectively.

[0100] In this example implementation, when the server host needs to access the target memory 400, the server host sends a command to the selector circuit 500 through the connection terminal 200 on the board gold finger 110, and gains control by modifying the contents of the internal register of the selector circuit 500, and connects the first input terminal and the first output terminal of the selector circuit 500.

[0101] Reference Figure 7 As shown, after the first input terminal and the first output terminal are connected, the server host can access the board management circuit 300 and the target memory 400 through the selector circuit 500. It can be understood that at this time, both the board management circuit 300 and the target memory 400 are slave devices, and their slave addresses are different. Therefore, based on the slave address carried in the signal sent by the server host, the server host can access the target memory 400 and read the FRU information stored in the target memory 400.

[0102] When the server host needs to access the board management circuit 300, the principle is the same as described above. The difference is that the slave address carried in the signal sent by the server host is the slave address of the board management circuit 300. Thus, the server host can access the board management circuit 300 through the selector circuit 500 and read the single board management information in the board management circuit 300.

[0103] When the board management circuit 300 needs to access the target memory 400, it sends a command to the second input of the selector circuit 500 through the first host port. By modifying the contents of the internal registers of the selector circuit 500, it gains control and connects the second input to the first output of the selector circuit 500. At this time, the board management circuit 300 can access the target memory 400 through the selector circuit 500 via the first host port and read the FRU information stored in the target memory 400.

[0104] As described above, this embodiment enables access and communication between the server host, the board management circuit, and the target memory of the FRU board, thereby improving the communication capabilities between various components on the board. Furthermore, the use of a selector circuit enables communication between components in different power domains, ensuring stable board operation and reducing the risk of component damage during power supply.

[0105] Furthermore, considering that the board management circuit 300 and other devices are located in different power domains, in order to achieve communication stability between devices, a buffer circuit is correspondingly set on the communication circuit when communicating across power domains to improve the stability of data communication. The following section will discuss this in conjunction with... Figure 8 The implementation method is described below.

[0106] like Figure 8As shown, the board management circuit 300 is configured in the main power domain, and the target memory 400 and selector circuit 500 are configured in the auxiliary power domain AUX. The first output terminal of the selector circuit 500 and the first slave port of the board management circuit 300 communicate across power domains through the first buffer circuit (Buffer 1).

[0107] Specifically, the first buffer circuit (Buffer 1) includes a first terminal, a second terminal, and a first enable terminal. The first terminal is configured in the main power domain (Main) and powered by the main power supply circuit. The first terminal is connected to the first slave port of the board management circuit 300. The second terminal is configured in the auxiliary power domain (AUX) and powered by the auxiliary power supply circuit. The second terminal is connected to the first output terminal of the selector circuit 500.

[0108] The first enable terminal refers to the control terminal of the first buffer circuit (Buffer 1). The first enable terminal is enabled by the main power supply, thereby controlling the connection and disconnection between the first and second terminals. When the main power supply is powered on, the first enable terminal is enabled, thus controlling the conduction between the first and second terminals. When the main power supply is powered off, the first enable terminal is disabled, thus disconnecting the first and second terminals.

[0109] Continue to refer to Figure 8 The first host port of the board management circuit 300 is connected to the second input terminal of the selector circuit 500 through the second buffer circuit (Buffer 2) to realize cross-power domain communication.

[0110] Specifically, the second buffer circuit (Buffer 2) includes a third terminal, a fourth terminal, and a second enable terminal. The third terminal is configured in the main power domain (Main) and is powered by the main power supply circuit. The third terminal is connected to the first host port of the board management circuit 300. The fourth terminal is configured in the auxiliary power domain (AUX) and is powered by the auxiliary power supply circuit. The fourth terminal is connected to the second input terminal of the selector circuit 500.

[0111] The second enable terminal refers to the control terminal of the second buffer circuit (Buffer 2). This second enable terminal is powered by the main power supply (Main) and thus controls the connection / disconnection of the third and fourth terminals. When the main power supply (Main) is powered on, the second enable terminal is also powered on, thus controlling the conduction of the third and fourth terminals. When the main power supply (Main) is powered off, the second enable terminal is deactivated, thus disconnecting the third and fourth terminals.

[0112] Figure 8 In the illustrated embodiment, when the main power domain (Main) is powered on, the first and second terminals of the first buffer circuit (Buffer 1) are turned on, and the third and fourth terminals of the second buffer circuit (Buffer 2) are turned on. At this time, the communication circuit operates as follows: Figure 7The same applies to the above, and will not be repeated here.

[0113] When the main power domain (Main) is powered off, the first and second terminals of the first buffer circuit (Buffer 1) are disconnected, and the third and fourth terminals of the second buffer circuit (Buffer 2) are disconnected. At this time, the board management circuit 300 is completely isolated from the auxiliary power domain (AUX) circuit. However, the server host and the target memory 400 can still establish a communication connection through the selector circuit 500. In other words, even when Main is powered off, the server host can still access the target memory 400.

[0114] As described above, this embodiment enables communication between the server host, the board management circuit, and the target memory of the FRU board, improving the communication capabilities between various components on the board. A selector circuit is used to achieve communication between components in different power domains, ensuring stable board operation and reducing the risk of device damage during power supply. Furthermore, when the main power supply (Main) is powered off, the board management circuit is isolated, ensuring normal system operation while the server host can still access the target memory, further enhancing board communication capabilities.

[0115] In the above Figure 7 , Figure 8 In this embodiment, the first slave port of the board management circuit 300 is connected to the first output terminal of the selector circuit 500. In other embodiments, the first slave port of the board management circuit 300 can also be directly connected to the connection terminal 200 of the gold finger 110, which can also realize access communication between the server host, the board management circuit, and the target memory of the FRU board. The following describes the process in conjunction with... Figure 9 The implementation method is described below.

[0116] like Figure 9 As shown, in this embodiment, the first slave port of the board management circuit 300 is connected to the connection terminal 200 of the gold finger 110, and the remaining connection structures are... Figure 7 The implementation method is the same, and those skilled in the art can refer to the foregoing. Figure 7 The implementation methods are readily understood and fully implemented, and will not be elaborated further in this disclosure.

[0117] In this example implementation, the board management circuit 300 can be directly connected to the server host via the connection terminal 200, without going through the selector circuit 500. When the server host needs to access the board management circuit 300, it can directly access the board management circuit 300 through the connection terminal on the board's gold fingers 110.

[0118] When the server host needs to access the target memory 400, it sends a command to the selector circuit 500 through the connection terminal 200 on the board's gold finger 110. By modifying the contents of the selector circuit 500's internal registers, it gains control and connects the first input and first output terminals of the selector circuit 500. Its principle is similar to... Figure 7 The implementation method is the same, and will not be described again here.

[0119] When the board management circuit 300 needs to access the target memory 400, it sends a command to the second input of the selector circuit 500 through the first host port. By modifying the contents of the internal registers of the selector circuit 500, it gains control and connects the second input to the first output of the selector circuit 500. Its principle is similar to... Figure 7 The implementation method is the same, and will not be described again here.

[0120] As described above, this embodiment enables access and communication between the server host, the board management circuit, and the target memory of the FRU board, thereby improving the communication capabilities between various components on the board. Furthermore, the use of a selector circuit enables communication between components in different power domains, ensuring stable board operation and reducing the risk of component damage during power supply.

[0121] Similarly, in Figure 9 In this implementation, the board management circuit 300 and other devices are located in different power domains. To ensure communication stability between devices, a buffer circuit is correspondingly set on the communication circuit when communicating across power domains, thereby improving the stability of data communication. The following section will describe this in conjunction with... Figure 10 The implementation method is described below.

[0122] like Figure 10 As shown, the board management circuit 300 is configured in the main power domain, while the target memory 400 and the selector circuit 500 are configured in the auxiliary power domain (AUX). The first slave port of the board management circuit 300 is connected to the connection terminal 200 via a first buffer circuit (Buffer 1) to achieve cross-power domain communication. The first master port of the board management circuit 300 is connected to the second input terminal of the selector circuit 500 via a second buffer circuit (Buffer 2) to achieve cross-power domain communication.

[0123] The working principles of the various devices in the communication circuit can be understood and fully implemented by those skilled in the art by referring to the foregoing, and this disclosure will not elaborate further.

[0124] In some implementations, the selector circuit 500 can be implemented using a PCA9541 chip. Figure 11The circuit structure of the PCA9541 chip is shown. Those skilled in the art can understand and fully implement it by referring to relevant technologies, and this disclosure will not elaborate further.

[0125] In some embodiments, the communication circuits in the various embodiments of this disclosure above may use an I2C (Inter-Integrated Circuit, synchronous serial communication) bus for communication between devices.

[0126] As described above, this embodiment enables communication between the server host, the board management circuit, and the target memory of the FRU board, improving the communication capabilities between various components on the board. A selector circuit is used to achieve communication between components in different power domains, ensuring stable board operation and reducing the risk of device damage during power supply. Furthermore, when the main power supply (Main) is powered off, the board management circuit is isolated, ensuring normal system operation while the server host can still access the target memory, further enhancing board communication capabilities.

[0127] Secondly, embodiments of this disclosure provide a board that may include the communication circuit described in any of the above embodiments. This board may be of any type, such as a PCIe board, and this disclosure does not impose any limitations on it.

[0128] The circuit structure and working principle of the board in the embodiments of this disclosure can be understood and fully implemented by those skilled in the art by referring to the board 100 in any of the foregoing embodiments, and will not be described again in this disclosure.

[0129] Thirdly, this disclosure provides an electronic device, including: the board described in any of the above embodiments.

[0130] As described above, the board in this embodiment enables communication between the server host, the board management circuit, and the target memory of the FRU board, improving the communication capabilities between the various components of the board. Furthermore, since the server can access all the data information of the board, and the board management circuit can also access the FRU information of the board, this helps monitor the board's operating status, ensures the normal operation of the server, and improves communication performance.

[0131] Obviously, the above embodiments are merely examples for clear illustration and are not intended to limit the embodiments. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all embodiments here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this disclosure.

Claims

1. A communication circuit, characterized in that, include: Connection terminals, suitable for establishing communication connections with external devices; The board management circuit includes a first slave port and a first master port; The target memory is configured with a second slave port and is used to store relevant information of the target device; The selector circuit includes a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal and the second input terminal are controlled to switch to communication with the first output terminal, wherein the connection terminal is connected to the first input terminal, the first master port is connected to the second input terminal, and the first output terminal is connected to the first slave port and the second slave port; The board management circuit is located in the main power domain and is powered by the main power circuit; the target memory and the selector circuit are located in the auxiliary power domain and are powered by the auxiliary circuit.

2. The communication circuit according to claim 1, characterized in that... When the board management circuit receives an access signal from an external device through the first slave port, it determines the target device based on the slave address carried by the access signal. In response to the target device being the board management circuit, the board management circuit establishes data communication with the external device.

3. The communication circuit according to claim 1, characterized in that, When the board management circuit receives an access signal from an external device through the first slave port, it determines the target device based on the slave address carried by the access signal. In response to the target device being the target memory, the board management circuit sends the access signal to the target memory through the first host port, receives the return signal from the target memory, and sends the return signal to the external device through the first slave port.

4. The communication circuit according to claim 1, characterized in that, The connection terminal is connected to the first slave port of the board management circuit via a first bus, and the first master port of the board management circuit is connected to the second slave port of the target memory via a second bus. The first bus includes an SMBUS bus or an I2C bus, and the second bus includes an I2C bus or an SPI bus.

5. The communication circuit according to claim 1, characterized in that, The board management circuit includes an MCU chip circuit, and the power supply of the MCU chip circuit is no greater than 3.3V.

6. The communication circuit according to claim 1, characterized in that, The first slave port of the board management circuit is connected to the first output terminal or the connection terminal through the first buffer circuit. The first buffer circuit includes a first terminal, a second terminal, and a first enable terminal. The first terminal is connected to the first slave port, the second terminal is connected to the first output terminal or the connection terminal, and the first enable terminal is enabled by the main power supply circuit to control the on / off state of the first terminal and the second terminal.

7. The communication circuit according to claim 6, characterized in that, The first buffer circuit further includes a first port power supply for supplying power to the first end and a second port power supply for supplying power to the second end. The first port power supply is connected to the main power supply circuit, and the second port power supply is connected to the auxiliary power supply circuit.

8. The communication circuit according to claim 1, characterized in that, The first host port of the board management circuit is connected to the second input terminal of the selector circuit through the second buffer circuit; The second buffer circuit includes a third terminal, a fourth terminal, and a second enable terminal. The third terminal is connected to the first host port, the fourth terminal is connected to the second input terminal, and the second enable terminal is powered by the main power supply circuit to control the on / off state of the third terminal and the fourth terminal.

9. The communication circuit according to claim 8, characterized in that, The second buffer circuit also includes a third port power supply for supplying power to the third terminal and a fourth port power supply for supplying power to the fourth terminal. The third port power supply is connected to the main power supply circuit, and the fourth port power supply is connected to the auxiliary power supply circuit.

10. A circuit board, characterized in that, include: The communication circuit according to any one of claims 1 to 9; and The gold fingers are adapted for pluggable communication with the slot of the external device, and the connection terminals are provided on the gold fingers.

11. An electronic device, characterized in that, include: The board according to claim 10.

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