Gating methods for stacked structures, storage devices, and chips.

Abstract

This disclosure provides a stacked structure, a storage device, and a chip selection method. The stacked structure includes N stacked chip groups, each chip group including M stacked chip layers, and each chip group including a specific group identification signal and a selection circuit. Each selection circuit is used to match the group identification signal of the corresponding chip group with an input group selection signal and output a selection signal to the corresponding chip group. The selection signal is used to control the selection state of the chip in the corresponding chip group. N and M are both positive integers.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a gating method for a stacked structure, a memory device, and a chip. Background Technology

[0002] High-bandwidth memory (HBM) comprises multiple stacked chips. In related technologies, when selecting chips in HBM by group, it is typically necessary to pre-program different fuse information into each layer of chips, and use this fuse information as the storey identifier (SID) signal for each chip. When the received group selection signal matches the chip's group identifier signal, the corresponding chip is selected, thus achieving chip selection by group.

[0003] However, due to the complexity of chip stacking technology and the fact that the yield varies on each chip, it is impossible to predict in advance how many chips are needed for each group of identification signals (SIDs) at the single wafer stage. Therefore, in related technologies, the scheme of selecting chips by group in multi-layer stacked chips involves considerable complexity in material management before stacking. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a method for selecting a stacked structure, a storage device, and a chip.

[0005] In a first aspect, embodiments of this disclosure provide a stacked structure, comprising: N stacked chip groups, each chip group including M stacked chip layers, each chip group including a specific group identification signal and a gating circuit; each gating circuit is configured to: match the group identification signal of the corresponding chip group with an input group gating signal, and output a gating signal to the corresponding chip group, the gating signal being used to control the gating state of the chip in the corresponding chip group; wherein, N and M are both positive integers.

[0006] In some embodiments, when the group identifier signal of the chipset matches the input group gating signal, the gating circuit outputs a first sub-gating signal, which is used to control the chips of the chipset to be in a gated state; when the group identifier signal of the chipset does not match the input group gating signal, the gating circuit outputs a second sub-gating signal, which is used to control the chips of the chipset to be in a de-gated state.

[0007] In some embodiments, the gating circuit includes a logic operation circuit, which is used to perform an XOR operation on the group identifier signal and the group gating signal and output a gating signal to the corresponding chipset according to the result of the XOR operation.

[0008] In some embodiments, the gating circuit includes a selection circuit, which is used to select a group of signals to be selected based on the group identification signal, and output a gating signal to the corresponding chipset according to the selection result; wherein the group of signals to be selected is obtained by decoding the group gating signal.

[0009] In some embodiments, each of the gating circuits includes M gating sub-circuits, and each layer of the chip includes one gating sub-circuit. The gating sub-circuit is used to match the group identification signal and the group gating signal and output a gating signal to the corresponding chip.

[0010] In some embodiments, the gating sub-circuit includes: a logic operation circuit, which is used to perform an XOR operation on the group identification signal and the group gating signal and output a gating signal to the corresponding chip according to the result of the XOR operation.

[0011] In some embodiments, the logic operation circuit includes: at least two XOR gates and an AND gate connected to each of the XOR gates; wherein the XOR gates are used to perform an XOR operation on the same signal bit of the group identification signal and the group strobe signal; and the AND gates are used to perform an AND operation on the result of each XOR operation and output the strobe signal.

[0012] In some embodiments, the gating sub-circuit includes: a selection circuit, which is used to select a group of signals to be selected based on the group identification signal, and output a gating signal to the corresponding chip according to the selection result; wherein the group of signals to be selected is obtained by decoding the group gating signal.

[0013] In some embodiments, each chipset further includes an adder, configured to: add a preset integer value to the group identifier signal of the chipset to obtain the group identifier signal of the next chipset, and transmit the group identifier signal of the next chipset to the adder and the gating circuit in the next chipset respectively, wherein the group identifier signal of the first chipset is the input initial group identifier signal.

[0014] In some embodiments, the stacked structure further includes a first transmission structure and a second transmission structure; wherein, the first transmission structure is used to: transmit the initial group identification signal to the adder in the first group of chipsets; and transmit the group identification signal of the (n+1)th group of chipsets output by the adder in the (n+1)th group of chipsets to the gating circuit and the adder in the (n+1)th group of chipsets respectively; the second transmission structure is used to electrically connect the N groups of chipsets and transmit the group gating signal to each of the gating circuits; wherein n is an integer greater than 0 and less than N.

[0015] In some embodiments, each adder includes M sub-adders, and each layer of the chip includes one sub-adder. The sub-adder is used to add a preset integer value to the group identifier signal of its own chip group to obtain the group identifier signal of the next chip group, and transmits it to the sub-adder of the chip in the corresponding layer of the next chip group and the gating circuit of the next chip group, respectively.

[0016] In some embodiments, the stacked structure further includes a third transmission structure and a fourth transmission structure; wherein, the third transmission structure is used to: transmit the initial group identification signal to the sub-adder of each layer of the first chipset and the gating circuit of the first chipset; transmit the group identification signal of the (n+1)th chipset output by the sub-adder of each layer of the nth chipset to the sub-adder of each layer of the (n+1)th chipset and the gating circuit of the (n+1)th chipset respectively; the fourth transmission structure is used to electrically connect the N chipsets and transmit the group gating signal to each of the gating circuits; where n is an integer greater than 0 and less than N.

[0017] In some embodiments, the third transmission structure includes M third transmission substructures; wherein the m-th third transmission substructure is used to: electrically connect the m-th layer chip in each chipset; transmit the initial group identification signal to the sub-adder of the m-th layer chip in the first chipset and the gating circuit of the first chipset; transmit the group identification signal of the (n+1)-th chipset output by the sub-adder of the m-th layer chip in the n-th chipset to the sub-adder of the m-th layer chip in the (n+1)-th chipset and the gating circuit of the (n+1)-th chipset; where m is an integer greater than 0 and less than M+1.

[0018] In some embodiments, the third transport substructure includes a first through-silicon via (TSV), and the fourth transport structure includes a second TSV.

[0019] In some embodiments, the first through-silicon via (TSV) includes at least two first sub-TSVs, and each first sub-TSV is used to transmit a signal bit of the group identification signal; the second TSV includes at least two second sub-TSVs, and each second sub-TSV is used to transmit a signal bit of the group strobe signal.

[0020] In some embodiments, N is 2, M is 4, the first through-silicon via includes 2 first sub-through-silicon vias, the second through-silicon via includes 2 second sub-through-silicon vias, and the initial group identification signal is 00.

[0021] In some embodiments, the stacked structure further includes: a first driving circuit connected to each of the gating circuits, for receiving and transmitting the group gating signal to each of the gating circuits; and / or a second driving circuit connected to each of the gating circuits, for receiving and transmitting a group identifier signal of each chipset to the corresponding chipset gating circuit.

[0022] In some embodiments, both the first driving circuit and the second driving circuit include an amplifier or an inverter chain.

[0023] In a second aspect, embodiments of this disclosure provide a storage device, including: a packaging substrate, an interposer layer located on the packaging substrate, a processor, and a stacked structure as described in any of the above embodiments; wherein the stacked structure and the processor are electrically connected through the interposer layer, and the processor is configured to: acquire a group strobe signal of a chip to be accessed and a set initial group identifier signal; transmit the initial group identifier signal to the stacked structure so that the strobe circuit of each chip group in the stacked structure receives the group identifier signal of the corresponding chip group; transmit the group strobe signal to the stacked structure to select the chip in the stacked structure whose group identifier signal matches the group strobe signal.

[0024] Thirdly, embodiments of this disclosure provide a chip selection method, comprising: acquiring a group selection signal of a chip to be accessed and a set initial group identifier signal; transmitting the initial group identifier signal to the stacked structure described in any of the above embodiments, so that the selection circuit of each chip group in the stacked structure receives the group identifier signal of the corresponding chip group; and transmitting the group selection signal to the stacked structure to select chips in the stacked structure whose group identifier signal matches the group selection signal.

[0025] In this embodiment of the present disclosure, each of the N stacked chipsets includes M stacked layers of chips. Each chipset includes a specific group identification signal and a gating circuit. The gating circuit can match the group identification signal of the corresponding chipset with the input group gating signal and output a gating signal to the corresponding chipset to control the gating state of the chips in the corresponding chipset. This allows for simple and quick selection of the required chipset and the chips in the chipset. Attached Figure Description

[0026] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0027] Figure 1 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0028] Figure 2 A schematic diagram of the composition structure of a logic operation circuit provided in an embodiment of this disclosure;

[0029] Figure 3 A schematic diagram of the composition structure of a selection circuit provided in an embodiment of this disclosure;

[0030] Figure 4 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0031] Figure 5 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0032] Figure 6 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0033] Figure 7 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0034] Figure 8 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0035] Figure 9 This is a schematic diagram of the composition of a stacked structure provided in an embodiment of the present disclosure;

[0036] Figure 10 This is a schematic diagram of the composition structure of a storage device provided in an embodiment of the present disclosure;

[0037] Figure 11 This is a schematic diagram illustrating the implementation process of a chip selection method provided in an embodiment of this disclosure. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] This disclosure provides a stacking structure, with reference to... Figure 1 The stacked structure 100 includes:

[0044] N stacked chip groups 10, ..., n0, ..., N0; each chip group includes M stacked layers of chips. For example, chip group 10 includes chip 101, chip 102, ..., chip 10m, ..., chip 10M; chip group n0 includes chip n01, chip n02, ..., chip n0m, ..., chip n0M; chip group N0 includes chip N01, chip N02, ..., chip N0m, ..., chip N0M.

[0045] Each chipset includes a specific group identification signal and a gating circuit; each gating circuit is used to: match the group identification signal of the corresponding chipset with the input group gating signal, and output a gating signal to the corresponding chipset, the gating signal being used to control the gating state of the chips in the corresponding chipset.

[0046] Where N and M are both positive integers.

[0047] Continue to refer to Figure 1 Chipset 10 includes a specific group identification signal SID11 and a gating circuit 11. The gating circuit 11 matches the group identification signal SID11 with the input group gating signal SID2 and outputs a gating signal to the chipset 10. Chipset n0 includes a specific group identification signal SID1n and a gating circuit n1. The gating circuit n1 matches the group identification signal SID1n with the input group gating signal SID2 and outputs a gating signal to the chipset n0. Chipset N0 includes a specific group identification signal SID1N and a gating circuit N1. The gating circuit N1 matches the group identification signal SID1N with the input group gating signal SID2 and outputs a gating signal to the chipset N0.

[0048] It should be noted that the number N of stacked chipsets can be 2, 3, 4, etc., and the number M of chips in a chipset can vary depending on the design of the semiconductor device; this disclosure does not limit this. When N equals 2 and M equals 4, the stacked structure can be an 8-layer HBM; when N equals 4 and M equals 4, the stacked structure can be a 16-layer HBM. In the stacked structure, adjacent chipsets and adjacent chips within each chipset can be connected via vias and bumps.

[0049] The chips in the chipset can be Dynamic Random Access Memory (DRAM) chips, Static Random Access Memory (SRAM) chips, NOR flash memory chips, NAND flash memory chips, etc. This disclosure does not limit the type of chip; the chips in the same chipset can be of the same or different types. In implementation, it is necessary to ensure that the chips in the stacked structure can fulfill the design task. The chips may include a cell array for storing data and circuitry for writing data to and reading data from the cell array.

[0050] The group identifier signal is the identifier signal for each chipset group, used to mark different chipsets. Each layer of chips in the chipset has the same identifier signal. In implementation, the group identifier signal can include 1, 2, or 3 signal bits, which can be denoted as SID[0], SID[1:0], SID[2:0], etc. When the group identifier signal includes two signal bits, the group identifier signal can have 4 possible values: 00, 01, 10, and 11. That is, L (L is a positive integer) signal bits can correspond to 2 L Group identification signal, can mark 2 L Each chipset. During implementation, the number of signal bits for the group identifier can be selected based on the number of chipset groups. For example, when the chipset has 4 groups, a group identifier signal with 2 signal bits can be selected, or a group identifier signal with more than 2 signal bits can be selected.

[0051] Group strobe signals can be based on processor inputs from processing events or can be manually set. Group strobe signals can be the same as or different from a group identification signal.

[0052] The gating circuit can be any circuit that can match the group identifier signal and the group gating signal and output a gating signal to the chipset. For example, it can be a selection circuit or a logic operation circuit. This part will be described in detail later.

[0053] The gating circuit for each chipset can be located in any chip within the chipset, for example, in the first layer of chips in each chipset. The gating signal output by the gating circuit to the chipset can be transmitted through a transmission structure to each chip in the chipset, thereby enabling or disabling each chip in the chipset.

[0054] In this embodiment of the present disclosure, each of the N stacked chipsets includes M stacked layers of chips. Each chipset includes a specific group identification signal and a gating circuit. The gating circuit can match the group identification signal of the corresponding chipset with the input group gating signal and output a gating signal to the corresponding chipset to control the gating state of the chips in the corresponding chipset. This allows for simple and quick selection of the required chipset and the chips in the chipset.

[0055] The gating circuit in each chip layer outputs a gating signal for the corresponding chip, which can be used to control the corresponding chip to be in a gated or de-gated state. Therefore, in some embodiments, when the group identifier signal of the chipset matches the input group gating signal, the gating circuit outputs a first sub-gating signal, which is used to control the chip in the chipset to be in a gated state; when the group identifier signal of the chipset does not match the input group gating signal, the gating circuit outputs a second sub-gating signal, which is used to control the chip in the chipset to be in a de-gated state.

[0056] In this embodiment of the disclosure, when the gating circuit outputs the first sub-gating signal, the corresponding chip is in a gating state. In this way, the processor can interact with the chip to perform data reading and / or storage operations on the chip, such as reading data from the chip or storing data into the chip.

[0057] In some embodiments, the gating circuit includes a logic operation circuit, which performs an XOR operation on the group identifier signal and the group gating signal and outputs a gating signal to the corresponding chipset based on the result of the XOR operation.

[0058] Taking the gating circuit 11 in chipset 10 as an example, and referring to... Figure 1 and Figure 2 , Figure 2 This is a schematic diagram of the structure of the logic operation circuit 111. The gating circuit 11 includes the logic operation circuit 111, which performs an XOR operation on the group identifier signal SID11 and the group gating signal SID2, and outputs a gating signal to the corresponding chipset 10 based on the result of the XOR operation. The gating circuits in other chipsets can be understood by referring to the gating circuit 11 in chipset 10.

[0059] In implementation, the logic operation circuit includes at least two XOR gates and an AND gate connected to each XOR gate. The XOR gates perform an XOR operation on the same signal bit in the group identifier signal and the group strobe signal. The AND gates perform an AND operation on the result of each XOR operation and output the strobe signal. This simple structure of XOR gates and AND gates allows for the selection of the corresponding chip, thus simplifying the composition of the stacked structure.

[0060] It should be noted that the number of XOR gates can be the same as the number of signal bits of the group identifier signal and the group strobe signal.

[0061] When the group identifier signal SID11 and the group strobe signal SID2 both include two signal bits (e.g., group identifier signal SID11 is 00 and group strobe signal SID2 is 01), refer to Figure 2 The logic operation circuit 111 may include two XOR gates 1111 and one AND gate 1112. One XOR gate 1111 performs an XOR operation on the signal 0 on the first signal bit of the group identifier signal SID11 and the signal 0 on the first signal bit of the group strobe signal SID2, with a result of 1. The other XOR gate 1111 performs an XOR operation on the signal 0 on the second signal of the group identifier signal SID11 and the signal 1 on the second signal of the group strobe signal SID2, with a result of 0. The two inputs of the AND gate 1112 are used to input the results of the two XOR gates 1111, 0 and 1, respectively. The output result of the AND gate 1112, i.e., the strobe signal, is 0, which means that the group identifier signal SID11 and the group strobe signal SID2 do not match. Therefore, the chipset 10 is not selected.

[0062] In some embodiments, the gating circuit includes: a selection circuit, which is used to select a group of signals to be selected based on a group identifier signal, and output a gating signal to the corresponding chipset according to the selection result; wherein, the group of signals to be selected is obtained by decoding the group gating signal.

[0063] Here, the group identifier signal is used as the input signal for the control terminal of the selection circuit. For example, when the selection circuit includes an N-to-1 data selector, the group identifier signal serves as the address input signal of the N-to-1 data selector, thereby controlling the N-to-1 data selector to output the corresponding selectable signal. Different group identifier signals can control the output of different signals.

[0064] In this embodiment of the disclosure, a selection circuit is used to select a group of signals to be selected based on a group identifier signal, and a gating signal is output to the corresponding chipset according to the selection result to select the corresponding chipset. This provides another way to implement the gating circuit, so that it can be flexibly selected.

[0065] Taking the gating circuit 11 in chipset 10 as an example, and referring to... Figure 1 and Figure 3 , Figure 3The diagram illustrates the structural composition of selection circuit 112. Selection circuit 11 includes a selection circuit 112, which selects a group of signals Y (including signals Y1, Y2, Y3, and Y4) to be selected based on group identifier signal SID11, and outputs a strobe signal to the corresponding chipset 10 according to the selection result. The group of signals Y to be selected is obtained by decoding the group strobe signal SID2. The selection circuits 112 in other chipsets can be understood by referring to the selection circuit 112 in chipset 11.

[0066] Here, the method for obtaining a set of selectable signals Y is explained. In implementation, the strobe signal SID2 can be transmitted to the decoding circuit to obtain a set of selectable signals Y. In some embodiments, the decoding circuit can be a circuit composed of multiple logic gates, such as a circuit composed of multiple AND gates and NOT gates.

[0067] In implementation, a decoder can be used to decode the group strobe signal to obtain a set of signals to be selected. The type of decoder can be selected according to the number of signal bits of the group strobe signal. For example, if the number of signal bits of the group strobe signal is 2, then the decoder type can be a 2-line to 4-line decoder. 2 lines means that the decoder has two input terminals, and 4 lines means that the decoder has four output terminals.

[0068] For example, when the strobe signal SID2 is SID2[1:0], it can be decoded by a 2-line to 4-line decoder, which has four outputs. When SID2 is 00, only the first output outputs a high level 1 (assuming high level is active), and the other outputs output a low level 0, so Y1, Y2, Y3, and Y4 are 1, 0, 0, and 0 respectively; when SID2 is 01, only the second output outputs 1, and the other outputs output 0, so Y1, Y2, Y3, and Y4 are 0, 1, 0, and 0 respectively; when SID2 is 10, only the third output outputs 1, and the other outputs output 0, so Y1, Y2, Y3, and Y4 are 0, 0, 1, and 0 respectively; when SID2 is 11, only the fourth output outputs 1, and the other outputs output 0, so Y1, Y2, Y3, and Y4 are 0, 0, 0, and 1 respectively.

[0069] In some embodiments, if the low level is active, for each group strobe signal SID2, only one output of the decoder is 0, and the rest are 1.

[0070] In implementation, the selection circuit may include a data selector 1121. The type of data selector can be selected based on the number of outputs of the decoder (i.e., the number of signals in a set of selectable signals). For example, if a set of selectable signals includes four signals, such as 1, 0, 0, and 0 respectively, and the decoder is a 2-to-4 line decoder with four outputs, the selector type can be a 4-to-1 data selector. The four inputs of the data selector 1121 are used to connect to the four outputs of the decoder, see reference [reference]. Figure 3 Y1, Y2, Y3, and Y4 are transmitted to the four input terminals RX1, RX2, RX3, and RX4 of the data selector 1121, respectively. The set of selectable signals Y obtained by encoding the strobe signals will be used as the input signals of the four-to-one data selector. The data channel is selected based on the group identifier signal, thereby selecting one signal from the set of selectable signals for output.

[0071] The explanation will be based on the selection circuit 112 in chipset 10. When the group identifier signal SID11 and the group strobe signal SID2 of chipset 10 are 00, the decoder outputs a set of selectable signals 1, 0, 0 and 0. Thus, the first data channel of the 4-to-1 data selector is selected and connected to the corresponding first input terminal, thereby outputting the signal of the first input terminal, i.e., signal 1. Since it is active high, chipset 10 will be selected.

[0072] In some embodiments, each gating circuit includes M gating sub-circuits, and each chip layer includes one gating sub-circuit. The gating sub-circuit is used to match the group identification signal and the group gating signal and output a gating signal to the corresponding chip.

[0073] Figure 4 The stacked structure includes two chipsets, each consisting of four stacked layers of chips. Figure 4 This is a schematic diagram of the stacking structure with N equal to 2 and M equal to 4 as an example. See below for reference. Figure 4 The gating sub-circuit in the stacked structure is explained.

[0074] The stacked structure 100 includes two stacked chipsets 10 and 20. Chipset 10 includes four stacked layers of chips 101, 102, 103, and 104; wherein chip 101 is located on the first layer, chip 102 on the second layer, chip 103 on the third layer, and chip 104 on the fourth layer. Chipset 20 includes four stacked layers of chips 201, 202, 203, and 204; wherein chip 201 is located on the first layer, chip 202 on the second layer, chip 203 on the third layer, and chip 204 on the fourth layer.

[0075] Chipset 10 includes a gating circuit 11, which includes four gating sub-circuits 11a. Chips 101, 102, 103, and 104 each include one gating sub-circuit 11a. Therefore, the gating circuit 11 may include four gating sub-circuits 11a.

[0076] Chipset 20 includes a gating circuit 21, which includes four gating sub-circuits 21a. Chips 201, 202, 203, and 204 each include one gating sub-circuit 21a. Therefore, the gating circuit 21 may include four gating sub-circuits 21a.

[0077] In some embodiments, the gating sub-circuit includes: a logic operation circuit, which performs an XOR operation on the group identifier signal and the group gating signal and outputs a gating signal to the corresponding chip according to the result of the XOR operation.

[0078] Here, the logic operation circuit in the selection sub-circuit can be understood by referring to the logic operation circuit in the selection circuit. The difference between them is that the logic operation circuit in the selection sub-circuit outputs a selection signal to the corresponding chip, while the logic operation circuit in the selection circuit outputs a selection signal to the corresponding chipset.

[0079] In some embodiments, the gating sub-circuit includes: a selection circuit, which is used to select a group of signals to be selected based on a group identifier signal, and output a gating signal to the corresponding chip according to the selection result; wherein, the group of signals to be selected is obtained by decoding the group gating signal.

[0080] Here, the selection circuit in the selection sub-circuit can be understood by referring to the selection circuit in the selection circuit. The difference between them is that the selection circuit in the selection sub-circuit outputs a selection signal to the corresponding chip, while the selection circuit in the selection circuit outputs a selection signal to all chips in the corresponding chip group.

[0081] In some embodiments, each chipset further includes an adder, configured to add a preset integer value to the group identifier signal of the chipset to obtain the group identifier signal of the next chipset, and transmit the group identifier signal of the next chipset to the adder and the gating circuit in the next chipset respectively, wherein the group identifier signal of the first chipset is the input initial group identifier signal.

[0082] It should be noted that the gating circuit here can be the gating circuit in the chipset (which can be a logic operation circuit or a selection circuit), or it can be the gating sub-circuit included in the gating circuit in the chipset.

[0083] In this embodiment, the adder can be any structure capable of adding a preset integer value to the group identifier signal of the nth chipset to obtain the group identifier signal of the next chipset. The preset integer value can be a positive integer or a negative integer. For example, the initial group identifier signal can be 11, and the group identifier signal of the second chipset can be the result of adding a negative 1 to the adder, which is 10. For example, the initial group identifier signal can be 00, and the group identifier signal of the second chipset can be the result of adding a positive 1 to the adder, which is 01.

[0084] In this embodiment, each chipset includes an adder. After an initial group identification signal is input, the initial group identification signal automatically becomes the group identification signal of the first chipset. Each layer of chip in the first chipset has an identification signal, which is the group identification signal of the chipset it belongs to. The adder in the first chipset adds a preset value to the initial group identification signal to obtain the group identification signal of the second chipset, and so on. Each chipset will obtain a group identification signal. In this way, the identification signal of each chipset or each layer of chip in the chipset can be quickly obtained without pre-programming fuse information for each chipset, thereby saving time and simplifying the material management operation before stacking.

[0085] Continue to refer to Figure 1 Chipset 10 also includes adder 12, which adds a preset integer value to the initial group identifier signal SID1 (i.e., the group identifier signal SID11 of the first chipset 10) to obtain the group identifier signal of the second chipset. Chipset n0 also includes adder n2, and chipset N0 also includes adder N2.

[0086] In some embodiments, the stacked structure further includes a first transmission structure and a second transmission structure.

[0087] The first transmission structure is used to: transmit the initial group identifier signal to the adder in the first group of chipsets; and transmit the group identifier signal of the next group of chipsets output by the adder in the nth group of chipsets to the gating circuit and adder in the next group of chipsets respectively.

[0088] The second transmission structure is used to electrically connect N groups of chipsets and transmit the group selection signal to each selection circuit.

[0089] n is an integer greater than 0 and less than N.

[0090] refer to Figure 5 The stacked structure 100 further includes: a first transmission structure 120 and a second transmission structure 130; wherein:

[0091] The first transmission structure 120 is used to: transmit the initial group identification signal SID1 (i.e., the group identification signal SID11 of the first chipset 10) to the adder 12 in the chipset 10; and transmit the group identification signal of the next chipset output by the adder n2 in the nth chipset n0 to the gating circuit and adder in the next chipset respectively.

[0092] The second transmission structure 130 is used to electrically connect N groups of chipsets (including 10, ..., n0, ..., N0) and transmit the group selection signal SID2 to each selection circuit (including 11, ..., n1, ..., N1).

[0093] In some embodiments, each adder includes M sub-adders, and each layer of chips includes one sub-adder. The sub-adder is used to add a preset integer value to the group identifier signal of its own chipset to obtain the group identifier signal of the next chipset, and transmits it to the sub-adder of the corresponding layer of the chip in the next chipset and the gating circuit in the next chipset.

[0094] It should be noted that the gating circuit here can be the gating circuit in the chipset, or the gating sub-circuit included in the gating circuit in the chipset.

[0095] refer to Figure 6 Adder 12 includes M sub-adders 12a, adder n2 includes M sub-adders n2a, and adder N2 includes M sub-adders N2a. Each chip layer includes one sub-adder. Taking the sub-adder 12a in chip 101 of chipset 10 as an example, its function is explained as follows: the sub-adder 12a in chip 101 is used to add a preset value to the group identifier signal SID11 (i.e., the initial group identifier signal SID1) of chipset 10 to obtain the group identifier signal of the second chipset, and then transmits the group identifier signal of the second chipset to the sub-adder of the first layer chip in the second chipset and the gating circuit in the second chipset.

[0096] In some embodiments, the stacked structure further includes a third transmission structure and a fourth transmission structure.

[0097] The third transmission structure is used to: transmit the initial group identification signal to the sub-adder of each layer of the first chip group and the gating circuit of the first chip group; and transmit the group identification signal of the (n+1)th chip group output by the sub-adder of each layer of the nth chip group to the sub-adder of each layer of the (n+1)th chip group and the gating circuit of the (n+1)th chip group respectively.

[0098] The fourth transmission structure is used to electrically connect N groups of chipsets and transmit group selection signals to each selection circuit; n is an integer greater than 0 and less than N.

[0099] Continue to refer to Figure 6 The stacked structure 100 includes a third transmission structure 140 and a fourth transmission structure 150.

[0100] Wherein: the third transmission structure 140 is used to: transmit the initial group identification signal SID1 (that is, the group identification signal SID11 of the first group of chipsets 10) to the sub-adder 12a of each layer of chips in chipset 10 and the gating circuit 11 of the first group of chipsets 10; and transmit the group identification signal of the (n+1)th group of chipsets output by the sub-adder n2a of each layer of chips in the (n+1)th group of chipsets to the sub-adder of each layer of chips in the (n+1)th group of chipsets and the gating circuit of the (n+1)th group of chipsets respectively.

[0101] The fourth transmission structure 150 is used to electrically connect N groups of chipsets (including 10, ..., n0, ..., N0) and transmit the group selection signal SID2 to each selection circuit (including 11, ..., n1, ..., N1).

[0102] In some embodiments, the third transmission structure includes M third transmission substructures. The m-th third transmission substructure is used to: electrically connect the m-th layer chip in each chipset; transmit the initial group identification signal to the sub-adder of the m-th layer chip in the first chipset and the gating circuit of the first chipset; and transmit the group identification signal of the (n+1)-th chipset output by the sub-adder of the m-th layer chip in the (n+1)-th chipset to the sub-adder of the m-th layer chip in the (n+1)-th chipset and the gating circuit of the (n+1)-th chipset.

[0103] Here, m is an integer greater than 0 and less than M+1. In implementation, the number of third transport substructures can be determined based on the number of chipsets in each chipset group.

[0104] refer to Figure 7 The third transmission structure 140 includes four third transmission substructures 1401, 1402, 1403, and 1404. Taking m=1 as an example, the third transmission substructure is described as follows: Third transmission substructure 1401 is used to: electrically connect the first layer chips 101, ..., n0, ..., N0 in chipsets 10, ..., n01, ..., N01; and transmit the initial group identifier signal SID1 to the sub-adder 12a of the first layer chip 101 in the first chipset 10 and the gating circuit 11 of the first chipset 10. It also transmits the group identifier signal of the (n+1)th chipset, output from the sub-adder n2a of the m-th layer chip n0m in the n-th chipset n0, to the sub-adder of the first layer chip in the (n+1)th chipset and the gating circuit of the (n+1)th chipset. Third transmission substructures 1402, 1403, and 1404 are similar to third transmission substructure 1401.

[0105] It should be noted that, in order to more intuitively understand each third transmission substructure, Figure 7 The third transport substructure shown is spiral-shaped; in practice, the first transport substructure can also be vertical.

[0106] In some embodiments, the third transmission substructure may include a first through-silicon via (TSV), and the fourth transmission structure may include a second TSV. Since TSVs are vertical interconnects between chips, using TSVs as the third and fourth transmission substructures can reduce interconnect length, thereby reducing signal delay and capacitance. This enables low-power, high-speed communication between chips, increases bandwidth, and facilitates miniaturization of device integration.

[0107] In some embodiments, the third transmission substructure may include a spiral TSV, which can reduce the need for channel selection and complex wiring.

[0108] In implementation, the first through-silicon via (TSV) may include at least two first sub-TSVs, each of which is used to transmit one signal bit of the group identification signal; the second TSV may include at least two second sub-TSVs, each of which is used to transmit one signal bit of the group strobe signal. In implementation, the number of first sub-TSVs can be determined based on the number of signal bits in the group identification signal. For example, if the group identification signal has three signal bits, then three first sub-TSVs are required. Transmitting one signal bit of the group identification signal through one first sub-TSV and one signal bit of the group strobe signal through one second sub-TSV reduces crosstalk between different signal bits, thereby reducing the likelihood of errors during signal transmission.

[0109] In some embodiments, N is 2, M is 4, the first through-silicon via includes 2 first sub-through-silicon vias, and the second through-silicon via includes 2 second sub-through-silicon vias; the initial group identification signal is 00.

[0110] During implementation, the initial group identifier signal is 00. Therefore, the group identifier signal of the first chipset and the identifier of each layer of chips in the first chipset are both 00. The sub-adder in the first layer of the first chipset adds 1 to the initial group identifier signal 00 to obtain the identifier signal 01 for the first layer of the second chipset. Similarly, the sub-adder in the second layer of the first chipset adds 1 to the initial group identifier signal 00 to obtain the identifier signal 01 for the second layer of the second chipset. The sub-adder in the third layer of the first chipset adds 1 to the initial group identifier signal 00 to obtain the identifier signal 01 for the third layer of the second chipset. Finally, the sub-adder in the fourth layer of the first chipset adds 1 to the initial group identifier signal 00 to obtain the identifier signal 01 for the fourth layer of the second chipset. In this way, chips in the stacked structure can automatically generate group identifier signals based on their chipset number and layer number, eliminating the need to pre-program fuse information to each chip and solving the chip management problem. After the chip is powered on, the group identifier signal of each chip group will remain unchanged. If the group identifier signal matches the input group strobe signal, the chip in the corresponding chip group will be selected.

[0111] In some embodiments, the stacking structure further includes:

[0112] A first driving circuit is connected to each gating circuit and is used to receive and transmit the group gating signal to each gating circuit.

[0113] And / or, a second driving circuit, connected to each gating circuit, for receiving and transmitting the group identifier signal of each chipset to the corresponding chipset gating circuit.

[0114] In some embodiments, the second driving circuit is further configured to transmit the initial group identification signal to the sub-adder in each chip of the first group of chipsets.

[0115] In this embodiment of the present disclosure, the group selection signal and the group identification signal are transmitted by the first driving circuit and the second driving circuit respectively, which can improve the performance of the group identification signal and the group selection signal, thereby improving the accuracy of the group identification signal and the group selection signal subsequently transmitted to each selection circuit in the chipset.

[0116] In some embodiments, both the first driving circuit and the second driving circuit include an amplifier or an inverter chain. This reduces interference from adjacent group identification signals and output errors caused by a weak group identification signal, as the amplifier amplifies the group identification signal. The inverter chain shapes the group identification signal and converts it to a standard voltage output, improving the performance of the group identification signal; it also enhances the load-driving capability of the logic gates.

[0117] In some embodiments, reference Figure 4 The stacked structure 100 further includes: a substrate 110, on which N groups of chips are stacked. The substrate 110 includes a control circuit, which is used to: transmit a group selection signal output by a first driving circuit to each selection circuit, and / or transmit a group identification signal of the first group of chips output by a second driving circuit to the selection circuit of the first group of chips.

[0118] This disclosure provides a stacking structure, with reference to... Figure 8 The stacked structure 100 includes: a stacked chipset 10 and a chipset 20.

[0119] Chipset 10 includes four layers of chips 101, 102, 103, and 104 stacked sequentially. Each layer of chips in chipset 10 includes a gating sub-circuit 11a and a sub-adder 12a. The four gating sub-circuits 11a can form a gating circuit 11, and the four sub-adders 12a can form an adder 12. Each gating sub-circuit 11a may include, for example... Figure 2 The logic operation circuit 111 is shown. The gating sub-circuit 11a is used to match the group identifier signal SID11 and the group gating signal SID2 and output a gating signal to the corresponding chip. Each sub-adder 12a adds a preset integer value to the group identifier signal of its respective chipset to obtain the group identifier signal of the next chipset, and then transmits the group identifier signal of the next chipset to the sub-adder of the corresponding layer chip in the next chipset and the gating circuit of the next chipset.

[0120] Chipset 20 includes four layers of chips 201, 202, 203, and 204 stacked sequentially. Each layer of chips in chipset 20 includes a gating sub-circuit 21a and a sub-adder 22a. Four gating sub-circuits 21a can form a gating circuit 21, and four sub-adders 22a can form an adder 22. Each gating sub-circuit 21a may include logic operation circuitry. The gating sub-circuit 21a is used to match the group identifier signal SID12 and the group gating signal SID2 and output a gating signal to the corresponding chip.

[0121] The third transmission structure 140 is used to: transmit the initial group identification signal SID1 (i.e., the group identification signal SID11 of the first chip group 10) to the sub-adder 12a of each layer of chips in the chip group 10 and the gating circuit 11 of the first chip group 10; and transmit the group identification signal of the (n+1)th chip group output by the sub-adder n2a of each layer of chips in the (n+1)th chip group to the sub-adder of each layer of chips in the (n+1)th chip group and the gating circuit of the (n+1)th chip group respectively.

[0122] The fourth transmission structure 150 is used to electrically connect chipsets 10 and 20 and substrate 110, and to transmit group strobe signal SID2 to each strobe circuit.

[0123] The first driving circuit 160 is connected to each gating circuit and is used to receive and transmit the group gating signal to each gating circuit.

[0124] The second driving circuit 170 is connected to each gating circuit and is used to receive and transmit the group identifier signal of each chipset to the corresponding chipset gating circuit.

[0125] This disclosure provides a stacking structure, with reference to... Figure 9 The sub-gating circuit 11a in the gating circuit 11 is Figure 3 The selection circuit 112 shown is illustrated. The fourth transmission structure 150 is also used to transmit a set of signals Y to be selected. Since the set of signals Y to be selected includes four signals Y1, Y2, Y3 and Y4, the fourth transmission structure includes four fourth transmission substructures, namely 1501, 1502, 1503 and 1504. The fourth transmission substructure 1501 is used to transmit signal Y1 to the first input terminal in each selection circuit 112, the fourth transmission substructure 1502 is used to transmit signal Y2 to the second input terminal in each selection circuit 112, the fourth transmission substructure 1503 is used to transmit signal Y3 to the third input terminal in each selection circuit 112, and the fourth transmission substructure 1504 is used to transmit signal Y4 to the fourth input terminal in each selection circuit 112.

[0126] In implementation, a set of selectable signals Y is obtained by decoding the group selection signal SID2 through decoding circuit 180. In addition to the above description, Figure 9 The stacked structure 100 shown is with Figure 8 The stacking structure 100 is similar elsewhere; you can refer to the example below. Figure 8 To understand this, refer to the description of the stacked structure 100.

[0127] For example, when the group selection signal SID2 is 01, the decoder circuit 180 outputs a group of selectable signals Y1, Y2, Y3 and Y4, which are 0, 1, 0 and 0 respectively. Y1, Y2, Y3 and Y4 are transmitted to the selection sub-circuit in each group of chipsets through the fourth transmission substructures 1501, 1502, 1503 and 1504 respectively. The initial group identification signal 00 is transmitted to the sub-adder 12a and the gating sub-circuit 11a in the chipset 10 through the third transmission substructures 1401, 1402, 1403 and 1404 in the third transmission structure 140. The sub-adder 12a adds 1 to the initial group identification signal 00 to obtain the group identification signal 01 of the chipset 20, and transmits the group identification signal 01 of the chipset 20 to the sub-adder 22a and the gating sub-circuit 21a in the chips 201, 202, 203 and 204 through the third transmission substructures 1401, 1402, 1403 and 1404. Since the group identifier signal of chipset 10 is 00, the first data channel in the data selector is selected, and the data at input terminal RX1, i.e., Y1, will be output, and chipset 10 will not be selected; since the group identifier signal of chipset 20 is 01, the second data channel in the data selector is selected, and the data at input terminal RX2, i.e., Y2, will be output, and chipset 20 will be selected.

[0128] This disclosure also provides a storage device, see embodiments thereof. Figure 10 It includes a packaging substrate 190, an intermediary layer 220 located on the packaging substrate 190, a processor 210, and a stacked structure 100 in any of the above embodiments.

[0129] Also refer to Figures 1 to 10 The stack structure 100 and the processor 210 are electrically connected through an interposer layer 220. The processor 210 is used to: acquire the group strobe signal SID2 and the set initial group identifier signal SID1 of the chip to be accessed; transmit the initial group identifier signal SID1 to the stack structure 100 so that the strobe circuit of each chip group in the stack structure 100 receives the group identifier signal of the corresponding chip group; and transmit the group strobe signal to the stack structure 100 so as to select the chip in the stack structure 100 whose group identifier signal matches the group strobe signal SID2.

[0130] In implementation, the stacked structure 100 includes a physical (PHY) interface 100a. The PHY interface 100a may include input interfaces for a group strobe signal and an initial group identifier signal. In implementation, the input interfaces for the group strobe signal and the initial group identifier signal can be coupled to the second transmission structure 130 (or the fourth input structure 150) and the first transmission structure 120 (or the third input structure 140), respectively, thereby inputting the group strobe signal and the initial group identifier signal to the stacked structure 100. The processor 210 includes a PHY interface 210a, which may include an output interface for the group strobe signal, used to output the group strobe signal. The PHY interface 100a and the PHY interface 210a can be coupled through an interposer 220. The PHY interface 100a can serve as an interface for communication between the stacked structure 100 and the processor 210, and it can also serve as a communication interface between the substrate in the stacked structure 100 and the processor 210. In other embodiments, the stack structure is also provided with a direct access (DA) interface, which can be used as an interface for testing the stack structure 100.

[0131] The storage device in this embodiment can select chips in the stacked structure whose group identification signal matches the group strobe signal, so as to perform data reading and / or data storage operations on the selected chips.

[0132] This disclosure also provides a chip selection method, wherein the execution subject of the method may be a processor in a storage device, referencing... Figure 11 This includes steps S11 to S13, wherein:

[0133] Step S11: Obtain the group strobe signal and the set initial group identifier signal of the chip to be accessed;

[0134] Here, the processor can obtain the group strobe signal and initial group identifier signal of the chipset to be accessed based on the processing event.

[0135] Step S12: Transmit the initial group identification signal to the stacking structure in any of the above embodiments, so that the gating circuit of each chip group in the stacking structure receives the group identification signal of the corresponding chip group.

[0136] Step S13: The group selection signal is transmitted to the stacked structure to select the chip in the stacked structure whose group identification signal matches the group selection signal.

[0137] In implementation, the initial group identification signal can be transmitted to the adder and gating circuit in the first group of chipsets in the stacked structure through the first transmission structure, or the initial group identification signal can be transmitted to the sub-adder and gating circuit in the first group of chipsets in the stacked structure through the third transmission structure, so that the gating circuit of each chipset in the stacked structure receives the group identification signal of the corresponding chipset.

[0138] In implementation, the group strobe signal can be transmitted to the strobe circuit of each group of chipsets in the stacked structure through the second or fourth transmission structure.

[0139] In this embodiment of the disclosure, by acquiring the group selection signal and the set initial group identifier signal of the chip to be accessed, and transmitting the initial group identifier signal and the group selection signal to the stacked structure, the selection circuit of the chip group can receive the corresponding chip group's group identifier signal, so as to match the group identifier signal with the group selection signal. If the match is successful, the chip in the corresponding chip group will be selected, thereby enabling data reading and / or data storage operations to be performed on the chip.

[0140] In some embodiments, the chip gating method may further include:

[0141] Step S14: Store data in the selected chip or read data from the selected chip.

[0142] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0143] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0144] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0145] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A stacked structure, characterized in that, include: N stacked chip groups, each chip group including M stacked layers of chips, each chip group including a specific group identification signal and a gating circuit; Each of the gating circuits is configured to: match the group identifier signal of the corresponding chipset with the input group gating signal, and output a gating signal to the corresponding chipset, wherein the gating signal is used to control the gating state of the chip in the corresponding chipset; Each of the gating circuits includes M gating sub-circuits, and each layer of the chip includes one gating sub-circuit. The gating sub-circuit is used to match the group identification signal and the group gating signal and output a gating signal to the corresponding chip. The gating sub-circuit includes a selection circuit, which is used to select a group of signals to be selected based on the group identification signal, and output a gating signal to the corresponding chip according to the selection result; wherein, the group of signals to be selected is obtained by decoding the group gating signal; Where N is a positive integer and M=4.

2. The structure according to claim 1, characterized in that, When the group identifier signal of the chipset matches the input group strobe signal, the strobe circuit outputs a first sub-strobe signal, which is used to control the chips of the chipset to be in a strobe state; when the group identifier signal of the chipset does not match the input group strobe signal, the strobe circuit outputs a second sub-strobe signal, which is used to control the chips of the chipset to be in a non-strobe state.

3. The structure according to claim 1, characterized in that, The gating sub-circuit includes a logic operation circuit, which performs an XOR operation on the group identifier signal and the group gating signal and outputs a gating signal to the corresponding chip according to the result of the XOR operation.

4. The structure according to claim 3, characterized in that, The logic operation circuit includes: at least two XOR gates and an AND gate connected to each of the XOR gates; wherein, the XOR gates are used to perform an XOR operation on the same signal bit of the group identification signal and the group strobe signal; the AND gates are used to perform an AND operation on the result of each XOR operation and output the strobe signal.

5. The structure according to any one of claims 1 to 4, characterized in that, Each of the chipsets further includes an adder, used to add a preset integer value to the group identifier signal of the chipset to obtain the group identifier signal of the next chipset, and transmit the group identifier signal of the next chipset to the adder and the gating circuit in the next chipset respectively, wherein the group identifier signal of the first chipset is the input initial group identifier signal.

6. The structure according to claim 5, characterized in that, The stacked structure further includes a first transmission structure and a second transmission structure; The first transmission structure is used to: transmit the initial group identifier signal to the adder in the first group of chipsets; and transmit the group identifier signal of the (n+1)th group of chipsets output by the adder in the (n+1)th group of chipsets to the gating circuit and the adder in the (n+1)th group of chipsets respectively. The second transmission structure is used to electrically connect the N groups of chipsets and transmit the group selection signal to each of the selection circuits; The n is an integer greater than 0 and less than N.

7. The structure according to claim 5, characterized in that, Each adder includes M sub-adders, and each layer of the chip includes one sub-adder. The sub-adder is used to add a preset integer value to the group identifier signal of its own chip group to obtain the group identifier signal of the next chip group, and transmits it to the sub-adder of the chip in the corresponding layer of the next chip group and the selection circuit of the next chip group.

8. The structure according to claim 7, characterized in that, The stacked structure further includes a third transmission structure and a fourth transmission structure; The third transmission structure is used to: transmit the initial group identification signal to the sub-adder of each layer of chips in the first group of chips and the gating circuit of the first group of chips; and transmit the group identification signal of the (n+1)th group of chips output by the sub-adder of each layer of chips in the (n+1)th group of chips to the sub-adder of each layer of chips in the (n+1)th group of chips and the gating circuit of the (n+1)th group of chips respectively. The fourth transmission structure is used to electrically connect the N groups of chipsets and transmit the group selection signal to each of the selection circuits. The n is an integer greater than 0 and less than N.

9. The structure according to claim 8, characterized in that, The third transmission structure includes M third transmission substructures; The m-th third transmission substructure is used to: electrically connect the m-th layer chip in each chipset; transmit the initial group identification signal to the sub-adder of the m-th layer chip in the first chipset and the gating circuit of the first chipset; and transmit the group identification signal of the (n+1)-th chipset output by the sub-adder of the m-th layer chip in the (n+1)-th chipset to the sub-adder of the m-th layer chip in the (n+1)-th chipset and the gating circuit of the (n+1)-th chipset. The m is an integer greater than 0 and less than M+1.

10. The structure according to claim 9, characterized in that, The third transmission substructure includes a first through-silicon via (TSV), and the fourth transmission structure includes a second TSV.

11. The structure according to claim 10, characterized in that, The first through-silicon via includes at least two first sub-through-silicon vias, and each first sub-through-silicon via is used to transmit a signal bit of the group identification signal; The second through-silicon via includes at least two second sub-through-silicon vias, and each second sub-through-silicon via is used to transmit one signal bit of the group select signal.

12. The structure according to claim 11, characterized in that, The value of N is 2, the first through-silicon via includes two first sub-through-silicon vias, and the second through-silicon via includes two second sub-through-silicon vias; the initial group identification signal is 00.

13. The structure according to any one of claims 1 to 4, characterized in that, The stacked structure further includes: A first driving circuit, connected to each of the gating circuits, is used to receive and transmit the group gating signal to each of the gating circuits. And / or, a second driving circuit, connected to each of the gating circuits, for receiving and transmitting the group identifier signal of each chipset to the corresponding gating circuit of the chipset.

14. The structure according to claim 13, characterized in that, Both the first driving circuit and the second driving circuit include an amplifier or an inverter chain.

15. A storage device, characterized in that, include: The packaging substrate, the interposer layer on the packaging substrate, the processor, and the stacked structure as described in any one of claims 1 to 14; The stacked structure is electrically connected to the processor via the interposer layer. The processor is configured to: acquire a group strobe signal and a set initial group identifier signal of the chip to be accessed; transmit the initial group identifier signal to the stacked structure so that the strobe circuit of each chip group in the stacked structure receives the corresponding chip group's group identifier signal; and transmit the group strobe signal to the stacked structure to select the chip in the stacked structure whose group identifier signal matches the group strobe signal.

16. A chip selection method, characterized in that, include: Obtain the group strobe signal and the set initial group identifier signal of the chip to be accessed; The initial group identification signal is transmitted to the stacking structure as described in any one of claims 1 to 14, so that the gating circuit of each chipset in the stacking structure receives the group identification signal of the corresponding chipset. The group strobe signal is transmitted to the stacked structure to select the chip in the stacked structure whose group identification signal matches the group strobe signal.

Images