Methods for fabricating compound semiconductor wafers

Abstract

This invention provides a method for fabricating a compound semiconductor wafer, comprising: providing a substrate, wherein an epitaxial structure of the compound semiconductor wafer, a front-side device structure, and an lead-out metal layer are sequentially formed on the front side of the substrate; forming a passivation protective layer covering the front-side device structure; temporarily bonding the front side of the compound semiconductor wafer to a first support substrate; performing a back-side process on the compound semiconductor wafer; debonding a thin wafer from the first support substrate, and adhering the back side of the thin wafer to a second support substrate using thermal adhesive; forming metal bumps on the front side of the thin wafer, the metal bumps being connected to the lead-out metal layer; and separating the thin wafer from the second support substrate. This invention performs the front-side metal bump formation step after completing the back-side process, facilitating stacked bonding and packaging between the compound semiconductor wafer and another wafer, which helps improve device integration, reduce component bonding wires, and ensure the reliability of the packaged device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method for fabricating compound semiconductor wafers. Background Technology

[0002] With the increasing demand for functional integration, compound semiconductor devices have gradually evolved into wafer-level packaging (WLP). This is typically achieved through wafer stacking and interconnection, using stacking and interconnect wiring to connect chips on different wafers. This avoids the space waste caused by traditional gold wire bonding. Wafer-level packaging technology offers advantages in many aspects, including achieving multi-functional chip integration, increasing chip integration density, reducing signal transmission and power consumption, and improving chip heat dissipation.

[0003] Third-generation compound semiconductor devices, represented by gallium nitride (GaN), offer higher electron mobility and a wider operating frequency range compared to silicon devices, leading to their gradual replacement in high-frequency power applications. However, radio frequency (RF) devices typically require substrate thinning during back-side processing. The resulting thin or ultra-thin wafers are flexible, fragile, and prone to warping. Currently, the fabrication of thin or ultra-thin compound semiconductor wafers often employs temporary bonding processes to perform back-side processes, including thinning and back-side metallization, before debonding the wafer from the carrier. When wafers are thinned to less than 100 micrometers, or even to ultra-thin wafers between 25 and 75 micrometers, after back-side via etching and back-side metallization, the wafer becomes stress-sensitive during debonding. Therefore, the choice of bonding adhesive and process in temporary bonding technology is crucial to wafer yield. Furthermore, chip stacking structures require interconnection structures to achieve circuit connections between chips, such as front-side metal bumps. Fabricating a wafer with front-side metal bumps typically requires transferring the wafer with the completed back-side processing onto a second support substrate, ensuring the front side is facing up, before fabricating the front-side metal bumps. However, the presence of back-side vias presents numerous problems with the temporary bonding process used in this second transfer, such as residual bonding adhesive / wax within the deep vias, and uneven bonding and debonding stress leading to fragmentation.

[0004] Therefore, it is necessary to provide a method for fabricating a compound semiconductor wafer with front-side metal bumps. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating compound semiconductor wafers, which solves the problems of residual bonding adhesive / bonding wax in the vias during the fabrication of metal bumps on the front side of thin wafers with back vias and separation from the second support substrate, as well as the problems of low yield or product yield caused by wafer microcracks or fractures.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a compound semiconductor wafer, characterized in that the fabrication method includes:

[0007] A substrate is provided, wherein an epitaxial structure of a compound semiconductor wafer, a front-side device structure, and an lead-out metal layer are sequentially formed on the front side of the substrate;

[0008] A passivation protective layer is formed over the front device structure of the compound semiconductor wafer;

[0009] The front side of the compound semiconductor wafer faces the first support substrate and is temporarily bonded to the first support substrate;

[0010] Performing a back-side process on the compound semiconductor wafer includes:

[0011] The back side of the compound semiconductor wafer is thinned to obtain a thin wafer;

[0012] The thin wafer is subjected to back-side via etching;

[0013] The thin wafer is then back-side metallized;

[0014] The thin wafer is debonded from the first support substrate, and the thin wafer is transferred to the second support substrate and the back side of the thin wafer is fixed to the second support substrate with thermal adhesive.

[0015] Metal bumps are formed on the front side of the thin wafer, and the metal bumps are connected to the lead-out metal layer;

[0016] This separates the thin wafer from the second support substrate.

[0017] Optionally, the substrate includes one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a sapphire substrate, and the thickness of the thin wafer ranges from 25 micrometers to 100 micrometers.

[0018] Optionally, the metal bump is made of one metal material selected from copper, gold, indium and tin, or an alloy of two or more metals, and the height of the metal bump is not less than 50 micrometers.

[0019] Optionally, the step of forming the metal bump includes: forming an opening in the passivation protective layer by an etching process, the opening exposing the electrode portion of the lead-out metal layer; and sequentially forming a bump under-metallization seed layer, an electroplated metal pillar, and a welding metal layer that are electrically connected to the electrode portion of the lead-out metal layer on the front side of the thin wafer from bottom to top.

[0020] Optionally, performing a back-side process on the compound semiconductor wafer further includes: defining a dicing region on the back side of the wafer using a photolithography process, wherein the metal bump is positioned close to the dicing region of the wafer and located on the periphery of a single semiconductor device, the width of the metal bump is not less than 30 micrometers, and the distance between the metal bump and the dicing is not less than 10 micrometers.

[0021] Optionally, after performing the back-side process on the compound semiconductor wafer, the back side of the wafer is adhered to the second support substrate using thermal adhesive; subsequently, metal bumps are formed on the front side of the wafer, wherein the thermal adhesive is a double-sided thermal adhesive tape.

[0022] Optionally, the double-sided thermal adhesive is desorbed by heat treatment to separate the thin wafer from the second support substrate, wherein the thermal adhesive has a temperature resistance of not less than 120°C.

[0023] Optionally, the step of de-adhesiveizing the double-sided thermal tape includes: adjusting the heating temperature to maintain the temperature difference between the front and back sides of the double-sided thermal tape at no more than + / -2℃, so that the front and back sides of the double-sided thermal tape de-adhesive simultaneously.

[0024] Optionally, the front side of the compound semiconductor wafer is temporarily bonded to the first support substrate via bonding adhesive or bonding wax, wherein the bonding adhesive or bonding wax has a temperature resistance of 180°C or higher.

[0025] Optionally, the fabrication method further includes: debonding the thin wafer to the first support substrate by heat treatment, and cleaning the front side of the thin wafer.

[0026] As described above, the present invention provides a method for fabricating a compound semiconductor wafer, which has the following beneficial effects:

[0027] This invention, after thinning and metallizing the back side of the wafer, uses thermal adhesive to transfer the thin wafer onto a second support substrate with the front side facing up, and then performs the step of forming metal bumps on the front side of the wafer. Compared with conventional temporary bonding processes, this reduces the stress caused by the wafer transfer step and avoids damage or breakage of the thin wafer due to stress sensitivity. At the same time, it avoids the drawback of incomplete removal of bonding adhesive or bonding wax into the back vias in conventional bonding processes, simplifies the cleaning process, and improves product yield.

[0028] This invention forms metal bumps on the front side of the chip while fabricating the compound semiconductor wafer, which facilitates the stacking and bonding of the compound semiconductor wafer with another semiconductor wafer, reduces the number of bonding wires in the component packaging, ensures the reliability of the packaged device, and helps to improve the integration of the device, enabling multi-functional chip integration. Attached Figure Description

[0029] Figure 1 The flowchart shown is a method for fabricating a compound semiconductor wafer according to an embodiment of the present invention. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0032] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0033] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0034] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] like Figure 1 As shown, this embodiment provides a method for fabricating a compound semiconductor wafer, including the following steps:

[0036] First, in step S100, a substrate is provided, on which an epitaxial structure of a compound semiconductor wafer, a front-side device structure, and an lead-out metal layer are sequentially formed.

[0037] As an example, the substrate includes one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a sapphire substrate. Accordingly, the material used to form the compound semiconductor wafer can be a III-V compound semiconductor material, such as InP, GaAs, or GaN.

[0038] Furthermore, after the epitaxial process, the compound semiconductor wafer may be surface cleaned to remove surface contaminants and particles, thereby improving the quality of the semiconductor device.

[0039] As an example, step S100 may include photolithography, vapor deposition, annealing, or a similar front-side process for the wafer to form a front-side device structure, metal electrodes, and lead-out metal layers.

[0040] As an example, the compound semiconductor device unit can be a semiconductor device unit based on group III-V compounds, such as InP devices, GaAs devices, or GaN devices. In this embodiment, GaN-based radio frequency device units can be formed on the substrate.

[0041] As an example, the lead-out metal layer includes a source lead-out terminal electrically connected to the source, a drain lead-out terminal electrically connected to the drain, a gate lead-out terminal electrically connected to the gate electrode, and an electrode portion.

[0042] Next, step S110 is performed to form a passivation protective layer over the front device structure of the compound semiconductor wafer.

[0043] As an example, the passivation protective layer can be formed on the surface of the front device structure by, for example, physical vapor deposition or chemical vapor deposition processes, for surface passivation and to reduce damage to the device surface caused by stress unevenness in subsequent back-side processes.

[0044] See also Figure 1 As shown, step S120 is then performed, in which the front side of the compound semiconductor wafer faces the first support substrate and is temporarily bonded to the first support substrate.

[0045] As an example, the material of the supporting substrate can be quartz, glass, semiconductor, or metal.

[0046] Specifically, step S120 includes: coating a bonding adhesive or bonding wax onto the front side of a compound semiconductor wafer, so that the front side of the compound semiconductor wafer faces the first support substrate and is bonded to the first support substrate, thereby forming a bonded sheet. Since the temporary bonding system composed of the bonding adhesive or bonding wax is subjected to the high temperatures of the back-side processing in the subsequent back-side metallization process, the bonding adhesive or bonding wax needs to have thermal stability. Specifically, the bonding adhesive or bonding wax has a temperature resistance of above 180°C.

[0047] Next, step S130 is performed to perform a back-side process on the compound semiconductor wafer. Specifically, step S130 includes: thinning the back side of the substrate using the bonding sheet obtained in step S120 to obtain a thin wafer; etching back-side vias on the thin wafer; and metallizing the back side of the thin wafer.

[0048] As an example, step S130 further includes: after thinning the back side of the substrate, polishing the back side of the substrate to improve the roughness and uniformity of the processed surface. During the thinning and surface polishing process, the supporting substrate provides support for the entire substrate, thus avoiding damage to the device.

[0049] As an example, the thinned substrate is polished to obtain a thin wafer bonded to a first supporting substrate, wherein the thickness of the thin wafer ranges from 25 micrometers to 100 micrometers. In this embodiment, the thickness of the thin wafer ranges from 25 micrometers to 100 micrometers, for example, 75 micrometers.

[0050] As an example, the back-side via etching of a thin wafer includes at least the following steps: forming a via from the back side of the thin wafer to the contact metal layer using an etching process, for realizing the back-side lead-out of device units in the thin wafer.

[0051] As an example, metallizing the back side of the wafer includes at least the following steps: forming a metal seed layer on the back side of the wafer; and forming a metal plating layer on the back side of the wafer.

[0052] As an example, performing a back-side process on the compound semiconductor wafer further includes defining a dicing region on the back side of the wafer using a photolithography process.

[0053] like Figure 1 As shown, step S140 is performed to debond the thin wafer from the first support substrate and transfer the thin wafer to the second support substrate, and to adhere the back side of the thin wafer to the second support substrate with thermal adhesive.

[0054] As an example, the bonding adhesive or bonding wax is heated by a hot plate to debond the thin wafer from the first support substrate, and the thin wafer is transferred to the second support substrate and the back side of the thin wafer is adhered to the second support substrate by a heat-sensitive adhesive.

[0055] As an example, the front side of the thin wafer after debonding from the second support substrate is cleaned.

[0056] Specifically, the back side of the thin wafer is adhered to the second support substrate to form a bonding sheet, wherein the thermal adhesive is a double-sided thermal adhesive tape. The back side of the thin wafer is adhered to the second support substrate, but the thermal adhesive does not adhere to the through-holes on the back side of the thin wafer, which simplifies the cleaning steps on the wafer surface after separation. Preferably, the thermal adhesive has a temperature resistance of not less than 120°C.

[0057] As an example, the second support substrate is slightly larger than or equal to the size of the wafer to provide support for the wafer.

[0058] As an example, the front side of the thin wafer is wet-cleaned to remove bonding adhesive / bonding wax remaining on the front side of the wafer after the first support substrate is debonded from the wafer.

[0059] Next, step S150 is performed to form metal bumps on the front side of the thin wafer. The metal bumps are connected to the lead-out metal layer for electrical coupling to an integrated circuit or another chip, such as bonding to the bonding portion of a silicon chip and / or a memory chip. This facilitates stacked bonding and packaging of the compound semiconductor wafer with another semiconductor wafer, which helps to improve the integration of compound semiconductor devices and multifunctional integration.

[0060] As an example, step S150 further includes: forming an opening in the passivation protective layer by an etching process, the opening exposing the electrode portion of the lead-out metal layer. In this embodiment, the pattern of the opening is defined on the surface of the passivation protective layer by a photolithography process.

[0061] As an example, the metal bump is made of a metal material selected from copper, gold, indium and tin, or an alloy of two or more of them.

[0062] As an example, metal bumps can be formed on the front side of a wafer, positioned close to the dicing region of the wafer and located on the periphery of a single semiconductor device unit, with the distance between the metal bumps and the dicing region not less than 10 micrometers.

[0063] As an example, the height of the metal bump is not less than 50 micrometers, for example, more than 60 micrometers, and the width of the metal bump is not less than 30 micrometers.

[0064] Since the thin wafers obtained after the back-side process become fragile, metal bumps are formed on the front side of the chip after the back-side process, which includes thinning and back-side metallization, to avoid warping or damage to the thin wafers that are prone to stress sensitivity during the back-side process.

[0065] As an example, step S150 further includes: after forming an opening on the passivation protective layer, sequentially forming a bump under-metallization seed layer, an electroplated metal pillar, and a solder metal layer that are electrically connected to the electrode portion of the lead-out metal layer from bottom to top on the front side of the thin wafer. In this embodiment, the photoresist retained after the etching process forms metal bumps within the patterned area defined by the opening and the photoresist.

[0066] Step S160 is performed to separate the thin wafer from the second support substrate.

[0067] In this embodiment, the bonding sheet consisting of a thin wafer and a second supporting substrate is placed on a hot plate, causing the double-sided thermal adhesive tape to desorb. The tape melts or degrades under heat, reducing or eliminating its adhesiveness, thus separating the thin wafer from the second supporting substrate. Because heat treatment reduces or eliminates the adhesive's stickiness, compared to conventionally used bonding adhesives or bonding waxes, it reduces stress from wafer transfer technology and minimizes adhesive residue, thereby preventing wafer warpage that might be caused by adhesive residue before cleaning the thin wafer surface. In this embodiment, the step of desorbing the double-sided thermal adhesive tape includes adjusting the heating temperature to maintain the temperature difference between the front and back sides of the tape at no more than + / -2°C, so that both sides of the tape desorb simultaneously, achieving one-time peeling of the double-sided thermal adhesive tape.

[0068] Following step S160, the method for fabricating the compound semiconductor wafer further includes: after completing the stacked bonding and packaging of the compound semiconductor wafer and another semiconductor wafer, performing a dicing process based on the dicing kerf region, wherein the dicing kerf region may be defined in the front and back metallization processes. For example, the wafer-level dicing process may be performed using laser cutting and / or mechanical cutting with a blade wheel.

[0069] As an example, the manufacturing method further includes the following step: before performing the dicing process based on the dicing area, the surface of the stacked packaging structure including the thin wafer can be cleaned.

[0070] As described above, the method for fabricating compound semiconductor wafers provided by the present invention has the following beneficial effects:

[0071] This invention, after thinning and metallizing the back side of the wafer, uses thermal adhesive to transfer the thin wafer onto a second support substrate with the front side facing up, and then performs the step of forming metal bumps on the front side of the wafer. Compared with conventional temporary bonding processes, this reduces the stress caused by the wafer transfer step and avoids damage or breakage of the thin wafer due to stress sensitivity. At the same time, it avoids the drawback of incomplete removal of bonding adhesive or bonding wax into the back vias in conventional bonding processes, simplifies the cleaning process, and improves product yield.

[0072] This invention forms metal bumps on the front side of the chip while fabricating the compound semiconductor wafer, which facilitates the stacking and bonding of the compound semiconductor wafer with another semiconductor wafer, reduces the number of bonding wires in the component packaging, ensures the reliability of the packaged device, and helps to improve the integration of the device, enabling multi-functional chip integration.

[0073] Therefore, this invention effectively overcomes several shortcomings of the prior art and has high industrial application value.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a compound semiconductor wafer, characterized in that, The manufacturing method includes: A substrate is provided, wherein an epitaxial structure of a compound semiconductor wafer, a front-side device structure, and an lead-out metal layer are sequentially formed on the front side of the substrate; A passivation protective layer is formed over the front device structure of the compound semiconductor wafer; The front side of the compound semiconductor wafer faces the first support substrate and is temporarily bonded to the first support substrate; Performing a back-side process on the compound semiconductor wafer includes: The back side of the compound semiconductor wafer is thinned to obtain a thin wafer; The thin wafer is subjected to back-side via etching; The thin wafer is back-side metallized; the thin wafer is debonded from the first support substrate; and the thin wafer is transferred to the second support substrate, with the back side of the thin wafer adhered to the second support substrate by thermal adhesive; wherein the thermal adhesive is a double-sided thermal adhesive tape. Metal bumps are formed on the front side of the thin wafer, and the metal bumps are connected to the lead-out metal layer; By adjusting the heating temperature, the temperature difference between the front and back sides of the double-sided thermal adhesive tape is maintained at no more than + / -2℃, so that the front and back sides of the double-sided thermal adhesive tape are desorbed simultaneously, thereby separating the thin wafer from the second support substrate. The temperature resistance of the double-sided thermal adhesive is not lower than 120℃.

2. The manufacturing method according to claim 1, characterized in that, The substrate includes one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a sapphire substrate, and the thickness of the thin wafer ranges from 25 micrometers to 100 micrometers.

3. The manufacturing method according to claim 1, characterized in that, The metal bump is made of one or more metals selected from copper, gold, indium and tin, or an alloy of two or more of them, and the height of the metal bump is not less than 50 micrometers.

4. The manufacturing method according to claim 1, characterized in that, The steps for forming metal bumps include: forming an opening in the passivation protective layer by etching, the opening exposing the electrode portion of the lead-out metal layer; and forming, from bottom to top, a bump under-metallization seed layer, an electroplated metal pillar, and a welding metal layer that are electrically connected to the electrode portion of the lead-out metal layer on the front side of the thin wafer.

5. The manufacturing method according to claim 1, characterized in that, Performing a back-side process on the compound semiconductor wafer further includes: defining a dicing region on the back side of the wafer using a photolithography process, wherein the metal bump is positioned close to the dicing region of the wafer and located on the periphery of a single semiconductor device, the width of the metal bump is not less than 30 micrometers, and the distance between the metal bump and the dicing is not less than 10 micrometers.

6. The manufacturing method according to claim 1, characterized in that, The front side of the compound semiconductor wafer is temporarily bonded to the first support substrate via bonding adhesive or bonding wax, wherein the bonding adhesive or bonding wax has a temperature resistance of 180°C or higher.

7. The manufacturing method according to claim 6, characterized in that, The manufacturing method further includes: debonding the thin wafer to the first support substrate by heat treatment, and cleaning the surface of the thin wafer.

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